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pinctrl: intel: wrap Intel pin control drivers in an architecture check
[mirror_ubuntu-focal-kernel.git] / drivers / pinctrl / pinctrl-rockchip.c
CommitLineData
d3e51161
HS		 1/*
2 * Pinctrl driver for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * With some ideas taken from pinctrl-samsung:
8 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
9 * http://www.samsung.com
10 * Copyright (c) 2012 Linaro Ltd
11 * http://www.linaro.org
12 *
13 * and pinctrl-at91:
14 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as published
18 * by the Free Software Foundation.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 */
25
2f436204 26#include <linux/init.h>
d3e51161
HS		 27#include <linux/platform_device.h>
28#include <linux/io.h>
29#include <linux/bitops.h>
30#include <linux/gpio.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf.h>
35#include <linux/pinctrl/pinctrl.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pinctrl/pinconf-generic.h>
38#include <linux/irqchip/chained_irq.h>
7e865abb 39#include <linux/clk.h>
751a99ab 40#include <linux/regmap.h>
14dee867 41#include <linux/mfd/syscon.h>
d3e51161
HS		 42#include <dt-bindings/pinctrl/rockchip.h>
43
44#include "core.h"
45#include "pinconf.h"
46
47/* GPIO control registers */
48#define GPIO_SWPORT_DR 0x00
49#define GPIO_SWPORT_DDR 0x04
50#define GPIO_INTEN 0x30
51#define GPIO_INTMASK 0x34
52#define GPIO_INTTYPE_LEVEL 0x38
53#define GPIO_INT_POLARITY 0x3c
54#define GPIO_INT_STATUS 0x40
55#define GPIO_INT_RAWSTATUS 0x44
56#define GPIO_DEBOUNCE 0x48
57#define GPIO_PORTS_EOI 0x4c
58#define GPIO_EXT_PORT 0x50
59#define GPIO_LS_SYNC 0x60
60
a282926d 61enum rockchip_pinctrl_type {
b9c6dcab 62 RV1108,
a282926d
HS		 63 RK2928,
64 RK3066B,
d23c66df 65 RK3128,
a282926d 66 RK3188,
66d750e1 67 RK3288,
daecdc66 68 RK3368,
b6c23275 69 RK3399,
a282926d
HS		 70};
71
fc72c923
HS		 72/**
73 * Encode variants of iomux registers into a type variable
74 */
75#define IOMUX_GPIO_ONLY BIT(0)
03716e1d 76#define IOMUX_WIDTH_4BIT BIT(1)
95ec8ae4 77#define IOMUX_SOURCE_PMU BIT(2)
62f49226 78#define IOMUX_UNROUTED BIT(3)
8b6c6f93 79#define IOMUX_WIDTH_3BIT BIT(4)
fc72c923
HS		 80
81/**
82 * @type: iomux variant using IOMUX_* constants
6bc0d121
HS		 83 * @offset: if initialized to -1 it will be autocalculated, by specifying
84 * an initial offset value the relevant source offset can be reset
85 * to a new value for autocalculating the following iomux registers.
fc72c923
HS		 86 */
87struct rockchip_iomux {
88 int type;
6bc0d121 89 int offset;
65fca613
HS		 90};
91
b6c23275
DW		 92/**
93 * enum type index corresponding to rockchip_perpin_drv_list arrays index.
94 */
95enum rockchip_pin_drv_type {
96 DRV_TYPE_IO_DEFAULT = 0,
97 DRV_TYPE_IO_1V8_OR_3V0,
98 DRV_TYPE_IO_1V8_ONLY,
99 DRV_TYPE_IO_1V8_3V0_AUTO,
100 DRV_TYPE_IO_3V3_ONLY,
101 DRV_TYPE_MAX
102};
103
3ba6767a
DW		 104/**
105 * enum type index corresponding to rockchip_pull_list arrays index.
106 */
107enum rockchip_pin_pull_type {
108 PULL_TYPE_IO_DEFAULT = 0,
109 PULL_TYPE_IO_1V8_ONLY,
110 PULL_TYPE_MAX
111};
112
b6c23275
DW		 113/**
114 * @drv_type: drive strength variant using rockchip_perpin_drv_type
115 * @offset: if initialized to -1 it will be autocalculated, by specifying
116 * an initial offset value the relevant source offset can be reset
117 * to a new value for autocalculating the following drive strength
118 * registers. if used chips own cal_drv func instead to calculate
119 * registers offset, the variant could be ignored.
120 */
121struct rockchip_drv {
122 enum rockchip_pin_drv_type drv_type;
123 int offset;
124};
125
d3e51161
HS		 126/**
127 * @reg_base: register base of the gpio bank
6ca5274d 128 * @reg_pull: optional separate register for additional pull settings
d3e51161
HS		 129 * @clk: clock of the gpio bank
130 * @irq: interrupt of the gpio bank
5ae0c7ad 131 * @saved_masks: Saved content of GPIO_INTEN at suspend time.
d3e51161
HS		 132 * @pin_base: first pin number
133 * @nr_pins: number of pins in this bank
134 * @name: name of the bank
135 * @bank_num: number of the bank, to account for holes
fc72c923 136 * @iomux: array describing the 4 iomux sources of the bank
b6c23275 137 * @drv: array describing the 4 drive strength sources of the bank
3ba6767a 138 * @pull_type: array describing the 4 pull type sources of the bank
d3e51161
HS		 139 * @valid: are all necessary informations present
140 * @of_node: dt node of this bank
141 * @drvdata: common pinctrl basedata
142 * @domain: irqdomain of the gpio bank
143 * @gpio_chip: gpiolib chip
144 * @grange: gpio range
145 * @slock: spinlock for the gpio bank
bd35b9bf 146 * @route_mask: bits describing the routing pins of per bank
d3e51161
HS		 147 */
148struct rockchip_pin_bank {
149 void __iomem *reg_base;
751a99ab 150 struct regmap *regmap_pull;
d3e51161
HS		 151 struct clk *clk;
152 int irq;
5ae0c7ad 153 u32 saved_masks;
d3e51161
HS		 154 u32 pin_base;
155 u8 nr_pins;
156 char *name;
157 u8 bank_num;
fc72c923 158 struct rockchip_iomux iomux[4];
b6c23275 159 struct rockchip_drv drv[4];
3ba6767a 160 enum rockchip_pin_pull_type pull_type[4];
d3e51161
HS		 161 bool valid;
162 struct device_node *of_node;
163 struct rockchip_pinctrl *drvdata;
164 struct irq_domain *domain;
165 struct gpio_chip gpio_chip;
166 struct pinctrl_gpio_range grange;
70b7aa7a 167 raw_spinlock_t slock;
5a927501 168 u32 toggle_edge_mode;
c04c3fa6 169 u32 recalced_mask;
bd35b9bf 170 u32 route_mask;
d3e51161
HS		 171};
172
173#define PIN_BANK(id, pins, label) \
174 { \
175 .bank_num = id, \
176 .nr_pins = pins, \
177 .name = label, \
6bc0d121
HS		 178 .iomux = { \
179 { .offset = -1 }, \
180 { .offset = -1 }, \
181 { .offset = -1 }, \
182 { .offset = -1 }, \
183 }, \
d3e51161
HS		 184 }
185
fc72c923
HS		 186#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \
187 { \
188 .bank_num = id, \
189 .nr_pins = pins, \
190 .name = label, \
191 .iomux = { \
6bc0d121
HS		 192 { .type = iom0, .offset = -1 }, \
193 { .type = iom1, .offset = -1 }, \
194 { .type = iom2, .offset = -1 }, \
195 { .type = iom3, .offset = -1 }, \
fc72c923
HS		 196 }, \
197 }
198
b6c23275
DW		 199#define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \
200 { \
201 .bank_num = id, \
202 .nr_pins = pins, \
203 .name = label, \
204 .iomux = { \
205 { .offset = -1 }, \
206 { .offset = -1 }, \
207 { .offset = -1 }, \
208 { .offset = -1 }, \
209 }, \
210 .drv = { \
211 { .drv_type = type0, .offset = -1 }, \
212 { .drv_type = type1, .offset = -1 }, \
213 { .drv_type = type2, .offset = -1 }, \
214 { .drv_type = type3, .offset = -1 }, \
215 }, \
216 }
217
3ba6767a
DW		 218#define PIN_BANK_DRV_FLAGS_PULL_FLAGS(id, pins, label, drv0, drv1, \
219 drv2, drv3, pull0, pull1, \
220 pull2, pull3) \
221 { \
222 .bank_num = id, \
223 .nr_pins = pins, \
224 .name = label, \
225 .iomux = { \
226 { .offset = -1 }, \
227 { .offset = -1 }, \
228 { .offset = -1 }, \
229 { .offset = -1 }, \
230 }, \
231 .drv = { \
232 { .drv_type = drv0, .offset = -1 }, \
233 { .drv_type = drv1, .offset = -1 }, \
234 { .drv_type = drv2, .offset = -1 }, \
235 { .drv_type = drv3, .offset = -1 }, \
236 }, \
237 .pull_type[0] = pull0, \
238 .pull_type[1] = pull1, \
239 .pull_type[2] = pull2, \
240 .pull_type[3] = pull3, \
241 }
242
b6c23275
DW		 243#define PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(id, pins, label, iom0, iom1, \
244 iom2, iom3, drv0, drv1, drv2, \
245 drv3, offset0, offset1, \
246 offset2, offset3) \
247 { \
248 .bank_num = id, \
249 .nr_pins = pins, \
250 .name = label, \
251 .iomux = { \
252 { .type = iom0, .offset = -1 }, \
253 { .type = iom1, .offset = -1 }, \
254 { .type = iom2, .offset = -1 }, \
255 { .type = iom3, .offset = -1 }, \
256 }, \
257 .drv = { \
258 { .drv_type = drv0, .offset = offset0 }, \
259 { .drv_type = drv1, .offset = offset1 }, \
260 { .drv_type = drv2, .offset = offset2 }, \
261 { .drv_type = drv3, .offset = offset3 }, \
262 }, \
263 }
264
3ba6767a
DW		 265#define PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(id, pins, \
266 label, iom0, iom1, iom2, \
267 iom3, drv0, drv1, drv2, \
268 drv3, offset0, offset1, \
269 offset2, offset3, pull0, \
270 pull1, pull2, pull3) \
271 { \
272 .bank_num = id, \
273 .nr_pins = pins, \
274 .name = label, \
275 .iomux = { \
276 { .type = iom0, .offset = -1 }, \
277 { .type = iom1, .offset = -1 }, \
278 { .type = iom2, .offset = -1 }, \
279 { .type = iom3, .offset = -1 }, \
280 }, \
281 .drv = { \
282 { .drv_type = drv0, .offset = offset0 }, \
283 { .drv_type = drv1, .offset = offset1 }, \
284 { .drv_type = drv2, .offset = offset2 }, \
285 { .drv_type = drv3, .offset = offset3 }, \
286 }, \
287 .pull_type[0] = pull0, \
288 .pull_type[1] = pull1, \
289 .pull_type[2] = pull2, \
290 .pull_type[3] = pull3, \
291 }
292
c04c3fa6
DW		 293/**
294 * struct rockchip_mux_recalced_data: represent a pin iomux data.
295 * @num: bank number.
296 * @pin: pin number.
297 * @bit: index at register.
298 * @reg: register offset.
299 * @mask: mask bit
300 */
301struct rockchip_mux_recalced_data {
302 u8 num;
303 u8 pin;
304 u8 reg;
305 u8 bit;
306 u8 mask;
307};
308
bd35b9bf
DW		 309/**
310 * struct rockchip_mux_recalced_data: represent a pin iomux data.
311 * @bank_num: bank number.
312 * @pin: index at register or used to calc index.
313 * @func: the min pin.
314 * @route_offset: the max pin.
315 * @route_val: the register offset.
316 */
317struct rockchip_mux_route_data {
318 u8 bank_num;
319 u8 pin;
320 u8 func;
321 u32 route_offset;
322 u32 route_val;
323};
324
d3e51161 325/**
d3e51161
HS		 326 */
327struct rockchip_pin_ctrl {
328 struct rockchip_pin_bank *pin_banks;
329 u32 nr_banks;
330 u32 nr_pins;
331 char *label;
a282926d 332 enum rockchip_pinctrl_type type;
95ec8ae4
HS		 333 int grf_mux_offset;
334 int pmu_mux_offset;
b6c23275
DW		 335 int grf_drv_offset;
336 int pmu_drv_offset;
c04c3fa6
DW		 337 struct rockchip_mux_recalced_data *iomux_recalced;
338 u32 niomux_recalced;
bd35b9bf
DW		 339 struct rockchip_mux_route_data *iomux_routes;
340 u32 niomux_routes;
b6c23275 341
751a99ab
HS		 342 void (*pull_calc_reg)(struct rockchip_pin_bank *bank,
343 int pin_num, struct regmap **regmap,
344 int *reg, u8 *bit);
ef17f69f
HS		 345 void (*drv_calc_reg)(struct rockchip_pin_bank *bank,
346 int pin_num, struct regmap **regmap,
347 int *reg, u8 *bit);
e3b357d7 348 int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank,
349 int pin_num, struct regmap **regmap,
350 int *reg, u8 *bit);
d3e51161
HS		 351};
352
353struct rockchip_pin_config {
354 unsigned int func;
355 unsigned long *configs;
356 unsigned int nconfigs;
357};
358
359/**
360 * struct rockchip_pin_group: represent group of pins of a pinmux function.
361 * @name: name of the pin group, used to lookup the group.
362 * @pins: the pins included in this group.
363 * @npins: number of pins included in this group.
364 * @func: the mux function number to be programmed when selected.
365 * @configs: the config values to be set for each pin
366 * @nconfigs: number of configs for each pin
367 */
368struct rockchip_pin_group {
369 const char *name;
370 unsigned int npins;
371 unsigned int *pins;
372 struct rockchip_pin_config *data;
373};
374
375/**
376 * struct rockchip_pmx_func: represent a pin function.
377 * @name: name of the pin function, used to lookup the function.
378 * @groups: one or more names of pin groups that provide this function.
379 * @num_groups: number of groups included in @groups.
380 */
381struct rockchip_pmx_func {
382 const char *name;
383 const char **groups;
384 u8 ngroups;
385};
386
387struct rockchip_pinctrl {
751a99ab 388 struct regmap *regmap_base;
bfc7a42a 389 int reg_size;
751a99ab 390 struct regmap *regmap_pull;
14dee867 391 struct regmap *regmap_pmu;
d3e51161
HS		 392 struct device *dev;
393 struct rockchip_pin_ctrl *ctrl;
394 struct pinctrl_desc pctl;
395 struct pinctrl_dev *pctl_dev;
396 struct rockchip_pin_group *groups;
397 unsigned int ngroups;
398 struct rockchip_pmx_func *functions;
399 unsigned int nfunctions;
400};
401
751a99ab
HS		 402static struct regmap_config rockchip_regmap_config = {
403 .reg_bits = 32,
404 .val_bits = 32,
405 .reg_stride = 4,
406};
407
56411f3c 408static inline const struct rockchip_pin_group *pinctrl_name_to_group(
d3e51161
HS		 409 const struct rockchip_pinctrl *info,
410 const char *name)
411{
d3e51161
HS		 412 int i;
413
414 for (i = 0; i < info->ngroups; i++) {
1cb95395
AL		 415 if (!strcmp(info->groups[i].name, name))
416 return &info->groups[i];
d3e51161
HS		 417 }
418
1cb95395 419 return NULL;
d3e51161
HS		 420}
421
422/*
423 * given a pin number that is local to a pin controller, find out the pin bank
424 * and the register base of the pin bank.
425 */
426static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info,
427 unsigned pin)
428{
429 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
430
51578b9b 431 while (pin >= (b->pin_base + b->nr_pins))
d3e51161
HS		 432 b++;
433
434 return b;
435}
436
437static struct rockchip_pin_bank *bank_num_to_bank(
438 struct rockchip_pinctrl *info,
439 unsigned num)
440{
441 struct rockchip_pin_bank *b = info->ctrl->pin_banks;
442 int i;
443
1cb95395 444 for (i = 0; i < info->ctrl->nr_banks; i++, b++) {
d3e51161 445 if (b->bank_num == num)
1cb95395 446 return b;
d3e51161
HS		 447 }
448
1cb95395 449 return ERR_PTR(-EINVAL);
d3e51161
HS		 450}
451
452/*
453 * Pinctrl_ops handling
454 */
455
456static int rockchip_get_groups_count(struct pinctrl_dev *pctldev)
457{
458 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
459
460 return info->ngroups;
461}
462
463static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev,
464 unsigned selector)
465{
466 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
467
468 return info->groups[selector].name;
469}
470
471static int rockchip_get_group_pins(struct pinctrl_dev *pctldev,
472 unsigned selector, const unsigned **pins,
473 unsigned *npins)
474{
475 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
476
477 if (selector >= info->ngroups)
478 return -EINVAL;
479
480 *pins = info->groups[selector].pins;
481 *npins = info->groups[selector].npins;
482
483 return 0;
484}
485
486static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev,
487 struct device_node *np,
488 struct pinctrl_map **map, unsigned *num_maps)
489{
490 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
491 const struct rockchip_pin_group *grp;
492 struct pinctrl_map *new_map;
493 struct device_node *parent;
494 int map_num = 1;
495 int i;
496
497 /*
498 * first find the group of this node and check if we need to create
499 * config maps for pins
500 */
501 grp = pinctrl_name_to_group(info, np->name);
502 if (!grp) {
503 dev_err(info->dev, "unable to find group for node %s\n",
504 np->name);
505 return -EINVAL;
506 }
507
508 map_num += grp->npins;
509 new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num,
510 GFP_KERNEL);
511 if (!new_map)
512 return -ENOMEM;
513
514 *map = new_map;
515 *num_maps = map_num;
516
517 /* create mux map */
518 parent = of_get_parent(np);
519 if (!parent) {
520 devm_kfree(pctldev->dev, new_map);
521 return -EINVAL;
522 }
523 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
524 new_map[0].data.mux.function = parent->name;
525 new_map[0].data.mux.group = np->name;
526 of_node_put(parent);
527
528 /* create config map */
529 new_map++;
530 for (i = 0; i < grp->npins; i++) {
531 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
532 new_map[i].data.configs.group_or_pin =
533 pin_get_name(pctldev, grp->pins[i]);
534 new_map[i].data.configs.configs = grp->data[i].configs;
535 new_map[i].data.configs.num_configs = grp->data[i].nconfigs;
536 }
537
538 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
539 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
540
541 return 0;
542}
543
544static void rockchip_dt_free_map(struct pinctrl_dev *pctldev,
545 struct pinctrl_map *map, unsigned num_maps)
546{
547}
548
549static const struct pinctrl_ops rockchip_pctrl_ops = {
550 .get_groups_count = rockchip_get_groups_count,
551 .get_group_name = rockchip_get_group_name,
552 .get_group_pins = rockchip_get_group_pins,
553 .dt_node_to_map = rockchip_dt_node_to_map,
554 .dt_free_map = rockchip_dt_free_map,
555};
556
557/*
558 * Hardware access
559 */
560
d23c66df
DW		 561static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
562 {
563 .num = 2,
564 .pin = 20,
565 .reg = 0xe8,
566 .bit = 0,
567 .mask = 0x7
568 }, {
569 .num = 2,
570 .pin = 21,
571 .reg = 0xe8,
572 .bit = 4,
573 .mask = 0x7
574 }, {
575 .num = 2,
576 .pin = 22,
577 .reg = 0xe8,
578 .bit = 8,
579 .mask = 0x7
580 }, {
581 .num = 2,
582 .pin = 23,
583 .reg = 0xe8,
584 .bit = 12,
585 .mask = 0x7
586 }, {
587 .num = 2,
588 .pin = 24,
589 .reg = 0xd4,
590 .bit = 12,
591 .mask = 0x7
592 },
593};
594
c04c3fa6 595static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
3818e4a7 596 {
597 .num = 2,
598 .pin = 12,
599 .reg = 0x24,
600 .bit = 8,
601 .mask = 0x3
602 }, {
603 .num = 2,
604 .pin = 15,
605 .reg = 0x28,
606 .bit = 0,
607 .mask = 0x7
608 }, {
609 .num = 2,
610 .pin = 23,
611 .reg = 0x30,
612 .bit = 14,
613 .mask = 0x3
614 },
615};
616
c04c3fa6
DW		 617static void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin,
618 int *reg, u8 *bit, int *mask)
3818e4a7 619{
c04c3fa6
DW		 620 struct rockchip_pinctrl *info = bank->drvdata;
621 struct rockchip_pin_ctrl *ctrl = info->ctrl;
622 struct rockchip_mux_recalced_data *data;
3818e4a7 623 int i;
624
c04c3fa6
DW		 625 for (i = 0; i < ctrl->niomux_recalced; i++) {
626 data = &ctrl->iomux_recalced[i];
627 if (data->num == bank->bank_num &&
628 data->pin == pin)
3818e4a7 629 break;
c04c3fa6 630 }
3818e4a7 631
c04c3fa6 632 if (i >= ctrl->niomux_recalced)
3818e4a7 633 return;
634
635 *reg = data->reg;
636 *mask = data->mask;
637 *bit = data->bit;
638}
639
d23c66df
DW		 640static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
641 {
642 /* spi-0 */
643 .bank_num = 1,
644 .pin = 10,
645 .func = 1,
646 .route_offset = 0x144,
647 .route_val = BIT(16 + 3) | BIT(16 + 4),
648 }, {
649 /* spi-1 */
650 .bank_num = 1,
651 .pin = 27,
652 .func = 3,
653 .route_offset = 0x144,
654 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
655 }, {
656 /* spi-2 */
657 .bank_num = 0,
658 .pin = 13,
659 .func = 2,
660 .route_offset = 0x144,
661 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
662 }, {
663 /* i2s-0 */
664 .bank_num = 1,
665 .pin = 5,
666 .func = 1,
667 .route_offset = 0x144,
668 .route_val = BIT(16 + 5),
669 }, {
670 /* i2s-1 */
671 .bank_num = 0,
672 .pin = 14,
673 .func = 1,
674 .route_offset = 0x144,
675 .route_val = BIT(16 + 5) | BIT(5),
676 }, {
677 /* emmc-0 */
678 .bank_num = 1,
679 .pin = 22,
680 .func = 2,
681 .route_offset = 0x144,
682 .route_val = BIT(16 + 6),
683 }, {
684 /* emmc-1 */
685 .bank_num = 2,
686 .pin = 4,
687 .func = 2,
688 .route_offset = 0x144,
689 .route_val = BIT(16 + 6) | BIT(6),
690 },
691};
692
d4970ee0
DW		 693static struct rockchip_mux_route_data rk3228_mux_route_data[] = {
694 {
695 /* pwm0-0 */
696 .bank_num = 0,
697 .pin = 26,
698 .func = 1,
699 .route_offset = 0x50,
700 .route_val = BIT(16),
701 }, {
702 /* pwm0-1 */
703 .bank_num = 3,
704 .pin = 21,
705 .func = 1,
706 .route_offset = 0x50,
707 .route_val = BIT(16) | BIT(0),
708 }, {
709 /* pwm1-0 */
710 .bank_num = 0,
711 .pin = 27,
712 .func = 1,
713 .route_offset = 0x50,
714 .route_val = BIT(16 + 1),
715 }, {
716 /* pwm1-1 */
717 .bank_num = 0,
718 .pin = 30,
719 .func = 2,
720 .route_offset = 0x50,
721 .route_val = BIT(16 + 1) | BIT(1),
722 }, {
723 /* pwm2-0 */
724 .bank_num = 0,
725 .pin = 28,
726 .func = 1,
727 .route_offset = 0x50,
728 .route_val = BIT(16 + 2),
729 }, {
730 /* pwm2-1 */
731 .bank_num = 1,
732 .pin = 12,
733 .func = 2,
734 .route_offset = 0x50,
735 .route_val = BIT(16 + 2) | BIT(2),
736 }, {
737 /* pwm3-0 */
738 .bank_num = 3,
739 .pin = 26,
740 .func = 1,
741 .route_offset = 0x50,
742 .route_val = BIT(16 + 3),
743 }, {
744 /* pwm3-1 */
745 .bank_num = 1,
746 .pin = 11,
747 .func = 2,
748 .route_offset = 0x50,
749 .route_val = BIT(16 + 3) | BIT(3),
750 }, {
751 /* sdio-0_d0 */
752 .bank_num = 1,
753 .pin = 1,
754 .func = 1,
755 .route_offset = 0x50,
756 .route_val = BIT(16 + 4),
757 }, {
758 /* sdio-1_d0 */
759 .bank_num = 3,
760 .pin = 2,
761 .func = 1,
762 .route_offset = 0x50,
763 .route_val = BIT(16 + 4) | BIT(4),
764 }, {
765 /* spi-0_rx */
766 .bank_num = 0,
767 .pin = 13,
768 .func = 2,
769 .route_offset = 0x50,
770 .route_val = BIT(16 + 5),
771 }, {
772 /* spi-1_rx */
773 .bank_num = 2,
774 .pin = 0,
775 .func = 2,
776 .route_offset = 0x50,
777 .route_val = BIT(16 + 5) | BIT(5),
778 }, {
779 /* emmc-0_cmd */
780 .bank_num = 1,
781 .pin = 22,
782 .func = 2,
783 .route_offset = 0x50,
784 .route_val = BIT(16 + 7),
785 }, {
786 /* emmc-1_cmd */
787 .bank_num = 2,
788 .pin = 4,
789 .func = 2,
790 .route_offset = 0x50,
791 .route_val = BIT(16 + 7) | BIT(7),
792 }, {
793 /* uart2-0_rx */
794 .bank_num = 1,
795 .pin = 19,
796 .func = 2,
797 .route_offset = 0x50,
798 .route_val = BIT(16 + 8),
799 }, {
800 /* uart2-1_rx */
801 .bank_num = 1,
802 .pin = 10,
803 .func = 2,
804 .route_offset = 0x50,
805 .route_val = BIT(16 + 8) | BIT(8),
806 }, {
807 /* uart1-0_rx */
808 .bank_num = 1,
809 .pin = 10,
810 .func = 1,
811 .route_offset = 0x50,
812 .route_val = BIT(16 + 11),
813 }, {
814 /* uart1-1_rx */
815 .bank_num = 3,
816 .pin = 13,
817 .func = 1,
818 .route_offset = 0x50,
819 .route_val = BIT(16 + 11) | BIT(11),
820 },
821};
822
cedc964a
DW		 823static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
824 {
825 /* uart2dbg_rxm0 */
826 .bank_num = 1,
827 .pin = 1,
828 .func = 2,
829 .route_offset = 0x50,
830 .route_val = BIT(16) | BIT(16 + 1),
831 }, {
832 /* uart2dbg_rxm1 */
833 .bank_num = 2,
834 .pin = 1,
835 .func = 1,
836 .route_offset = 0x50,
837 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
838 }, {
839 /* gmac-m1-optimized_rxd0 */
840 .bank_num = 1,
841 .pin = 11,
842 .func = 2,
843 .route_offset = 0x50,
844 .route_val = BIT(16 + 2) | BIT(16 + 10) | BIT(2) | BIT(10),
845 }, {
846 /* pdm_sdi0m0 */
847 .bank_num = 2,
848 .pin = 19,
849 .func = 2,
850 .route_offset = 0x50,
851 .route_val = BIT(16 + 3),
852 }, {
853 /* pdm_sdi0m1 */
854 .bank_num = 1,
855 .pin = 23,
856 .func = 3,
857 .route_offset = 0x50,
858 .route_val = BIT(16 + 3) | BIT(3),
859 }, {
860 /* spi_rxdm2 */
861 .bank_num = 3,
862 .pin = 2,
863 .func = 4,
864 .route_offset = 0x50,
865 .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
866 }, {
867 /* i2s2_sdim0 */
868 .bank_num = 1,
869 .pin = 24,
870 .func = 1,
871 .route_offset = 0x50,
872 .route_val = BIT(16 + 6),
873 }, {
874 /* i2s2_sdim1 */
875 .bank_num = 3,
876 .pin = 2,
877 .func = 6,
878 .route_offset = 0x50,
879 .route_val = BIT(16 + 6) | BIT(6),
880 }, {
881 /* card_iom1 */
882 .bank_num = 2,
883 .pin = 22,
884 .func = 3,
885 .route_offset = 0x50,
886 .route_val = BIT(16 + 7) | BIT(7),
887 }, {
888 /* tsp_d5m1 */
889 .bank_num = 2,
890 .pin = 16,
891 .func = 3,
892 .route_offset = 0x50,
893 .route_val = BIT(16 + 8) | BIT(8),
894 }, {
895 /* cif_data5m1 */
896 .bank_num = 2,
897 .pin = 16,
898 .func = 4,
899 .route_offset = 0x50,
900 .route_val = BIT(16 + 9) | BIT(9),
901 },
902};
903
accc1ce7
DW		 904static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
905 {
906 /* uart2dbga_rx */
907 .bank_num = 4,
908 .pin = 8,
909 .func = 2,
910 .route_offset = 0xe21c,
911 .route_val = BIT(16 + 10) | BIT(16 + 11),
912 }, {
913 /* uart2dbgb_rx */
914 .bank_num = 4,
915 .pin = 16,
916 .func = 2,
917 .route_offset = 0xe21c,
918 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
919 }, {
920 /* uart2dbgc_rx */
921 .bank_num = 4,
922 .pin = 19,
923 .func = 1,
924 .route_offset = 0xe21c,
925 .route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
926 }, {
927 /* pcie_clkreqn */
928 .bank_num = 2,
929 .pin = 26,
930 .func = 2,
931 .route_offset = 0xe21c,
932 .route_val = BIT(16 + 14),
933 }, {
934 /* pcie_clkreqnb */
935 .bank_num = 4,
936 .pin = 24,
937 .func = 1,
938 .route_offset = 0xe21c,
939 .route_val = BIT(16 + 14) | BIT(14),
940 },
941};
942
bd35b9bf
DW		 943static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
944 int mux, u32 *reg, u32 *value)
945{
946 struct rockchip_pinctrl *info = bank->drvdata;
947 struct rockchip_pin_ctrl *ctrl = info->ctrl;
948 struct rockchip_mux_route_data *data;
949 int i;
950
951 for (i = 0; i < ctrl->niomux_routes; i++) {
952 data = &ctrl->iomux_routes[i];
953 if ((data->bank_num == bank->bank_num) &&
954 (data->pin == pin) && (data->func == mux))
955 break;
956 }
957
958 if (i >= ctrl->niomux_routes)
959 return false;
960
961 *reg = data->route_offset;
962 *value = data->route_val;
963
964 return true;
965}
966
a076e2ed
HS		 967static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin)
968{
969 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 970 int iomux_num = (pin / 8);
95ec8ae4 971 struct regmap *regmap;
751a99ab 972 unsigned int val;
ea262ad6 973 int reg, ret, mask, mux_type;
a076e2ed
HS		 974 u8 bit;
975
fc72c923
HS		 976 if (iomux_num > 3)
977 return -EINVAL;
978
62f49226
HS		 979 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
980 dev_err(info->dev, "pin %d is unrouted\n", pin);
981 return -EINVAL;
982 }
983
fc72c923 984 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
a076e2ed
HS		 985 return RK_FUNC_GPIO;
986
95ec8ae4
HS		 987 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
988 ? info->regmap_pmu : info->regmap_base;
989
a076e2ed 990 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 991 mux_type = bank->iomux[iomux_num].type;
6bc0d121 992 reg = bank->iomux[iomux_num].offset;
ea262ad6 993 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 994 if ((pin % 8) >= 4)
995 reg += 0x4;
996 bit = (pin % 4) * 4;
8b6c6f93 997 mask = 0xf;
ea262ad6 998 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 999 if ((pin % 8) >= 5)
1000 reg += 0x4;
1001 bit = (pin % 8 % 5) * 3;
1002 mask = 0x7;
03716e1d
HS		 1003 } else {
1004 bit = (pin % 8) * 2;
8b6c6f93 1005 mask = 0x3;
03716e1d 1006 }
a076e2ed 1007
c04c3fa6
DW		 1008 if (bank->recalced_mask & BIT(pin))
1009 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1010
95ec8ae4 1011 ret = regmap_read(regmap, reg, &val);
751a99ab
HS		 1012 if (ret)
1013 return ret;
1014
03716e1d 1015 return ((val >> bit) & mask);
a076e2ed
HS		 1016}
1017
05709c3e
JK		 1018static int rockchip_verify_mux(struct rockchip_pin_bank *bank,
1019 int pin, int mux)
1020{
1021 struct rockchip_pinctrl *info = bank->drvdata;
1022 int iomux_num = (pin / 8);
1023
1024 if (iomux_num > 3)
1025 return -EINVAL;
1026
1027 if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) {
1028 dev_err(info->dev, "pin %d is unrouted\n", pin);
1029 return -EINVAL;
1030 }
1031
1032 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) {
1033 if (mux != RK_FUNC_GPIO) {
1034 dev_err(info->dev,
1035 "pin %d only supports a gpio mux\n", pin);
1036 return -ENOTSUPP;
1037 }
1038 }
1039
1040 return 0;
1041}
1042
d3e51161
HS		 1043/*
1044 * Set a new mux function for a pin.
1045 *
1046 * The register is divided into the upper and lower 16 bit. When changing
1047 * a value, the previous register value is not read and changed. Instead
1048 * it seems the changed bits are marked in the upper 16 bit, while the
1049 * changed value gets set in the same offset in the lower 16 bit.
1050 * All pin settings seem to be 2 bit wide in both the upper and lower
1051 * parts.
1052 * @bank: pin bank to change
1053 * @pin: pin to change
1054 * @mux: new mux function to set
1055 */
14797189 1056static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
d3e51161
HS		 1057{
1058 struct rockchip_pinctrl *info = bank->drvdata;
fc72c923 1059 int iomux_num = (pin / 8);
95ec8ae4 1060 struct regmap *regmap;
ea262ad6 1061 int reg, ret, mask, mux_type;
d3e51161 1062 u8 bit;
bd35b9bf 1063 u32 data, rmask, route_reg, route_val;
d3e51161 1064
05709c3e
JK		 1065 ret = rockchip_verify_mux(bank, pin, mux);
1066 if (ret < 0)
1067 return ret;
62f49226 1068
05709c3e
JK		 1069 if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY)
1070 return 0;
c4a532de 1071
d3e51161
HS		 1072 dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n",
1073 bank->bank_num, pin, mux);
1074
95ec8ae4
HS		 1075 regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU)
1076 ? info->regmap_pmu : info->regmap_base;
1077
d3e51161 1078 /* get basic quadrupel of mux registers and the correct reg inside */
ea262ad6 1079 mux_type = bank->iomux[iomux_num].type;
6bc0d121 1080 reg = bank->iomux[iomux_num].offset;
ea262ad6 1081 if (mux_type & IOMUX_WIDTH_4BIT) {
03716e1d
HS		 1082 if ((pin % 8) >= 4)
1083 reg += 0x4;
1084 bit = (pin % 4) * 4;
8b6c6f93 1085 mask = 0xf;
ea262ad6 1086 } else if (mux_type & IOMUX_WIDTH_3BIT) {
8b6c6f93 1087 if ((pin % 8) >= 5)
1088 reg += 0x4;
1089 bit = (pin % 8 % 5) * 3;
1090 mask = 0x7;
03716e1d
HS		 1091 } else {
1092 bit = (pin % 8) * 2;
8b6c6f93 1093 mask = 0x3;
03716e1d 1094 }
d3e51161 1095
c04c3fa6
DW		 1096 if (bank->recalced_mask & BIT(pin))
1097 rockchip_get_recalced_mux(bank, pin, &reg, &bit, &mask);
ea262ad6 1098
bd35b9bf
DW		 1099 if (bank->route_mask & BIT(pin)) {
1100 if (rockchip_get_mux_route(bank, pin, mux, &route_reg,
1101 &route_val)) {
1102 ret = regmap_write(regmap, route_reg, route_val);
1103 if (ret)
1104 return ret;
1105 }
1106 }
1107
03716e1d 1108 data = (mask << (bit + 16));
99e872d9 1109 rmask = data | (data >> 16);
03716e1d 1110 data |= (mux & mask) << bit;
99e872d9 1111 ret = regmap_update_bits(regmap, reg, rmask, data);
d3e51161 1112
751a99ab 1113 return ret;
d3e51161
HS		 1114}
1115
b9c6dcab
AY		 1116#define RV1108_PULL_PMU_OFFSET 0x10
1117#define RV1108_PULL_OFFSET 0x110
1118#define RV1108_PULL_PINS_PER_REG 8
1119#define RV1108_PULL_BITS_PER_PIN 2
1120#define RV1108_PULL_BANK_STRIDE 16
688daf23 1121
b9c6dcab 1122static void rv1108_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1123 int pin_num, struct regmap **regmap,
1124 int *reg, u8 *bit)
1125{
1126 struct rockchip_pinctrl *info = bank->drvdata;
1127
1128 /* The first 24 pins of the first bank are located in PMU */
1129 if (bank->bank_num == 0) {
1130 *regmap = info->regmap_pmu;
b9c6dcab 1131 *reg = RV1108_PULL_PMU_OFFSET;
688daf23 1132 } else {
b9c6dcab 1133 *reg = RV1108_PULL_OFFSET;
688daf23
AY		 1134 *regmap = info->regmap_base;
1135 /* correct the offset, as we're starting with the 2nd bank */
1136 *reg -= 0x10;
b9c6dcab 1137 *reg += bank->bank_num * RV1108_PULL_BANK_STRIDE;
688daf23
AY		 1138 }
1139
b9c6dcab
AY		 1140 *reg += ((pin_num / RV1108_PULL_PINS_PER_REG) * 4);
1141 *bit = (pin_num % RV1108_PULL_PINS_PER_REG);
1142 *bit *= RV1108_PULL_BITS_PER_PIN;
688daf23
AY		 1143}
1144
b9c6dcab
AY		 1145#define RV1108_DRV_PMU_OFFSET 0x20
1146#define RV1108_DRV_GRF_OFFSET 0x210
1147#define RV1108_DRV_BITS_PER_PIN 2
1148#define RV1108_DRV_PINS_PER_REG 8
1149#define RV1108_DRV_BANK_STRIDE 16
688daf23 1150
b9c6dcab 1151static void rv1108_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
688daf23
AY		 1152 int pin_num, struct regmap **regmap,
1153 int *reg, u8 *bit)
1154{
1155 struct rockchip_pinctrl *info = bank->drvdata;
1156
1157 /* The first 24 pins of the first bank are located in PMU */
1158 if (bank->bank_num == 0) {
1159 *regmap = info->regmap_pmu;
b9c6dcab 1160 *reg = RV1108_DRV_PMU_OFFSET;
688daf23
AY		 1161 } else {
1162 *regmap = info->regmap_base;
b9c6dcab 1163 *reg = RV1108_DRV_GRF_OFFSET;
688daf23
AY		 1164
1165 /* correct the offset, as we're starting with the 2nd bank */
1166 *reg -= 0x10;
b9c6dcab 1167 *reg += bank->bank_num * RV1108_DRV_BANK_STRIDE;
688daf23
AY		 1168 }
1169
b9c6dcab
AY		 1170 *reg += ((pin_num / RV1108_DRV_PINS_PER_REG) * 4);
1171 *bit = pin_num % RV1108_DRV_PINS_PER_REG;
1172 *bit *= RV1108_DRV_BITS_PER_PIN;
688daf23
AY		 1173}
1174
a282926d
HS		 1175#define RK2928_PULL_OFFSET 0x118
1176#define RK2928_PULL_PINS_PER_REG 16
1177#define RK2928_PULL_BANK_STRIDE 8
1178
1179static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1180 int pin_num, struct regmap **regmap,
1181 int *reg, u8 *bit)
a282926d
HS		 1182{
1183 struct rockchip_pinctrl *info = bank->drvdata;
1184
751a99ab
HS		 1185 *regmap = info->regmap_base;
1186 *reg = RK2928_PULL_OFFSET;
a282926d
HS		 1187 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1188 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
1189
1190 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1191};
1192
d23c66df
DW		 1193#define RK3128_PULL_OFFSET 0x118
1194
1195static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1196 int pin_num, struct regmap **regmap,
1197 int *reg, u8 *bit)
1198{
1199 struct rockchip_pinctrl *info = bank->drvdata;
1200
1201 *regmap = info->regmap_base;
1202 *reg = RK3128_PULL_OFFSET;
1203 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
1204 *reg += ((pin_num / RK2928_PULL_PINS_PER_REG) * 4);
1205
1206 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
1207}
1208
bfc7a42a 1209#define RK3188_PULL_OFFSET 0x164
6ca5274d
HS		 1210#define RK3188_PULL_BITS_PER_PIN 2
1211#define RK3188_PULL_PINS_PER_REG 8
1212#define RK3188_PULL_BANK_STRIDE 16
14dee867 1213#define RK3188_PULL_PMU_OFFSET 0x64
6ca5274d
HS		 1214
1215static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
751a99ab
HS		 1216 int pin_num, struct regmap **regmap,
1217 int *reg, u8 *bit)
6ca5274d
HS		 1218{
1219 struct rockchip_pinctrl *info = bank->drvdata;
1220
1221 /* The first 12 pins of the first bank are located elsewhere */
fc72c923 1222 if (bank->bank_num == 0 && pin_num < 12) {
14dee867
HS		 1223 *regmap = info->regmap_pmu ? info->regmap_pmu
1224 : bank->regmap_pull;
1225 *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0;
751a99ab 1226 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
6ca5274d
HS		 1227 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1228 *bit *= RK3188_PULL_BITS_PER_PIN;
1229 } else {
751a99ab
HS		 1230 *regmap = info->regmap_pull ? info->regmap_pull
1231 : info->regmap_base;
1232 *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET;
1233
bfc7a42a
HS		 1234 /* correct the offset, as it is the 2nd pull register */
1235 *reg -= 4;
6ca5274d
HS		 1236 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1237 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1238
1239 /*
1240 * The bits in these registers have an inverse ordering
1241 * with the lowest pin being in bits 15:14 and the highest
1242 * pin in bits 1:0
1243 */
1244 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
1245 *bit *= RK3188_PULL_BITS_PER_PIN;
1246 }
1247}
1248
304f077d
HS		 1249#define RK3288_PULL_OFFSET 0x140
1250static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1251 int pin_num, struct regmap **regmap,
1252 int *reg, u8 *bit)
1253{
1254 struct rockchip_pinctrl *info = bank->drvdata;
1255
1256 /* The first 24 pins of the first bank are located in PMU */
1257 if (bank->bank_num == 0) {
1258 *regmap = info->regmap_pmu;
1259 *reg = RK3188_PULL_PMU_OFFSET;
1260
1261 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1262 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1263 *bit *= RK3188_PULL_BITS_PER_PIN;
1264 } else {
1265 *regmap = info->regmap_base;
1266 *reg = RK3288_PULL_OFFSET;
1267
1268 /* correct the offset, as we're starting with the 2nd bank */
1269 *reg -= 0x10;
1270 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1271 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1272
1273 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1274 *bit *= RK3188_PULL_BITS_PER_PIN;
1275 }
1276}
1277
b547c800
HS		 1278#define RK3288_DRV_PMU_OFFSET 0x70
1279#define RK3288_DRV_GRF_OFFSET 0x1c0
1280#define RK3288_DRV_BITS_PER_PIN 2
1281#define RK3288_DRV_PINS_PER_REG 8
1282#define RK3288_DRV_BANK_STRIDE 16
b547c800
HS		 1283
1284static void rk3288_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1285 int pin_num, struct regmap **regmap,
1286 int *reg, u8 *bit)
1287{
1288 struct rockchip_pinctrl *info = bank->drvdata;
1289
1290 /* The first 24 pins of the first bank are located in PMU */
1291 if (bank->bank_num == 0) {
1292 *regmap = info->regmap_pmu;
1293 *reg = RK3288_DRV_PMU_OFFSET;
1294
1295 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1296 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1297 *bit *= RK3288_DRV_BITS_PER_PIN;
1298 } else {
1299 *regmap = info->regmap_base;
1300 *reg = RK3288_DRV_GRF_OFFSET;
1301
1302 /* correct the offset, as we're starting with the 2nd bank */
1303 *reg -= 0x10;
1304 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1305 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1306
1307 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1308 *bit *= RK3288_DRV_BITS_PER_PIN;
1309 }
1310}
1311
fea0fe60
JC		 1312#define RK3228_PULL_OFFSET 0x100
1313
1314static void rk3228_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1315 int pin_num, struct regmap **regmap,
1316 int *reg, u8 *bit)
1317{
1318 struct rockchip_pinctrl *info = bank->drvdata;
1319
1320 *regmap = info->regmap_base;
1321 *reg = RK3228_PULL_OFFSET;
1322 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1323 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1324
1325 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1326 *bit *= RK3188_PULL_BITS_PER_PIN;
1327}
1328
1329#define RK3228_DRV_GRF_OFFSET 0x200
1330
1331static void rk3228_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1332 int pin_num, struct regmap **regmap,
1333 int *reg, u8 *bit)
1334{
1335 struct rockchip_pinctrl *info = bank->drvdata;
1336
1337 *regmap = info->regmap_base;
1338 *reg = RK3228_DRV_GRF_OFFSET;
1339 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1340 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1341
1342 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1343 *bit *= RK3288_DRV_BITS_PER_PIN;
1344}
1345
daecdc66
HS		 1346#define RK3368_PULL_GRF_OFFSET 0x100
1347#define RK3368_PULL_PMU_OFFSET 0x10
1348
1349static void rk3368_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1350 int pin_num, struct regmap **regmap,
1351 int *reg, u8 *bit)
1352{
1353 struct rockchip_pinctrl *info = bank->drvdata;
1354
1355 /* The first 32 pins of the first bank are located in PMU */
1356 if (bank->bank_num == 0) {
1357 *regmap = info->regmap_pmu;
1358 *reg = RK3368_PULL_PMU_OFFSET;
1359
1360 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1361 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1362 *bit *= RK3188_PULL_BITS_PER_PIN;
1363 } else {
1364 *regmap = info->regmap_base;
1365 *reg = RK3368_PULL_GRF_OFFSET;
1366
1367 /* correct the offset, as we're starting with the 2nd bank */
1368 *reg -= 0x10;
1369 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1370 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1371
1372 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1373 *bit *= RK3188_PULL_BITS_PER_PIN;
1374 }
1375}
1376
1377#define RK3368_DRV_PMU_OFFSET 0x20
1378#define RK3368_DRV_GRF_OFFSET 0x200
1379
1380static void rk3368_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1381 int pin_num, struct regmap **regmap,
1382 int *reg, u8 *bit)
1383{
1384 struct rockchip_pinctrl *info = bank->drvdata;
1385
1386 /* The first 32 pins of the first bank are located in PMU */
1387 if (bank->bank_num == 0) {
1388 *regmap = info->regmap_pmu;
1389 *reg = RK3368_DRV_PMU_OFFSET;
1390
1391 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1392 *bit = pin_num % RK3288_DRV_PINS_PER_REG;
1393 *bit *= RK3288_DRV_BITS_PER_PIN;
1394 } else {
1395 *regmap = info->regmap_base;
1396 *reg = RK3368_DRV_GRF_OFFSET;
1397
1398 /* correct the offset, as we're starting with the 2nd bank */
1399 *reg -= 0x10;
1400 *reg += bank->bank_num * RK3288_DRV_BANK_STRIDE;
1401 *reg += ((pin_num / RK3288_DRV_PINS_PER_REG) * 4);
1402
1403 *bit = (pin_num % RK3288_DRV_PINS_PER_REG);
1404 *bit *= RK3288_DRV_BITS_PER_PIN;
1405 }
1406}
1407
b6c23275
DW		 1408#define RK3399_PULL_GRF_OFFSET 0xe040
1409#define RK3399_PULL_PMU_OFFSET 0x40
1410#define RK3399_DRV_3BITS_PER_PIN 3
1411
1412static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
1413 int pin_num, struct regmap **regmap,
1414 int *reg, u8 *bit)
1415{
1416 struct rockchip_pinctrl *info = bank->drvdata;
1417
1418 /* The bank0:16 and bank1:32 pins are located in PMU */
1419 if ((bank->bank_num == 0) || (bank->bank_num == 1)) {
1420 *regmap = info->regmap_pmu;
1421 *reg = RK3399_PULL_PMU_OFFSET;
1422
1423 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1424
1425 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1426 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
1427 *bit *= RK3188_PULL_BITS_PER_PIN;
1428 } else {
1429 *regmap = info->regmap_base;
1430 *reg = RK3399_PULL_GRF_OFFSET;
1431
1432 /* correct the offset, as we're starting with the 3rd bank */
1433 *reg -= 0x20;
1434 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
1435 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
1436
1437 *bit = (pin_num % RK3188_PULL_PINS_PER_REG);
1438 *bit *= RK3188_PULL_BITS_PER_PIN;
1439 }
1440}
1441
1442static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
1443 int pin_num, struct regmap **regmap,
1444 int *reg, u8 *bit)
1445{
1446 struct rockchip_pinctrl *info = bank->drvdata;
1447 int drv_num = (pin_num / 8);
1448
1449 /* The bank0:16 and bank1:32 pins are located in PMU */
1450 if ((bank->bank_num == 0) || (bank->bank_num == 1))
1451 *regmap = info->regmap_pmu;
1452 else
1453 *regmap = info->regmap_base;
1454
1455 *reg = bank->drv[drv_num].offset;
1456 if ((bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
1457 (bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY))
1458 *bit = (pin_num % 8) * 3;
1459 else
1460 *bit = (pin_num % 8) * 2;
1461}
1462
1463static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
1464 { 2, 4, 8, 12, -1, -1, -1, -1 },
1465 { 3, 6, 9, 12, -1, -1, -1, -1 },
1466 { 5, 10, 15, 20, -1, -1, -1, -1 },
1467 { 4, 6, 8, 10, 12, 14, 16, 18 },
1468 { 4, 7, 10, 13, 16, 19, 22, 26 }
1469};
ef17f69f
HS		 1470
1471static int rockchip_get_drive_perpin(struct rockchip_pin_bank *bank,
1472 int pin_num)
b547c800 1473{
ef17f69f
HS		 1474 struct rockchip_pinctrl *info = bank->drvdata;
1475 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800
HS		 1476 struct regmap *regmap;
1477 int reg, ret;
b6c23275 1478 u32 data, temp, rmask_bits;
b547c800 1479 u8 bit;
b6c23275 1480 int drv_type = bank->drv[pin_num / 8].drv_type;
b547c800 1481
ef17f69f 1482 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800 1483
b6c23275
DW		 1484 switch (drv_type) {
1485 case DRV_TYPE_IO_1V8_3V0_AUTO:
1486 case DRV_TYPE_IO_3V3_ONLY:
1487 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1488 switch (bit) {
1489 case 0 ... 12:
1490 /* regular case, nothing to do */
1491 break;
1492 case 15:
1493 /*
1494 * drive-strength offset is special, as it is
1495 * spread over 2 registers
1496 */
1497 ret = regmap_read(regmap, reg, &data);
1498 if (ret)
1499 return ret;
1500
1501 ret = regmap_read(regmap, reg + 0x4, &temp);
1502 if (ret)
1503 return ret;
1504
1505 /*
1506 * the bit data[15] contains bit 0 of the value
1507 * while temp[1:0] contains bits 2 and 1
1508 */
1509 data >>= 15;
1510 temp &= 0x3;
1511 temp <<= 1;
1512 data |= temp;
1513
1514 return rockchip_perpin_drv_list[drv_type][data];
1515 case 18 ... 21:
1516 /* setting fully enclosed in the second register */
1517 reg += 4;
1518 bit -= 16;
1519 break;
1520 default:
1521 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1522 bit, drv_type);
1523 return -EINVAL;
1524 }
1525
1526 break;
1527 case DRV_TYPE_IO_DEFAULT:
1528 case DRV_TYPE_IO_1V8_OR_3V0:
1529 case DRV_TYPE_IO_1V8_ONLY:
1530 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1531 break;
1532 default:
1533 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1534 drv_type);
1535 return -EINVAL;
1536 }
1537
b547c800
HS		 1538 ret = regmap_read(regmap, reg, &data);
1539 if (ret)
1540 return ret;
1541
1542 data >>= bit;
b6c23275 1543 data &= (1 << rmask_bits) - 1;
b547c800 1544
b6c23275 1545 return rockchip_perpin_drv_list[drv_type][data];
b547c800
HS		 1546}
1547
ef17f69f
HS		 1548static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
1549 int pin_num, int strength)
b547c800
HS		 1550{
1551 struct rockchip_pinctrl *info = bank->drvdata;
ef17f69f 1552 struct rockchip_pin_ctrl *ctrl = info->ctrl;
b547c800 1553 struct regmap *regmap;
b547c800 1554 int reg, ret, i;
b6c23275 1555 u32 data, rmask, rmask_bits, temp;
b547c800 1556 u8 bit;
b6c23275
DW		 1557 int drv_type = bank->drv[pin_num / 8].drv_type;
1558
1559 dev_dbg(info->dev, "setting drive of GPIO%d-%d to %d\n",
1560 bank->bank_num, pin_num, strength);
b547c800 1561
ef17f69f 1562 ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
b547c800
HS		 1563
1564 ret = -EINVAL;
b6c23275
DW		 1565 for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
1566 if (rockchip_perpin_drv_list[drv_type][i] == strength) {
b547c800
HS		 1567 ret = i;
1568 break;
b6c23275
DW		 1569 } else if (rockchip_perpin_drv_list[drv_type][i] < 0) {
1570 ret = rockchip_perpin_drv_list[drv_type][i];
1571 break;
b547c800
HS		 1572 }
1573 }
1574
1575 if (ret < 0) {
1576 dev_err(info->dev, "unsupported driver strength %d\n",
1577 strength);
1578 return ret;
1579 }
1580
b6c23275
DW		 1581 switch (drv_type) {
1582 case DRV_TYPE_IO_1V8_3V0_AUTO:
1583 case DRV_TYPE_IO_3V3_ONLY:
1584 rmask_bits = RK3399_DRV_3BITS_PER_PIN;
1585 switch (bit) {
1586 case 0 ... 12:
1587 /* regular case, nothing to do */
1588 break;
1589 case 15:
1590 /*
1591 * drive-strength offset is special, as it is spread
1592 * over 2 registers, the bit data[15] contains bit 0
1593 * of the value while temp[1:0] contains bits 2 and 1
1594 */
1595 data = (ret & 0x1) << 15;
1596 temp = (ret >> 0x1) & 0x3;
1597
1598 rmask = BIT(15) | BIT(31);
1599 data |= BIT(31);
1600 ret = regmap_update_bits(regmap, reg, rmask, data);
f07bedc3 1601 if (ret)
b6c23275 1602 return ret;
b6c23275
DW		 1603
1604 rmask = 0x3 | (0x3 << 16);
1605 temp |= (0x3 << 16);
1606 reg += 0x4;
1607 ret = regmap_update_bits(regmap, reg, rmask, temp);
1608
b6c23275
DW		 1609 return ret;
1610 case 18 ... 21:
1611 /* setting fully enclosed in the second register */
1612 reg += 4;
1613 bit -= 16;
1614 break;
1615 default:
b6c23275
DW		 1616 dev_err(info->dev, "unsupported bit: %d for pinctrl drive type: %d\n",
1617 bit, drv_type);
1618 return -EINVAL;
1619 }
1620 break;
1621 case DRV_TYPE_IO_DEFAULT:
1622 case DRV_TYPE_IO_1V8_OR_3V0:
1623 case DRV_TYPE_IO_1V8_ONLY:
1624 rmask_bits = RK3288_DRV_BITS_PER_PIN;
1625 break;
1626 default:
b6c23275
DW		 1627 dev_err(info->dev, "unsupported pinctrl drive type: %d\n",
1628 drv_type);
1629 return -EINVAL;
1630 }
1631
b547c800 1632 /* enable the write to the equivalent lower bits */
b6c23275 1633 data = ((1 << rmask_bits) - 1) << (bit + 16);
99e872d9 1634 rmask = data | (data >> 16);
b547c800
HS		 1635 data |= (ret << bit);
1636
99e872d9 1637 ret = regmap_update_bits(regmap, reg, rmask, data);
b547c800
HS		 1638
1639 return ret;
1640}
1641
3ba6767a
DW		 1642static int rockchip_pull_list[PULL_TYPE_MAX][4] = {
1643 {
1644 PIN_CONFIG_BIAS_DISABLE,
1645 PIN_CONFIG_BIAS_PULL_UP,
1646 PIN_CONFIG_BIAS_PULL_DOWN,
1647 PIN_CONFIG_BIAS_BUS_HOLD
1648 },
1649 {
1650 PIN_CONFIG_BIAS_DISABLE,
1651 PIN_CONFIG_BIAS_PULL_DOWN,
1652 PIN_CONFIG_BIAS_DISABLE,
1653 PIN_CONFIG_BIAS_PULL_UP
1654 },
1655};
1656
d3e51161
HS		 1657static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
1658{
1659 struct rockchip_pinctrl *info = bank->drvdata;
1660 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1661 struct regmap *regmap;
3ba6767a 1662 int reg, ret, pull_type;
d3e51161 1663 u8 bit;
6ca5274d 1664 u32 data;
d3e51161
HS		 1665
1666 /* rk3066b does support any pulls */
a282926d 1667 if (ctrl->type == RK3066B)
d3e51161
HS		 1668 return PIN_CONFIG_BIAS_DISABLE;
1669
751a99ab
HS		 1670 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1671
1672 ret = regmap_read(regmap, reg, &data);
1673 if (ret)
1674 return ret;
6ca5274d 1675
a282926d
HS		 1676 switch (ctrl->type) {
1677 case RK2928:
d23c66df 1678 case RK3128:
751a99ab 1679 return !(data & BIT(bit))
d3e51161
HS		 1680 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
1681 : PIN_CONFIG_BIAS_DISABLE;
b9c6dcab 1682 case RV1108:
a282926d 1683 case RK3188:
66d750e1 1684 case RK3288:
daecdc66 1685 case RK3368:
b6c23275 1686 case RK3399:
3ba6767a 1687 pull_type = bank->pull_type[pin_num / 8];
751a99ab 1688 data >>= bit;
6ca5274d
HS		 1689 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
1690
3ba6767a 1691 return rockchip_pull_list[pull_type][data];
a282926d
HS		 1692 default:
1693 dev_err(info->dev, "unsupported pinctrl type\n");
1694 return -EINVAL;
1695 };
d3e51161
HS		 1696}
1697
1698static int rockchip_set_pull(struct rockchip_pin_bank *bank,
1699 int pin_num, int pull)
1700{
1701 struct rockchip_pinctrl *info = bank->drvdata;
1702 struct rockchip_pin_ctrl *ctrl = info->ctrl;
751a99ab 1703 struct regmap *regmap;
3ba6767a 1704 int reg, ret, i, pull_type;
d3e51161 1705 u8 bit;
99e872d9 1706 u32 data, rmask;
d3e51161
HS		 1707
1708 dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n",
1709 bank->bank_num, pin_num, pull);
1710
1711 /* rk3066b does support any pulls */
a282926d 1712 if (ctrl->type == RK3066B)
d3e51161
HS		 1713 return pull ? -EINVAL : 0;
1714
751a99ab 1715 ctrl->pull_calc_reg(bank, pin_num, &regmap, &reg, &bit);
6ca5274d 1716
a282926d
HS		 1717 switch (ctrl->type) {
1718 case RK2928:
d23c66df 1719 case RK3128:
d3e51161
HS		 1720 data = BIT(bit + 16);
1721 if (pull == PIN_CONFIG_BIAS_DISABLE)
1722 data |= BIT(bit);
751a99ab 1723 ret = regmap_write(regmap, reg, data);
a282926d 1724 break;
b9c6dcab 1725 case RV1108:
a282926d 1726 case RK3188:
66d750e1 1727 case RK3288:
daecdc66 1728 case RK3368:
b6c23275 1729 case RK3399:
3ba6767a
DW		 1730 pull_type = bank->pull_type[pin_num / 8];
1731 ret = -EINVAL;
1732 for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
1733 i++) {
1734 if (rockchip_pull_list[pull_type][i] == pull) {
1735 ret = i;
1736 break;
1737 }
1738 }
1739
1740 if (ret < 0) {
1741 dev_err(info->dev, "unsupported pull setting %d\n",
1742 pull);
1743 return ret;
1744 }
1745
6ca5274d
HS		 1746 /* enable the write to the equivalent lower bits */
1747 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
99e872d9 1748 rmask = data | (data >> 16);
3ba6767a 1749 data |= (ret << bit);
6ca5274d 1750
99e872d9 1751 ret = regmap_update_bits(regmap, reg, rmask, data);
6ca5274d 1752 break;
a282926d
HS		 1753 default:
1754 dev_err(info->dev, "unsupported pinctrl type\n");
1755 return -EINVAL;
d3e51161
HS		 1756 }
1757
751a99ab 1758 return ret;
d3e51161
HS		 1759}
1760
728d3f5a 1761#define RK3328_SCHMITT_BITS_PER_PIN 1
1762#define RK3328_SCHMITT_PINS_PER_REG 16
1763#define RK3328_SCHMITT_BANK_STRIDE 8
1764#define RK3328_SCHMITT_GRF_OFFSET 0x380
1765
1766static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
1767 int pin_num,
1768 struct regmap **regmap,
1769 int *reg, u8 *bit)
1770{
1771 struct rockchip_pinctrl *info = bank->drvdata;
1772
1773 *regmap = info->regmap_base;
1774 *reg = RK3328_SCHMITT_GRF_OFFSET;
1775
1776 *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
1777 *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
1778 *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
1779
1780 return 0;
1781}
1782
e3b357d7 1783static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
1784{
1785 struct rockchip_pinctrl *info = bank->drvdata;
1786 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1787 struct regmap *regmap;
1788 int reg, ret;
1789 u8 bit;
1790 u32 data;
1791
1792 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1793 if (ret)
1794 return ret;
1795
1796 ret = regmap_read(regmap, reg, &data);
1797 if (ret)
1798 return ret;
1799
1800 data >>= bit;
1801 return data & 0x1;
1802}
1803
1804static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
1805 int pin_num, int enable)
1806{
1807 struct rockchip_pinctrl *info = bank->drvdata;
1808 struct rockchip_pin_ctrl *ctrl = info->ctrl;
1809 struct regmap *regmap;
1810 int reg, ret;
e3b357d7 1811 u8 bit;
1812 u32 data, rmask;
1813
1814 dev_dbg(info->dev, "setting input schmitt of GPIO%d-%d to %d\n",
1815 bank->bank_num, pin_num, enable);
1816
1817 ret = ctrl->schmitt_calc_reg(bank, pin_num, &regmap, &reg, &bit);
1818 if (ret)
1819 return ret;
1820
e3b357d7 1821 /* enable the write to the equivalent lower bits */
1822 data = BIT(bit + 16) | (enable << bit);
1823 rmask = BIT(bit + 16) | BIT(bit);
1824
f07bedc3 1825 return regmap_update_bits(regmap, reg, rmask, data);
e3b357d7 1826}
1827
d3e51161
HS		 1828/*
1829 * Pinmux_ops handling
1830 */
1831
1832static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
1833{
1834 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1835
1836 return info->nfunctions;
1837}
1838
1839static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev,
1840 unsigned selector)
1841{
1842 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1843
1844 return info->functions[selector].name;
1845}
1846
1847static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev,
1848 unsigned selector, const char * const **groups,
1849 unsigned * const num_groups)
1850{
1851 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1852
1853 *groups = info->functions[selector].groups;
1854 *num_groups = info->functions[selector].ngroups;
1855
1856 return 0;
1857}
1858
03e9f0ca
LW		 1859static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
1860 unsigned group)
d3e51161
HS		 1861{
1862 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1863 const unsigned int *pins = info->groups[group].pins;
1864 const struct rockchip_pin_config *data = info->groups[group].data;
1865 struct rockchip_pin_bank *bank;
14797189 1866 int cnt, ret = 0;
d3e51161
HS		 1867
1868 dev_dbg(info->dev, "enable function %s group %s\n",
1869 info->functions[selector].name, info->groups[group].name);
1870
1871 /*
1872 * for each pin in the pin group selected, program the correspoding pin
1873 * pin function number in the config register.
1874 */
1875 for (cnt = 0; cnt < info->groups[group].npins; cnt++) {
1876 bank = pin_to_bank(info, pins[cnt]);
14797189
HS		 1877 ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base,
1878 data[cnt].func);
1879 if (ret)
1880 break;
1881 }
1882
1883 if (ret) {
1884 /* revert the already done pin settings */
1885 for (cnt--; cnt >= 0; cnt--)
1886 rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0);
1887
1888 return ret;
d3e51161
HS		 1889 }
1890
1891 return 0;
1892}
1893
6ba20a00
CW		 1894static int rockchip_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
1895{
1896 struct rockchip_pin_bank *bank = gpiochip_get_data(chip);
1897 u32 data;
1898
1899 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1900
1901 return !(data & BIT(offset));
1902}
1903
d3e51161
HS		 1904/*
1905 * The calls to gpio_direction_output() and gpio_direction_input()
1906 * leads to this function call (via the pinctrl_gpio_direction_{input|output}()
1907 * function called from the gpiolib interface).
1908 */
e5c2c9db
DA		 1909static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip,
1910 int pin, bool input)
d3e51161 1911{
d3e51161 1912 struct rockchip_pin_bank *bank;
e5c2c9db 1913 int ret;
fab262f5 1914 unsigned long flags;
d3e51161
HS		 1915 u32 data;
1916
03bf81f1 1917 bank = gpiochip_get_data(chip);
d3e51161 1918
14797189
HS		 1919 ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO);
1920 if (ret < 0)
1921 return ret;
d3e51161 1922
07a06ae9 1923 clk_enable(bank->clk);
70b7aa7a 1924 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 1925
d3e51161
HS		 1926 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1927 /* set bit to 1 for output, 0 for input */
1928 if (!input)
1929 data |= BIT(pin);
1930 else
1931 data &= ~BIT(pin);
1932 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1933
70b7aa7a 1934 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 1935 clk_disable(bank->clk);
fab262f5 1936
d3e51161
HS		 1937 return 0;
1938}
1939
e5c2c9db
DA		 1940static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
1941 struct pinctrl_gpio_range *range,
1942 unsigned offset, bool input)
1943{
1944 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1945 struct gpio_chip *chip;
1946 int pin;
1947
1948 chip = range->gc;
1949 pin = offset - chip->base;
1950 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n",
1951 offset, range->name, pin, input ? "input" : "output");
1952
1953 return _rockchip_pmx_gpio_set_direction(chip, offset - chip->base,
1954 input);
1955}
1956
d3e51161
HS		 1957static const struct pinmux_ops rockchip_pmx_ops = {
1958 .get_functions_count = rockchip_pmx_get_funcs_count,
1959 .get_function_name = rockchip_pmx_get_func_name,
1960 .get_function_groups = rockchip_pmx_get_groups,
03e9f0ca 1961 .set_mux = rockchip_pmx_set,
d3e51161
HS		 1962 .gpio_set_direction = rockchip_pmx_gpio_set_direction,
1963};
1964
1965/*
1966 * Pinconf_ops handling
1967 */
1968
44b6d930
HS		 1969static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
1970 enum pin_config_param pull)
1971{
a282926d
HS		 1972 switch (ctrl->type) {
1973 case RK2928:
d23c66df 1974 case RK3128:
a282926d
HS		 1975 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
1976 pull == PIN_CONFIG_BIAS_DISABLE);
1977 case RK3066B:
44b6d930 1978 return pull ? false : true;
b9c6dcab 1979 case RV1108:
a282926d 1980 case RK3188:
66d750e1 1981 case RK3288:
daecdc66 1982 case RK3368:
b6c23275 1983 case RK3399:
a282926d 1984 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
44b6d930
HS		 1985 }
1986
a282926d 1987 return false;
44b6d930
HS		 1988}
1989
e5c2c9db 1990static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
a076e2ed
HS		 1991static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset);
1992
d3e51161
HS		 1993/* set the pin config settings for a specified pin */
1994static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
03b054e9 1995 unsigned long *configs, unsigned num_configs)
d3e51161
HS		 1996{
1997 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1998 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
03b054e9 1999 enum pin_config_param param;
58957d2e 2000 u32 arg;
03b054e9
SY		 2001 int i;
2002 int rc;
2003
2004 for (i = 0; i < num_configs; i++) {
2005 param = pinconf_to_config_param(configs[i]);
2006 arg = pinconf_to_config_argument(configs[i]);
2007
2008 switch (param) {
2009 case PIN_CONFIG_BIAS_DISABLE:
2010 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2011 param);
2012 if (rc)
2013 return rc;
2014 break;
2015 case PIN_CONFIG_BIAS_PULL_UP:
2016 case PIN_CONFIG_BIAS_PULL_DOWN:
2017 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2018 case PIN_CONFIG_BIAS_BUS_HOLD:
03b054e9
SY		 2019 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2020 return -ENOTSUPP;
2021
2022 if (!arg)
2023 return -EINVAL;
2024
2025 rc = rockchip_set_pull(bank, pin - bank->pin_base,
2026 param);
2027 if (rc)
2028 return rc;
2029 break;
a076e2ed 2030 case PIN_CONFIG_OUTPUT:
e5c2c9db
DA		 2031 rockchip_gpio_set(&bank->gpio_chip,
2032 pin - bank->pin_base, arg);
2033 rc = _rockchip_pmx_gpio_set_direction(&bank->gpio_chip,
2034 pin - bank->pin_base, false);
a076e2ed
HS		 2035 if (rc)
2036 return rc;
2037 break;
b547c800
HS		 2038 case PIN_CONFIG_DRIVE_STRENGTH:
2039 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2040 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2041 return -ENOTSUPP;
2042
ef17f69f
HS		 2043 rc = rockchip_set_drive_perpin(bank,
2044 pin - bank->pin_base, arg);
b547c800
HS		 2045 if (rc < 0)
2046 return rc;
2047 break;
e3b357d7 2048 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2049 if (!info->ctrl->schmitt_calc_reg)
2050 return -ENOTSUPP;
2051
2052 rc = rockchip_set_schmitt(bank,
2053 pin - bank->pin_base, arg);
2054 if (rc < 0)
2055 return rc;
2056 break;
03b054e9 2057 default:
44b6d930 2058 return -ENOTSUPP;
03b054e9
SY		 2059 break;
2060 }
2061 } /* for each config */
d3e51161
HS		 2062
2063 return 0;
2064}
2065
2066/* get the pin config settings for a specified pin */
2067static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
2068 unsigned long *config)
2069{
2070 struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
2071 struct rockchip_pin_bank *bank = pin_to_bank(info, pin);
2072 enum pin_config_param param = pinconf_to_config_param(*config);
dab3eba7 2073 u16 arg;
a076e2ed 2074 int rc;
d3e51161
HS		 2075
2076 switch (param) {
2077 case PIN_CONFIG_BIAS_DISABLE:
44b6d930
HS		 2078 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
2079 return -EINVAL;
2080
dab3eba7 2081 arg = 0;
44b6d930 2082 break;
d3e51161
HS		 2083 case PIN_CONFIG_BIAS_PULL_UP:
2084 case PIN_CONFIG_BIAS_PULL_DOWN:
2085 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
6ca5274d 2086 case PIN_CONFIG_BIAS_BUS_HOLD:
44b6d930
HS		 2087 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
2088 return -ENOTSUPP;
d3e51161 2089
44b6d930 2090 if (rockchip_get_pull(bank, pin - bank->pin_base) != param)
d3e51161
HS		 2091 return -EINVAL;
2092
dab3eba7 2093 arg = 1;
d3e51161 2094 break;
a076e2ed
HS		 2095 case PIN_CONFIG_OUTPUT:
2096 rc = rockchip_get_mux(bank, pin - bank->pin_base);
2097 if (rc != RK_FUNC_GPIO)
2098 return -EINVAL;
2099
2100 rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base);
2101 if (rc < 0)
2102 return rc;
2103
2104 arg = rc ? 1 : 0;
2105 break;
b547c800
HS		 2106 case PIN_CONFIG_DRIVE_STRENGTH:
2107 /* rk3288 is the first with per-pin drive-strength */
ef17f69f 2108 if (!info->ctrl->drv_calc_reg)
b547c800
HS		 2109 return -ENOTSUPP;
2110
ef17f69f 2111 rc = rockchip_get_drive_perpin(bank, pin - bank->pin_base);
b547c800
HS		 2112 if (rc < 0)
2113 return rc;
2114
e3b357d7 2115 arg = rc;
2116 break;
2117 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
2118 if (!info->ctrl->schmitt_calc_reg)
2119 return -ENOTSUPP;
2120
2121 rc = rockchip_get_schmitt(bank, pin - bank->pin_base);
2122 if (rc < 0)
2123 return rc;
2124
b547c800
HS		 2125 arg = rc;
2126 break;
d3e51161
HS		 2127 default:
2128 return -ENOTSUPP;
2129 break;
2130 }
2131
dab3eba7
HS		 2132 *config = pinconf_to_config_packed(param, arg);
2133
d3e51161
HS		 2134 return 0;
2135}
2136
2137static const struct pinconf_ops rockchip_pinconf_ops = {
2138 .pin_config_get = rockchip_pinconf_get,
2139 .pin_config_set = rockchip_pinconf_set,
ed62f2f2 2140 .is_generic = true,
d3e51161
HS		 2141};
2142
65fca613
HS		 2143static const struct of_device_id rockchip_bank_match[] = {
2144 { .compatible = "rockchip,gpio-bank" },
6ca5274d 2145 { .compatible = "rockchip,rk3188-gpio-bank0" },
65fca613
HS		 2146 {},
2147};
d3e51161
HS		 2148
2149static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
2150 struct device_node *np)
2151{
2152 struct device_node *child;
2153
2154 for_each_child_of_node(np, child) {
65fca613 2155 if (of_match_node(rockchip_bank_match, child))
d3e51161
HS		 2156 continue;
2157
2158 info->nfunctions++;
2159 info->ngroups += of_get_child_count(child);
2160 }
2161}
2162
2163static int rockchip_pinctrl_parse_groups(struct device_node *np,
2164 struct rockchip_pin_group *grp,
2165 struct rockchip_pinctrl *info,
2166 u32 index)
2167{
2168 struct rockchip_pin_bank *bank;
2169 int size;
2170 const __be32 *list;
2171 int num;
2172 int i, j;
2173 int ret;
2174
2175 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
2176
2177 /* Initialise group */
2178 grp->name = np->name;
2179
2180 /*
2181 * the binding format is rockchip,pins = <bank pin mux CONFIG>,
2182 * do sanity check and calculate pins number
2183 */
2184 list = of_get_property(np, "rockchip,pins", &size);
2185 /* we do not check return since it's safe node passed down */
2186 size /= sizeof(*list);
2187 if (!size || size % 4) {
2188 dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n");
2189 return -EINVAL;
2190 }
2191
2192 grp->npins = size / 4;
2193
2194 grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
2195 GFP_KERNEL);
2196 grp->data = devm_kzalloc(info->dev, grp->npins *
2197 sizeof(struct rockchip_pin_config),
2198 GFP_KERNEL);
2199 if (!grp->pins || !grp->data)
2200 return -ENOMEM;
2201
2202 for (i = 0, j = 0; i < size; i += 4, j++) {
2203 const __be32 *phandle;
2204 struct device_node *np_config;
2205
2206 num = be32_to_cpu(*list++);
2207 bank = bank_num_to_bank(info, num);
2208 if (IS_ERR(bank))
2209 return PTR_ERR(bank);
2210
2211 grp->pins[j] = bank->pin_base + be32_to_cpu(*list++);
2212 grp->data[j].func = be32_to_cpu(*list++);
2213
2214 phandle = list++;
2215 if (!phandle)
2216 return -EINVAL;
2217
2218 np_config = of_find_node_by_phandle(be32_to_cpup(phandle));
dd4d01f7 2219 ret = pinconf_generic_parse_dt_config(np_config, NULL,
d3e51161
HS		 2220 &grp->data[j].configs, &grp->data[j].nconfigs);
2221 if (ret)
2222 return ret;
2223 }
2224
2225 return 0;
2226}
2227
2228static int rockchip_pinctrl_parse_functions(struct device_node *np,
2229 struct rockchip_pinctrl *info,
2230 u32 index)
2231{
2232 struct device_node *child;
2233 struct rockchip_pmx_func *func;
2234 struct rockchip_pin_group *grp;
2235 int ret;
2236 static u32 grp_index;
2237 u32 i = 0;
2238
2239 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
2240
2241 func = &info->functions[index];
2242
2243 /* Initialise function */
2244 func->name = np->name;
2245 func->ngroups = of_get_child_count(np);
2246 if (func->ngroups <= 0)
2247 return 0;
2248
2249 func->groups = devm_kzalloc(info->dev,
2250 func->ngroups * sizeof(char *), GFP_KERNEL);
2251 if (!func->groups)
2252 return -ENOMEM;
2253
2254 for_each_child_of_node(np, child) {
2255 func->groups[i] = child->name;
2256 grp = &info->groups[grp_index++];
2257 ret = rockchip_pinctrl_parse_groups(child, grp, info, i++);
f7a81b7f
JL		 2258 if (ret) {
2259 of_node_put(child);
d3e51161 2260 return ret;
f7a81b7f 2261 }
d3e51161
HS		 2262 }
2263
2264 return 0;
2265}
2266
2267static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
2268 struct rockchip_pinctrl *info)
2269{
2270 struct device *dev = &pdev->dev;
2271 struct device_node *np = dev->of_node;
2272 struct device_node *child;
2273 int ret;
2274 int i;
2275
2276 rockchip_pinctrl_child_count(info, np);
2277
2278 dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
2279 dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups);
2280
2281 info->functions = devm_kzalloc(dev, info->nfunctions *
2282 sizeof(struct rockchip_pmx_func),
2283 GFP_KERNEL);
2284 if (!info->functions) {
2285 dev_err(dev, "failed to allocate memory for function list\n");
2286 return -EINVAL;
2287 }
2288
2289 info->groups = devm_kzalloc(dev, info->ngroups *
2290 sizeof(struct rockchip_pin_group),
2291 GFP_KERNEL);
2292 if (!info->groups) {
2293 dev_err(dev, "failed allocate memory for ping group list\n");
2294 return -EINVAL;
2295 }
2296
2297 i = 0;
2298
2299 for_each_child_of_node(np, child) {
65fca613 2300 if (of_match_node(rockchip_bank_match, child))
d3e51161 2301 continue;
65fca613 2302
d3e51161
HS		 2303 ret = rockchip_pinctrl_parse_functions(child, info, i++);
2304 if (ret) {
2305 dev_err(&pdev->dev, "failed to parse function\n");
f7a81b7f 2306 of_node_put(child);
d3e51161
HS		 2307 return ret;
2308 }
2309 }
2310
2311 return 0;
2312}
2313
2314static int rockchip_pinctrl_register(struct platform_device *pdev,
2315 struct rockchip_pinctrl *info)
2316{
2317 struct pinctrl_desc *ctrldesc = &info->pctl;
2318 struct pinctrl_pin_desc *pindesc, *pdesc;
2319 struct rockchip_pin_bank *pin_bank;
2320 int pin, bank, ret;
2321 int k;
2322
2323 ctrldesc->name = "rockchip-pinctrl";
2324 ctrldesc->owner = THIS_MODULE;
2325 ctrldesc->pctlops = &rockchip_pctrl_ops;
2326 ctrldesc->pmxops = &rockchip_pmx_ops;
2327 ctrldesc->confops = &rockchip_pinconf_ops;
2328
2329 pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) *
2330 info->ctrl->nr_pins, GFP_KERNEL);
2331 if (!pindesc) {
2332 dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n");
2333 return -ENOMEM;
2334 }
2335 ctrldesc->pins = pindesc;
2336 ctrldesc->npins = info->ctrl->nr_pins;
2337
2338 pdesc = pindesc;
2339 for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) {
2340 pin_bank = &info->ctrl->pin_banks[bank];
2341 for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) {
2342 pdesc->number = k;
2343 pdesc->name = kasprintf(GFP_KERNEL, "%s-%d",
2344 pin_bank->name, pin);
2345 pdesc++;
2346 }
2347 }
2348
0fb7dcb1
DA		 2349 ret = rockchip_pinctrl_parse_dt(pdev, info);
2350 if (ret)
2351 return ret;
2352
0085a2b4 2353 info->pctl_dev = devm_pinctrl_register(&pdev->dev, ctrldesc, info);
323de9ef 2354 if (IS_ERR(info->pctl_dev)) {
d3e51161 2355 dev_err(&pdev->dev, "could not register pinctrl driver\n");
323de9ef 2356 return PTR_ERR(info->pctl_dev);
d3e51161
HS		 2357 }
2358
2359 for (bank = 0; bank < info->ctrl->nr_banks; ++bank) {
2360 pin_bank = &info->ctrl->pin_banks[bank];
2361 pin_bank->grange.name = pin_bank->name;
2362 pin_bank->grange.id = bank;
2363 pin_bank->grange.pin_base = pin_bank->pin_base;
2364 pin_bank->grange.base = pin_bank->gpio_chip.base;
2365 pin_bank->grange.npins = pin_bank->gpio_chip.ngpio;
2366 pin_bank->grange.gc = &pin_bank->gpio_chip;
2367 pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange);
2368 }
2369
d3e51161
HS		 2370 return 0;
2371}
2372
2373/*
2374 * GPIO handling
2375 */
2376
2377static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2378{
03bf81f1 2379 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2380 void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR;
2381 unsigned long flags;
2382 u32 data;
2383
07a06ae9 2384 clk_enable(bank->clk);
70b7aa7a 2385 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2386
2387 data = readl(reg);
2388 data &= ~BIT(offset);
2389 if (value)
2390 data |= BIT(offset);
2391 writel(data, reg);
2392
70b7aa7a 2393 raw_spin_unlock_irqrestore(&bank->slock, flags);
07a06ae9 2394 clk_disable(bank->clk);
d3e51161
HS		 2395}
2396
2397/*
2398 * Returns the level of the pin for input direction and setting of the DR
2399 * register for output gpios.
2400 */
2401static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset)
2402{
03bf81f1 2403 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2404 u32 data;
2405
07a06ae9 2406 clk_enable(bank->clk);
d3e51161 2407 data = readl(bank->reg_base + GPIO_EXT_PORT);
07a06ae9 2408 clk_disable(bank->clk);
d3e51161
HS		 2409 data >>= offset;
2410 data &= 1;
2411 return data;
2412}
2413
2414/*
2415 * gpiolib gpio_direction_input callback function. The setting of the pin
2416 * mux function as 'gpio input' will be handled by the pinctrl susbsystem
2417 * interface.
2418 */
2419static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
2420{
2421 return pinctrl_gpio_direction_input(gc->base + offset);
2422}
2423
2424/*
2425 * gpiolib gpio_direction_output callback function. The setting of the pin
2426 * mux function as 'gpio output' will be handled by the pinctrl susbsystem
2427 * interface.
2428 */
2429static int rockchip_gpio_direction_output(struct gpio_chip *gc,
2430 unsigned offset, int value)
2431{
2432 rockchip_gpio_set(gc, offset, value);
2433 return pinctrl_gpio_direction_output(gc->base + offset);
2434}
2435
2436/*
2437 * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin
2438 * and a virtual IRQ, if not already present.
2439 */
2440static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
2441{
03bf81f1 2442 struct rockchip_pin_bank *bank = gpiochip_get_data(gc);
d3e51161
HS		 2443 unsigned int virq;
2444
2445 if (!bank->domain)
2446 return -ENXIO;
2447
2448 virq = irq_create_mapping(bank->domain, offset);
2449
2450 return (virq) ? : -ENXIO;
2451}
2452
2453static const struct gpio_chip rockchip_gpiolib_chip = {
98c85d58
JG		 2454 .request = gpiochip_generic_request,
2455 .free = gpiochip_generic_free,
d3e51161
HS		 2456 .set = rockchip_gpio_set,
2457 .get = rockchip_gpio_get,
6ba20a00 2458 .get_direction = rockchip_gpio_get_direction,
d3e51161
HS		 2459 .direction_input = rockchip_gpio_direction_input,
2460 .direction_output = rockchip_gpio_direction_output,
2461 .to_irq = rockchip_gpio_to_irq,
2462 .owner = THIS_MODULE,
2463};
2464
2465/*
2466 * Interrupt handling
2467 */
2468
bd0b9ac4 2469static void rockchip_irq_demux(struct irq_desc *desc)
d3e51161 2470{
5663bb27
JL		 2471 struct irq_chip *chip = irq_desc_get_chip(desc);
2472 struct rockchip_pin_bank *bank = irq_desc_get_handler_data(desc);
d3e51161
HS		 2473 u32 pend;
2474
2475 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
2476
2477 chained_irq_enter(chip, desc);
2478
2479 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
2480
2481 while (pend) {
415f748c 2482 unsigned int irq, virq;
d3e51161
HS		 2483
2484 irq = __ffs(pend);
2485 pend &= ~BIT(irq);
2486 virq = irq_linear_revmap(bank->domain, irq);
2487
2488 if (!virq) {
2489 dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq);
2490 continue;
2491 }
2492
2493 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
2494
5a927501
HS		 2495 /*
2496 * Triggering IRQ on both rising and falling edge
2497 * needs manual intervention.
2498 */
2499 if (bank->toggle_edge_mode & BIT(irq)) {
53b1bfc7
DA		 2500 u32 data, data_old, polarity;
2501 unsigned long flags;
2502
2503 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
2504 do {
70b7aa7a 2505 raw_spin_lock_irqsave(&bank->slock, flags);
53b1bfc7
DA		 2506
2507 polarity = readl_relaxed(bank->reg_base +
2508 GPIO_INT_POLARITY);
2509 if (data & BIT(irq))
2510 polarity &= ~BIT(irq);
2511 else
2512 polarity |= BIT(irq);
2513 writel(polarity,
2514 bank->reg_base + GPIO_INT_POLARITY);
2515
70b7aa7a 2516 raw_spin_unlock_irqrestore(&bank->slock, flags);
53b1bfc7
DA		 2517
2518 data_old = data;
2519 data = readl_relaxed(bank->reg_base +
2520 GPIO_EXT_PORT);
2521 } while ((data & BIT(irq)) != (data_old & BIT(irq)));
5a927501
HS		 2522 }
2523
d3e51161
HS		 2524 generic_handle_irq(virq);
2525 }
2526
2527 chained_irq_exit(chip, desc);
2528}
2529
2530static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
2531{
2532 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2533 struct rockchip_pin_bank *bank = gc->private;
2534 u32 mask = BIT(d->hwirq);
2535 u32 polarity;
2536 u32 level;
2537 u32 data;
fab262f5 2538 unsigned long flags;
14797189 2539 int ret;
d3e51161 2540
5a927501 2541 /* make sure the pin is configured as gpio input */
1d80df93 2542 ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
14797189
HS		 2543 if (ret < 0)
2544 return ret;
2545
1d80df93 2546 clk_enable(bank->clk);
70b7aa7a 2547 raw_spin_lock_irqsave(&bank->slock, flags);
fab262f5 2548
5a927501
HS		 2549 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
2550 data &= ~mask;
2551 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
2552
70b7aa7a 2553 raw_spin_unlock_irqrestore(&bank->slock, flags);
fab262f5 2554
d3e51161 2555 if (type & IRQ_TYPE_EDGE_BOTH)
2dbf1bc5 2556 irq_set_handler_locked(d, handle_edge_irq);
d3e51161 2557 else
2dbf1bc5 2558 irq_set_handler_locked(d, handle_level_irq);
d3e51161 2559
70b7aa7a 2560 raw_spin_lock_irqsave(&bank->slock, flags);
d3e51161
HS		 2561 irq_gc_lock(gc);
2562
2563 level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL);
2564 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
2565
2566 switch (type) {
5a927501
HS		 2567 case IRQ_TYPE_EDGE_BOTH:
2568 bank->toggle_edge_mode |= mask;
2569 level |= mask;
2570
2571 /*
2572 * Determine gpio state. If 1 next interrupt should be falling
2573 * otherwise rising.
2574 */
2575 data = readl(bank->reg_base + GPIO_EXT_PORT);
2576 if (data & mask)
2577 polarity &= ~mask;
2578 else
2579 polarity |= mask;
2580 break;
d3e51161 2581 case IRQ_TYPE_EDGE_RISING:
5a927501 2582 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2583 level |= mask;
2584 polarity |= mask;
2585 break;
2586 case IRQ_TYPE_EDGE_FALLING:
5a927501 2587 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2588 level |= mask;
2589 polarity &= ~mask;
2590 break;
2591 case IRQ_TYPE_LEVEL_HIGH:
5a927501 2592 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2593 level &= ~mask;
2594 polarity |= mask;
2595 break;
2596 case IRQ_TYPE_LEVEL_LOW:
5a927501 2597 bank->toggle_edge_mode &= ~mask;
d3e51161
HS		 2598 level &= ~mask;
2599 polarity &= ~mask;
2600 break;
2601 default:
7cc5f970 2602 irq_gc_unlock(gc);
70b7aa7a 2603 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2604 clk_disable(bank->clk);
d3e51161
HS		 2605 return -EINVAL;
2606 }
2607
2608 writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL);
2609 writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY);
2610
2611 irq_gc_unlock(gc);
70b7aa7a 2612 raw_spin_unlock_irqrestore(&bank->slock, flags);
1d80df93 2613 clk_disable(bank->clk);
d3e51161 2614
d3e51161
HS		 2615 return 0;
2616}
2617
68bda47c
DA		 2618static void rockchip_irq_suspend(struct irq_data *d)
2619{
2620 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2621 struct rockchip_pin_bank *bank = gc->private;
2622
07a06ae9 2623 clk_enable(bank->clk);
5ae0c7ad
DA		 2624 bank->saved_masks = irq_reg_readl(gc, GPIO_INTMASK);
2625 irq_reg_writel(gc, ~gc->wake_active, GPIO_INTMASK);
07a06ae9 2626 clk_disable(bank->clk);
68bda47c
DA		 2627}
2628
2629static void rockchip_irq_resume(struct irq_data *d)
2630{
2631 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2632 struct rockchip_pin_bank *bank = gc->private;
2633
07a06ae9 2634 clk_enable(bank->clk);
5ae0c7ad 2635 irq_reg_writel(gc, bank->saved_masks, GPIO_INTMASK);
07a06ae9
LH		 2636 clk_disable(bank->clk);
2637}
2638
d468289a 2639static void rockchip_irq_enable(struct irq_data *d)
07a06ae9
LH		 2640{
2641 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2642 struct rockchip_pin_bank *bank = gc->private;
2643
2644 clk_enable(bank->clk);
2645 irq_gc_mask_clr_bit(d);
2646}
2647
d468289a 2648static void rockchip_irq_disable(struct irq_data *d)
07a06ae9
LH		 2649{
2650 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
2651 struct rockchip_pin_bank *bank = gc->private;
2652
2653 irq_gc_mask_set_bit(d);
2654 clk_disable(bank->clk);
f2dd028c
DA		 2655}
2656
d3e51161
HS		 2657static int rockchip_interrupts_register(struct platform_device *pdev,
2658 struct rockchip_pinctrl *info)
2659{
2660 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2661 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2662 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
2663 struct irq_chip_generic *gc;
2664 int ret;
07a06ae9 2665 int i, j;
d3e51161
HS		 2666
2667 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2668 if (!bank->valid) {
2669 dev_warn(&pdev->dev, "bank %s is not valid\n",
2670 bank->name);
2671 continue;
2672 }
2673
07a06ae9
LH		 2674 ret = clk_enable(bank->clk);
2675 if (ret) {
2676 dev_err(&pdev->dev, "failed to enable clock for bank %s\n",
2677 bank->name);
2678 continue;
2679 }
2680
d3e51161
HS		 2681 bank->domain = irq_domain_add_linear(bank->of_node, 32,
2682 &irq_generic_chip_ops, NULL);
2683 if (!bank->domain) {
2684 dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n",
2685 bank->name);
07a06ae9 2686 clk_disable(bank->clk);
d3e51161
HS		 2687 continue;
2688 }
2689
2690 ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1,
2691 "rockchip_gpio_irq", handle_level_irq,
2692 clr, 0, IRQ_GC_INIT_MASK_CACHE);
2693 if (ret) {
2694 dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n",
2695 bank->name);
2696 irq_domain_remove(bank->domain);
07a06ae9 2697 clk_disable(bank->clk);
d3e51161
HS		 2698 continue;
2699 }
2700
5ae0c7ad
DA		 2701 /*
2702 * Linux assumes that all interrupts start out disabled/masked.
2703 * Our driver only uses the concept of masked and always keeps
2704 * things enabled, so for us that's all masked and all enabled.
2705 */
2706 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTMASK);
2707 writel_relaxed(0xffffffff, bank->reg_base + GPIO_INTEN);
2708
d3e51161
HS		 2709 gc = irq_get_domain_generic_chip(bank->domain, 0);
2710 gc->reg_base = bank->reg_base;
2711 gc->private = bank;
f2dd028c 2712 gc->chip_types[0].regs.mask = GPIO_INTMASK;
d3e51161
HS		 2713 gc->chip_types[0].regs.ack = GPIO_PORTS_EOI;
2714 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
d468289a
JC		 2715 gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
2716 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;
2717 gc->chip_types[0].chip.irq_enable = rockchip_irq_enable;
2718 gc->chip_types[0].chip.irq_disable = rockchip_irq_disable;
d3e51161 2719 gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake;
68bda47c
DA		 2720 gc->chip_types[0].chip.irq_suspend = rockchip_irq_suspend;
2721 gc->chip_types[0].chip.irq_resume = rockchip_irq_resume;
d3e51161 2722 gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type;
876d716b 2723 gc->wake_enabled = IRQ_MSK(bank->nr_pins);
d3e51161 2724
03051bc2
TG		 2725 irq_set_chained_handler_and_data(bank->irq,
2726 rockchip_irq_demux, bank);
07a06ae9
LH		 2727
2728 /* map the gpio irqs here, when the clock is still running */
2729 for (j = 0 ; j < 32 ; j++)
2730 irq_create_mapping(bank->domain, j);
2731
2732 clk_disable(bank->clk);
d3e51161
HS		 2733 }
2734
2735 return 0;
2736}
2737
2738static int rockchip_gpiolib_register(struct platform_device *pdev,
2739 struct rockchip_pinctrl *info)
2740{
2741 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2742 struct rockchip_pin_bank *bank = ctrl->pin_banks;
2743 struct gpio_chip *gc;
2744 int ret;
2745 int i;
2746
2747 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2748 if (!bank->valid) {
2749 dev_warn(&pdev->dev, "bank %s is not valid\n",
2750 bank->name);
2751 continue;
2752 }
2753
2754 bank->gpio_chip = rockchip_gpiolib_chip;
2755
2756 gc = &bank->gpio_chip;
2757 gc->base = bank->pin_base;
2758 gc->ngpio = bank->nr_pins;
58383c78 2759 gc->parent = &pdev->dev;
d3e51161
HS		 2760 gc->of_node = bank->of_node;
2761 gc->label = bank->name;
2762
03bf81f1 2763 ret = gpiochip_add_data(gc, bank);
d3e51161
HS		 2764 if (ret) {
2765 dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
2766 gc->label, ret);
2767 goto fail;
2768 }
2769 }
2770
2771 rockchip_interrupts_register(pdev, info);
2772
2773 return 0;
2774
2775fail:
2776 for (--i, --bank; i >= 0; --i, --bank) {
2777 if (!bank->valid)
2778 continue;
b4e7c55d 2779 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2780 }
2781 return ret;
2782}
2783
2784static int rockchip_gpiolib_unregister(struct platform_device *pdev,
2785 struct rockchip_pinctrl *info)
2786{
2787 struct rockchip_pin_ctrl *ctrl = info->ctrl;
2788 struct rockchip_pin_bank *bank = ctrl->pin_banks;
d3e51161
HS		 2789 int i;
2790
b4e7c55d 2791 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
d3e51161
HS		 2792 if (!bank->valid)
2793 continue;
b4e7c55d 2794 gpiochip_remove(&bank->gpio_chip);
d3e51161
HS		 2795 }
2796
b4e7c55d 2797 return 0;
d3e51161
HS		 2798}
2799
2800static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
622f3237 2801 struct rockchip_pinctrl *info)
d3e51161
HS		 2802{
2803 struct resource res;
751a99ab 2804 void __iomem *base;
d3e51161
HS		 2805
2806 if (of_address_to_resource(bank->of_node, 0, &res)) {
622f3237 2807 dev_err(info->dev, "cannot find IO resource for bank\n");
d3e51161
HS		 2808 return -ENOENT;
2809 }
2810
622f3237 2811 bank->reg_base = devm_ioremap_resource(info->dev, &res);
d3e51161
HS		 2812 if (IS_ERR(bank->reg_base))
2813 return PTR_ERR(bank->reg_base);
2814
6ca5274d
HS		 2815 /*
2816 * special case, where parts of the pull setting-registers are
2817 * part of the PMU register space
2818 */
2819 if (of_device_is_compatible(bank->of_node,
2820 "rockchip,rk3188-gpio-bank0")) {
a658efaa 2821 struct device_node *node;
bfc7a42a 2822
a658efaa
HS		 2823 node = of_parse_phandle(bank->of_node->parent,
2824 "rockchip,pmu", 0);
2825 if (!node) {
2826 if (of_address_to_resource(bank->of_node, 1, &res)) {
2827 dev_err(info->dev, "cannot find IO resource for bank\n");
2828 return -ENOENT;
2829 }
2830
2831 base = devm_ioremap_resource(info->dev, &res);
2832 if (IS_ERR(base))
2833 return PTR_ERR(base);
2834 rockchip_regmap_config.max_register =
2835 resource_size(&res) - 4;
2836 rockchip_regmap_config.name =
2837 "rockchip,rk3188-gpio-bank0-pull";
2838 bank->regmap_pull = devm_regmap_init_mmio(info->dev,
2839 base,
2840 &rockchip_regmap_config);
6ca5274d 2841 }
6ca5274d 2842 }
65fca613 2843
d3e51161
HS		 2844 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
2845
2846 bank->clk = of_clk_get(bank->of_node, 0);
2847 if (IS_ERR(bank->clk))
2848 return PTR_ERR(bank->clk);
2849
07a06ae9 2850 return clk_prepare(bank->clk);
d3e51161
HS		 2851}
2852
2853static const struct of_device_id rockchip_pinctrl_dt_match[];
2854
2855/* retrieve the soc specific data */
2856static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(
2857 struct rockchip_pinctrl *d,
2858 struct platform_device *pdev)
2859{
2860 const struct of_device_id *match;
2861 struct device_node *node = pdev->dev.of_node;
2862 struct device_node *np;
2863 struct rockchip_pin_ctrl *ctrl;
2864 struct rockchip_pin_bank *bank;
b6c23275 2865 int grf_offs, pmu_offs, drv_grf_offs, drv_pmu_offs, i, j;
d3e51161
HS		 2866
2867 match = of_match_node(rockchip_pinctrl_dt_match, node);
2868 ctrl = (struct rockchip_pin_ctrl *)match->data;
2869
2870 for_each_child_of_node(node, np) {
2871 if (!of_find_property(np, "gpio-controller", NULL))
2872 continue;
2873
2874 bank = ctrl->pin_banks;
2875 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
2876 if (!strcmp(bank->name, np->name)) {
2877 bank->of_node = np;
2878
622f3237 2879 if (!rockchip_get_bank_data(bank, d))
d3e51161
HS		 2880 bank->valid = true;
2881
2882 break;
2883 }
2884 }
2885 }
2886
95ec8ae4
HS		 2887 grf_offs = ctrl->grf_mux_offset;
2888 pmu_offs = ctrl->pmu_mux_offset;
b6c23275
DW		 2889 drv_pmu_offs = ctrl->pmu_drv_offset;
2890 drv_grf_offs = ctrl->grf_drv_offset;
d3e51161
HS		 2891 bank = ctrl->pin_banks;
2892 for (i = 0; i < ctrl->nr_banks; ++i, ++bank) {
6bc0d121
HS		 2893 int bank_pins = 0;
2894
70b7aa7a 2895 raw_spin_lock_init(&bank->slock);
d3e51161
HS		 2896 bank->drvdata = d;
2897 bank->pin_base = ctrl->nr_pins;
2898 ctrl->nr_pins += bank->nr_pins;
6bc0d121 2899
b6c23275 2900 /* calculate iomux and drv offsets */
6bc0d121
HS		 2901 for (j = 0; j < 4; j++) {
2902 struct rockchip_iomux *iom = &bank->iomux[j];
b6c23275 2903 struct rockchip_drv *drv = &bank->drv[j];
03716e1d 2904 int inc;
6bc0d121
HS		 2905
2906 if (bank_pins >= bank->nr_pins)
2907 break;
2908
b6c23275 2909 /* preset iomux offset value, set new start value */
6bc0d121 2910 if (iom->offset >= 0) {
95ec8ae4
HS		 2911 if (iom->type & IOMUX_SOURCE_PMU)
2912 pmu_offs = iom->offset;
2913 else
2914 grf_offs = iom->offset;
b6c23275 2915 } else { /* set current iomux offset */
95ec8ae4
HS		 2916 iom->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2917 pmu_offs : grf_offs;
6bc0d121
HS		 2918 }
2919
b6c23275
DW		 2920 /* preset drv offset value, set new start value */
2921 if (drv->offset >= 0) {
2922 if (iom->type & IOMUX_SOURCE_PMU)
2923 drv_pmu_offs = drv->offset;
2924 else
2925 drv_grf_offs = drv->offset;
2926 } else { /* set current drv offset */
2927 drv->offset = (iom->type & IOMUX_SOURCE_PMU) ?
2928 drv_pmu_offs : drv_grf_offs;
2929 }
2930
2931 dev_dbg(d->dev, "bank %d, iomux %d has iom_offset 0x%x drv_offset 0x%x\n",
2932 i, j, iom->offset, drv->offset);
6bc0d121
HS		 2933
2934 /*
2935 * Increase offset according to iomux width.
03716e1d 2936 * 4bit iomux'es are spread over two registers.
6bc0d121 2937 */
8b6c6f93 2938 inc = (iom->type & (IOMUX_WIDTH_4BIT |
2939 IOMUX_WIDTH_3BIT)) ? 8 : 4;
95ec8ae4
HS		 2940 if (iom->type & IOMUX_SOURCE_PMU)
2941 pmu_offs += inc;
2942 else
2943 grf_offs += inc;
6bc0d121 2944
b6c23275
DW		 2945 /*
2946 * Increase offset according to drv width.
2947 * 3bit drive-strenth'es are spread over two registers.
2948 */
2949 if ((drv->drv_type == DRV_TYPE_IO_1V8_3V0_AUTO) ||
2950 (drv->drv_type == DRV_TYPE_IO_3V3_ONLY))
2951 inc = 8;
2952 else
2953 inc = 4;
2954
2955 if (iom->type & IOMUX_SOURCE_PMU)
2956 drv_pmu_offs += inc;
2957 else
2958 drv_grf_offs += inc;
2959
6bc0d121
HS		 2960 bank_pins += 8;
2961 }
bd35b9bf 2962
c04c3fa6
DW		 2963 /* calculate the per-bank recalced_mask */
2964 for (j = 0; j < ctrl->niomux_recalced; j++) {
2965 int pin = 0;
2966
2967 if (ctrl->iomux_recalced[j].num == bank->bank_num) {
2968 pin = ctrl->iomux_recalced[j].pin;
2969 bank->recalced_mask |= BIT(pin);
2970 }
2971 }
2972
bd35b9bf
DW		 2973 /* calculate the per-bank route_mask */
2974 for (j = 0; j < ctrl->niomux_routes; j++) {
2975 int pin = 0;
2976
2977 if (ctrl->iomux_routes[j].bank_num == bank->bank_num) {
2978 pin = ctrl->iomux_routes[j].pin;
2979 bank->route_mask |= BIT(pin);
2980 }
2981 }
d3e51161
HS		 2982 }
2983
2984 return ctrl;
2985}
2986
8dca9331
CZ		 2987#define RK3288_GRF_GPIO6C_IOMUX 0x64
2988#define GPIO6C6_SEL_WRITE_ENABLE BIT(28)
2989
2990static u32 rk3288_grf_gpio6c_iomux;
2991
9198f509
CZ		 2992static int __maybe_unused rockchip_pinctrl_suspend(struct device *dev)
2993{
2994 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 2995 int ret = pinctrl_force_sleep(info->pctl_dev);
2996
2997 if (ret)
2998 return ret;
2999
3000 /*
3001 * RK3288 GPIO6_C6 mux would be modified by Maskrom when resume, so save
3002 * the setting here, and restore it at resume.
3003 */
3004 if (info->ctrl->type == RK3288) {
3005 ret = regmap_read(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3006 &rk3288_grf_gpio6c_iomux);
3007 if (ret) {
3008 pinctrl_force_default(info->pctl_dev);
3009 return ret;
3010 }
3011 }
9198f509 3012
8dca9331 3013 return 0;
9198f509
CZ		 3014}
3015
3016static int __maybe_unused rockchip_pinctrl_resume(struct device *dev)
3017{
3018 struct rockchip_pinctrl *info = dev_get_drvdata(dev);
8dca9331
CZ		 3019 int ret = regmap_write(info->regmap_base, RK3288_GRF_GPIO6C_IOMUX,
3020 rk3288_grf_gpio6c_iomux |
3021 GPIO6C6_SEL_WRITE_ENABLE);
3022
3023 if (ret)
3024 return ret;
9198f509
CZ		 3025
3026 return pinctrl_force_default(info->pctl_dev);
3027}
3028
3029static SIMPLE_DEV_PM_OPS(rockchip_pinctrl_dev_pm_ops, rockchip_pinctrl_suspend,
3030 rockchip_pinctrl_resume);
3031
d3e51161
HS		 3032static int rockchip_pinctrl_probe(struct platform_device *pdev)
3033{
3034 struct rockchip_pinctrl *info;
3035 struct device *dev = &pdev->dev;
3036 struct rockchip_pin_ctrl *ctrl;
14dee867 3037 struct device_node *np = pdev->dev.of_node, *node;
d3e51161 3038 struct resource *res;
751a99ab 3039 void __iomem *base;
d3e51161
HS		 3040 int ret;
3041
3042 if (!dev->of_node) {
3043 dev_err(dev, "device tree node not found\n");
3044 return -ENODEV;
3045 }
3046
3047 info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL);
3048 if (!info)
3049 return -ENOMEM;
3050
622f3237
HS		 3051 info->dev = dev;
3052
d3e51161
HS		 3053 ctrl = rockchip_pinctrl_get_soc_data(info, pdev);
3054 if (!ctrl) {
3055 dev_err(dev, "driver data not available\n");
3056 return -EINVAL;
3057 }
3058 info->ctrl = ctrl;
d3e51161 3059
1e747e59
HS		 3060 node = of_parse_phandle(np, "rockchip,grf", 0);
3061 if (node) {
3062 info->regmap_base = syscon_node_to_regmap(node);
3063 if (IS_ERR(info->regmap_base))
3064 return PTR_ERR(info->regmap_base);
3065 } else {
3066 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
751a99ab
HS		 3067 base = devm_ioremap_resource(&pdev->dev, res);
3068 if (IS_ERR(base))
3069 return PTR_ERR(base);
3070
3071 rockchip_regmap_config.max_register = resource_size(res) - 4;
1e747e59
HS		 3072 rockchip_regmap_config.name = "rockchip,pinctrl";
3073 info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base,
3074 &rockchip_regmap_config);
3075
3076 /* to check for the old dt-bindings */
3077 info->reg_size = resource_size(res);
3078
3079 /* Honor the old binding, with pull registers as 2nd resource */
3080 if (ctrl->type == RK3188 && info->reg_size < 0x200) {
3081 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3082 base = devm_ioremap_resource(&pdev->dev, res);
3083 if (IS_ERR(base))
3084 return PTR_ERR(base);
3085
3086 rockchip_regmap_config.max_register =
3087 resource_size(res) - 4;
3088 rockchip_regmap_config.name = "rockchip,pinctrl-pull";
3089 info->regmap_pull = devm_regmap_init_mmio(&pdev->dev,
3090 base,
3091 &rockchip_regmap_config);
3092 }
6ca5274d
HS		 3093 }
3094
14dee867
HS		 3095 /* try to find the optional reference to the pmu syscon */
3096 node = of_parse_phandle(np, "rockchip,pmu", 0);
3097 if (node) {
3098 info->regmap_pmu = syscon_node_to_regmap(node);
3099 if (IS_ERR(info->regmap_pmu))
3100 return PTR_ERR(info->regmap_pmu);
3101 }
3102
d3e51161
HS		 3103 ret = rockchip_gpiolib_register(pdev, info);
3104 if (ret)
3105 return ret;
3106
3107 ret = rockchip_pinctrl_register(pdev, info);
3108 if (ret) {
3109 rockchip_gpiolib_unregister(pdev, info);
3110 return ret;
3111 }
3112
3113 platform_set_drvdata(pdev, info);
3114
3115 return 0;
3116}
3117
b9c6dcab 3118static struct rockchip_pin_bank rv1108_pin_banks[] = {
688daf23
AY		 3119 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3120 IOMUX_SOURCE_PMU,
3121 IOMUX_SOURCE_PMU,
3122 IOMUX_SOURCE_PMU),
3123 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3124 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, 0),
3125 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, 0),
3126};
3127
b9c6dcab
AY		 3128static struct rockchip_pin_ctrl rv1108_pin_ctrl = {
3129 .pin_banks = rv1108_pin_banks,
3130 .nr_banks = ARRAY_SIZE(rv1108_pin_banks),
3131 .label = "RV1108-GPIO",
3132 .type = RV1108,
688daf23
AY		 3133 .grf_mux_offset = 0x10,
3134 .pmu_mux_offset = 0x0,
b9c6dcab
AY		 3135 .pull_calc_reg = rv1108_calc_pull_reg_and_bit,
3136 .drv_calc_reg = rv1108_calc_drv_reg_and_bit,
688daf23
AY		 3137};
3138
d3e51161
HS		 3139static struct rockchip_pin_bank rk2928_pin_banks[] = {
3140 PIN_BANK(0, 32, "gpio0"),
3141 PIN_BANK(1, 32, "gpio1"),
3142 PIN_BANK(2, 32, "gpio2"),
3143 PIN_BANK(3, 32, "gpio3"),
3144};
3145
3146static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
3147 .pin_banks = rk2928_pin_banks,
3148 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
3149 .label = "RK2928-GPIO",
a282926d 3150 .type = RK2928,
95ec8ae4 3151 .grf_mux_offset = 0xa8,
a282926d 3152 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3153};
3154
c5ce7670
XZ		 3155static struct rockchip_pin_bank rk3036_pin_banks[] = {
3156 PIN_BANK(0, 32, "gpio0"),
3157 PIN_BANK(1, 32, "gpio1"),
3158 PIN_BANK(2, 32, "gpio2"),
3159};
3160
3161static struct rockchip_pin_ctrl rk3036_pin_ctrl = {
3162 .pin_banks = rk3036_pin_banks,
3163 .nr_banks = ARRAY_SIZE(rk3036_pin_banks),
3164 .label = "RK3036-GPIO",
3165 .type = RK2928,
3166 .grf_mux_offset = 0xa8,
3167 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
3168};
3169
d3e51161
HS		 3170static struct rockchip_pin_bank rk3066a_pin_banks[] = {
3171 PIN_BANK(0, 32, "gpio0"),
3172 PIN_BANK(1, 32, "gpio1"),
3173 PIN_BANK(2, 32, "gpio2"),
3174 PIN_BANK(3, 32, "gpio3"),
3175 PIN_BANK(4, 32, "gpio4"),
3176 PIN_BANK(6, 16, "gpio6"),
3177};
3178
3179static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
3180 .pin_banks = rk3066a_pin_banks,
3181 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
3182 .label = "RK3066a-GPIO",
a282926d 3183 .type = RK2928,
95ec8ae4 3184 .grf_mux_offset = 0xa8,
a282926d 3185 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
d3e51161
HS		 3186};
3187
3188static struct rockchip_pin_bank rk3066b_pin_banks[] = {
3189 PIN_BANK(0, 32, "gpio0"),
3190 PIN_BANK(1, 32, "gpio1"),
3191 PIN_BANK(2, 32, "gpio2"),
3192 PIN_BANK(3, 32, "gpio3"),
3193};
3194
3195static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
3196 .pin_banks = rk3066b_pin_banks,
3197 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
3198 .label = "RK3066b-GPIO",
a282926d 3199 .type = RK3066B,
95ec8ae4 3200 .grf_mux_offset = 0x60,
d3e51161
HS		 3201};
3202
d23c66df
DW		 3203static struct rockchip_pin_bank rk3128_pin_banks[] = {
3204 PIN_BANK(0, 32, "gpio0"),
3205 PIN_BANK(1, 32, "gpio1"),
3206 PIN_BANK(2, 32, "gpio2"),
3207 PIN_BANK(3, 32, "gpio3"),
3208};
3209
3210static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
3211 .pin_banks = rk3128_pin_banks,
3212 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
3213 .label = "RK3128-GPIO",
3214 .type = RK3128,
3215 .grf_mux_offset = 0xa8,
3216 .iomux_recalced = rk3128_mux_recalced_data,
3217 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
3218 .iomux_routes = rk3128_mux_route_data,
3219 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
3220 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
3221};
3222
d3e51161 3223static struct rockchip_pin_bank rk3188_pin_banks[] = {
fc72c923 3224 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0),
d3e51161
HS		 3225 PIN_BANK(1, 32, "gpio1"),
3226 PIN_BANK(2, 32, "gpio2"),
3227 PIN_BANK(3, 32, "gpio3"),
3228};
3229
3230static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
3231 .pin_banks = rk3188_pin_banks,
3232 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
3233 .label = "RK3188-GPIO",
a282926d 3234 .type = RK3188,
95ec8ae4 3235 .grf_mux_offset = 0x60,
6ca5274d 3236 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
d3e51161
HS		 3237};
3238
fea0fe60
JC		 3239static struct rockchip_pin_bank rk3228_pin_banks[] = {
3240 PIN_BANK(0, 32, "gpio0"),
3241 PIN_BANK(1, 32, "gpio1"),
3242 PIN_BANK(2, 32, "gpio2"),
3243 PIN_BANK(3, 32, "gpio3"),
3244};
3245
3246static struct rockchip_pin_ctrl rk3228_pin_ctrl = {
3247 .pin_banks = rk3228_pin_banks,
3248 .nr_banks = ARRAY_SIZE(rk3228_pin_banks),
3249 .label = "RK3228-GPIO",
3250 .type = RK3288,
3251 .grf_mux_offset = 0x0,
d4970ee0
DW		 3252 .iomux_routes = rk3228_mux_route_data,
3253 .niomux_routes = ARRAY_SIZE(rk3228_mux_route_data),
fea0fe60
JC		 3254 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3255 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
3256};
3257
304f077d
HS		 3258static struct rockchip_pin_bank rk3288_pin_banks[] = {
3259 PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU,
3260 IOMUX_SOURCE_PMU,
3261 IOMUX_SOURCE_PMU,
3262 IOMUX_UNROUTED
3263 ),
3264 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED,
3265 IOMUX_UNROUTED,
3266 IOMUX_UNROUTED,
3267 0
3268 ),
3269 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED),
3270 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT),
3271 PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
3272 IOMUX_WIDTH_4BIT,
3273 0,
3274 0
3275 ),
3276 PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED,
3277 0,
3278 0,
3279 IOMUX_UNROUTED
3280 ),
3281 PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED),
3282 PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0,
3283 0,
3284 IOMUX_WIDTH_4BIT,
3285 IOMUX_UNROUTED
3286 ),
3287 PIN_BANK(8, 16, "gpio8"),
3288};
3289
3290static struct rockchip_pin_ctrl rk3288_pin_ctrl = {
3291 .pin_banks = rk3288_pin_banks,
3292 .nr_banks = ARRAY_SIZE(rk3288_pin_banks),
3293 .label = "RK3288-GPIO",
66d750e1 3294 .type = RK3288,
304f077d
HS		 3295 .grf_mux_offset = 0x0,
3296 .pmu_mux_offset = 0x84,
3297 .pull_calc_reg = rk3288_calc_pull_reg_and_bit,
ef17f69f 3298 .drv_calc_reg = rk3288_calc_drv_reg_and_bit,
304f077d
HS		 3299};
3300
3818e4a7 3301static struct rockchip_pin_bank rk3328_pin_banks[] = {
3302 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
3303 PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
3304 PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
c04c3fa6
DW		 3305 IOMUX_WIDTH_3BIT,
3306 IOMUX_WIDTH_3BIT,
3818e4a7 3307 0),
3308 PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
3309 IOMUX_WIDTH_3BIT,
c04c3fa6 3310 IOMUX_WIDTH_3BIT,
3818e4a7 3311 0,
3312 0),
3313};
3314
3315static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
3316 .pin_banks = rk3328_pin_banks,
3317 .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
3318 .label = "RK3328-GPIO",
3319 .type = RK3288,
3320 .grf_mux_offset = 0x0,
c04c3fa6
DW		 3321 .iomux_recalced = rk3328_mux_recalced_data,
3322 .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
cedc964a
DW		 3323 .iomux_routes = rk3328_mux_route_data,
3324 .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
3818e4a7 3325 .pull_calc_reg = rk3228_calc_pull_reg_and_bit,
3326 .drv_calc_reg = rk3228_calc_drv_reg_and_bit,
728d3f5a 3327 .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
3818e4a7 3328};
3329
daecdc66
HS		 3330static struct rockchip_pin_bank rk3368_pin_banks[] = {
3331 PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
3332 IOMUX_SOURCE_PMU,
3333 IOMUX_SOURCE_PMU,
3334 IOMUX_SOURCE_PMU
3335 ),
3336 PIN_BANK(1, 32, "gpio1"),
3337 PIN_BANK(2, 32, "gpio2"),
3338 PIN_BANK(3, 32, "gpio3"),
3339};
3340
3341static struct rockchip_pin_ctrl rk3368_pin_ctrl = {
3342 .pin_banks = rk3368_pin_banks,
3343 .nr_banks = ARRAY_SIZE(rk3368_pin_banks),
3344 .label = "RK3368-GPIO",
3345 .type = RK3368,
3346 .grf_mux_offset = 0x0,
3347 .pmu_mux_offset = 0x0,
3348 .pull_calc_reg = rk3368_calc_pull_reg_and_bit,
3349 .drv_calc_reg = rk3368_calc_drv_reg_and_bit,
3350};
3351
b6c23275 3352static struct rockchip_pin_bank rk3399_pin_banks[] = {
3ba6767a
DW		 3353 PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
3354 IOMUX_SOURCE_PMU,
3355 IOMUX_SOURCE_PMU,
3356 IOMUX_SOURCE_PMU,
3357 IOMUX_SOURCE_PMU,
3358 DRV_TYPE_IO_1V8_ONLY,
3359 DRV_TYPE_IO_1V8_ONLY,
3360 DRV_TYPE_IO_DEFAULT,
3361 DRV_TYPE_IO_DEFAULT,
3362 0x0,
3363 0x8,
3364 -1,
3365 -1,
3366 PULL_TYPE_IO_1V8_ONLY,
3367 PULL_TYPE_IO_1V8_ONLY,
3368 PULL_TYPE_IO_DEFAULT,
3369 PULL_TYPE_IO_DEFAULT
3370 ),
b6c23275
DW		 3371 PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
3372 IOMUX_SOURCE_PMU,
3373 IOMUX_SOURCE_PMU,
3374 IOMUX_SOURCE_PMU,
3375 DRV_TYPE_IO_1V8_OR_3V0,
3376 DRV_TYPE_IO_1V8_OR_3V0,
3377 DRV_TYPE_IO_1V8_OR_3V0,
3378 DRV_TYPE_IO_1V8_OR_3V0,
3379 0x20,
3380 0x28,
3381 0x30,
3382 0x38
3383 ),
3ba6767a
DW		 3384 PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
3385 DRV_TYPE_IO_1V8_OR_3V0,
3386 DRV_TYPE_IO_1V8_ONLY,
3387 DRV_TYPE_IO_1V8_ONLY,
3388 PULL_TYPE_IO_DEFAULT,
3389 PULL_TYPE_IO_DEFAULT,
3390 PULL_TYPE_IO_1V8_ONLY,
3391 PULL_TYPE_IO_1V8_ONLY
3392 ),
b6c23275
DW		 3393 PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
3394 DRV_TYPE_IO_3V3_ONLY,
3395 DRV_TYPE_IO_3V3_ONLY,
3396 DRV_TYPE_IO_1V8_OR_3V0
3397 ),
3398 PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
3399 DRV_TYPE_IO_1V8_3V0_AUTO,
3400 DRV_TYPE_IO_1V8_OR_3V0,
3401 DRV_TYPE_IO_1V8_OR_3V0
3402 ),
3403};
3404
3405static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
3406 .pin_banks = rk3399_pin_banks,
3407 .nr_banks = ARRAY_SIZE(rk3399_pin_banks),
3408 .label = "RK3399-GPIO",
3409 .type = RK3399,
3410 .grf_mux_offset = 0xe000,
3411 .pmu_mux_offset = 0x0,
3412 .grf_drv_offset = 0xe100,
3413 .pmu_drv_offset = 0x80,
accc1ce7
DW		 3414 .iomux_routes = rk3399_mux_route_data,
3415 .niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
b6c23275
DW		 3416 .pull_calc_reg = rk3399_calc_pull_reg_and_bit,
3417 .drv_calc_reg = rk3399_calc_drv_reg_and_bit,
3418};
daecdc66 3419
d3e51161 3420static const struct of_device_id rockchip_pinctrl_dt_match[] = {
b9c6dcab 3421 { .compatible = "rockchip,rv1108-pinctrl",
cdbbd26f 3422 .data = &rv1108_pin_ctrl },
d3e51161 3423 { .compatible = "rockchip,rk2928-pinctrl",
cdbbd26f 3424 .data = &rk2928_pin_ctrl },
c5ce7670 3425 { .compatible = "rockchip,rk3036-pinctrl",
cdbbd26f 3426 .data = &rk3036_pin_ctrl },
d3e51161 3427 { .compatible = "rockchip,rk3066a-pinctrl",
cdbbd26f 3428 .data = &rk3066a_pin_ctrl },
d3e51161 3429 { .compatible = "rockchip,rk3066b-pinctrl",
cdbbd26f 3430 .data = &rk3066b_pin_ctrl },
d23c66df
DW		 3431 { .compatible = "rockchip,rk3128-pinctrl",
3432 .data = (void *)&rk3128_pin_ctrl },
d3e51161 3433 { .compatible = "rockchip,rk3188-pinctrl",
cdbbd26f 3434 .data = &rk3188_pin_ctrl },
fea0fe60 3435 { .compatible = "rockchip,rk3228-pinctrl",
cdbbd26f 3436 .data = &rk3228_pin_ctrl },
304f077d 3437 { .compatible = "rockchip,rk3288-pinctrl",
cdbbd26f 3438 .data = &rk3288_pin_ctrl },
3818e4a7 3439 { .compatible = "rockchip,rk3328-pinctrl",
cdbbd26f 3440 .data = &rk3328_pin_ctrl },
daecdc66 3441 { .compatible = "rockchip,rk3368-pinctrl",
cdbbd26f 3442 .data = &rk3368_pin_ctrl },
b6c23275 3443 { .compatible = "rockchip,rk3399-pinctrl",
cdbbd26f 3444 .data = &rk3399_pin_ctrl },
d3e51161
HS		 3445 {},
3446};
d3e51161
HS		 3447
3448static struct platform_driver rockchip_pinctrl_driver = {
3449 .probe = rockchip_pinctrl_probe,
3450 .driver = {
3451 .name = "rockchip-pinctrl",
9198f509 3452 .pm = &rockchip_pinctrl_dev_pm_ops,
0be9e70d 3453 .of_match_table = rockchip_pinctrl_dt_match,
d3e51161
HS		 3454 },
3455};
3456
3457static int __init rockchip_pinctrl_drv_register(void)
3458{
3459 return platform_driver_register(&rockchip_pinctrl_driver);
3460}
3461postcore_initcall(rockchip_pinctrl_drv_register);
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