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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
7e865abb | 39 | #include <linux/clk.h> |
751a99ab | 40 | #include <linux/regmap.h> |
14dee867 | 41 | #include <linux/mfd/syscon.h> |
d3e51161 HS |
42 | #include <dt-bindings/pinctrl/rockchip.h> |
43 | ||
44 | #include "core.h" | |
45 | #include "pinconf.h" | |
46 | ||
47 | /* GPIO control registers */ | |
48 | #define GPIO_SWPORT_DR 0x00 | |
49 | #define GPIO_SWPORT_DDR 0x04 | |
50 | #define GPIO_INTEN 0x30 | |
51 | #define GPIO_INTMASK 0x34 | |
52 | #define GPIO_INTTYPE_LEVEL 0x38 | |
53 | #define GPIO_INT_POLARITY 0x3c | |
54 | #define GPIO_INT_STATUS 0x40 | |
55 | #define GPIO_INT_RAWSTATUS 0x44 | |
56 | #define GPIO_DEBOUNCE 0x48 | |
57 | #define GPIO_PORTS_EOI 0x4c | |
58 | #define GPIO_EXT_PORT 0x50 | |
59 | #define GPIO_LS_SYNC 0x60 | |
60 | ||
a282926d HS |
61 | enum rockchip_pinctrl_type { |
62 | RK2928, | |
63 | RK3066B, | |
64 | RK3188, | |
66d750e1 | 65 | RK3288, |
a282926d HS |
66 | }; |
67 | ||
fc72c923 HS |
68 | /** |
69 | * Encode variants of iomux registers into a type variable | |
70 | */ | |
71 | #define IOMUX_GPIO_ONLY BIT(0) | |
03716e1d | 72 | #define IOMUX_WIDTH_4BIT BIT(1) |
95ec8ae4 | 73 | #define IOMUX_SOURCE_PMU BIT(2) |
62f49226 | 74 | #define IOMUX_UNROUTED BIT(3) |
fc72c923 HS |
75 | |
76 | /** | |
77 | * @type: iomux variant using IOMUX_* constants | |
6bc0d121 HS |
78 | * @offset: if initialized to -1 it will be autocalculated, by specifying |
79 | * an initial offset value the relevant source offset can be reset | |
80 | * to a new value for autocalculating the following iomux registers. | |
fc72c923 HS |
81 | */ |
82 | struct rockchip_iomux { | |
83 | int type; | |
6bc0d121 | 84 | int offset; |
65fca613 HS |
85 | }; |
86 | ||
d3e51161 HS |
87 | /** |
88 | * @reg_base: register base of the gpio bank | |
6ca5274d | 89 | * @reg_pull: optional separate register for additional pull settings |
d3e51161 HS |
90 | * @clk: clock of the gpio bank |
91 | * @irq: interrupt of the gpio bank | |
92 | * @pin_base: first pin number | |
93 | * @nr_pins: number of pins in this bank | |
94 | * @name: name of the bank | |
95 | * @bank_num: number of the bank, to account for holes | |
fc72c923 | 96 | * @iomux: array describing the 4 iomux sources of the bank |
d3e51161 HS |
97 | * @valid: are all necessary informations present |
98 | * @of_node: dt node of this bank | |
99 | * @drvdata: common pinctrl basedata | |
100 | * @domain: irqdomain of the gpio bank | |
101 | * @gpio_chip: gpiolib chip | |
102 | * @grange: gpio range | |
103 | * @slock: spinlock for the gpio bank | |
104 | */ | |
105 | struct rockchip_pin_bank { | |
106 | void __iomem *reg_base; | |
751a99ab | 107 | struct regmap *regmap_pull; |
d3e51161 HS |
108 | struct clk *clk; |
109 | int irq; | |
110 | u32 pin_base; | |
111 | u8 nr_pins; | |
112 | char *name; | |
113 | u8 bank_num; | |
fc72c923 | 114 | struct rockchip_iomux iomux[4]; |
d3e51161 HS |
115 | bool valid; |
116 | struct device_node *of_node; | |
117 | struct rockchip_pinctrl *drvdata; | |
118 | struct irq_domain *domain; | |
119 | struct gpio_chip gpio_chip; | |
120 | struct pinctrl_gpio_range grange; | |
121 | spinlock_t slock; | |
5a927501 | 122 | u32 toggle_edge_mode; |
d3e51161 HS |
123 | }; |
124 | ||
125 | #define PIN_BANK(id, pins, label) \ | |
126 | { \ | |
127 | .bank_num = id, \ | |
128 | .nr_pins = pins, \ | |
129 | .name = label, \ | |
6bc0d121 HS |
130 | .iomux = { \ |
131 | { .offset = -1 }, \ | |
132 | { .offset = -1 }, \ | |
133 | { .offset = -1 }, \ | |
134 | { .offset = -1 }, \ | |
135 | }, \ | |
d3e51161 HS |
136 | } |
137 | ||
fc72c923 HS |
138 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
139 | { \ | |
140 | .bank_num = id, \ | |
141 | .nr_pins = pins, \ | |
142 | .name = label, \ | |
143 | .iomux = { \ | |
6bc0d121 HS |
144 | { .type = iom0, .offset = -1 }, \ |
145 | { .type = iom1, .offset = -1 }, \ | |
146 | { .type = iom2, .offset = -1 }, \ | |
147 | { .type = iom3, .offset = -1 }, \ | |
fc72c923 HS |
148 | }, \ |
149 | } | |
150 | ||
d3e51161 | 151 | /** |
d3e51161 HS |
152 | */ |
153 | struct rockchip_pin_ctrl { | |
154 | struct rockchip_pin_bank *pin_banks; | |
155 | u32 nr_banks; | |
156 | u32 nr_pins; | |
157 | char *label; | |
a282926d | 158 | enum rockchip_pinctrl_type type; |
95ec8ae4 HS |
159 | int grf_mux_offset; |
160 | int pmu_mux_offset; | |
751a99ab HS |
161 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
162 | int pin_num, struct regmap **regmap, | |
163 | int *reg, u8 *bit); | |
d3e51161 HS |
164 | }; |
165 | ||
166 | struct rockchip_pin_config { | |
167 | unsigned int func; | |
168 | unsigned long *configs; | |
169 | unsigned int nconfigs; | |
170 | }; | |
171 | ||
172 | /** | |
173 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
174 | * @name: name of the pin group, used to lookup the group. | |
175 | * @pins: the pins included in this group. | |
176 | * @npins: number of pins included in this group. | |
177 | * @func: the mux function number to be programmed when selected. | |
178 | * @configs: the config values to be set for each pin | |
179 | * @nconfigs: number of configs for each pin | |
180 | */ | |
181 | struct rockchip_pin_group { | |
182 | const char *name; | |
183 | unsigned int npins; | |
184 | unsigned int *pins; | |
185 | struct rockchip_pin_config *data; | |
186 | }; | |
187 | ||
188 | /** | |
189 | * struct rockchip_pmx_func: represent a pin function. | |
190 | * @name: name of the pin function, used to lookup the function. | |
191 | * @groups: one or more names of pin groups that provide this function. | |
192 | * @num_groups: number of groups included in @groups. | |
193 | */ | |
194 | struct rockchip_pmx_func { | |
195 | const char *name; | |
196 | const char **groups; | |
197 | u8 ngroups; | |
198 | }; | |
199 | ||
200 | struct rockchip_pinctrl { | |
751a99ab | 201 | struct regmap *regmap_base; |
bfc7a42a | 202 | int reg_size; |
751a99ab | 203 | struct regmap *regmap_pull; |
14dee867 | 204 | struct regmap *regmap_pmu; |
d3e51161 HS |
205 | struct device *dev; |
206 | struct rockchip_pin_ctrl *ctrl; | |
207 | struct pinctrl_desc pctl; | |
208 | struct pinctrl_dev *pctl_dev; | |
209 | struct rockchip_pin_group *groups; | |
210 | unsigned int ngroups; | |
211 | struct rockchip_pmx_func *functions; | |
212 | unsigned int nfunctions; | |
213 | }; | |
214 | ||
751a99ab HS |
215 | static struct regmap_config rockchip_regmap_config = { |
216 | .reg_bits = 32, | |
217 | .val_bits = 32, | |
218 | .reg_stride = 4, | |
219 | }; | |
220 | ||
d3e51161 HS |
221 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) |
222 | { | |
223 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
224 | } | |
225 | ||
226 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
227 | const struct rockchip_pinctrl *info, | |
228 | const char *name) | |
229 | { | |
d3e51161 HS |
230 | int i; |
231 | ||
232 | for (i = 0; i < info->ngroups; i++) { | |
1cb95395 AL |
233 | if (!strcmp(info->groups[i].name, name)) |
234 | return &info->groups[i]; | |
d3e51161 HS |
235 | } |
236 | ||
1cb95395 | 237 | return NULL; |
d3e51161 HS |
238 | } |
239 | ||
240 | /* | |
241 | * given a pin number that is local to a pin controller, find out the pin bank | |
242 | * and the register base of the pin bank. | |
243 | */ | |
244 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
245 | unsigned pin) | |
246 | { | |
247 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
248 | ||
51578b9b | 249 | while (pin >= (b->pin_base + b->nr_pins)) |
d3e51161 HS |
250 | b++; |
251 | ||
252 | return b; | |
253 | } | |
254 | ||
255 | static struct rockchip_pin_bank *bank_num_to_bank( | |
256 | struct rockchip_pinctrl *info, | |
257 | unsigned num) | |
258 | { | |
259 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
260 | int i; | |
261 | ||
1cb95395 | 262 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
d3e51161 | 263 | if (b->bank_num == num) |
1cb95395 | 264 | return b; |
d3e51161 HS |
265 | } |
266 | ||
1cb95395 | 267 | return ERR_PTR(-EINVAL); |
d3e51161 HS |
268 | } |
269 | ||
270 | /* | |
271 | * Pinctrl_ops handling | |
272 | */ | |
273 | ||
274 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
275 | { | |
276 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
277 | ||
278 | return info->ngroups; | |
279 | } | |
280 | ||
281 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
282 | unsigned selector) | |
283 | { | |
284 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
285 | ||
286 | return info->groups[selector].name; | |
287 | } | |
288 | ||
289 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
290 | unsigned selector, const unsigned **pins, | |
291 | unsigned *npins) | |
292 | { | |
293 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
294 | ||
295 | if (selector >= info->ngroups) | |
296 | return -EINVAL; | |
297 | ||
298 | *pins = info->groups[selector].pins; | |
299 | *npins = info->groups[selector].npins; | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
304 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
305 | struct device_node *np, | |
306 | struct pinctrl_map **map, unsigned *num_maps) | |
307 | { | |
308 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
309 | const struct rockchip_pin_group *grp; | |
310 | struct pinctrl_map *new_map; | |
311 | struct device_node *parent; | |
312 | int map_num = 1; | |
313 | int i; | |
314 | ||
315 | /* | |
316 | * first find the group of this node and check if we need to create | |
317 | * config maps for pins | |
318 | */ | |
319 | grp = pinctrl_name_to_group(info, np->name); | |
320 | if (!grp) { | |
321 | dev_err(info->dev, "unable to find group for node %s\n", | |
322 | np->name); | |
323 | return -EINVAL; | |
324 | } | |
325 | ||
326 | map_num += grp->npins; | |
327 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
328 | GFP_KERNEL); | |
329 | if (!new_map) | |
330 | return -ENOMEM; | |
331 | ||
332 | *map = new_map; | |
333 | *num_maps = map_num; | |
334 | ||
335 | /* create mux map */ | |
336 | parent = of_get_parent(np); | |
337 | if (!parent) { | |
338 | devm_kfree(pctldev->dev, new_map); | |
339 | return -EINVAL; | |
340 | } | |
341 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
342 | new_map[0].data.mux.function = parent->name; | |
343 | new_map[0].data.mux.group = np->name; | |
344 | of_node_put(parent); | |
345 | ||
346 | /* create config map */ | |
347 | new_map++; | |
348 | for (i = 0; i < grp->npins; i++) { | |
349 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
350 | new_map[i].data.configs.group_or_pin = | |
351 | pin_get_name(pctldev, grp->pins[i]); | |
352 | new_map[i].data.configs.configs = grp->data[i].configs; | |
353 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
354 | } | |
355 | ||
356 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
357 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
363 | struct pinctrl_map *map, unsigned num_maps) | |
364 | { | |
365 | } | |
366 | ||
367 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
368 | .get_groups_count = rockchip_get_groups_count, | |
369 | .get_group_name = rockchip_get_group_name, | |
370 | .get_group_pins = rockchip_get_group_pins, | |
371 | .dt_node_to_map = rockchip_dt_node_to_map, | |
372 | .dt_free_map = rockchip_dt_free_map, | |
373 | }; | |
374 | ||
375 | /* | |
376 | * Hardware access | |
377 | */ | |
378 | ||
a076e2ed HS |
379 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
380 | { | |
381 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 382 | int iomux_num = (pin / 8); |
95ec8ae4 | 383 | struct regmap *regmap; |
751a99ab | 384 | unsigned int val; |
03716e1d | 385 | int reg, ret, mask; |
a076e2ed HS |
386 | u8 bit; |
387 | ||
fc72c923 HS |
388 | if (iomux_num > 3) |
389 | return -EINVAL; | |
390 | ||
62f49226 HS |
391 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
392 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
393 | return -EINVAL; | |
394 | } | |
395 | ||
fc72c923 | 396 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) |
a076e2ed HS |
397 | return RK_FUNC_GPIO; |
398 | ||
95ec8ae4 HS |
399 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
400 | ? info->regmap_pmu : info->regmap_base; | |
401 | ||
a076e2ed | 402 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 403 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 404 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
405 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
406 | if ((pin % 8) >= 4) | |
407 | reg += 0x4; | |
408 | bit = (pin % 4) * 4; | |
409 | } else { | |
410 | bit = (pin % 8) * 2; | |
411 | } | |
a076e2ed | 412 | |
95ec8ae4 | 413 | ret = regmap_read(regmap, reg, &val); |
751a99ab HS |
414 | if (ret) |
415 | return ret; | |
416 | ||
03716e1d | 417 | return ((val >> bit) & mask); |
a076e2ed HS |
418 | } |
419 | ||
d3e51161 HS |
420 | /* |
421 | * Set a new mux function for a pin. | |
422 | * | |
423 | * The register is divided into the upper and lower 16 bit. When changing | |
424 | * a value, the previous register value is not read and changed. Instead | |
425 | * it seems the changed bits are marked in the upper 16 bit, while the | |
426 | * changed value gets set in the same offset in the lower 16 bit. | |
427 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
428 | * parts. | |
429 | * @bank: pin bank to change | |
430 | * @pin: pin to change | |
431 | * @mux: new mux function to set | |
432 | */ | |
14797189 | 433 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
d3e51161 HS |
434 | { |
435 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 436 | int iomux_num = (pin / 8); |
95ec8ae4 | 437 | struct regmap *regmap; |
03716e1d | 438 | int reg, ret, mask; |
d3e51161 HS |
439 | unsigned long flags; |
440 | u8 bit; | |
441 | u32 data; | |
442 | ||
fc72c923 HS |
443 | if (iomux_num > 3) |
444 | return -EINVAL; | |
445 | ||
62f49226 HS |
446 | if (bank->iomux[iomux_num].type & IOMUX_UNROUTED) { |
447 | dev_err(info->dev, "pin %d is unrouted\n", pin); | |
448 | return -EINVAL; | |
449 | } | |
450 | ||
fc72c923 | 451 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { |
c4a532de HS |
452 | if (mux != RK_FUNC_GPIO) { |
453 | dev_err(info->dev, | |
454 | "pin %d only supports a gpio mux\n", pin); | |
455 | return -ENOTSUPP; | |
456 | } else { | |
457 | return 0; | |
458 | } | |
459 | } | |
460 | ||
d3e51161 HS |
461 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
462 | bank->bank_num, pin, mux); | |
463 | ||
95ec8ae4 HS |
464 | regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) |
465 | ? info->regmap_pmu : info->regmap_base; | |
466 | ||
d3e51161 | 467 | /* get basic quadrupel of mux registers and the correct reg inside */ |
03716e1d | 468 | mask = (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) ? 0xf : 0x3; |
6bc0d121 | 469 | reg = bank->iomux[iomux_num].offset; |
03716e1d HS |
470 | if (bank->iomux[iomux_num].type & IOMUX_WIDTH_4BIT) { |
471 | if ((pin % 8) >= 4) | |
472 | reg += 0x4; | |
473 | bit = (pin % 4) * 4; | |
474 | } else { | |
475 | bit = (pin % 8) * 2; | |
476 | } | |
d3e51161 HS |
477 | |
478 | spin_lock_irqsave(&bank->slock, flags); | |
479 | ||
03716e1d HS |
480 | data = (mask << (bit + 16)); |
481 | data |= (mux & mask) << bit; | |
95ec8ae4 | 482 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
483 | |
484 | spin_unlock_irqrestore(&bank->slock, flags); | |
14797189 | 485 | |
751a99ab | 486 | return ret; |
d3e51161 HS |
487 | } |
488 | ||
a282926d HS |
489 | #define RK2928_PULL_OFFSET 0x118 |
490 | #define RK2928_PULL_PINS_PER_REG 16 | |
491 | #define RK2928_PULL_BANK_STRIDE 8 | |
492 | ||
493 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
494 | int pin_num, struct regmap **regmap, |
495 | int *reg, u8 *bit) | |
a282926d HS |
496 | { |
497 | struct rockchip_pinctrl *info = bank->drvdata; | |
498 | ||
751a99ab HS |
499 | *regmap = info->regmap_base; |
500 | *reg = RK2928_PULL_OFFSET; | |
a282926d HS |
501 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
502 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; | |
503 | ||
504 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; | |
505 | }; | |
506 | ||
bfc7a42a | 507 | #define RK3188_PULL_OFFSET 0x164 |
6ca5274d HS |
508 | #define RK3188_PULL_BITS_PER_PIN 2 |
509 | #define RK3188_PULL_PINS_PER_REG 8 | |
510 | #define RK3188_PULL_BANK_STRIDE 16 | |
14dee867 | 511 | #define RK3188_PULL_PMU_OFFSET 0x64 |
6ca5274d HS |
512 | |
513 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
514 | int pin_num, struct regmap **regmap, |
515 | int *reg, u8 *bit) | |
6ca5274d HS |
516 | { |
517 | struct rockchip_pinctrl *info = bank->drvdata; | |
518 | ||
519 | /* The first 12 pins of the first bank are located elsewhere */ | |
fc72c923 | 520 | if (bank->bank_num == 0 && pin_num < 12) { |
14dee867 HS |
521 | *regmap = info->regmap_pmu ? info->regmap_pmu |
522 | : bank->regmap_pull; | |
523 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; | |
751a99ab | 524 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
6ca5274d HS |
525 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
526 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
527 | } else { | |
751a99ab HS |
528 | *regmap = info->regmap_pull ? info->regmap_pull |
529 | : info->regmap_base; | |
530 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; | |
531 | ||
bfc7a42a HS |
532 | /* correct the offset, as it is the 2nd pull register */ |
533 | *reg -= 4; | |
6ca5274d HS |
534 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
535 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
536 | ||
537 | /* | |
538 | * The bits in these registers have an inverse ordering | |
539 | * with the lowest pin being in bits 15:14 and the highest | |
540 | * pin in bits 1:0 | |
541 | */ | |
542 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); | |
543 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
544 | } | |
545 | } | |
546 | ||
304f077d HS |
547 | #define RK3288_PULL_OFFSET 0x140 |
548 | static void rk3288_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
549 | int pin_num, struct regmap **regmap, | |
550 | int *reg, u8 *bit) | |
551 | { | |
552 | struct rockchip_pinctrl *info = bank->drvdata; | |
553 | ||
554 | /* The first 24 pins of the first bank are located in PMU */ | |
555 | if (bank->bank_num == 0) { | |
556 | *regmap = info->regmap_pmu; | |
557 | *reg = RK3188_PULL_PMU_OFFSET; | |
558 | ||
559 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
560 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; | |
561 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
562 | } else { | |
563 | *regmap = info->regmap_base; | |
564 | *reg = RK3288_PULL_OFFSET; | |
565 | ||
566 | /* correct the offset, as we're starting with the 2nd bank */ | |
567 | *reg -= 0x10; | |
568 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; | |
569 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
570 | ||
571 | *bit = (pin_num % RK3188_PULL_PINS_PER_REG); | |
572 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
573 | } | |
574 | } | |
575 | ||
d3e51161 HS |
576 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
577 | { | |
578 | struct rockchip_pinctrl *info = bank->drvdata; | |
579 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
580 | struct regmap *regmap; |
581 | int reg, ret; | |
d3e51161 | 582 | u8 bit; |
6ca5274d | 583 | u32 data; |
d3e51161 HS |
584 | |
585 | /* rk3066b does support any pulls */ | |
a282926d | 586 | if (ctrl->type == RK3066B) |
d3e51161 HS |
587 | return PIN_CONFIG_BIAS_DISABLE; |
588 | ||
751a99ab HS |
589 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
590 | ||
591 | ret = regmap_read(regmap, reg, &data); | |
592 | if (ret) | |
593 | return ret; | |
6ca5274d | 594 | |
a282926d HS |
595 | switch (ctrl->type) { |
596 | case RK2928: | |
751a99ab | 597 | return !(data & BIT(bit)) |
d3e51161 HS |
598 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
599 | : PIN_CONFIG_BIAS_DISABLE; | |
a282926d | 600 | case RK3188: |
66d750e1 | 601 | case RK3288: |
751a99ab | 602 | data >>= bit; |
6ca5274d HS |
603 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
604 | ||
605 | switch (data) { | |
606 | case 0: | |
607 | return PIN_CONFIG_BIAS_DISABLE; | |
608 | case 1: | |
609 | return PIN_CONFIG_BIAS_PULL_UP; | |
610 | case 2: | |
611 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
612 | case 3: | |
613 | return PIN_CONFIG_BIAS_BUS_HOLD; | |
614 | } | |
615 | ||
616 | dev_err(info->dev, "unknown pull setting\n"); | |
d3e51161 | 617 | return -EIO; |
a282926d HS |
618 | default: |
619 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
620 | return -EINVAL; | |
621 | }; | |
d3e51161 HS |
622 | } |
623 | ||
624 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
625 | int pin_num, int pull) | |
626 | { | |
627 | struct rockchip_pinctrl *info = bank->drvdata; | |
628 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
629 | struct regmap *regmap; |
630 | int reg, ret; | |
d3e51161 HS |
631 | unsigned long flags; |
632 | u8 bit; | |
633 | u32 data; | |
634 | ||
635 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
636 | bank->bank_num, pin_num, pull); | |
637 | ||
638 | /* rk3066b does support any pulls */ | |
a282926d | 639 | if (ctrl->type == RK3066B) |
d3e51161 HS |
640 | return pull ? -EINVAL : 0; |
641 | ||
751a99ab | 642 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
6ca5274d | 643 | |
a282926d HS |
644 | switch (ctrl->type) { |
645 | case RK2928: | |
d3e51161 HS |
646 | spin_lock_irqsave(&bank->slock, flags); |
647 | ||
648 | data = BIT(bit + 16); | |
649 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
650 | data |= BIT(bit); | |
751a99ab | 651 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
652 | |
653 | spin_unlock_irqrestore(&bank->slock, flags); | |
a282926d HS |
654 | break; |
655 | case RK3188: | |
66d750e1 | 656 | case RK3288: |
6ca5274d HS |
657 | spin_lock_irqsave(&bank->slock, flags); |
658 | ||
659 | /* enable the write to the equivalent lower bits */ | |
660 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); | |
661 | ||
662 | switch (pull) { | |
663 | case PIN_CONFIG_BIAS_DISABLE: | |
664 | break; | |
665 | case PIN_CONFIG_BIAS_PULL_UP: | |
666 | data |= (1 << bit); | |
667 | break; | |
668 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
669 | data |= (2 << bit); | |
670 | break; | |
671 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
672 | data |= (3 << bit); | |
673 | break; | |
674 | default: | |
d32c3e26 | 675 | spin_unlock_irqrestore(&bank->slock, flags); |
6ca5274d HS |
676 | dev_err(info->dev, "unsupported pull setting %d\n", |
677 | pull); | |
678 | return -EINVAL; | |
679 | } | |
680 | ||
751a99ab | 681 | ret = regmap_write(regmap, reg, data); |
6ca5274d HS |
682 | |
683 | spin_unlock_irqrestore(&bank->slock, flags); | |
684 | break; | |
a282926d HS |
685 | default: |
686 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
687 | return -EINVAL; | |
d3e51161 HS |
688 | } |
689 | ||
751a99ab | 690 | return ret; |
d3e51161 HS |
691 | } |
692 | ||
693 | /* | |
694 | * Pinmux_ops handling | |
695 | */ | |
696 | ||
697 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
698 | { | |
699 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
700 | ||
701 | return info->nfunctions; | |
702 | } | |
703 | ||
704 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
705 | unsigned selector) | |
706 | { | |
707 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
708 | ||
709 | return info->functions[selector].name; | |
710 | } | |
711 | ||
712 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
713 | unsigned selector, const char * const **groups, | |
714 | unsigned * const num_groups) | |
715 | { | |
716 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
717 | ||
718 | *groups = info->functions[selector].groups; | |
719 | *num_groups = info->functions[selector].ngroups; | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
724 | static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
725 | unsigned group) | |
726 | { | |
727 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
728 | const unsigned int *pins = info->groups[group].pins; | |
729 | const struct rockchip_pin_config *data = info->groups[group].data; | |
730 | struct rockchip_pin_bank *bank; | |
14797189 | 731 | int cnt, ret = 0; |
d3e51161 HS |
732 | |
733 | dev_dbg(info->dev, "enable function %s group %s\n", | |
734 | info->functions[selector].name, info->groups[group].name); | |
735 | ||
736 | /* | |
737 | * for each pin in the pin group selected, program the correspoding pin | |
738 | * pin function number in the config register. | |
739 | */ | |
740 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
741 | bank = pin_to_bank(info, pins[cnt]); | |
14797189 HS |
742 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
743 | data[cnt].func); | |
744 | if (ret) | |
745 | break; | |
746 | } | |
747 | ||
748 | if (ret) { | |
749 | /* revert the already done pin settings */ | |
750 | for (cnt--; cnt >= 0; cnt--) | |
751 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
752 | ||
753 | return ret; | |
d3e51161 HS |
754 | } |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
d3e51161 HS |
759 | /* |
760 | * The calls to gpio_direction_output() and gpio_direction_input() | |
761 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
762 | * function called from the gpiolib interface). | |
763 | */ | |
764 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
765 | struct pinctrl_gpio_range *range, | |
766 | unsigned offset, bool input) | |
767 | { | |
768 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
769 | struct rockchip_pin_bank *bank; | |
770 | struct gpio_chip *chip; | |
14797189 | 771 | int pin, ret; |
d3e51161 HS |
772 | u32 data; |
773 | ||
774 | chip = range->gc; | |
775 | bank = gc_to_pin_bank(chip); | |
776 | pin = offset - chip->base; | |
777 | ||
778 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
779 | offset, range->name, pin, input ? "input" : "output"); | |
780 | ||
14797189 HS |
781 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
782 | if (ret < 0) | |
783 | return ret; | |
d3e51161 HS |
784 | |
785 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
786 | /* set bit to 1 for output, 0 for input */ | |
787 | if (!input) | |
788 | data |= BIT(pin); | |
789 | else | |
790 | data &= ~BIT(pin); | |
791 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
792 | ||
793 | return 0; | |
794 | } | |
795 | ||
796 | static const struct pinmux_ops rockchip_pmx_ops = { | |
797 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
798 | .get_function_name = rockchip_pmx_get_func_name, | |
799 | .get_function_groups = rockchip_pmx_get_groups, | |
800 | .enable = rockchip_pmx_enable, | |
d3e51161 HS |
801 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
802 | }; | |
803 | ||
804 | /* | |
805 | * Pinconf_ops handling | |
806 | */ | |
807 | ||
44b6d930 HS |
808 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
809 | enum pin_config_param pull) | |
810 | { | |
a282926d HS |
811 | switch (ctrl->type) { |
812 | case RK2928: | |
813 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || | |
814 | pull == PIN_CONFIG_BIAS_DISABLE); | |
815 | case RK3066B: | |
44b6d930 | 816 | return pull ? false : true; |
a282926d | 817 | case RK3188: |
66d750e1 | 818 | case RK3288: |
a282926d | 819 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); |
44b6d930 HS |
820 | } |
821 | ||
a282926d | 822 | return false; |
44b6d930 HS |
823 | } |
824 | ||
a076e2ed HS |
825 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, |
826 | unsigned offset, int value); | |
827 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); | |
828 | ||
d3e51161 HS |
829 | /* set the pin config settings for a specified pin */ |
830 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 831 | unsigned long *configs, unsigned num_configs) |
d3e51161 HS |
832 | { |
833 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
834 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
03b054e9 SY |
835 | enum pin_config_param param; |
836 | u16 arg; | |
837 | int i; | |
838 | int rc; | |
839 | ||
840 | for (i = 0; i < num_configs; i++) { | |
841 | param = pinconf_to_config_param(configs[i]); | |
842 | arg = pinconf_to_config_argument(configs[i]); | |
843 | ||
844 | switch (param) { | |
845 | case PIN_CONFIG_BIAS_DISABLE: | |
846 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
847 | param); | |
848 | if (rc) | |
849 | return rc; | |
850 | break; | |
851 | case PIN_CONFIG_BIAS_PULL_UP: | |
852 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
853 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 854 | case PIN_CONFIG_BIAS_BUS_HOLD: |
03b054e9 SY |
855 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
856 | return -ENOTSUPP; | |
857 | ||
858 | if (!arg) | |
859 | return -EINVAL; | |
860 | ||
861 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
862 | param); | |
863 | if (rc) | |
864 | return rc; | |
865 | break; | |
a076e2ed HS |
866 | case PIN_CONFIG_OUTPUT: |
867 | rc = rockchip_gpio_direction_output(&bank->gpio_chip, | |
868 | pin - bank->pin_base, | |
869 | arg); | |
870 | if (rc) | |
871 | return rc; | |
872 | break; | |
03b054e9 | 873 | default: |
44b6d930 | 874 | return -ENOTSUPP; |
03b054e9 SY |
875 | break; |
876 | } | |
877 | } /* for each config */ | |
d3e51161 HS |
878 | |
879 | return 0; | |
880 | } | |
881 | ||
882 | /* get the pin config settings for a specified pin */ | |
883 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
884 | unsigned long *config) | |
885 | { | |
886 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
887 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
888 | enum pin_config_param param = pinconf_to_config_param(*config); | |
dab3eba7 | 889 | u16 arg; |
a076e2ed | 890 | int rc; |
d3e51161 HS |
891 | |
892 | switch (param) { | |
893 | case PIN_CONFIG_BIAS_DISABLE: | |
44b6d930 HS |
894 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
895 | return -EINVAL; | |
896 | ||
dab3eba7 | 897 | arg = 0; |
44b6d930 | 898 | break; |
d3e51161 HS |
899 | case PIN_CONFIG_BIAS_PULL_UP: |
900 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
901 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 902 | case PIN_CONFIG_BIAS_BUS_HOLD: |
44b6d930 HS |
903 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
904 | return -ENOTSUPP; | |
d3e51161 | 905 | |
44b6d930 | 906 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
d3e51161 HS |
907 | return -EINVAL; |
908 | ||
dab3eba7 | 909 | arg = 1; |
d3e51161 | 910 | break; |
a076e2ed HS |
911 | case PIN_CONFIG_OUTPUT: |
912 | rc = rockchip_get_mux(bank, pin - bank->pin_base); | |
913 | if (rc != RK_FUNC_GPIO) | |
914 | return -EINVAL; | |
915 | ||
916 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); | |
917 | if (rc < 0) | |
918 | return rc; | |
919 | ||
920 | arg = rc ? 1 : 0; | |
921 | break; | |
d3e51161 HS |
922 | default: |
923 | return -ENOTSUPP; | |
924 | break; | |
925 | } | |
926 | ||
dab3eba7 HS |
927 | *config = pinconf_to_config_packed(param, arg); |
928 | ||
d3e51161 HS |
929 | return 0; |
930 | } | |
931 | ||
932 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
933 | .pin_config_get = rockchip_pinconf_get, | |
934 | .pin_config_set = rockchip_pinconf_set, | |
ed62f2f2 | 935 | .is_generic = true, |
d3e51161 HS |
936 | }; |
937 | ||
65fca613 HS |
938 | static const struct of_device_id rockchip_bank_match[] = { |
939 | { .compatible = "rockchip,gpio-bank" }, | |
6ca5274d | 940 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
65fca613 HS |
941 | {}, |
942 | }; | |
d3e51161 HS |
943 | |
944 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
945 | struct device_node *np) | |
946 | { | |
947 | struct device_node *child; | |
948 | ||
949 | for_each_child_of_node(np, child) { | |
65fca613 | 950 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 HS |
951 | continue; |
952 | ||
953 | info->nfunctions++; | |
954 | info->ngroups += of_get_child_count(child); | |
955 | } | |
956 | } | |
957 | ||
958 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
959 | struct rockchip_pin_group *grp, | |
960 | struct rockchip_pinctrl *info, | |
961 | u32 index) | |
962 | { | |
963 | struct rockchip_pin_bank *bank; | |
964 | int size; | |
965 | const __be32 *list; | |
966 | int num; | |
967 | int i, j; | |
968 | int ret; | |
969 | ||
970 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
971 | ||
972 | /* Initialise group */ | |
973 | grp->name = np->name; | |
974 | ||
975 | /* | |
976 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
977 | * do sanity check and calculate pins number | |
978 | */ | |
979 | list = of_get_property(np, "rockchip,pins", &size); | |
980 | /* we do not check return since it's safe node passed down */ | |
981 | size /= sizeof(*list); | |
982 | if (!size || size % 4) { | |
983 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
984 | return -EINVAL; | |
985 | } | |
986 | ||
987 | grp->npins = size / 4; | |
988 | ||
989 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
990 | GFP_KERNEL); | |
991 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
992 | sizeof(struct rockchip_pin_config), | |
993 | GFP_KERNEL); | |
994 | if (!grp->pins || !grp->data) | |
995 | return -ENOMEM; | |
996 | ||
997 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
998 | const __be32 *phandle; | |
999 | struct device_node *np_config; | |
1000 | ||
1001 | num = be32_to_cpu(*list++); | |
1002 | bank = bank_num_to_bank(info, num); | |
1003 | if (IS_ERR(bank)) | |
1004 | return PTR_ERR(bank); | |
1005 | ||
1006 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
1007 | grp->data[j].func = be32_to_cpu(*list++); | |
1008 | ||
1009 | phandle = list++; | |
1010 | if (!phandle) | |
1011 | return -EINVAL; | |
1012 | ||
1013 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
1014 | ret = pinconf_generic_parse_dt_config(np_config, | |
1015 | &grp->data[j].configs, &grp->data[j].nconfigs); | |
1016 | if (ret) | |
1017 | return ret; | |
1018 | } | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
1024 | struct rockchip_pinctrl *info, | |
1025 | u32 index) | |
1026 | { | |
1027 | struct device_node *child; | |
1028 | struct rockchip_pmx_func *func; | |
1029 | struct rockchip_pin_group *grp; | |
1030 | int ret; | |
1031 | static u32 grp_index; | |
1032 | u32 i = 0; | |
1033 | ||
1034 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
1035 | ||
1036 | func = &info->functions[index]; | |
1037 | ||
1038 | /* Initialise function */ | |
1039 | func->name = np->name; | |
1040 | func->ngroups = of_get_child_count(np); | |
1041 | if (func->ngroups <= 0) | |
1042 | return 0; | |
1043 | ||
1044 | func->groups = devm_kzalloc(info->dev, | |
1045 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
1046 | if (!func->groups) | |
1047 | return -ENOMEM; | |
1048 | ||
1049 | for_each_child_of_node(np, child) { | |
1050 | func->groups[i] = child->name; | |
1051 | grp = &info->groups[grp_index++]; | |
1052 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
1053 | if (ret) | |
1054 | return ret; | |
1055 | } | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
1061 | struct rockchip_pinctrl *info) | |
1062 | { | |
1063 | struct device *dev = &pdev->dev; | |
1064 | struct device_node *np = dev->of_node; | |
1065 | struct device_node *child; | |
1066 | int ret; | |
1067 | int i; | |
1068 | ||
1069 | rockchip_pinctrl_child_count(info, np); | |
1070 | ||
1071 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
1072 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
1073 | ||
1074 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
1075 | sizeof(struct rockchip_pmx_func), | |
1076 | GFP_KERNEL); | |
1077 | if (!info->functions) { | |
1078 | dev_err(dev, "failed to allocate memory for function list\n"); | |
1079 | return -EINVAL; | |
1080 | } | |
1081 | ||
1082 | info->groups = devm_kzalloc(dev, info->ngroups * | |
1083 | sizeof(struct rockchip_pin_group), | |
1084 | GFP_KERNEL); | |
1085 | if (!info->groups) { | |
1086 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
1087 | return -EINVAL; | |
1088 | } | |
1089 | ||
1090 | i = 0; | |
1091 | ||
1092 | for_each_child_of_node(np, child) { | |
65fca613 | 1093 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 | 1094 | continue; |
65fca613 | 1095 | |
d3e51161 HS |
1096 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
1097 | if (ret) { | |
1098 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1099 | return ret; | |
1100 | } | |
1101 | } | |
1102 | ||
1103 | return 0; | |
1104 | } | |
1105 | ||
1106 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
1107 | struct rockchip_pinctrl *info) | |
1108 | { | |
1109 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
1110 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
1111 | struct rockchip_pin_bank *pin_bank; | |
1112 | int pin, bank, ret; | |
1113 | int k; | |
1114 | ||
1115 | ctrldesc->name = "rockchip-pinctrl"; | |
1116 | ctrldesc->owner = THIS_MODULE; | |
1117 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
1118 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
1119 | ctrldesc->confops = &rockchip_pinconf_ops; | |
1120 | ||
1121 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
1122 | info->ctrl->nr_pins, GFP_KERNEL); | |
1123 | if (!pindesc) { | |
1124 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
1125 | return -ENOMEM; | |
1126 | } | |
1127 | ctrldesc->pins = pindesc; | |
1128 | ctrldesc->npins = info->ctrl->nr_pins; | |
1129 | ||
1130 | pdesc = pindesc; | |
1131 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
1132 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1133 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
1134 | pdesc->number = k; | |
1135 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
1136 | pin_bank->name, pin); | |
1137 | pdesc++; | |
1138 | } | |
1139 | } | |
1140 | ||
1141 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); | |
1142 | if (!info->pctl_dev) { | |
1143 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); | |
1144 | return -EINVAL; | |
1145 | } | |
1146 | ||
1147 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
1148 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1149 | pin_bank->grange.name = pin_bank->name; | |
1150 | pin_bank->grange.id = bank; | |
1151 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
1152 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
1153 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
1154 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
1155 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
1156 | } | |
1157 | ||
1158 | ret = rockchip_pinctrl_parse_dt(pdev, info); | |
1159 | if (ret) { | |
1160 | pinctrl_unregister(info->pctl_dev); | |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | return 0; | |
1165 | } | |
1166 | ||
1167 | /* | |
1168 | * GPIO handling | |
1169 | */ | |
1170 | ||
0351c287 AL |
1171 | static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) |
1172 | { | |
1173 | return pinctrl_request_gpio(chip->base + offset); | |
1174 | } | |
1175 | ||
1176 | static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1177 | { | |
1178 | pinctrl_free_gpio(chip->base + offset); | |
1179 | } | |
1180 | ||
d3e51161 HS |
1181 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) |
1182 | { | |
1183 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1184 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
1185 | unsigned long flags; | |
1186 | u32 data; | |
1187 | ||
1188 | spin_lock_irqsave(&bank->slock, flags); | |
1189 | ||
1190 | data = readl(reg); | |
1191 | data &= ~BIT(offset); | |
1192 | if (value) | |
1193 | data |= BIT(offset); | |
1194 | writel(data, reg); | |
1195 | ||
1196 | spin_unlock_irqrestore(&bank->slock, flags); | |
1197 | } | |
1198 | ||
1199 | /* | |
1200 | * Returns the level of the pin for input direction and setting of the DR | |
1201 | * register for output gpios. | |
1202 | */ | |
1203 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
1204 | { | |
1205 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1206 | u32 data; | |
1207 | ||
1208 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1209 | data >>= offset; | |
1210 | data &= 1; | |
1211 | return data; | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
1216 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
1217 | * interface. | |
1218 | */ | |
1219 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
1220 | { | |
1221 | return pinctrl_gpio_direction_input(gc->base + offset); | |
1222 | } | |
1223 | ||
1224 | /* | |
1225 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
1226 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
1227 | * interface. | |
1228 | */ | |
1229 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
1230 | unsigned offset, int value) | |
1231 | { | |
1232 | rockchip_gpio_set(gc, offset, value); | |
1233 | return pinctrl_gpio_direction_output(gc->base + offset); | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
1238 | * and a virtual IRQ, if not already present. | |
1239 | */ | |
1240 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
1241 | { | |
1242 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1243 | unsigned int virq; | |
1244 | ||
1245 | if (!bank->domain) | |
1246 | return -ENXIO; | |
1247 | ||
1248 | virq = irq_create_mapping(bank->domain, offset); | |
1249 | ||
1250 | return (virq) ? : -ENXIO; | |
1251 | } | |
1252 | ||
1253 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
0351c287 AL |
1254 | .request = rockchip_gpio_request, |
1255 | .free = rockchip_gpio_free, | |
d3e51161 HS |
1256 | .set = rockchip_gpio_set, |
1257 | .get = rockchip_gpio_get, | |
1258 | .direction_input = rockchip_gpio_direction_input, | |
1259 | .direction_output = rockchip_gpio_direction_output, | |
1260 | .to_irq = rockchip_gpio_to_irq, | |
1261 | .owner = THIS_MODULE, | |
1262 | }; | |
1263 | ||
1264 | /* | |
1265 | * Interrupt handling | |
1266 | */ | |
1267 | ||
1268 | static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) | |
1269 | { | |
1270 | struct irq_chip *chip = irq_get_chip(irq); | |
1271 | struct rockchip_pin_bank *bank = irq_get_handler_data(irq); | |
5a927501 | 1272 | u32 polarity = 0, data = 0; |
d3e51161 | 1273 | u32 pend; |
5a927501 | 1274 | bool edge_changed = false; |
d3e51161 HS |
1275 | |
1276 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
1277 | ||
1278 | chained_irq_enter(chip, desc); | |
1279 | ||
1280 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
1281 | ||
5a927501 HS |
1282 | if (bank->toggle_edge_mode) { |
1283 | polarity = readl_relaxed(bank->reg_base + | |
1284 | GPIO_INT_POLARITY); | |
1285 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); | |
1286 | } | |
1287 | ||
d3e51161 HS |
1288 | while (pend) { |
1289 | unsigned int virq; | |
1290 | ||
1291 | irq = __ffs(pend); | |
1292 | pend &= ~BIT(irq); | |
1293 | virq = irq_linear_revmap(bank->domain, irq); | |
1294 | ||
1295 | if (!virq) { | |
1296 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
1297 | continue; | |
1298 | } | |
1299 | ||
1300 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
1301 | ||
5a927501 HS |
1302 | /* |
1303 | * Triggering IRQ on both rising and falling edge | |
1304 | * needs manual intervention. | |
1305 | */ | |
1306 | if (bank->toggle_edge_mode & BIT(irq)) { | |
1307 | if (data & BIT(irq)) | |
1308 | polarity &= ~BIT(irq); | |
1309 | else | |
1310 | polarity |= BIT(irq); | |
1311 | ||
1312 | edge_changed = true; | |
1313 | } | |
1314 | ||
d3e51161 HS |
1315 | generic_handle_irq(virq); |
1316 | } | |
1317 | ||
5a927501 HS |
1318 | if (bank->toggle_edge_mode && edge_changed) { |
1319 | /* Interrupt params should only be set with ints disabled */ | |
1320 | data = readl_relaxed(bank->reg_base + GPIO_INTEN); | |
1321 | writel_relaxed(0, bank->reg_base + GPIO_INTEN); | |
1322 | writel(polarity, bank->reg_base + GPIO_INT_POLARITY); | |
1323 | writel(data, bank->reg_base + GPIO_INTEN); | |
1324 | } | |
1325 | ||
d3e51161 HS |
1326 | chained_irq_exit(chip, desc); |
1327 | } | |
1328 | ||
1329 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
1330 | { | |
1331 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1332 | struct rockchip_pin_bank *bank = gc->private; | |
1333 | u32 mask = BIT(d->hwirq); | |
1334 | u32 polarity; | |
1335 | u32 level; | |
1336 | u32 data; | |
14797189 | 1337 | int ret; |
d3e51161 | 1338 | |
5a927501 | 1339 | /* make sure the pin is configured as gpio input */ |
14797189 HS |
1340 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
1341 | if (ret < 0) | |
1342 | return ret; | |
1343 | ||
5a927501 HS |
1344 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
1345 | data &= ~mask; | |
1346 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1347 | ||
d3e51161 HS |
1348 | if (type & IRQ_TYPE_EDGE_BOTH) |
1349 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
1350 | else | |
1351 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
1352 | ||
1353 | irq_gc_lock(gc); | |
1354 | ||
1355 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1356 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
1357 | ||
1358 | switch (type) { | |
5a927501 HS |
1359 | case IRQ_TYPE_EDGE_BOTH: |
1360 | bank->toggle_edge_mode |= mask; | |
1361 | level |= mask; | |
1362 | ||
1363 | /* | |
1364 | * Determine gpio state. If 1 next interrupt should be falling | |
1365 | * otherwise rising. | |
1366 | */ | |
1367 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1368 | if (data & mask) | |
1369 | polarity &= ~mask; | |
1370 | else | |
1371 | polarity |= mask; | |
1372 | break; | |
d3e51161 | 1373 | case IRQ_TYPE_EDGE_RISING: |
5a927501 | 1374 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1375 | level |= mask; |
1376 | polarity |= mask; | |
1377 | break; | |
1378 | case IRQ_TYPE_EDGE_FALLING: | |
5a927501 | 1379 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1380 | level |= mask; |
1381 | polarity &= ~mask; | |
1382 | break; | |
1383 | case IRQ_TYPE_LEVEL_HIGH: | |
5a927501 | 1384 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1385 | level &= ~mask; |
1386 | polarity |= mask; | |
1387 | break; | |
1388 | case IRQ_TYPE_LEVEL_LOW: | |
5a927501 | 1389 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1390 | level &= ~mask; |
1391 | polarity &= ~mask; | |
1392 | break; | |
1393 | default: | |
7cc5f970 | 1394 | irq_gc_unlock(gc); |
d3e51161 HS |
1395 | return -EINVAL; |
1396 | } | |
1397 | ||
1398 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1399 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1400 | ||
1401 | irq_gc_unlock(gc); | |
1402 | ||
d3e51161 HS |
1403 | return 0; |
1404 | } | |
1405 | ||
1406 | static int rockchip_interrupts_register(struct platform_device *pdev, | |
1407 | struct rockchip_pinctrl *info) | |
1408 | { | |
1409 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1410 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1411 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1412 | struct irq_chip_generic *gc; | |
1413 | int ret; | |
1414 | int i; | |
1415 | ||
1416 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1417 | if (!bank->valid) { | |
1418 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1419 | bank->name); | |
1420 | continue; | |
1421 | } | |
1422 | ||
1423 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
1424 | &irq_generic_chip_ops, NULL); | |
1425 | if (!bank->domain) { | |
1426 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1427 | bank->name); | |
1428 | continue; | |
1429 | } | |
1430 | ||
1431 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1432 | "rockchip_gpio_irq", handle_level_irq, | |
1433 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1434 | if (ret) { | |
1435 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1436 | bank->name); | |
1437 | irq_domain_remove(bank->domain); | |
1438 | continue; | |
1439 | } | |
1440 | ||
1441 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
1442 | gc->reg_base = bank->reg_base; | |
1443 | gc->private = bank; | |
1444 | gc->chip_types[0].regs.mask = GPIO_INTEN; | |
1445 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; | |
1446 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
1447 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
1448 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
1449 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
1450 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
1451 | ||
1452 | irq_set_handler_data(bank->irq, bank); | |
1453 | irq_set_chained_handler(bank->irq, rockchip_irq_demux); | |
1454 | } | |
1455 | ||
1456 | return 0; | |
1457 | } | |
1458 | ||
1459 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1460 | struct rockchip_pinctrl *info) | |
1461 | { | |
1462 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1463 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1464 | struct gpio_chip *gc; | |
1465 | int ret; | |
1466 | int i; | |
1467 | ||
1468 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1469 | if (!bank->valid) { | |
1470 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1471 | bank->name); | |
1472 | continue; | |
1473 | } | |
1474 | ||
1475 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1476 | ||
1477 | gc = &bank->gpio_chip; | |
1478 | gc->base = bank->pin_base; | |
1479 | gc->ngpio = bank->nr_pins; | |
1480 | gc->dev = &pdev->dev; | |
1481 | gc->of_node = bank->of_node; | |
1482 | gc->label = bank->name; | |
1483 | ||
1484 | ret = gpiochip_add(gc); | |
1485 | if (ret) { | |
1486 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1487 | gc->label, ret); | |
1488 | goto fail; | |
1489 | } | |
1490 | } | |
1491 | ||
1492 | rockchip_interrupts_register(pdev, info); | |
1493 | ||
1494 | return 0; | |
1495 | ||
1496 | fail: | |
1497 | for (--i, --bank; i >= 0; --i, --bank) { | |
1498 | if (!bank->valid) | |
1499 | continue; | |
b4e7c55d | 1500 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1501 | } |
1502 | return ret; | |
1503 | } | |
1504 | ||
1505 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1506 | struct rockchip_pinctrl *info) | |
1507 | { | |
1508 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1509 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
d3e51161 HS |
1510 | int i; |
1511 | ||
b4e7c55d | 1512 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { |
d3e51161 HS |
1513 | if (!bank->valid) |
1514 | continue; | |
b4e7c55d | 1515 | gpiochip_remove(&bank->gpio_chip); |
d3e51161 HS |
1516 | } |
1517 | ||
b4e7c55d | 1518 | return 0; |
d3e51161 HS |
1519 | } |
1520 | ||
1521 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
622f3237 | 1522 | struct rockchip_pinctrl *info) |
d3e51161 HS |
1523 | { |
1524 | struct resource res; | |
751a99ab | 1525 | void __iomem *base; |
d3e51161 HS |
1526 | |
1527 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
622f3237 | 1528 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
d3e51161 HS |
1529 | return -ENOENT; |
1530 | } | |
1531 | ||
622f3237 | 1532 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
d3e51161 HS |
1533 | if (IS_ERR(bank->reg_base)) |
1534 | return PTR_ERR(bank->reg_base); | |
1535 | ||
6ca5274d HS |
1536 | /* |
1537 | * special case, where parts of the pull setting-registers are | |
1538 | * part of the PMU register space | |
1539 | */ | |
1540 | if (of_device_is_compatible(bank->of_node, | |
1541 | "rockchip,rk3188-gpio-bank0")) { | |
a658efaa | 1542 | struct device_node *node; |
bfc7a42a | 1543 | |
a658efaa HS |
1544 | node = of_parse_phandle(bank->of_node->parent, |
1545 | "rockchip,pmu", 0); | |
1546 | if (!node) { | |
1547 | if (of_address_to_resource(bank->of_node, 1, &res)) { | |
1548 | dev_err(info->dev, "cannot find IO resource for bank\n"); | |
1549 | return -ENOENT; | |
1550 | } | |
1551 | ||
1552 | base = devm_ioremap_resource(info->dev, &res); | |
1553 | if (IS_ERR(base)) | |
1554 | return PTR_ERR(base); | |
1555 | rockchip_regmap_config.max_register = | |
1556 | resource_size(&res) - 4; | |
1557 | rockchip_regmap_config.name = | |
1558 | "rockchip,rk3188-gpio-bank0-pull"; | |
1559 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, | |
1560 | base, | |
1561 | &rockchip_regmap_config); | |
6ca5274d | 1562 | } |
6ca5274d | 1563 | } |
65fca613 | 1564 | |
d3e51161 HS |
1565 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
1566 | ||
1567 | bank->clk = of_clk_get(bank->of_node, 0); | |
1568 | if (IS_ERR(bank->clk)) | |
1569 | return PTR_ERR(bank->clk); | |
1570 | ||
1571 | return clk_prepare_enable(bank->clk); | |
1572 | } | |
1573 | ||
1574 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1575 | ||
1576 | /* retrieve the soc specific data */ | |
1577 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1578 | struct rockchip_pinctrl *d, | |
1579 | struct platform_device *pdev) | |
1580 | { | |
1581 | const struct of_device_id *match; | |
1582 | struct device_node *node = pdev->dev.of_node; | |
1583 | struct device_node *np; | |
1584 | struct rockchip_pin_ctrl *ctrl; | |
1585 | struct rockchip_pin_bank *bank; | |
95ec8ae4 | 1586 | int grf_offs, pmu_offs, i, j; |
d3e51161 HS |
1587 | |
1588 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1589 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1590 | ||
1591 | for_each_child_of_node(node, np) { | |
1592 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1593 | continue; | |
1594 | ||
1595 | bank = ctrl->pin_banks; | |
1596 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1597 | if (!strcmp(bank->name, np->name)) { | |
1598 | bank->of_node = np; | |
1599 | ||
622f3237 | 1600 | if (!rockchip_get_bank_data(bank, d)) |
d3e51161 HS |
1601 | bank->valid = true; |
1602 | ||
1603 | break; | |
1604 | } | |
1605 | } | |
1606 | } | |
1607 | ||
95ec8ae4 HS |
1608 | grf_offs = ctrl->grf_mux_offset; |
1609 | pmu_offs = ctrl->pmu_mux_offset; | |
d3e51161 HS |
1610 | bank = ctrl->pin_banks; |
1611 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
6bc0d121 HS |
1612 | int bank_pins = 0; |
1613 | ||
d3e51161 HS |
1614 | spin_lock_init(&bank->slock); |
1615 | bank->drvdata = d; | |
1616 | bank->pin_base = ctrl->nr_pins; | |
1617 | ctrl->nr_pins += bank->nr_pins; | |
6bc0d121 HS |
1618 | |
1619 | /* calculate iomux offsets */ | |
1620 | for (j = 0; j < 4; j++) { | |
1621 | struct rockchip_iomux *iom = &bank->iomux[j]; | |
03716e1d | 1622 | int inc; |
6bc0d121 HS |
1623 | |
1624 | if (bank_pins >= bank->nr_pins) | |
1625 | break; | |
1626 | ||
1627 | /* preset offset value, set new start value */ | |
1628 | if (iom->offset >= 0) { | |
95ec8ae4 HS |
1629 | if (iom->type & IOMUX_SOURCE_PMU) |
1630 | pmu_offs = iom->offset; | |
1631 | else | |
1632 | grf_offs = iom->offset; | |
6bc0d121 | 1633 | } else { /* set current offset */ |
95ec8ae4 HS |
1634 | iom->offset = (iom->type & IOMUX_SOURCE_PMU) ? |
1635 | pmu_offs : grf_offs; | |
6bc0d121 HS |
1636 | } |
1637 | ||
1638 | dev_dbg(d->dev, "bank %d, iomux %d has offset 0x%x\n", | |
1639 | i, j, iom->offset); | |
1640 | ||
1641 | /* | |
1642 | * Increase offset according to iomux width. | |
03716e1d | 1643 | * 4bit iomux'es are spread over two registers. |
6bc0d121 | 1644 | */ |
03716e1d | 1645 | inc = (iom->type & IOMUX_WIDTH_4BIT) ? 8 : 4; |
95ec8ae4 HS |
1646 | if (iom->type & IOMUX_SOURCE_PMU) |
1647 | pmu_offs += inc; | |
1648 | else | |
1649 | grf_offs += inc; | |
6bc0d121 HS |
1650 | |
1651 | bank_pins += 8; | |
1652 | } | |
d3e51161 HS |
1653 | } |
1654 | ||
1655 | return ctrl; | |
1656 | } | |
1657 | ||
1658 | static int rockchip_pinctrl_probe(struct platform_device *pdev) | |
1659 | { | |
1660 | struct rockchip_pinctrl *info; | |
1661 | struct device *dev = &pdev->dev; | |
1662 | struct rockchip_pin_ctrl *ctrl; | |
14dee867 | 1663 | struct device_node *np = pdev->dev.of_node, *node; |
d3e51161 | 1664 | struct resource *res; |
751a99ab | 1665 | void __iomem *base; |
d3e51161 HS |
1666 | int ret; |
1667 | ||
1668 | if (!dev->of_node) { | |
1669 | dev_err(dev, "device tree node not found\n"); | |
1670 | return -ENODEV; | |
1671 | } | |
1672 | ||
1673 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1674 | if (!info) | |
1675 | return -ENOMEM; | |
1676 | ||
622f3237 HS |
1677 | info->dev = dev; |
1678 | ||
d3e51161 HS |
1679 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
1680 | if (!ctrl) { | |
1681 | dev_err(dev, "driver data not available\n"); | |
1682 | return -EINVAL; | |
1683 | } | |
1684 | info->ctrl = ctrl; | |
d3e51161 | 1685 | |
1e747e59 HS |
1686 | node = of_parse_phandle(np, "rockchip,grf", 0); |
1687 | if (node) { | |
1688 | info->regmap_base = syscon_node_to_regmap(node); | |
1689 | if (IS_ERR(info->regmap_base)) | |
1690 | return PTR_ERR(info->regmap_base); | |
1691 | } else { | |
1692 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751a99ab HS |
1693 | base = devm_ioremap_resource(&pdev->dev, res); |
1694 | if (IS_ERR(base)) | |
1695 | return PTR_ERR(base); | |
1696 | ||
1697 | rockchip_regmap_config.max_register = resource_size(res) - 4; | |
1e747e59 HS |
1698 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
1699 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, | |
1700 | &rockchip_regmap_config); | |
1701 | ||
1702 | /* to check for the old dt-bindings */ | |
1703 | info->reg_size = resource_size(res); | |
1704 | ||
1705 | /* Honor the old binding, with pull registers as 2nd resource */ | |
1706 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { | |
1707 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1708 | base = devm_ioremap_resource(&pdev->dev, res); | |
1709 | if (IS_ERR(base)) | |
1710 | return PTR_ERR(base); | |
1711 | ||
1712 | rockchip_regmap_config.max_register = | |
1713 | resource_size(res) - 4; | |
1714 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; | |
1715 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, | |
1716 | base, | |
1717 | &rockchip_regmap_config); | |
1718 | } | |
6ca5274d HS |
1719 | } |
1720 | ||
14dee867 HS |
1721 | /* try to find the optional reference to the pmu syscon */ |
1722 | node = of_parse_phandle(np, "rockchip,pmu", 0); | |
1723 | if (node) { | |
1724 | info->regmap_pmu = syscon_node_to_regmap(node); | |
1725 | if (IS_ERR(info->regmap_pmu)) | |
1726 | return PTR_ERR(info->regmap_pmu); | |
1727 | } | |
1728 | ||
d3e51161 HS |
1729 | ret = rockchip_gpiolib_register(pdev, info); |
1730 | if (ret) | |
1731 | return ret; | |
1732 | ||
1733 | ret = rockchip_pinctrl_register(pdev, info); | |
1734 | if (ret) { | |
1735 | rockchip_gpiolib_unregister(pdev, info); | |
1736 | return ret; | |
1737 | } | |
1738 | ||
1739 | platform_set_drvdata(pdev, info); | |
1740 | ||
1741 | return 0; | |
1742 | } | |
1743 | ||
1744 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
1745 | PIN_BANK(0, 32, "gpio0"), | |
1746 | PIN_BANK(1, 32, "gpio1"), | |
1747 | PIN_BANK(2, 32, "gpio2"), | |
1748 | PIN_BANK(3, 32, "gpio3"), | |
1749 | }; | |
1750 | ||
1751 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
1752 | .pin_banks = rk2928_pin_banks, | |
1753 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
1754 | .label = "RK2928-GPIO", | |
a282926d | 1755 | .type = RK2928, |
95ec8ae4 | 1756 | .grf_mux_offset = 0xa8, |
a282926d | 1757 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1758 | }; |
1759 | ||
1760 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { | |
1761 | PIN_BANK(0, 32, "gpio0"), | |
1762 | PIN_BANK(1, 32, "gpio1"), | |
1763 | PIN_BANK(2, 32, "gpio2"), | |
1764 | PIN_BANK(3, 32, "gpio3"), | |
1765 | PIN_BANK(4, 32, "gpio4"), | |
1766 | PIN_BANK(6, 16, "gpio6"), | |
1767 | }; | |
1768 | ||
1769 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
1770 | .pin_banks = rk3066a_pin_banks, | |
1771 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
1772 | .label = "RK3066a-GPIO", | |
a282926d | 1773 | .type = RK2928, |
95ec8ae4 | 1774 | .grf_mux_offset = 0xa8, |
a282926d | 1775 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1776 | }; |
1777 | ||
1778 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
1779 | PIN_BANK(0, 32, "gpio0"), | |
1780 | PIN_BANK(1, 32, "gpio1"), | |
1781 | PIN_BANK(2, 32, "gpio2"), | |
1782 | PIN_BANK(3, 32, "gpio3"), | |
1783 | }; | |
1784 | ||
1785 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
1786 | .pin_banks = rk3066b_pin_banks, | |
1787 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
1788 | .label = "RK3066b-GPIO", | |
a282926d | 1789 | .type = RK3066B, |
95ec8ae4 | 1790 | .grf_mux_offset = 0x60, |
d3e51161 HS |
1791 | }; |
1792 | ||
1793 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
fc72c923 | 1794 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
d3e51161 HS |
1795 | PIN_BANK(1, 32, "gpio1"), |
1796 | PIN_BANK(2, 32, "gpio2"), | |
1797 | PIN_BANK(3, 32, "gpio3"), | |
1798 | }; | |
1799 | ||
1800 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
1801 | .pin_banks = rk3188_pin_banks, | |
1802 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
1803 | .label = "RK3188-GPIO", | |
a282926d | 1804 | .type = RK3188, |
95ec8ae4 | 1805 | .grf_mux_offset = 0x60, |
6ca5274d | 1806 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
d3e51161 HS |
1807 | }; |
1808 | ||
304f077d HS |
1809 | static struct rockchip_pin_bank rk3288_pin_banks[] = { |
1810 | PIN_BANK_IOMUX_FLAGS(0, 24, "gpio0", IOMUX_SOURCE_PMU, | |
1811 | IOMUX_SOURCE_PMU, | |
1812 | IOMUX_SOURCE_PMU, | |
1813 | IOMUX_UNROUTED | |
1814 | ), | |
1815 | PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_UNROUTED, | |
1816 | IOMUX_UNROUTED, | |
1817 | IOMUX_UNROUTED, | |
1818 | 0 | |
1819 | ), | |
1820 | PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, 0, 0, IOMUX_UNROUTED), | |
1821 | PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", 0, 0, 0, IOMUX_WIDTH_4BIT), | |
1822 | PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT, | |
1823 | IOMUX_WIDTH_4BIT, | |
1824 | 0, | |
1825 | 0 | |
1826 | ), | |
1827 | PIN_BANK_IOMUX_FLAGS(5, 32, "gpio5", IOMUX_UNROUTED, | |
1828 | 0, | |
1829 | 0, | |
1830 | IOMUX_UNROUTED | |
1831 | ), | |
1832 | PIN_BANK_IOMUX_FLAGS(6, 32, "gpio6", 0, 0, 0, IOMUX_UNROUTED), | |
1833 | PIN_BANK_IOMUX_FLAGS(7, 32, "gpio7", 0, | |
1834 | 0, | |
1835 | IOMUX_WIDTH_4BIT, | |
1836 | IOMUX_UNROUTED | |
1837 | ), | |
1838 | PIN_BANK(8, 16, "gpio8"), | |
1839 | }; | |
1840 | ||
1841 | static struct rockchip_pin_ctrl rk3288_pin_ctrl = { | |
1842 | .pin_banks = rk3288_pin_banks, | |
1843 | .nr_banks = ARRAY_SIZE(rk3288_pin_banks), | |
1844 | .label = "RK3288-GPIO", | |
66d750e1 | 1845 | .type = RK3288, |
304f077d HS |
1846 | .grf_mux_offset = 0x0, |
1847 | .pmu_mux_offset = 0x84, | |
1848 | .pull_calc_reg = rk3288_calc_pull_reg_and_bit, | |
1849 | }; | |
1850 | ||
d3e51161 HS |
1851 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { |
1852 | { .compatible = "rockchip,rk2928-pinctrl", | |
1853 | .data = (void *)&rk2928_pin_ctrl }, | |
1854 | { .compatible = "rockchip,rk3066a-pinctrl", | |
1855 | .data = (void *)&rk3066a_pin_ctrl }, | |
1856 | { .compatible = "rockchip,rk3066b-pinctrl", | |
1857 | .data = (void *)&rk3066b_pin_ctrl }, | |
1858 | { .compatible = "rockchip,rk3188-pinctrl", | |
1859 | .data = (void *)&rk3188_pin_ctrl }, | |
304f077d HS |
1860 | { .compatible = "rockchip,rk3288-pinctrl", |
1861 | .data = (void *)&rk3288_pin_ctrl }, | |
d3e51161 HS |
1862 | {}, |
1863 | }; | |
1864 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
1865 | ||
1866 | static struct platform_driver rockchip_pinctrl_driver = { | |
1867 | .probe = rockchip_pinctrl_probe, | |
1868 | .driver = { | |
1869 | .name = "rockchip-pinctrl", | |
1870 | .owner = THIS_MODULE, | |
0be9e70d | 1871 | .of_match_table = rockchip_pinctrl_dt_match, |
d3e51161 HS |
1872 | }, |
1873 | }; | |
1874 | ||
1875 | static int __init rockchip_pinctrl_drv_register(void) | |
1876 | { | |
1877 | return platform_driver_register(&rockchip_pinctrl_driver); | |
1878 | } | |
1879 | postcore_initcall(rockchip_pinctrl_drv_register); | |
1880 | ||
1881 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
1882 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
1883 | MODULE_LICENSE("GPL v2"); |