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d3e51161 HS |
1 | /* |
2 | * Pinctrl driver for Rockchip SoCs | |
3 | * | |
4 | * Copyright (c) 2013 MundoReader S.L. | |
5 | * Author: Heiko Stuebner <heiko@sntech.de> | |
6 | * | |
7 | * With some ideas taken from pinctrl-samsung: | |
8 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
9 | * http://www.samsung.com | |
10 | * Copyright (c) 2012 Linaro Ltd | |
11 | * http://www.linaro.org | |
12 | * | |
13 | * and pinctrl-at91: | |
14 | * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as published | |
18 | * by the Free Software Foundation. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | */ | |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/platform_device.h> | |
28 | #include <linux/io.h> | |
29 | #include <linux/bitops.h> | |
30 | #include <linux/gpio.h> | |
31 | #include <linux/of_address.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pinctrl/machine.h> | |
34 | #include <linux/pinctrl/pinconf.h> | |
35 | #include <linux/pinctrl/pinctrl.h> | |
36 | #include <linux/pinctrl/pinmux.h> | |
37 | #include <linux/pinctrl/pinconf-generic.h> | |
38 | #include <linux/irqchip/chained_irq.h> | |
7e865abb | 39 | #include <linux/clk.h> |
751a99ab | 40 | #include <linux/regmap.h> |
14dee867 | 41 | #include <linux/mfd/syscon.h> |
d3e51161 HS |
42 | #include <dt-bindings/pinctrl/rockchip.h> |
43 | ||
44 | #include "core.h" | |
45 | #include "pinconf.h" | |
46 | ||
47 | /* GPIO control registers */ | |
48 | #define GPIO_SWPORT_DR 0x00 | |
49 | #define GPIO_SWPORT_DDR 0x04 | |
50 | #define GPIO_INTEN 0x30 | |
51 | #define GPIO_INTMASK 0x34 | |
52 | #define GPIO_INTTYPE_LEVEL 0x38 | |
53 | #define GPIO_INT_POLARITY 0x3c | |
54 | #define GPIO_INT_STATUS 0x40 | |
55 | #define GPIO_INT_RAWSTATUS 0x44 | |
56 | #define GPIO_DEBOUNCE 0x48 | |
57 | #define GPIO_PORTS_EOI 0x4c | |
58 | #define GPIO_EXT_PORT 0x50 | |
59 | #define GPIO_LS_SYNC 0x60 | |
60 | ||
a282926d HS |
61 | enum rockchip_pinctrl_type { |
62 | RK2928, | |
63 | RK3066B, | |
64 | RK3188, | |
65 | }; | |
66 | ||
fc72c923 HS |
67 | /** |
68 | * Encode variants of iomux registers into a type variable | |
69 | */ | |
70 | #define IOMUX_GPIO_ONLY BIT(0) | |
71 | ||
72 | /** | |
73 | * @type: iomux variant using IOMUX_* constants | |
74 | */ | |
75 | struct rockchip_iomux { | |
76 | int type; | |
65fca613 HS |
77 | }; |
78 | ||
d3e51161 HS |
79 | /** |
80 | * @reg_base: register base of the gpio bank | |
6ca5274d | 81 | * @reg_pull: optional separate register for additional pull settings |
d3e51161 HS |
82 | * @clk: clock of the gpio bank |
83 | * @irq: interrupt of the gpio bank | |
84 | * @pin_base: first pin number | |
85 | * @nr_pins: number of pins in this bank | |
86 | * @name: name of the bank | |
87 | * @bank_num: number of the bank, to account for holes | |
fc72c923 | 88 | * @iomux: array describing the 4 iomux sources of the bank |
d3e51161 HS |
89 | * @valid: are all necessary informations present |
90 | * @of_node: dt node of this bank | |
91 | * @drvdata: common pinctrl basedata | |
92 | * @domain: irqdomain of the gpio bank | |
93 | * @gpio_chip: gpiolib chip | |
94 | * @grange: gpio range | |
95 | * @slock: spinlock for the gpio bank | |
96 | */ | |
97 | struct rockchip_pin_bank { | |
98 | void __iomem *reg_base; | |
751a99ab | 99 | struct regmap *regmap_pull; |
d3e51161 HS |
100 | struct clk *clk; |
101 | int irq; | |
102 | u32 pin_base; | |
103 | u8 nr_pins; | |
104 | char *name; | |
105 | u8 bank_num; | |
fc72c923 | 106 | struct rockchip_iomux iomux[4]; |
d3e51161 HS |
107 | bool valid; |
108 | struct device_node *of_node; | |
109 | struct rockchip_pinctrl *drvdata; | |
110 | struct irq_domain *domain; | |
111 | struct gpio_chip gpio_chip; | |
112 | struct pinctrl_gpio_range grange; | |
113 | spinlock_t slock; | |
5a927501 | 114 | u32 toggle_edge_mode; |
d3e51161 HS |
115 | }; |
116 | ||
117 | #define PIN_BANK(id, pins, label) \ | |
118 | { \ | |
119 | .bank_num = id, \ | |
120 | .nr_pins = pins, \ | |
121 | .name = label, \ | |
122 | } | |
123 | ||
fc72c923 HS |
124 | #define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ |
125 | { \ | |
126 | .bank_num = id, \ | |
127 | .nr_pins = pins, \ | |
128 | .name = label, \ | |
129 | .iomux = { \ | |
130 | { .type = iom0, }, \ | |
131 | { .type = iom1, }, \ | |
132 | { .type = iom2, }, \ | |
133 | { .type = iom3, }, \ | |
134 | }, \ | |
135 | } | |
136 | ||
d3e51161 | 137 | /** |
d3e51161 HS |
138 | */ |
139 | struct rockchip_pin_ctrl { | |
140 | struct rockchip_pin_bank *pin_banks; | |
141 | u32 nr_banks; | |
142 | u32 nr_pins; | |
143 | char *label; | |
a282926d | 144 | enum rockchip_pinctrl_type type; |
d3e51161 | 145 | int mux_offset; |
751a99ab HS |
146 | void (*pull_calc_reg)(struct rockchip_pin_bank *bank, |
147 | int pin_num, struct regmap **regmap, | |
148 | int *reg, u8 *bit); | |
d3e51161 HS |
149 | }; |
150 | ||
151 | struct rockchip_pin_config { | |
152 | unsigned int func; | |
153 | unsigned long *configs; | |
154 | unsigned int nconfigs; | |
155 | }; | |
156 | ||
157 | /** | |
158 | * struct rockchip_pin_group: represent group of pins of a pinmux function. | |
159 | * @name: name of the pin group, used to lookup the group. | |
160 | * @pins: the pins included in this group. | |
161 | * @npins: number of pins included in this group. | |
162 | * @func: the mux function number to be programmed when selected. | |
163 | * @configs: the config values to be set for each pin | |
164 | * @nconfigs: number of configs for each pin | |
165 | */ | |
166 | struct rockchip_pin_group { | |
167 | const char *name; | |
168 | unsigned int npins; | |
169 | unsigned int *pins; | |
170 | struct rockchip_pin_config *data; | |
171 | }; | |
172 | ||
173 | /** | |
174 | * struct rockchip_pmx_func: represent a pin function. | |
175 | * @name: name of the pin function, used to lookup the function. | |
176 | * @groups: one or more names of pin groups that provide this function. | |
177 | * @num_groups: number of groups included in @groups. | |
178 | */ | |
179 | struct rockchip_pmx_func { | |
180 | const char *name; | |
181 | const char **groups; | |
182 | u8 ngroups; | |
183 | }; | |
184 | ||
185 | struct rockchip_pinctrl { | |
751a99ab | 186 | struct regmap *regmap_base; |
bfc7a42a | 187 | int reg_size; |
751a99ab | 188 | struct regmap *regmap_pull; |
14dee867 | 189 | struct regmap *regmap_pmu; |
d3e51161 HS |
190 | struct device *dev; |
191 | struct rockchip_pin_ctrl *ctrl; | |
192 | struct pinctrl_desc pctl; | |
193 | struct pinctrl_dev *pctl_dev; | |
194 | struct rockchip_pin_group *groups; | |
195 | unsigned int ngroups; | |
196 | struct rockchip_pmx_func *functions; | |
197 | unsigned int nfunctions; | |
198 | }; | |
199 | ||
751a99ab HS |
200 | static struct regmap_config rockchip_regmap_config = { |
201 | .reg_bits = 32, | |
202 | .val_bits = 32, | |
203 | .reg_stride = 4, | |
204 | }; | |
205 | ||
d3e51161 HS |
206 | static inline struct rockchip_pin_bank *gc_to_pin_bank(struct gpio_chip *gc) |
207 | { | |
208 | return container_of(gc, struct rockchip_pin_bank, gpio_chip); | |
209 | } | |
210 | ||
211 | static const inline struct rockchip_pin_group *pinctrl_name_to_group( | |
212 | const struct rockchip_pinctrl *info, | |
213 | const char *name) | |
214 | { | |
d3e51161 HS |
215 | int i; |
216 | ||
217 | for (i = 0; i < info->ngroups; i++) { | |
1cb95395 AL |
218 | if (!strcmp(info->groups[i].name, name)) |
219 | return &info->groups[i]; | |
d3e51161 HS |
220 | } |
221 | ||
1cb95395 | 222 | return NULL; |
d3e51161 HS |
223 | } |
224 | ||
225 | /* | |
226 | * given a pin number that is local to a pin controller, find out the pin bank | |
227 | * and the register base of the pin bank. | |
228 | */ | |
229 | static struct rockchip_pin_bank *pin_to_bank(struct rockchip_pinctrl *info, | |
230 | unsigned pin) | |
231 | { | |
232 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
233 | ||
51578b9b | 234 | while (pin >= (b->pin_base + b->nr_pins)) |
d3e51161 HS |
235 | b++; |
236 | ||
237 | return b; | |
238 | } | |
239 | ||
240 | static struct rockchip_pin_bank *bank_num_to_bank( | |
241 | struct rockchip_pinctrl *info, | |
242 | unsigned num) | |
243 | { | |
244 | struct rockchip_pin_bank *b = info->ctrl->pin_banks; | |
245 | int i; | |
246 | ||
1cb95395 | 247 | for (i = 0; i < info->ctrl->nr_banks; i++, b++) { |
d3e51161 | 248 | if (b->bank_num == num) |
1cb95395 | 249 | return b; |
d3e51161 HS |
250 | } |
251 | ||
1cb95395 | 252 | return ERR_PTR(-EINVAL); |
d3e51161 HS |
253 | } |
254 | ||
255 | /* | |
256 | * Pinctrl_ops handling | |
257 | */ | |
258 | ||
259 | static int rockchip_get_groups_count(struct pinctrl_dev *pctldev) | |
260 | { | |
261 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
262 | ||
263 | return info->ngroups; | |
264 | } | |
265 | ||
266 | static const char *rockchip_get_group_name(struct pinctrl_dev *pctldev, | |
267 | unsigned selector) | |
268 | { | |
269 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
270 | ||
271 | return info->groups[selector].name; | |
272 | } | |
273 | ||
274 | static int rockchip_get_group_pins(struct pinctrl_dev *pctldev, | |
275 | unsigned selector, const unsigned **pins, | |
276 | unsigned *npins) | |
277 | { | |
278 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
279 | ||
280 | if (selector >= info->ngroups) | |
281 | return -EINVAL; | |
282 | ||
283 | *pins = info->groups[selector].pins; | |
284 | *npins = info->groups[selector].npins; | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int rockchip_dt_node_to_map(struct pinctrl_dev *pctldev, | |
290 | struct device_node *np, | |
291 | struct pinctrl_map **map, unsigned *num_maps) | |
292 | { | |
293 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
294 | const struct rockchip_pin_group *grp; | |
295 | struct pinctrl_map *new_map; | |
296 | struct device_node *parent; | |
297 | int map_num = 1; | |
298 | int i; | |
299 | ||
300 | /* | |
301 | * first find the group of this node and check if we need to create | |
302 | * config maps for pins | |
303 | */ | |
304 | grp = pinctrl_name_to_group(info, np->name); | |
305 | if (!grp) { | |
306 | dev_err(info->dev, "unable to find group for node %s\n", | |
307 | np->name); | |
308 | return -EINVAL; | |
309 | } | |
310 | ||
311 | map_num += grp->npins; | |
312 | new_map = devm_kzalloc(pctldev->dev, sizeof(*new_map) * map_num, | |
313 | GFP_KERNEL); | |
314 | if (!new_map) | |
315 | return -ENOMEM; | |
316 | ||
317 | *map = new_map; | |
318 | *num_maps = map_num; | |
319 | ||
320 | /* create mux map */ | |
321 | parent = of_get_parent(np); | |
322 | if (!parent) { | |
323 | devm_kfree(pctldev->dev, new_map); | |
324 | return -EINVAL; | |
325 | } | |
326 | new_map[0].type = PIN_MAP_TYPE_MUX_GROUP; | |
327 | new_map[0].data.mux.function = parent->name; | |
328 | new_map[0].data.mux.group = np->name; | |
329 | of_node_put(parent); | |
330 | ||
331 | /* create config map */ | |
332 | new_map++; | |
333 | for (i = 0; i < grp->npins; i++) { | |
334 | new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN; | |
335 | new_map[i].data.configs.group_or_pin = | |
336 | pin_get_name(pctldev, grp->pins[i]); | |
337 | new_map[i].data.configs.configs = grp->data[i].configs; | |
338 | new_map[i].data.configs.num_configs = grp->data[i].nconfigs; | |
339 | } | |
340 | ||
341 | dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n", | |
342 | (*map)->data.mux.function, (*map)->data.mux.group, map_num); | |
343 | ||
344 | return 0; | |
345 | } | |
346 | ||
347 | static void rockchip_dt_free_map(struct pinctrl_dev *pctldev, | |
348 | struct pinctrl_map *map, unsigned num_maps) | |
349 | { | |
350 | } | |
351 | ||
352 | static const struct pinctrl_ops rockchip_pctrl_ops = { | |
353 | .get_groups_count = rockchip_get_groups_count, | |
354 | .get_group_name = rockchip_get_group_name, | |
355 | .get_group_pins = rockchip_get_group_pins, | |
356 | .dt_node_to_map = rockchip_dt_node_to_map, | |
357 | .dt_free_map = rockchip_dt_free_map, | |
358 | }; | |
359 | ||
360 | /* | |
361 | * Hardware access | |
362 | */ | |
363 | ||
a076e2ed HS |
364 | static int rockchip_get_mux(struct rockchip_pin_bank *bank, int pin) |
365 | { | |
366 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 367 | int iomux_num = (pin / 8); |
751a99ab HS |
368 | unsigned int val; |
369 | int reg, ret; | |
a076e2ed HS |
370 | u8 bit; |
371 | ||
fc72c923 HS |
372 | if (iomux_num > 3) |
373 | return -EINVAL; | |
374 | ||
375 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) | |
a076e2ed HS |
376 | return RK_FUNC_GPIO; |
377 | ||
378 | /* get basic quadrupel of mux registers and the correct reg inside */ | |
751a99ab | 379 | reg = info->ctrl->mux_offset; |
a076e2ed | 380 | reg += bank->bank_num * 0x10; |
fc72c923 | 381 | reg += iomux_num * 4; |
a076e2ed HS |
382 | bit = (pin % 8) * 2; |
383 | ||
751a99ab HS |
384 | ret = regmap_read(info->regmap_base, reg, &val); |
385 | if (ret) | |
386 | return ret; | |
387 | ||
388 | return ((val >> bit) & 3); | |
a076e2ed HS |
389 | } |
390 | ||
d3e51161 HS |
391 | /* |
392 | * Set a new mux function for a pin. | |
393 | * | |
394 | * The register is divided into the upper and lower 16 bit. When changing | |
395 | * a value, the previous register value is not read and changed. Instead | |
396 | * it seems the changed bits are marked in the upper 16 bit, while the | |
397 | * changed value gets set in the same offset in the lower 16 bit. | |
398 | * All pin settings seem to be 2 bit wide in both the upper and lower | |
399 | * parts. | |
400 | * @bank: pin bank to change | |
401 | * @pin: pin to change | |
402 | * @mux: new mux function to set | |
403 | */ | |
14797189 | 404 | static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) |
d3e51161 HS |
405 | { |
406 | struct rockchip_pinctrl *info = bank->drvdata; | |
fc72c923 | 407 | int iomux_num = (pin / 8); |
751a99ab | 408 | int reg, ret; |
d3e51161 HS |
409 | unsigned long flags; |
410 | u8 bit; | |
411 | u32 data; | |
412 | ||
fc72c923 HS |
413 | if (iomux_num > 3) |
414 | return -EINVAL; | |
415 | ||
416 | if (bank->iomux[iomux_num].type & IOMUX_GPIO_ONLY) { | |
c4a532de HS |
417 | if (mux != RK_FUNC_GPIO) { |
418 | dev_err(info->dev, | |
419 | "pin %d only supports a gpio mux\n", pin); | |
420 | return -ENOTSUPP; | |
421 | } else { | |
422 | return 0; | |
423 | } | |
424 | } | |
425 | ||
d3e51161 HS |
426 | dev_dbg(info->dev, "setting mux of GPIO%d-%d to %d\n", |
427 | bank->bank_num, pin, mux); | |
428 | ||
429 | /* get basic quadrupel of mux registers and the correct reg inside */ | |
751a99ab | 430 | reg = info->ctrl->mux_offset; |
d3e51161 | 431 | reg += bank->bank_num * 0x10; |
fc72c923 | 432 | reg += iomux_num * 4; |
d3e51161 HS |
433 | bit = (pin % 8) * 2; |
434 | ||
435 | spin_lock_irqsave(&bank->slock, flags); | |
436 | ||
437 | data = (3 << (bit + 16)); | |
438 | data |= (mux & 3) << bit; | |
751a99ab | 439 | ret = regmap_write(info->regmap_base, reg, data); |
d3e51161 HS |
440 | |
441 | spin_unlock_irqrestore(&bank->slock, flags); | |
14797189 | 442 | |
751a99ab | 443 | return ret; |
d3e51161 HS |
444 | } |
445 | ||
a282926d HS |
446 | #define RK2928_PULL_OFFSET 0x118 |
447 | #define RK2928_PULL_PINS_PER_REG 16 | |
448 | #define RK2928_PULL_BANK_STRIDE 8 | |
449 | ||
450 | static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
451 | int pin_num, struct regmap **regmap, |
452 | int *reg, u8 *bit) | |
a282926d HS |
453 | { |
454 | struct rockchip_pinctrl *info = bank->drvdata; | |
455 | ||
751a99ab HS |
456 | *regmap = info->regmap_base; |
457 | *reg = RK2928_PULL_OFFSET; | |
a282926d HS |
458 | *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE; |
459 | *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4; | |
460 | ||
461 | *bit = pin_num % RK2928_PULL_PINS_PER_REG; | |
462 | }; | |
463 | ||
bfc7a42a | 464 | #define RK3188_PULL_OFFSET 0x164 |
6ca5274d HS |
465 | #define RK3188_PULL_BITS_PER_PIN 2 |
466 | #define RK3188_PULL_PINS_PER_REG 8 | |
467 | #define RK3188_PULL_BANK_STRIDE 16 | |
14dee867 | 468 | #define RK3188_PULL_PMU_OFFSET 0x64 |
6ca5274d HS |
469 | |
470 | static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, | |
751a99ab HS |
471 | int pin_num, struct regmap **regmap, |
472 | int *reg, u8 *bit) | |
6ca5274d HS |
473 | { |
474 | struct rockchip_pinctrl *info = bank->drvdata; | |
475 | ||
476 | /* The first 12 pins of the first bank are located elsewhere */ | |
fc72c923 | 477 | if (bank->bank_num == 0 && pin_num < 12) { |
14dee867 HS |
478 | *regmap = info->regmap_pmu ? info->regmap_pmu |
479 | : bank->regmap_pull; | |
480 | *reg = info->regmap_pmu ? RK3188_PULL_PMU_OFFSET : 0; | |
751a99ab | 481 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); |
6ca5274d HS |
482 | *bit = pin_num % RK3188_PULL_PINS_PER_REG; |
483 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
484 | } else { | |
751a99ab HS |
485 | *regmap = info->regmap_pull ? info->regmap_pull |
486 | : info->regmap_base; | |
487 | *reg = info->regmap_pull ? 0 : RK3188_PULL_OFFSET; | |
488 | ||
bfc7a42a HS |
489 | /* correct the offset, as it is the 2nd pull register */ |
490 | *reg -= 4; | |
6ca5274d HS |
491 | *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE; |
492 | *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4); | |
493 | ||
494 | /* | |
495 | * The bits in these registers have an inverse ordering | |
496 | * with the lowest pin being in bits 15:14 and the highest | |
497 | * pin in bits 1:0 | |
498 | */ | |
499 | *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG); | |
500 | *bit *= RK3188_PULL_BITS_PER_PIN; | |
501 | } | |
502 | } | |
503 | ||
d3e51161 HS |
504 | static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) |
505 | { | |
506 | struct rockchip_pinctrl *info = bank->drvdata; | |
507 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
508 | struct regmap *regmap; |
509 | int reg, ret; | |
d3e51161 | 510 | u8 bit; |
6ca5274d | 511 | u32 data; |
d3e51161 HS |
512 | |
513 | /* rk3066b does support any pulls */ | |
a282926d | 514 | if (ctrl->type == RK3066B) |
d3e51161 HS |
515 | return PIN_CONFIG_BIAS_DISABLE; |
516 | ||
751a99ab HS |
517 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
518 | ||
519 | ret = regmap_read(regmap, reg, &data); | |
520 | if (ret) | |
521 | return ret; | |
6ca5274d | 522 | |
a282926d HS |
523 | switch (ctrl->type) { |
524 | case RK2928: | |
751a99ab | 525 | return !(data & BIT(bit)) |
d3e51161 HS |
526 | ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT |
527 | : PIN_CONFIG_BIAS_DISABLE; | |
a282926d | 528 | case RK3188: |
751a99ab | 529 | data >>= bit; |
6ca5274d HS |
530 | data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1; |
531 | ||
532 | switch (data) { | |
533 | case 0: | |
534 | return PIN_CONFIG_BIAS_DISABLE; | |
535 | case 1: | |
536 | return PIN_CONFIG_BIAS_PULL_UP; | |
537 | case 2: | |
538 | return PIN_CONFIG_BIAS_PULL_DOWN; | |
539 | case 3: | |
540 | return PIN_CONFIG_BIAS_BUS_HOLD; | |
541 | } | |
542 | ||
543 | dev_err(info->dev, "unknown pull setting\n"); | |
d3e51161 | 544 | return -EIO; |
a282926d HS |
545 | default: |
546 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
547 | return -EINVAL; | |
548 | }; | |
d3e51161 HS |
549 | } |
550 | ||
551 | static int rockchip_set_pull(struct rockchip_pin_bank *bank, | |
552 | int pin_num, int pull) | |
553 | { | |
554 | struct rockchip_pinctrl *info = bank->drvdata; | |
555 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
751a99ab HS |
556 | struct regmap *regmap; |
557 | int reg, ret; | |
d3e51161 HS |
558 | unsigned long flags; |
559 | u8 bit; | |
560 | u32 data; | |
561 | ||
562 | dev_dbg(info->dev, "setting pull of GPIO%d-%d to %d\n", | |
563 | bank->bank_num, pin_num, pull); | |
564 | ||
565 | /* rk3066b does support any pulls */ | |
a282926d | 566 | if (ctrl->type == RK3066B) |
d3e51161 HS |
567 | return pull ? -EINVAL : 0; |
568 | ||
751a99ab | 569 | ctrl->pull_calc_reg(bank, pin_num, ®map, ®, &bit); |
6ca5274d | 570 | |
a282926d HS |
571 | switch (ctrl->type) { |
572 | case RK2928: | |
d3e51161 HS |
573 | spin_lock_irqsave(&bank->slock, flags); |
574 | ||
575 | data = BIT(bit + 16); | |
576 | if (pull == PIN_CONFIG_BIAS_DISABLE) | |
577 | data |= BIT(bit); | |
751a99ab | 578 | ret = regmap_write(regmap, reg, data); |
d3e51161 HS |
579 | |
580 | spin_unlock_irqrestore(&bank->slock, flags); | |
a282926d HS |
581 | break; |
582 | case RK3188: | |
6ca5274d HS |
583 | spin_lock_irqsave(&bank->slock, flags); |
584 | ||
585 | /* enable the write to the equivalent lower bits */ | |
586 | data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16); | |
587 | ||
588 | switch (pull) { | |
589 | case PIN_CONFIG_BIAS_DISABLE: | |
590 | break; | |
591 | case PIN_CONFIG_BIAS_PULL_UP: | |
592 | data |= (1 << bit); | |
593 | break; | |
594 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
595 | data |= (2 << bit); | |
596 | break; | |
597 | case PIN_CONFIG_BIAS_BUS_HOLD: | |
598 | data |= (3 << bit); | |
599 | break; | |
600 | default: | |
d32c3e26 | 601 | spin_unlock_irqrestore(&bank->slock, flags); |
6ca5274d HS |
602 | dev_err(info->dev, "unsupported pull setting %d\n", |
603 | pull); | |
604 | return -EINVAL; | |
605 | } | |
606 | ||
751a99ab | 607 | ret = regmap_write(regmap, reg, data); |
6ca5274d HS |
608 | |
609 | spin_unlock_irqrestore(&bank->slock, flags); | |
610 | break; | |
a282926d HS |
611 | default: |
612 | dev_err(info->dev, "unsupported pinctrl type\n"); | |
613 | return -EINVAL; | |
d3e51161 HS |
614 | } |
615 | ||
751a99ab | 616 | return ret; |
d3e51161 HS |
617 | } |
618 | ||
619 | /* | |
620 | * Pinmux_ops handling | |
621 | */ | |
622 | ||
623 | static int rockchip_pmx_get_funcs_count(struct pinctrl_dev *pctldev) | |
624 | { | |
625 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
626 | ||
627 | return info->nfunctions; | |
628 | } | |
629 | ||
630 | static const char *rockchip_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
631 | unsigned selector) | |
632 | { | |
633 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
634 | ||
635 | return info->functions[selector].name; | |
636 | } | |
637 | ||
638 | static int rockchip_pmx_get_groups(struct pinctrl_dev *pctldev, | |
639 | unsigned selector, const char * const **groups, | |
640 | unsigned * const num_groups) | |
641 | { | |
642 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
643 | ||
644 | *groups = info->functions[selector].groups; | |
645 | *num_groups = info->functions[selector].ngroups; | |
646 | ||
647 | return 0; | |
648 | } | |
649 | ||
650 | static int rockchip_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector, | |
651 | unsigned group) | |
652 | { | |
653 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
654 | const unsigned int *pins = info->groups[group].pins; | |
655 | const struct rockchip_pin_config *data = info->groups[group].data; | |
656 | struct rockchip_pin_bank *bank; | |
14797189 | 657 | int cnt, ret = 0; |
d3e51161 HS |
658 | |
659 | dev_dbg(info->dev, "enable function %s group %s\n", | |
660 | info->functions[selector].name, info->groups[group].name); | |
661 | ||
662 | /* | |
663 | * for each pin in the pin group selected, program the correspoding pin | |
664 | * pin function number in the config register. | |
665 | */ | |
666 | for (cnt = 0; cnt < info->groups[group].npins; cnt++) { | |
667 | bank = pin_to_bank(info, pins[cnt]); | |
14797189 HS |
668 | ret = rockchip_set_mux(bank, pins[cnt] - bank->pin_base, |
669 | data[cnt].func); | |
670 | if (ret) | |
671 | break; | |
672 | } | |
673 | ||
674 | if (ret) { | |
675 | /* revert the already done pin settings */ | |
676 | for (cnt--; cnt >= 0; cnt--) | |
677 | rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); | |
678 | ||
679 | return ret; | |
d3e51161 HS |
680 | } |
681 | ||
682 | return 0; | |
683 | } | |
684 | ||
d3e51161 HS |
685 | /* |
686 | * The calls to gpio_direction_output() and gpio_direction_input() | |
687 | * leads to this function call (via the pinctrl_gpio_direction_{input|output}() | |
688 | * function called from the gpiolib interface). | |
689 | */ | |
690 | static int rockchip_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
691 | struct pinctrl_gpio_range *range, | |
692 | unsigned offset, bool input) | |
693 | { | |
694 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
695 | struct rockchip_pin_bank *bank; | |
696 | struct gpio_chip *chip; | |
14797189 | 697 | int pin, ret; |
d3e51161 HS |
698 | u32 data; |
699 | ||
700 | chip = range->gc; | |
701 | bank = gc_to_pin_bank(chip); | |
702 | pin = offset - chip->base; | |
703 | ||
704 | dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", | |
705 | offset, range->name, pin, input ? "input" : "output"); | |
706 | ||
14797189 HS |
707 | ret = rockchip_set_mux(bank, pin, RK_FUNC_GPIO); |
708 | if (ret < 0) | |
709 | return ret; | |
d3e51161 HS |
710 | |
711 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); | |
712 | /* set bit to 1 for output, 0 for input */ | |
713 | if (!input) | |
714 | data |= BIT(pin); | |
715 | else | |
716 | data &= ~BIT(pin); | |
717 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
722 | static const struct pinmux_ops rockchip_pmx_ops = { | |
723 | .get_functions_count = rockchip_pmx_get_funcs_count, | |
724 | .get_function_name = rockchip_pmx_get_func_name, | |
725 | .get_function_groups = rockchip_pmx_get_groups, | |
726 | .enable = rockchip_pmx_enable, | |
d3e51161 HS |
727 | .gpio_set_direction = rockchip_pmx_gpio_set_direction, |
728 | }; | |
729 | ||
730 | /* | |
731 | * Pinconf_ops handling | |
732 | */ | |
733 | ||
44b6d930 HS |
734 | static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, |
735 | enum pin_config_param pull) | |
736 | { | |
a282926d HS |
737 | switch (ctrl->type) { |
738 | case RK2928: | |
739 | return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT || | |
740 | pull == PIN_CONFIG_BIAS_DISABLE); | |
741 | case RK3066B: | |
44b6d930 | 742 | return pull ? false : true; |
a282926d HS |
743 | case RK3188: |
744 | return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT); | |
44b6d930 HS |
745 | } |
746 | ||
a282926d | 747 | return false; |
44b6d930 HS |
748 | } |
749 | ||
a076e2ed HS |
750 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, |
751 | unsigned offset, int value); | |
752 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset); | |
753 | ||
d3e51161 HS |
754 | /* set the pin config settings for a specified pin */ |
755 | static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
03b054e9 | 756 | unsigned long *configs, unsigned num_configs) |
d3e51161 HS |
757 | { |
758 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
759 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
03b054e9 SY |
760 | enum pin_config_param param; |
761 | u16 arg; | |
762 | int i; | |
763 | int rc; | |
764 | ||
765 | for (i = 0; i < num_configs; i++) { | |
766 | param = pinconf_to_config_param(configs[i]); | |
767 | arg = pinconf_to_config_argument(configs[i]); | |
768 | ||
769 | switch (param) { | |
770 | case PIN_CONFIG_BIAS_DISABLE: | |
771 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
772 | param); | |
773 | if (rc) | |
774 | return rc; | |
775 | break; | |
776 | case PIN_CONFIG_BIAS_PULL_UP: | |
777 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
778 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 779 | case PIN_CONFIG_BIAS_BUS_HOLD: |
03b054e9 SY |
780 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
781 | return -ENOTSUPP; | |
782 | ||
783 | if (!arg) | |
784 | return -EINVAL; | |
785 | ||
786 | rc = rockchip_set_pull(bank, pin - bank->pin_base, | |
787 | param); | |
788 | if (rc) | |
789 | return rc; | |
790 | break; | |
a076e2ed HS |
791 | case PIN_CONFIG_OUTPUT: |
792 | rc = rockchip_gpio_direction_output(&bank->gpio_chip, | |
793 | pin - bank->pin_base, | |
794 | arg); | |
795 | if (rc) | |
796 | return rc; | |
797 | break; | |
03b054e9 | 798 | default: |
44b6d930 | 799 | return -ENOTSUPP; |
03b054e9 SY |
800 | break; |
801 | } | |
802 | } /* for each config */ | |
d3e51161 HS |
803 | |
804 | return 0; | |
805 | } | |
806 | ||
807 | /* get the pin config settings for a specified pin */ | |
808 | static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
809 | unsigned long *config) | |
810 | { | |
811 | struct rockchip_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); | |
812 | struct rockchip_pin_bank *bank = pin_to_bank(info, pin); | |
813 | enum pin_config_param param = pinconf_to_config_param(*config); | |
dab3eba7 | 814 | u16 arg; |
a076e2ed | 815 | int rc; |
d3e51161 HS |
816 | |
817 | switch (param) { | |
818 | case PIN_CONFIG_BIAS_DISABLE: | |
44b6d930 HS |
819 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
820 | return -EINVAL; | |
821 | ||
dab3eba7 | 822 | arg = 0; |
44b6d930 | 823 | break; |
d3e51161 HS |
824 | case PIN_CONFIG_BIAS_PULL_UP: |
825 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
826 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
6ca5274d | 827 | case PIN_CONFIG_BIAS_BUS_HOLD: |
44b6d930 HS |
828 | if (!rockchip_pinconf_pull_valid(info->ctrl, param)) |
829 | return -ENOTSUPP; | |
d3e51161 | 830 | |
44b6d930 | 831 | if (rockchip_get_pull(bank, pin - bank->pin_base) != param) |
d3e51161 HS |
832 | return -EINVAL; |
833 | ||
dab3eba7 | 834 | arg = 1; |
d3e51161 | 835 | break; |
a076e2ed HS |
836 | case PIN_CONFIG_OUTPUT: |
837 | rc = rockchip_get_mux(bank, pin - bank->pin_base); | |
838 | if (rc != RK_FUNC_GPIO) | |
839 | return -EINVAL; | |
840 | ||
841 | rc = rockchip_gpio_get(&bank->gpio_chip, pin - bank->pin_base); | |
842 | if (rc < 0) | |
843 | return rc; | |
844 | ||
845 | arg = rc ? 1 : 0; | |
846 | break; | |
d3e51161 HS |
847 | default: |
848 | return -ENOTSUPP; | |
849 | break; | |
850 | } | |
851 | ||
dab3eba7 HS |
852 | *config = pinconf_to_config_packed(param, arg); |
853 | ||
d3e51161 HS |
854 | return 0; |
855 | } | |
856 | ||
857 | static const struct pinconf_ops rockchip_pinconf_ops = { | |
858 | .pin_config_get = rockchip_pinconf_get, | |
859 | .pin_config_set = rockchip_pinconf_set, | |
860 | }; | |
861 | ||
65fca613 HS |
862 | static const struct of_device_id rockchip_bank_match[] = { |
863 | { .compatible = "rockchip,gpio-bank" }, | |
6ca5274d | 864 | { .compatible = "rockchip,rk3188-gpio-bank0" }, |
65fca613 HS |
865 | {}, |
866 | }; | |
d3e51161 HS |
867 | |
868 | static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, | |
869 | struct device_node *np) | |
870 | { | |
871 | struct device_node *child; | |
872 | ||
873 | for_each_child_of_node(np, child) { | |
65fca613 | 874 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 HS |
875 | continue; |
876 | ||
877 | info->nfunctions++; | |
878 | info->ngroups += of_get_child_count(child); | |
879 | } | |
880 | } | |
881 | ||
882 | static int rockchip_pinctrl_parse_groups(struct device_node *np, | |
883 | struct rockchip_pin_group *grp, | |
884 | struct rockchip_pinctrl *info, | |
885 | u32 index) | |
886 | { | |
887 | struct rockchip_pin_bank *bank; | |
888 | int size; | |
889 | const __be32 *list; | |
890 | int num; | |
891 | int i, j; | |
892 | int ret; | |
893 | ||
894 | dev_dbg(info->dev, "group(%d): %s\n", index, np->name); | |
895 | ||
896 | /* Initialise group */ | |
897 | grp->name = np->name; | |
898 | ||
899 | /* | |
900 | * the binding format is rockchip,pins = <bank pin mux CONFIG>, | |
901 | * do sanity check and calculate pins number | |
902 | */ | |
903 | list = of_get_property(np, "rockchip,pins", &size); | |
904 | /* we do not check return since it's safe node passed down */ | |
905 | size /= sizeof(*list); | |
906 | if (!size || size % 4) { | |
907 | dev_err(info->dev, "wrong pins number or pins and configs should be by 4\n"); | |
908 | return -EINVAL; | |
909 | } | |
910 | ||
911 | grp->npins = size / 4; | |
912 | ||
913 | grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int), | |
914 | GFP_KERNEL); | |
915 | grp->data = devm_kzalloc(info->dev, grp->npins * | |
916 | sizeof(struct rockchip_pin_config), | |
917 | GFP_KERNEL); | |
918 | if (!grp->pins || !grp->data) | |
919 | return -ENOMEM; | |
920 | ||
921 | for (i = 0, j = 0; i < size; i += 4, j++) { | |
922 | const __be32 *phandle; | |
923 | struct device_node *np_config; | |
924 | ||
925 | num = be32_to_cpu(*list++); | |
926 | bank = bank_num_to_bank(info, num); | |
927 | if (IS_ERR(bank)) | |
928 | return PTR_ERR(bank); | |
929 | ||
930 | grp->pins[j] = bank->pin_base + be32_to_cpu(*list++); | |
931 | grp->data[j].func = be32_to_cpu(*list++); | |
932 | ||
933 | phandle = list++; | |
934 | if (!phandle) | |
935 | return -EINVAL; | |
936 | ||
937 | np_config = of_find_node_by_phandle(be32_to_cpup(phandle)); | |
938 | ret = pinconf_generic_parse_dt_config(np_config, | |
939 | &grp->data[j].configs, &grp->data[j].nconfigs); | |
940 | if (ret) | |
941 | return ret; | |
942 | } | |
943 | ||
944 | return 0; | |
945 | } | |
946 | ||
947 | static int rockchip_pinctrl_parse_functions(struct device_node *np, | |
948 | struct rockchip_pinctrl *info, | |
949 | u32 index) | |
950 | { | |
951 | struct device_node *child; | |
952 | struct rockchip_pmx_func *func; | |
953 | struct rockchip_pin_group *grp; | |
954 | int ret; | |
955 | static u32 grp_index; | |
956 | u32 i = 0; | |
957 | ||
958 | dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name); | |
959 | ||
960 | func = &info->functions[index]; | |
961 | ||
962 | /* Initialise function */ | |
963 | func->name = np->name; | |
964 | func->ngroups = of_get_child_count(np); | |
965 | if (func->ngroups <= 0) | |
966 | return 0; | |
967 | ||
968 | func->groups = devm_kzalloc(info->dev, | |
969 | func->ngroups * sizeof(char *), GFP_KERNEL); | |
970 | if (!func->groups) | |
971 | return -ENOMEM; | |
972 | ||
973 | for_each_child_of_node(np, child) { | |
974 | func->groups[i] = child->name; | |
975 | grp = &info->groups[grp_index++]; | |
976 | ret = rockchip_pinctrl_parse_groups(child, grp, info, i++); | |
977 | if (ret) | |
978 | return ret; | |
979 | } | |
980 | ||
981 | return 0; | |
982 | } | |
983 | ||
984 | static int rockchip_pinctrl_parse_dt(struct platform_device *pdev, | |
985 | struct rockchip_pinctrl *info) | |
986 | { | |
987 | struct device *dev = &pdev->dev; | |
988 | struct device_node *np = dev->of_node; | |
989 | struct device_node *child; | |
990 | int ret; | |
991 | int i; | |
992 | ||
993 | rockchip_pinctrl_child_count(info, np); | |
994 | ||
995 | dev_dbg(&pdev->dev, "nfunctions = %d\n", info->nfunctions); | |
996 | dev_dbg(&pdev->dev, "ngroups = %d\n", info->ngroups); | |
997 | ||
998 | info->functions = devm_kzalloc(dev, info->nfunctions * | |
999 | sizeof(struct rockchip_pmx_func), | |
1000 | GFP_KERNEL); | |
1001 | if (!info->functions) { | |
1002 | dev_err(dev, "failed to allocate memory for function list\n"); | |
1003 | return -EINVAL; | |
1004 | } | |
1005 | ||
1006 | info->groups = devm_kzalloc(dev, info->ngroups * | |
1007 | sizeof(struct rockchip_pin_group), | |
1008 | GFP_KERNEL); | |
1009 | if (!info->groups) { | |
1010 | dev_err(dev, "failed allocate memory for ping group list\n"); | |
1011 | return -EINVAL; | |
1012 | } | |
1013 | ||
1014 | i = 0; | |
1015 | ||
1016 | for_each_child_of_node(np, child) { | |
65fca613 | 1017 | if (of_match_node(rockchip_bank_match, child)) |
d3e51161 | 1018 | continue; |
65fca613 | 1019 | |
d3e51161 HS |
1020 | ret = rockchip_pinctrl_parse_functions(child, info, i++); |
1021 | if (ret) { | |
1022 | dev_err(&pdev->dev, "failed to parse function\n"); | |
1023 | return ret; | |
1024 | } | |
1025 | } | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int rockchip_pinctrl_register(struct platform_device *pdev, | |
1031 | struct rockchip_pinctrl *info) | |
1032 | { | |
1033 | struct pinctrl_desc *ctrldesc = &info->pctl; | |
1034 | struct pinctrl_pin_desc *pindesc, *pdesc; | |
1035 | struct rockchip_pin_bank *pin_bank; | |
1036 | int pin, bank, ret; | |
1037 | int k; | |
1038 | ||
1039 | ctrldesc->name = "rockchip-pinctrl"; | |
1040 | ctrldesc->owner = THIS_MODULE; | |
1041 | ctrldesc->pctlops = &rockchip_pctrl_ops; | |
1042 | ctrldesc->pmxops = &rockchip_pmx_ops; | |
1043 | ctrldesc->confops = &rockchip_pinconf_ops; | |
1044 | ||
1045 | pindesc = devm_kzalloc(&pdev->dev, sizeof(*pindesc) * | |
1046 | info->ctrl->nr_pins, GFP_KERNEL); | |
1047 | if (!pindesc) { | |
1048 | dev_err(&pdev->dev, "mem alloc for pin descriptors failed\n"); | |
1049 | return -ENOMEM; | |
1050 | } | |
1051 | ctrldesc->pins = pindesc; | |
1052 | ctrldesc->npins = info->ctrl->nr_pins; | |
1053 | ||
1054 | pdesc = pindesc; | |
1055 | for (bank = 0 , k = 0; bank < info->ctrl->nr_banks; bank++) { | |
1056 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1057 | for (pin = 0; pin < pin_bank->nr_pins; pin++, k++) { | |
1058 | pdesc->number = k; | |
1059 | pdesc->name = kasprintf(GFP_KERNEL, "%s-%d", | |
1060 | pin_bank->name, pin); | |
1061 | pdesc++; | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | info->pctl_dev = pinctrl_register(ctrldesc, &pdev->dev, info); | |
1066 | if (!info->pctl_dev) { | |
1067 | dev_err(&pdev->dev, "could not register pinctrl driver\n"); | |
1068 | return -EINVAL; | |
1069 | } | |
1070 | ||
1071 | for (bank = 0; bank < info->ctrl->nr_banks; ++bank) { | |
1072 | pin_bank = &info->ctrl->pin_banks[bank]; | |
1073 | pin_bank->grange.name = pin_bank->name; | |
1074 | pin_bank->grange.id = bank; | |
1075 | pin_bank->grange.pin_base = pin_bank->pin_base; | |
1076 | pin_bank->grange.base = pin_bank->gpio_chip.base; | |
1077 | pin_bank->grange.npins = pin_bank->gpio_chip.ngpio; | |
1078 | pin_bank->grange.gc = &pin_bank->gpio_chip; | |
1079 | pinctrl_add_gpio_range(info->pctl_dev, &pin_bank->grange); | |
1080 | } | |
1081 | ||
1082 | ret = rockchip_pinctrl_parse_dt(pdev, info); | |
1083 | if (ret) { | |
1084 | pinctrl_unregister(info->pctl_dev); | |
1085 | return ret; | |
1086 | } | |
1087 | ||
1088 | return 0; | |
1089 | } | |
1090 | ||
1091 | /* | |
1092 | * GPIO handling | |
1093 | */ | |
1094 | ||
0351c287 AL |
1095 | static int rockchip_gpio_request(struct gpio_chip *chip, unsigned offset) |
1096 | { | |
1097 | return pinctrl_request_gpio(chip->base + offset); | |
1098 | } | |
1099 | ||
1100 | static void rockchip_gpio_free(struct gpio_chip *chip, unsigned offset) | |
1101 | { | |
1102 | pinctrl_free_gpio(chip->base + offset); | |
1103 | } | |
1104 | ||
d3e51161 HS |
1105 | static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) |
1106 | { | |
1107 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1108 | void __iomem *reg = bank->reg_base + GPIO_SWPORT_DR; | |
1109 | unsigned long flags; | |
1110 | u32 data; | |
1111 | ||
1112 | spin_lock_irqsave(&bank->slock, flags); | |
1113 | ||
1114 | data = readl(reg); | |
1115 | data &= ~BIT(offset); | |
1116 | if (value) | |
1117 | data |= BIT(offset); | |
1118 | writel(data, reg); | |
1119 | ||
1120 | spin_unlock_irqrestore(&bank->slock, flags); | |
1121 | } | |
1122 | ||
1123 | /* | |
1124 | * Returns the level of the pin for input direction and setting of the DR | |
1125 | * register for output gpios. | |
1126 | */ | |
1127 | static int rockchip_gpio_get(struct gpio_chip *gc, unsigned offset) | |
1128 | { | |
1129 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1130 | u32 data; | |
1131 | ||
1132 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1133 | data >>= offset; | |
1134 | data &= 1; | |
1135 | return data; | |
1136 | } | |
1137 | ||
1138 | /* | |
1139 | * gpiolib gpio_direction_input callback function. The setting of the pin | |
1140 | * mux function as 'gpio input' will be handled by the pinctrl susbsystem | |
1141 | * interface. | |
1142 | */ | |
1143 | static int rockchip_gpio_direction_input(struct gpio_chip *gc, unsigned offset) | |
1144 | { | |
1145 | return pinctrl_gpio_direction_input(gc->base + offset); | |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * gpiolib gpio_direction_output callback function. The setting of the pin | |
1150 | * mux function as 'gpio output' will be handled by the pinctrl susbsystem | |
1151 | * interface. | |
1152 | */ | |
1153 | static int rockchip_gpio_direction_output(struct gpio_chip *gc, | |
1154 | unsigned offset, int value) | |
1155 | { | |
1156 | rockchip_gpio_set(gc, offset, value); | |
1157 | return pinctrl_gpio_direction_output(gc->base + offset); | |
1158 | } | |
1159 | ||
1160 | /* | |
1161 | * gpiolib gpio_to_irq callback function. Creates a mapping between a GPIO pin | |
1162 | * and a virtual IRQ, if not already present. | |
1163 | */ | |
1164 | static int rockchip_gpio_to_irq(struct gpio_chip *gc, unsigned offset) | |
1165 | { | |
1166 | struct rockchip_pin_bank *bank = gc_to_pin_bank(gc); | |
1167 | unsigned int virq; | |
1168 | ||
1169 | if (!bank->domain) | |
1170 | return -ENXIO; | |
1171 | ||
1172 | virq = irq_create_mapping(bank->domain, offset); | |
1173 | ||
1174 | return (virq) ? : -ENXIO; | |
1175 | } | |
1176 | ||
1177 | static const struct gpio_chip rockchip_gpiolib_chip = { | |
0351c287 AL |
1178 | .request = rockchip_gpio_request, |
1179 | .free = rockchip_gpio_free, | |
d3e51161 HS |
1180 | .set = rockchip_gpio_set, |
1181 | .get = rockchip_gpio_get, | |
1182 | .direction_input = rockchip_gpio_direction_input, | |
1183 | .direction_output = rockchip_gpio_direction_output, | |
1184 | .to_irq = rockchip_gpio_to_irq, | |
1185 | .owner = THIS_MODULE, | |
1186 | }; | |
1187 | ||
1188 | /* | |
1189 | * Interrupt handling | |
1190 | */ | |
1191 | ||
1192 | static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc) | |
1193 | { | |
1194 | struct irq_chip *chip = irq_get_chip(irq); | |
1195 | struct rockchip_pin_bank *bank = irq_get_handler_data(irq); | |
5a927501 | 1196 | u32 polarity = 0, data = 0; |
d3e51161 | 1197 | u32 pend; |
5a927501 | 1198 | bool edge_changed = false; |
d3e51161 HS |
1199 | |
1200 | dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); | |
1201 | ||
1202 | chained_irq_enter(chip, desc); | |
1203 | ||
1204 | pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); | |
1205 | ||
5a927501 HS |
1206 | if (bank->toggle_edge_mode) { |
1207 | polarity = readl_relaxed(bank->reg_base + | |
1208 | GPIO_INT_POLARITY); | |
1209 | data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); | |
1210 | } | |
1211 | ||
d3e51161 HS |
1212 | while (pend) { |
1213 | unsigned int virq; | |
1214 | ||
1215 | irq = __ffs(pend); | |
1216 | pend &= ~BIT(irq); | |
1217 | virq = irq_linear_revmap(bank->domain, irq); | |
1218 | ||
1219 | if (!virq) { | |
1220 | dev_err(bank->drvdata->dev, "unmapped irq %d\n", irq); | |
1221 | continue; | |
1222 | } | |
1223 | ||
1224 | dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); | |
1225 | ||
5a927501 HS |
1226 | /* |
1227 | * Triggering IRQ on both rising and falling edge | |
1228 | * needs manual intervention. | |
1229 | */ | |
1230 | if (bank->toggle_edge_mode & BIT(irq)) { | |
1231 | if (data & BIT(irq)) | |
1232 | polarity &= ~BIT(irq); | |
1233 | else | |
1234 | polarity |= BIT(irq); | |
1235 | ||
1236 | edge_changed = true; | |
1237 | } | |
1238 | ||
d3e51161 HS |
1239 | generic_handle_irq(virq); |
1240 | } | |
1241 | ||
5a927501 HS |
1242 | if (bank->toggle_edge_mode && edge_changed) { |
1243 | /* Interrupt params should only be set with ints disabled */ | |
1244 | data = readl_relaxed(bank->reg_base + GPIO_INTEN); | |
1245 | writel_relaxed(0, bank->reg_base + GPIO_INTEN); | |
1246 | writel(polarity, bank->reg_base + GPIO_INT_POLARITY); | |
1247 | writel(data, bank->reg_base + GPIO_INTEN); | |
1248 | } | |
1249 | ||
d3e51161 HS |
1250 | chained_irq_exit(chip, desc); |
1251 | } | |
1252 | ||
1253 | static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) | |
1254 | { | |
1255 | struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); | |
1256 | struct rockchip_pin_bank *bank = gc->private; | |
1257 | u32 mask = BIT(d->hwirq); | |
1258 | u32 polarity; | |
1259 | u32 level; | |
1260 | u32 data; | |
14797189 | 1261 | int ret; |
d3e51161 | 1262 | |
5a927501 | 1263 | /* make sure the pin is configured as gpio input */ |
14797189 HS |
1264 | ret = rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO); |
1265 | if (ret < 0) | |
1266 | return ret; | |
1267 | ||
5a927501 HS |
1268 | data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); |
1269 | data &= ~mask; | |
1270 | writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); | |
1271 | ||
d3e51161 HS |
1272 | if (type & IRQ_TYPE_EDGE_BOTH) |
1273 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
1274 | else | |
1275 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
1276 | ||
1277 | irq_gc_lock(gc); | |
1278 | ||
1279 | level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1280 | polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); | |
1281 | ||
1282 | switch (type) { | |
5a927501 HS |
1283 | case IRQ_TYPE_EDGE_BOTH: |
1284 | bank->toggle_edge_mode |= mask; | |
1285 | level |= mask; | |
1286 | ||
1287 | /* | |
1288 | * Determine gpio state. If 1 next interrupt should be falling | |
1289 | * otherwise rising. | |
1290 | */ | |
1291 | data = readl(bank->reg_base + GPIO_EXT_PORT); | |
1292 | if (data & mask) | |
1293 | polarity &= ~mask; | |
1294 | else | |
1295 | polarity |= mask; | |
1296 | break; | |
d3e51161 | 1297 | case IRQ_TYPE_EDGE_RISING: |
5a927501 | 1298 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1299 | level |= mask; |
1300 | polarity |= mask; | |
1301 | break; | |
1302 | case IRQ_TYPE_EDGE_FALLING: | |
5a927501 | 1303 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1304 | level |= mask; |
1305 | polarity &= ~mask; | |
1306 | break; | |
1307 | case IRQ_TYPE_LEVEL_HIGH: | |
5a927501 | 1308 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1309 | level &= ~mask; |
1310 | polarity |= mask; | |
1311 | break; | |
1312 | case IRQ_TYPE_LEVEL_LOW: | |
5a927501 | 1313 | bank->toggle_edge_mode &= ~mask; |
d3e51161 HS |
1314 | level &= ~mask; |
1315 | polarity &= ~mask; | |
1316 | break; | |
1317 | default: | |
7cc5f970 | 1318 | irq_gc_unlock(gc); |
d3e51161 HS |
1319 | return -EINVAL; |
1320 | } | |
1321 | ||
1322 | writel_relaxed(level, gc->reg_base + GPIO_INTTYPE_LEVEL); | |
1323 | writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); | |
1324 | ||
1325 | irq_gc_unlock(gc); | |
1326 | ||
d3e51161 HS |
1327 | return 0; |
1328 | } | |
1329 | ||
1330 | static int rockchip_interrupts_register(struct platform_device *pdev, | |
1331 | struct rockchip_pinctrl *info) | |
1332 | { | |
1333 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1334 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1335 | unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; | |
1336 | struct irq_chip_generic *gc; | |
1337 | int ret; | |
1338 | int i; | |
1339 | ||
1340 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1341 | if (!bank->valid) { | |
1342 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1343 | bank->name); | |
1344 | continue; | |
1345 | } | |
1346 | ||
1347 | bank->domain = irq_domain_add_linear(bank->of_node, 32, | |
1348 | &irq_generic_chip_ops, NULL); | |
1349 | if (!bank->domain) { | |
1350 | dev_warn(&pdev->dev, "could not initialize irq domain for bank %s\n", | |
1351 | bank->name); | |
1352 | continue; | |
1353 | } | |
1354 | ||
1355 | ret = irq_alloc_domain_generic_chips(bank->domain, 32, 1, | |
1356 | "rockchip_gpio_irq", handle_level_irq, | |
1357 | clr, 0, IRQ_GC_INIT_MASK_CACHE); | |
1358 | if (ret) { | |
1359 | dev_err(&pdev->dev, "could not alloc generic chips for bank %s\n", | |
1360 | bank->name); | |
1361 | irq_domain_remove(bank->domain); | |
1362 | continue; | |
1363 | } | |
1364 | ||
1365 | gc = irq_get_domain_generic_chip(bank->domain, 0); | |
1366 | gc->reg_base = bank->reg_base; | |
1367 | gc->private = bank; | |
1368 | gc->chip_types[0].regs.mask = GPIO_INTEN; | |
1369 | gc->chip_types[0].regs.ack = GPIO_PORTS_EOI; | |
1370 | gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit; | |
1371 | gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; | |
1372 | gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; | |
1373 | gc->chip_types[0].chip.irq_set_wake = irq_gc_set_wake; | |
1374 | gc->chip_types[0].chip.irq_set_type = rockchip_irq_set_type; | |
1375 | ||
1376 | irq_set_handler_data(bank->irq, bank); | |
1377 | irq_set_chained_handler(bank->irq, rockchip_irq_demux); | |
1378 | } | |
1379 | ||
1380 | return 0; | |
1381 | } | |
1382 | ||
1383 | static int rockchip_gpiolib_register(struct platform_device *pdev, | |
1384 | struct rockchip_pinctrl *info) | |
1385 | { | |
1386 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1387 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1388 | struct gpio_chip *gc; | |
1389 | int ret; | |
1390 | int i; | |
1391 | ||
1392 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1393 | if (!bank->valid) { | |
1394 | dev_warn(&pdev->dev, "bank %s is not valid\n", | |
1395 | bank->name); | |
1396 | continue; | |
1397 | } | |
1398 | ||
1399 | bank->gpio_chip = rockchip_gpiolib_chip; | |
1400 | ||
1401 | gc = &bank->gpio_chip; | |
1402 | gc->base = bank->pin_base; | |
1403 | gc->ngpio = bank->nr_pins; | |
1404 | gc->dev = &pdev->dev; | |
1405 | gc->of_node = bank->of_node; | |
1406 | gc->label = bank->name; | |
1407 | ||
1408 | ret = gpiochip_add(gc); | |
1409 | if (ret) { | |
1410 | dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n", | |
1411 | gc->label, ret); | |
1412 | goto fail; | |
1413 | } | |
1414 | } | |
1415 | ||
1416 | rockchip_interrupts_register(pdev, info); | |
1417 | ||
1418 | return 0; | |
1419 | ||
1420 | fail: | |
1421 | for (--i, --bank; i >= 0; --i, --bank) { | |
1422 | if (!bank->valid) | |
1423 | continue; | |
1424 | ||
1425 | if (gpiochip_remove(&bank->gpio_chip)) | |
1426 | dev_err(&pdev->dev, "gpio chip %s remove failed\n", | |
1427 | bank->gpio_chip.label); | |
1428 | } | |
1429 | return ret; | |
1430 | } | |
1431 | ||
1432 | static int rockchip_gpiolib_unregister(struct platform_device *pdev, | |
1433 | struct rockchip_pinctrl *info) | |
1434 | { | |
1435 | struct rockchip_pin_ctrl *ctrl = info->ctrl; | |
1436 | struct rockchip_pin_bank *bank = ctrl->pin_banks; | |
1437 | int ret = 0; | |
1438 | int i; | |
1439 | ||
1440 | for (i = 0; !ret && i < ctrl->nr_banks; ++i, ++bank) { | |
1441 | if (!bank->valid) | |
1442 | continue; | |
1443 | ||
1444 | ret = gpiochip_remove(&bank->gpio_chip); | |
1445 | } | |
1446 | ||
1447 | if (ret) | |
1448 | dev_err(&pdev->dev, "gpio chip remove failed\n"); | |
1449 | ||
1450 | return ret; | |
1451 | } | |
1452 | ||
1453 | static int rockchip_get_bank_data(struct rockchip_pin_bank *bank, | |
622f3237 | 1454 | struct rockchip_pinctrl *info) |
d3e51161 HS |
1455 | { |
1456 | struct resource res; | |
751a99ab | 1457 | void __iomem *base; |
d3e51161 HS |
1458 | |
1459 | if (of_address_to_resource(bank->of_node, 0, &res)) { | |
622f3237 | 1460 | dev_err(info->dev, "cannot find IO resource for bank\n"); |
d3e51161 HS |
1461 | return -ENOENT; |
1462 | } | |
1463 | ||
622f3237 | 1464 | bank->reg_base = devm_ioremap_resource(info->dev, &res); |
d3e51161 HS |
1465 | if (IS_ERR(bank->reg_base)) |
1466 | return PTR_ERR(bank->reg_base); | |
1467 | ||
6ca5274d HS |
1468 | /* |
1469 | * special case, where parts of the pull setting-registers are | |
1470 | * part of the PMU register space | |
1471 | */ | |
1472 | if (of_device_is_compatible(bank->of_node, | |
1473 | "rockchip,rk3188-gpio-bank0")) { | |
a658efaa | 1474 | struct device_node *node; |
bfc7a42a | 1475 | |
a658efaa HS |
1476 | node = of_parse_phandle(bank->of_node->parent, |
1477 | "rockchip,pmu", 0); | |
1478 | if (!node) { | |
1479 | if (of_address_to_resource(bank->of_node, 1, &res)) { | |
1480 | dev_err(info->dev, "cannot find IO resource for bank\n"); | |
1481 | return -ENOENT; | |
1482 | } | |
1483 | ||
1484 | base = devm_ioremap_resource(info->dev, &res); | |
1485 | if (IS_ERR(base)) | |
1486 | return PTR_ERR(base); | |
1487 | rockchip_regmap_config.max_register = | |
1488 | resource_size(&res) - 4; | |
1489 | rockchip_regmap_config.name = | |
1490 | "rockchip,rk3188-gpio-bank0-pull"; | |
1491 | bank->regmap_pull = devm_regmap_init_mmio(info->dev, | |
1492 | base, | |
1493 | &rockchip_regmap_config); | |
6ca5274d | 1494 | } |
6ca5274d | 1495 | } |
65fca613 | 1496 | |
d3e51161 HS |
1497 | bank->irq = irq_of_parse_and_map(bank->of_node, 0); |
1498 | ||
1499 | bank->clk = of_clk_get(bank->of_node, 0); | |
1500 | if (IS_ERR(bank->clk)) | |
1501 | return PTR_ERR(bank->clk); | |
1502 | ||
1503 | return clk_prepare_enable(bank->clk); | |
1504 | } | |
1505 | ||
1506 | static const struct of_device_id rockchip_pinctrl_dt_match[]; | |
1507 | ||
1508 | /* retrieve the soc specific data */ | |
1509 | static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( | |
1510 | struct rockchip_pinctrl *d, | |
1511 | struct platform_device *pdev) | |
1512 | { | |
1513 | const struct of_device_id *match; | |
1514 | struct device_node *node = pdev->dev.of_node; | |
1515 | struct device_node *np; | |
1516 | struct rockchip_pin_ctrl *ctrl; | |
1517 | struct rockchip_pin_bank *bank; | |
1518 | int i; | |
1519 | ||
1520 | match = of_match_node(rockchip_pinctrl_dt_match, node); | |
1521 | ctrl = (struct rockchip_pin_ctrl *)match->data; | |
1522 | ||
1523 | for_each_child_of_node(node, np) { | |
1524 | if (!of_find_property(np, "gpio-controller", NULL)) | |
1525 | continue; | |
1526 | ||
1527 | bank = ctrl->pin_banks; | |
1528 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1529 | if (!strcmp(bank->name, np->name)) { | |
1530 | bank->of_node = np; | |
1531 | ||
622f3237 | 1532 | if (!rockchip_get_bank_data(bank, d)) |
d3e51161 HS |
1533 | bank->valid = true; |
1534 | ||
1535 | break; | |
1536 | } | |
1537 | } | |
1538 | } | |
1539 | ||
1540 | bank = ctrl->pin_banks; | |
1541 | for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { | |
1542 | spin_lock_init(&bank->slock); | |
1543 | bank->drvdata = d; | |
1544 | bank->pin_base = ctrl->nr_pins; | |
1545 | ctrl->nr_pins += bank->nr_pins; | |
1546 | } | |
1547 | ||
1548 | return ctrl; | |
1549 | } | |
1550 | ||
1551 | static int rockchip_pinctrl_probe(struct platform_device *pdev) | |
1552 | { | |
1553 | struct rockchip_pinctrl *info; | |
1554 | struct device *dev = &pdev->dev; | |
1555 | struct rockchip_pin_ctrl *ctrl; | |
14dee867 | 1556 | struct device_node *np = pdev->dev.of_node, *node; |
d3e51161 | 1557 | struct resource *res; |
751a99ab | 1558 | void __iomem *base; |
d3e51161 HS |
1559 | int ret; |
1560 | ||
1561 | if (!dev->of_node) { | |
1562 | dev_err(dev, "device tree node not found\n"); | |
1563 | return -ENODEV; | |
1564 | } | |
1565 | ||
1566 | info = devm_kzalloc(dev, sizeof(struct rockchip_pinctrl), GFP_KERNEL); | |
1567 | if (!info) | |
1568 | return -ENOMEM; | |
1569 | ||
622f3237 HS |
1570 | info->dev = dev; |
1571 | ||
d3e51161 HS |
1572 | ctrl = rockchip_pinctrl_get_soc_data(info, pdev); |
1573 | if (!ctrl) { | |
1574 | dev_err(dev, "driver data not available\n"); | |
1575 | return -EINVAL; | |
1576 | } | |
1577 | info->ctrl = ctrl; | |
d3e51161 | 1578 | |
1e747e59 HS |
1579 | node = of_parse_phandle(np, "rockchip,grf", 0); |
1580 | if (node) { | |
1581 | info->regmap_base = syscon_node_to_regmap(node); | |
1582 | if (IS_ERR(info->regmap_base)) | |
1583 | return PTR_ERR(info->regmap_base); | |
1584 | } else { | |
1585 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
751a99ab HS |
1586 | base = devm_ioremap_resource(&pdev->dev, res); |
1587 | if (IS_ERR(base)) | |
1588 | return PTR_ERR(base); | |
1589 | ||
1590 | rockchip_regmap_config.max_register = resource_size(res) - 4; | |
1e747e59 HS |
1591 | rockchip_regmap_config.name = "rockchip,pinctrl"; |
1592 | info->regmap_base = devm_regmap_init_mmio(&pdev->dev, base, | |
1593 | &rockchip_regmap_config); | |
1594 | ||
1595 | /* to check for the old dt-bindings */ | |
1596 | info->reg_size = resource_size(res); | |
1597 | ||
1598 | /* Honor the old binding, with pull registers as 2nd resource */ | |
1599 | if (ctrl->type == RK3188 && info->reg_size < 0x200) { | |
1600 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
1601 | base = devm_ioremap_resource(&pdev->dev, res); | |
1602 | if (IS_ERR(base)) | |
1603 | return PTR_ERR(base); | |
1604 | ||
1605 | rockchip_regmap_config.max_register = | |
1606 | resource_size(res) - 4; | |
1607 | rockchip_regmap_config.name = "rockchip,pinctrl-pull"; | |
1608 | info->regmap_pull = devm_regmap_init_mmio(&pdev->dev, | |
1609 | base, | |
1610 | &rockchip_regmap_config); | |
1611 | } | |
6ca5274d HS |
1612 | } |
1613 | ||
14dee867 HS |
1614 | /* try to find the optional reference to the pmu syscon */ |
1615 | node = of_parse_phandle(np, "rockchip,pmu", 0); | |
1616 | if (node) { | |
1617 | info->regmap_pmu = syscon_node_to_regmap(node); | |
1618 | if (IS_ERR(info->regmap_pmu)) | |
1619 | return PTR_ERR(info->regmap_pmu); | |
1620 | } | |
1621 | ||
d3e51161 HS |
1622 | ret = rockchip_gpiolib_register(pdev, info); |
1623 | if (ret) | |
1624 | return ret; | |
1625 | ||
1626 | ret = rockchip_pinctrl_register(pdev, info); | |
1627 | if (ret) { | |
1628 | rockchip_gpiolib_unregister(pdev, info); | |
1629 | return ret; | |
1630 | } | |
1631 | ||
1632 | platform_set_drvdata(pdev, info); | |
1633 | ||
1634 | return 0; | |
1635 | } | |
1636 | ||
1637 | static struct rockchip_pin_bank rk2928_pin_banks[] = { | |
1638 | PIN_BANK(0, 32, "gpio0"), | |
1639 | PIN_BANK(1, 32, "gpio1"), | |
1640 | PIN_BANK(2, 32, "gpio2"), | |
1641 | PIN_BANK(3, 32, "gpio3"), | |
1642 | }; | |
1643 | ||
1644 | static struct rockchip_pin_ctrl rk2928_pin_ctrl = { | |
1645 | .pin_banks = rk2928_pin_banks, | |
1646 | .nr_banks = ARRAY_SIZE(rk2928_pin_banks), | |
1647 | .label = "RK2928-GPIO", | |
a282926d | 1648 | .type = RK2928, |
d3e51161 | 1649 | .mux_offset = 0xa8, |
a282926d | 1650 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1651 | }; |
1652 | ||
1653 | static struct rockchip_pin_bank rk3066a_pin_banks[] = { | |
1654 | PIN_BANK(0, 32, "gpio0"), | |
1655 | PIN_BANK(1, 32, "gpio1"), | |
1656 | PIN_BANK(2, 32, "gpio2"), | |
1657 | PIN_BANK(3, 32, "gpio3"), | |
1658 | PIN_BANK(4, 32, "gpio4"), | |
1659 | PIN_BANK(6, 16, "gpio6"), | |
1660 | }; | |
1661 | ||
1662 | static struct rockchip_pin_ctrl rk3066a_pin_ctrl = { | |
1663 | .pin_banks = rk3066a_pin_banks, | |
1664 | .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), | |
1665 | .label = "RK3066a-GPIO", | |
a282926d | 1666 | .type = RK2928, |
d3e51161 | 1667 | .mux_offset = 0xa8, |
a282926d | 1668 | .pull_calc_reg = rk2928_calc_pull_reg_and_bit, |
d3e51161 HS |
1669 | }; |
1670 | ||
1671 | static struct rockchip_pin_bank rk3066b_pin_banks[] = { | |
1672 | PIN_BANK(0, 32, "gpio0"), | |
1673 | PIN_BANK(1, 32, "gpio1"), | |
1674 | PIN_BANK(2, 32, "gpio2"), | |
1675 | PIN_BANK(3, 32, "gpio3"), | |
1676 | }; | |
1677 | ||
1678 | static struct rockchip_pin_ctrl rk3066b_pin_ctrl = { | |
1679 | .pin_banks = rk3066b_pin_banks, | |
1680 | .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), | |
1681 | .label = "RK3066b-GPIO", | |
a282926d | 1682 | .type = RK3066B, |
d3e51161 | 1683 | .mux_offset = 0x60, |
d3e51161 HS |
1684 | }; |
1685 | ||
1686 | static struct rockchip_pin_bank rk3188_pin_banks[] = { | |
fc72c923 | 1687 | PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), |
d3e51161 HS |
1688 | PIN_BANK(1, 32, "gpio1"), |
1689 | PIN_BANK(2, 32, "gpio2"), | |
1690 | PIN_BANK(3, 32, "gpio3"), | |
1691 | }; | |
1692 | ||
1693 | static struct rockchip_pin_ctrl rk3188_pin_ctrl = { | |
1694 | .pin_banks = rk3188_pin_banks, | |
1695 | .nr_banks = ARRAY_SIZE(rk3188_pin_banks), | |
1696 | .label = "RK3188-GPIO", | |
a282926d | 1697 | .type = RK3188, |
22c0d7e3 | 1698 | .mux_offset = 0x60, |
6ca5274d | 1699 | .pull_calc_reg = rk3188_calc_pull_reg_and_bit, |
d3e51161 HS |
1700 | }; |
1701 | ||
1702 | static const struct of_device_id rockchip_pinctrl_dt_match[] = { | |
1703 | { .compatible = "rockchip,rk2928-pinctrl", | |
1704 | .data = (void *)&rk2928_pin_ctrl }, | |
1705 | { .compatible = "rockchip,rk3066a-pinctrl", | |
1706 | .data = (void *)&rk3066a_pin_ctrl }, | |
1707 | { .compatible = "rockchip,rk3066b-pinctrl", | |
1708 | .data = (void *)&rk3066b_pin_ctrl }, | |
1709 | { .compatible = "rockchip,rk3188-pinctrl", | |
1710 | .data = (void *)&rk3188_pin_ctrl }, | |
1711 | {}, | |
1712 | }; | |
1713 | MODULE_DEVICE_TABLE(of, rockchip_pinctrl_dt_match); | |
1714 | ||
1715 | static struct platform_driver rockchip_pinctrl_driver = { | |
1716 | .probe = rockchip_pinctrl_probe, | |
1717 | .driver = { | |
1718 | .name = "rockchip-pinctrl", | |
1719 | .owner = THIS_MODULE, | |
0be9e70d | 1720 | .of_match_table = rockchip_pinctrl_dt_match, |
d3e51161 HS |
1721 | }, |
1722 | }; | |
1723 | ||
1724 | static int __init rockchip_pinctrl_drv_register(void) | |
1725 | { | |
1726 | return platform_driver_register(&rockchip_pinctrl_driver); | |
1727 | } | |
1728 | postcore_initcall(rockchip_pinctrl_drv_register); | |
1729 | ||
1730 | MODULE_AUTHOR("Heiko Stuebner <heiko@sntech.de>"); | |
1731 | MODULE_DESCRIPTION("Rockchip pinctrl driver"); | |
1732 | MODULE_LICENSE("GPL v2"); |