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[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / pinctrl-rza1.c
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5a49b644
JM		 1/*
2 * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
3 *
4 * Copyright (C) 2017 Jacopo Mondi
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/*
12 * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
13 * family.
14 * This includes SoCs which are sub- or super- sets of this particular line,
15 * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
16 */
17
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/gpio/driver.h>
21#include <linux/init.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/of_address.h>
26#include <linux/of_device.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/pinmux.h>
30#include <linux/slab.h>
31
32#include "core.h"
33#include "devicetree.h"
34#include "pinconf.h"
35#include "pinmux.h"
36
37#define DRIVER_NAME "pinctrl-rza1"
38
39#define RZA1_P_REG 0x0000
40#define RZA1_PPR_REG 0x0200
41#define RZA1_PM_REG 0x0300
42#define RZA1_PMC_REG 0x0400
43#define RZA1_PFC_REG 0x0500
44#define RZA1_PFCE_REG 0x0600
45#define RZA1_PFCEA_REG 0x0a00
46#define RZA1_PIBC_REG 0x4000
47#define RZA1_PBDC_REG 0x4100
48#define RZA1_PIPC_REG 0x4200
49
50#define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
51
52#define RZA1_NPORTS 12
53#define RZA1_PINS_PER_PORT 16
54#define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
55#define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
56#define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
57
58/*
59 * Use 16 lower bits [15:0] for pin identifier
60 * Use 16 higher bits [31:16] for pin mux function
61 */
62#define MUX_PIN_ID_MASK GENMASK(15, 0)
63#define MUX_FUNC_MASK GENMASK(31, 16)
64
65#define MUX_FUNC_OFFS 16
66#define MUX_FUNC(pinconf) \
67 ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
68#define MUX_FUNC_PFC_MASK BIT(0)
69#define MUX_FUNC_PFCE_MASK BIT(1)
70#define MUX_FUNC_PFCEA_MASK BIT(2)
71
72/* Pin mux flags */
73#define MUX_FLAGS_BIDIR BIT(0)
74#define MUX_FLAGS_SWIO_INPUT BIT(1)
75#define MUX_FLAGS_SWIO_OUTPUT BIT(2)
76
77/* ----------------------------------------------------------------------------
78 * RZ/A1 pinmux flags
79 */
80
81/**
82 * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
83 */
84struct rza1_bidir_pin {
85 u8 pin: 4;
86 u8 func: 4;
87};
88
89/**
90 * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
91 * Each struct rza1_bidir_entry describes a port.
92 */
93struct rza1_bidir_entry {
94 const unsigned int npins;
95 const struct rza1_bidir_pin *pins;
96};
97
98/**
99 * rza1_swio_pin - describe a single pin that needs bidir flag applied.
100 */
101struct rza1_swio_pin {
102 u16 pin: 4;
103 u16 port: 4;
104 u16 func: 4;
105 u16 input: 1;
106};
107
108/**
109 * rza1_swio_entry - describe a list of pins that needs swio flag applied
110 */
111struct rza1_swio_entry {
112 const unsigned int npins;
113 const struct rza1_swio_pin *pins;
114};
115
116/**
117 * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
118 */
119struct rza1_pinmux_conf {
120 const struct rza1_bidir_entry *bidir_entries;
121 const struct rza1_swio_entry *swio_entries;
122};
123
124/* ----------------------------------------------------------------------------
125 * RZ/A1H (r7s72100) pinmux flags
126 */
127
128static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
129 { .pin = 0, .func = 1 },
130 { .pin = 1, .func = 1 },
131 { .pin = 2, .func = 1 },
132 { .pin = 3, .func = 1 },
133 { .pin = 4, .func = 1 },
134 { .pin = 5, .func = 1 },
135 { .pin = 6, .func = 1 },
136 { .pin = 7, .func = 1 },
137};
138
139static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
140 { .pin = 0, .func = 1 },
141 { .pin = 1, .func = 1 },
142 { .pin = 2, .func = 1 },
143 { .pin = 3, .func = 1 },
144 { .pin = 4, .func = 1 },
145 { .pin = 0, .func = 4 },
146 { .pin = 1, .func = 4 },
147 { .pin = 2, .func = 4 },
148 { .pin = 3, .func = 4 },
149 { .pin = 5, .func = 1 },
150 { .pin = 6, .func = 1 },
151 { .pin = 7, .func = 1 },
152 { .pin = 8, .func = 1 },
153 { .pin = 9, .func = 1 },
154 { .pin = 10, .func = 1 },
155 { .pin = 11, .func = 1 },
156 { .pin = 12, .func = 1 },
157 { .pin = 13, .func = 1 },
158 { .pin = 14, .func = 1 },
159 { .pin = 15, .func = 1 },
160 { .pin = 12, .func = 4 },
161 { .pin = 13, .func = 4 },
162 { .pin = 14, .func = 4 },
163 { .pin = 15, .func = 4 },
164};
165
166static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
167 { .pin = 3, .func = 2 },
168 { .pin = 10, .func = 7 },
169 { .pin = 11, .func = 7 },
170 { .pin = 13, .func = 7 },
171 { .pin = 14, .func = 7 },
172 { .pin = 15, .func = 7 },
173 { .pin = 10, .func = 8 },
174 { .pin = 11, .func = 8 },
175 { .pin = 13, .func = 8 },
176 { .pin = 14, .func = 8 },
177 { .pin = 15, .func = 8 },
178};
179
180static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
181 { .pin = 0, .func = 8 },
182 { .pin = 1, .func = 8 },
183 { .pin = 2, .func = 8 },
184 { .pin = 3, .func = 8 },
185 { .pin = 10, .func = 3 },
186 { .pin = 11, .func = 3 },
187 { .pin = 13, .func = 3 },
188 { .pin = 14, .func = 3 },
189 { .pin = 15, .func = 3 },
190 { .pin = 10, .func = 4 },
191 { .pin = 11, .func = 4 },
192 { .pin = 13, .func = 4 },
193 { .pin = 14, .func = 4 },
194 { .pin = 15, .func = 4 },
195 { .pin = 12, .func = 5 },
196 { .pin = 13, .func = 5 },
197 { .pin = 14, .func = 5 },
198 { .pin = 15, .func = 5 },
199};
200
201static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
202 { .pin = 0, .func = 1 },
203 { .pin = 1, .func = 1 },
204 { .pin = 2, .func = 1 },
205 { .pin = 3, .func = 1 },
206 { .pin = 4, .func = 1 },
207 { .pin = 5, .func = 1 },
208 { .pin = 6, .func = 1 },
209 { .pin = 7, .func = 1 },
210 { .pin = 8, .func = 1 },
211 { .pin = 9, .func = 1 },
212 { .pin = 10, .func = 1 },
213 { .pin = 11, .func = 1 },
214 { .pin = 12, .func = 1 },
215 { .pin = 13, .func = 1 },
216 { .pin = 14, .func = 1 },
217 { .pin = 15, .func = 1 },
218};
219
220static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
221 { .pin = 13, .func = 3 },
222};
223
224static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
225 { .pin = 8, .func = 3 },
226 { .pin = 9, .func = 3 },
227 { .pin = 10, .func = 3 },
228 { .pin = 11, .func = 3 },
229 { .pin = 14, .func = 2 },
230 { .pin = 15, .func = 2 },
231 { .pin = 14, .func = 3 },
232 { .pin = 15, .func = 3 },
233};
234
235static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
236 { .pin = 0, .func = 2 },
237 { .pin = 1, .func = 2 },
238 { .pin = 4, .func = 2 },
239 { .pin = 5, .func = 2 },
240 { .pin = 6, .func = 2 },
241 { .pin = 7, .func = 2 },
242};
243
244static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
245 { .pin = 6, .func = 2 },
246 { .pin = 7, .func = 2 },
247 { .pin = 9, .func = 2 },
248 { .pin = 6, .func = 4 },
249 { .pin = 7, .func = 4 },
250 { .pin = 9, .func = 4 },
251 { .pin = 10, .func = 2 },
252 { .pin = 11, .func = 2 },
253 { .pin = 10, .func = 4 },
254 { .pin = 11, .func = 4 },
255 { .pin = 12, .func = 4 },
256 { .pin = 13, .func = 4 },
257 { .pin = 14, .func = 4 },
258 { .pin = 15, .func = 4 },
259};
260
261static const struct rza1_swio_pin rza1h_swio_pins[] = {
262 { .port = 2, .pin = 7, .func = 4, .input = 0 },
263 { .port = 2, .pin = 11, .func = 4, .input = 0 },
264 { .port = 3, .pin = 7, .func = 3, .input = 0 },
265 { .port = 3, .pin = 7, .func = 8, .input = 0 },
266 { .port = 4, .pin = 7, .func = 5, .input = 0 },
267 { .port = 4, .pin = 7, .func = 11, .input = 0 },
268 { .port = 4, .pin = 15, .func = 6, .input = 0 },
269 { .port = 5, .pin = 0, .func = 1, .input = 1 },
270 { .port = 5, .pin = 1, .func = 1, .input = 1 },
271 { .port = 5, .pin = 2, .func = 1, .input = 1 },
272 { .port = 5, .pin = 3, .func = 1, .input = 1 },
273 { .port = 5, .pin = 4, .func = 1, .input = 1 },
274 { .port = 5, .pin = 5, .func = 1, .input = 1 },
275 { .port = 5, .pin = 6, .func = 1, .input = 1 },
276 { .port = 5, .pin = 7, .func = 1, .input = 1 },
277 { .port = 7, .pin = 4, .func = 6, .input = 0 },
278 { .port = 7, .pin = 11, .func = 2, .input = 0 },
279 { .port = 8, .pin = 10, .func = 8, .input = 0 },
280 { .port = 10, .pin = 15, .func = 2, .input = 0 },
281};
282
283static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
284 [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
285 [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
286 [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
287 [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
288 [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
289 [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
290 [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
291 [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
292 [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
293};
294
295static const struct rza1_swio_entry rza1h_swio_entries[] = {
296 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
297};
298
299/* RZ/A1H (r7s72100x) pinmux flags table */
300static const struct rza1_pinmux_conf rza1h_pmx_conf = {
301 .bidir_entries = rza1h_bidir_entries,
302 .swio_entries = rza1h_swio_entries,
303};
304
039bc58e
CB		 305/* ----------------------------------------------------------------------------
306 * RZ/A1L (r7s72102) pinmux flags
307 */
308
309static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
310 { .pin = 0, .func = 1 },
311 { .pin = 1, .func = 1 },
312 { .pin = 2, .func = 1 },
313 { .pin = 3, .func = 1 },
314 { .pin = 4, .func = 1 },
315 { .pin = 5, .func = 1 },
316 { .pin = 6, .func = 1 },
317 { .pin = 7, .func = 1 },
318};
319
320static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
321 { .pin = 0, .func = 2 },
322 { .pin = 1, .func = 2 },
323 { .pin = 2, .func = 2 },
324 { .pin = 4, .func = 2 },
325 { .pin = 5, .func = 2 },
326 { .pin = 10, .func = 2 },
327 { .pin = 11, .func = 2 },
328 { .pin = 12, .func = 2 },
329 { .pin = 13, .func = 2 },
330};
331
332static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
333 { .pin = 1, .func = 4 },
334 { .pin = 2, .func = 2 },
335 { .pin = 3, .func = 2 },
336 { .pin = 6, .func = 2 },
337 { .pin = 7, .func = 2 },
338};
339
340static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
341 { .pin = 0, .func = 1 },
342 { .pin = 1, .func = 1 },
343 { .pin = 2, .func = 1 },
344 { .pin = 3, .func = 1 },
345 { .pin = 4, .func = 1 },
346 { .pin = 5, .func = 1 },
347 { .pin = 6, .func = 1 },
348 { .pin = 7, .func = 1 },
349 { .pin = 8, .func = 1 },
350 { .pin = 9, .func = 1 },
351 { .pin = 10, .func = 1 },
352 { .pin = 11, .func = 1 },
353 { .pin = 12, .func = 1 },
354 { .pin = 13, .func = 1 },
355 { .pin = 14, .func = 1 },
356 { .pin = 15, .func = 1 },
357 { .pin = 0, .func = 2 },
358 { .pin = 1, .func = 2 },
359 { .pin = 2, .func = 2 },
360 { .pin = 3, .func = 2 },
361};
362
363static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
364 { .pin = 0, .func = 1 },
365 { .pin = 1, .func = 1 },
366 { .pin = 2, .func = 1 },
367 { .pin = 3, .func = 1 },
368 { .pin = 4, .func = 1 },
369 { .pin = 5, .func = 1 },
370 { .pin = 6, .func = 1 },
371 { .pin = 7, .func = 1 },
372 { .pin = 8, .func = 1 },
373 { .pin = 9, .func = 1 },
374 { .pin = 10, .func = 1 },
375 { .pin = 11, .func = 1 },
376 { .pin = 12, .func = 1 },
377 { .pin = 13, .func = 1 },
378 { .pin = 14, .func = 1 },
379 { .pin = 15, .func = 1 },
380};
381
382static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
383 { .pin = 2, .func = 2 },
384 { .pin = 3, .func = 2 },
385 { .pin = 5, .func = 2 },
386 { .pin = 6, .func = 2 },
387 { .pin = 7, .func = 2 },
388 { .pin = 2, .func = 3 },
389 { .pin = 3, .func = 3 },
390 { .pin = 5, .func = 3 },
391 { .pin = 6, .func = 3 },
392 { .pin = 7, .func = 3 },
393};
394
395static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
396 { .pin = 1, .func = 2 },
397 { .pin = 0, .func = 3 },
398 { .pin = 1, .func = 3 },
399 { .pin = 3, .func = 3 },
400 { .pin = 4, .func = 3 },
401 { .pin = 5, .func = 3 },
402};
403
404static const struct rza1_swio_pin rza1l_swio_pins[] = {
405 { .port = 2, .pin = 8, .func = 2, .input = 0 },
406 { .port = 5, .pin = 6, .func = 3, .input = 0 },
407 { .port = 6, .pin = 6, .func = 3, .input = 0 },
408 { .port = 6, .pin = 10, .func = 3, .input = 0 },
409 { .port = 7, .pin = 10, .func = 2, .input = 0 },
410 { .port = 8, .pin = 2, .func = 3, .input = 0 },
411};
412
413static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
414 [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
415 [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
416 [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
417 [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
418 [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
419 [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
420 [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
421};
422
423static const struct rza1_swio_entry rza1l_swio_entries[] = {
424 [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
425};
426
427/* RZ/A1L (r7s72102x) pinmux flags table */
428static const struct rza1_pinmux_conf rza1l_pmx_conf = {
429 .bidir_entries = rza1l_bidir_entries,
430 .swio_entries = rza1l_swio_entries,
431};
432
5a49b644
JM		 433/* ----------------------------------------------------------------------------
434 * RZ/A1 types
435 */
436/**
437 * rza1_mux_conf - describes a pin multiplexing operation
438 *
439 * @id: the pin identifier from 0 to RZA1_NPINS
440 * @port: the port where pin sits on
441 * @pin: pin id
442 * @mux_func: alternate function id number
443 * @mux_flags: alternate function flags
444 * @value: output value to set the pin to
445 */
446struct rza1_mux_conf {
447 u16 id;
448 u8 port;
449 u8 pin;
450 u8 mux_func;
451 u8 mux_flags;
452 u8 value;
453};
454
455/**
456 * rza1_port - describes a pin port
457 *
458 * This is mostly useful to lock register writes per-bank and not globally.
459 *
460 * @lock: protect access to HW registers
461 * @id: port number
462 * @base: logical address base
463 * @pins: pins sitting on this port
464 */
465struct rza1_port {
466 spinlock_t lock;
467 unsigned int id;
468 void __iomem *base;
469 struct pinctrl_pin_desc *pins;
470};
471
472/**
473 * rza1_pinctrl - RZ pincontroller device
474 *
475 * @dev: parent device structure
476 * @mutex: protect [pinctrl|pinmux]_generic functions
477 * @base: logical address base
478 * @nports: number of pin controller ports
479 * @ports: pin controller banks
480 * @pins: pin array for pinctrl core
481 * @desc: pincontroller desc for pinctrl core
482 * @pctl: pinctrl device
483 * @data: device specific data
484 */
485struct rza1_pinctrl {
486 struct device *dev;
487
488 struct mutex mutex;
489
490 void __iomem *base;
491
492 unsigned int nport;
493 struct rza1_port *ports;
494
495 struct pinctrl_pin_desc *pins;
496 struct pinctrl_desc desc;
497 struct pinctrl_dev *pctl;
498
499 const void *data;
500};
501
502/* ----------------------------------------------------------------------------
503 * RZ/A1 pinmux flags
504 */
505static inline bool rza1_pinmux_get_bidir(unsigned int port,
506 unsigned int pin,
507 unsigned int func,
508 const struct rza1_bidir_entry *table)
509{
510 const struct rza1_bidir_entry *entry = &table[port];
511 const struct rza1_bidir_pin *bidir_pin;
512 unsigned int i;
513
514 for (i = 0; i < entry->npins; ++i) {
515 bidir_pin = &entry->pins[i];
516 if (bidir_pin->pin == pin && bidir_pin->func == func)
517 return true;
518 }
519
520 return false;
521}
522
523static inline int rza1_pinmux_get_swio(unsigned int port,
524 unsigned int pin,
525 unsigned int func,
526 const struct rza1_swio_entry *table)
527{
528 const struct rza1_swio_pin *swio_pin;
529 unsigned int i;
530
531
532 for (i = 0; i < table->npins; ++i) {
533 swio_pin = &table->pins[i];
534 if (swio_pin->port == port && swio_pin->pin == pin &&
535 swio_pin->func == func)
536 return swio_pin->input;
537 }
538
539 return -ENOENT;
540}
541
542/**
543 * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
544 */
545static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
546 unsigned int func,
547 struct rza1_pinctrl *rza1_pctl)
548
549{
550 const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
551 const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
552 const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
553 unsigned int pmx_flags = 0;
554 int ret;
555
556 if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
557 pmx_flags |= MUX_FLAGS_BIDIR;
558
559 ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
560 if (ret == 0)
561 pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
562 else if (ret > 0)
563 pmx_flags |= MUX_FLAGS_SWIO_INPUT;
564
565 return pmx_flags;
566}
567
568/* ----------------------------------------------------------------------------
569 * RZ/A1 SoC operations
570 */
571
572/**
573 * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
574 * registers
575 */
576static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
577 unsigned int bit, bool set)
578{
579 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
580 u16 val = ioread16(mem);
581
582 if (set)
583 val |= BIT(bit);
584 else
585 val &= ~BIT(bit);
586
587 iowrite16(val, mem);
588}
589
590static inline unsigned int rza1_get_bit(struct rza1_port *port,
591 unsigned int reg, unsigned int bit)
592{
593 void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
594
595 return ioread16(mem) & BIT(bit);
596}
597
598/**
599 * rza1_pin_reset() - reset a pin to default initial state
600 *
601 * Reset pin state disabling input buffer and bi-directional control,
602 * and configure it as input port.
603 * Note that pin is now configured with direction as input but with input
604 * buffer disabled. This implies the pin value cannot be read in this state.
605 *
606 * @port: port where pin sits on
607 * @pin: pin offset
608 */
609static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
610{
611 unsigned long irqflags;
612
613 spin_lock_irqsave(&port->lock, irqflags);
614 rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
615 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
616
617 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
618 rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
619 rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
620 spin_unlock_irqrestore(&port->lock, irqflags);
621}
622
623static inline int rza1_pin_get_direction(struct rza1_port *port,
624 unsigned int pin)
625{
626 unsigned long irqflags;
627 int input;
628
629 spin_lock_irqsave(&port->lock, irqflags);
630 input = rza1_get_bit(port, RZA1_PM_REG, pin);
631 spin_unlock_irqrestore(&port->lock, irqflags);
632
633 return !!input;
634}
635
636/**
637 * rza1_pin_set_direction() - set I/O direction on a pin in port mode
638 *
639 * When running in output port mode keep PBDC enabled to allow reading the
640 * pin value from PPR.
641 *
642 * @port: port where pin sits on
643 * @pin: pin offset
644 * @input: input enable/disable flag
645 */
646static inline void rza1_pin_set_direction(struct rza1_port *port,
647 unsigned int pin, bool input)
648{
649 unsigned long irqflags;
650
651 spin_lock_irqsave(&port->lock, irqflags);
652
653 rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
654 if (input) {
655 rza1_set_bit(port, RZA1_PM_REG, pin, 1);
656 rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
657 } else {
658 rza1_set_bit(port, RZA1_PM_REG, pin, 0);
659 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
660 }
661
662 spin_unlock_irqrestore(&port->lock, irqflags);
663}
664
665static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
666 unsigned int value)
667{
668 unsigned long irqflags;
669
670 spin_lock_irqsave(&port->lock, irqflags);
671 rza1_set_bit(port, RZA1_P_REG, pin, !!value);
672 spin_unlock_irqrestore(&port->lock, irqflags);
673}
674
675static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
676{
677 unsigned long irqflags;
678 int val;
679
680 spin_lock_irqsave(&port->lock, irqflags);
681 val = rza1_get_bit(port, RZA1_PPR_REG, pin);
682 spin_unlock_irqrestore(&port->lock, irqflags);
683
684 return val;
685}
686
687/**
688 * rza1_pin_mux_single() - configure pin multiplexing on a single pin
689 *
690 * @pinctrl: RZ/A1 pin controller device
691 * @mux_conf: pin multiplexing descriptor
692 */
693static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
694 struct rza1_mux_conf *mux_conf)
695{
696 struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
697 unsigned int pin = mux_conf->pin;
698 u8 mux_func = mux_conf->mux_func;
699 u8 mux_flags = mux_conf->mux_flags;
700 u8 mux_flags_from_table;
701
702 rza1_pin_reset(port, pin);
703
704 /* SWIO pinmux flags coming from DT are high precedence */
705 mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
706 rza1_pctl);
707 if (mux_flags)
708 mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
709 else
710 mux_flags = mux_flags_from_table;
711
712 if (mux_flags & MUX_FLAGS_BIDIR)
713 rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
714
715 /*
716 * Enable alternate function mode and select it.
717 *
718 * Be careful here: the pin mux sub-nodes in device tree
719 * enumerate alternate functions from 1 to 8;
720 * subtract 1 before using macros to match registers configuration
721 * which expects numbers from 0 to 7 instead.
722 *
723 * ----------------------------------------------------
724 * Alternate mode selection table:
725 *
726 * PMC PFC PFCE PFCAE (mux_func - 1)
727 * 1 0 0 0 0
728 * 1 1 0 0 1
729 * 1 0 1 0 2
730 * 1 1 1 0 3
731 * 1 0 0 1 4
732 * 1 1 0 1 5
733 * 1 0 1 1 6
734 * 1 1 1 1 7
735 * ----------------------------------------------------
736 */
737 mux_func -= 1;
738 rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
739 rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
740 rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
741
742 /*
743 * All alternate functions except a few need PIPCn = 1.
744 * If PIPCn has to stay disabled (SW IO mode), configure PMn according
745 * to I/O direction specified by pin configuration -after- PMC has been
746 * set to one.
747 */
748 if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
749 rza1_set_bit(port, RZA1_PM_REG, pin,
750 mux_flags & MUX_FLAGS_SWIO_INPUT);
751 else
752 rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
753
754 rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
755
756 return 0;
757}
758
759/* ----------------------------------------------------------------------------
760 * gpio operations
761 */
762
763/**
764 * rza1_gpio_request() - configure pin in port mode
765 *
766 * Configure a pin as gpio (port mode).
767 * After reset, the pin is in input mode with input buffer disabled.
768 * To use the pin as input or output, set_direction shall be called first
769 *
770 * @chip: gpio chip where the gpio sits on
771 * @gpio: gpio offset
772 */
773static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
774{
775 struct rza1_port *port = gpiochip_get_data(chip);
776
777 rza1_pin_reset(port, gpio);
778
779 return 0;
780}
781
782/**
783 * rza1_gpio_disable_free() - reset a pin
784 *
785 * Surprisingly, disable_free a gpio, is equivalent to request it.
786 * Reset pin to port mode, with input buffer disabled. This overwrites all
787 * port direction settings applied with set_direction
788 *
789 * @chip: gpio chip where the gpio sits on
790 * @gpio: gpio offset
791 */
792static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
793{
794 struct rza1_port *port = gpiochip_get_data(chip);
795
796 rza1_pin_reset(port, gpio);
797}
798
799static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
800{
801 struct rza1_port *port = gpiochip_get_data(chip);
802
803 return rza1_pin_get_direction(port, gpio);
804}
805
806static int rza1_gpio_direction_input(struct gpio_chip *chip,
807 unsigned int gpio)
808{
809 struct rza1_port *port = gpiochip_get_data(chip);
810
811 rza1_pin_set_direction(port, gpio, true);
812
813 return 0;
814}
815
816static int rza1_gpio_direction_output(struct gpio_chip *chip,
817 unsigned int gpio,
818 int value)
819{
820 struct rza1_port *port = gpiochip_get_data(chip);
821
822 /* Set value before driving pin direction */
823 rza1_pin_set(port, gpio, value);
824 rza1_pin_set_direction(port, gpio, false);
825
826 return 0;
827}
828
829/**
830 * rza1_gpio_get() - read a gpio pin value
831 *
832 * Read gpio pin value through PPR register.
833 * Requires bi-directional mode to work when reading the value of a pin
834 * in output mode
835 *
836 * @chip: gpio chip where the gpio sits on
837 * @gpio: gpio offset
838 */
839static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
840{
841 struct rza1_port *port = gpiochip_get_data(chip);
842
843 return rza1_pin_get(port, gpio);
844}
845
846static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
847 int value)
848{
849 struct rza1_port *port = gpiochip_get_data(chip);
850
851 rza1_pin_set(port, gpio, value);
852}
853
fa39210d 854static const struct gpio_chip rza1_gpiochip_template = {
5a49b644
JM		 855 .request = rza1_gpio_request,
856 .free = rza1_gpio_free,
857 .get_direction = rza1_gpio_get_direction,
858 .direction_input = rza1_gpio_direction_input,
859 .direction_output = rza1_gpio_direction_output,
860 .get = rza1_gpio_get,
861 .set = rza1_gpio_set,
862};
863/* ----------------------------------------------------------------------------
864 * pinctrl operations
865 */
866
867/**
868 * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
869 * children sub-nodes
870 *
871 * @np: device tree node to parse
872 */
873static int rza1_dt_node_pin_count(struct device_node *np)
874{
875 struct device_node *child;
876 struct property *of_pins;
877 unsigned int npins;
878
879 of_pins = of_find_property(np, "pinmux", NULL);
880 if (of_pins)
881 return of_pins->length / sizeof(u32);
882
883 npins = 0;
884 for_each_child_of_node(np, child) {
885 of_pins = of_find_property(child, "pinmux", NULL);
886 if (!of_pins)
887 return -EINVAL;
888
889 npins += of_pins->length / sizeof(u32);
890 }
891
892 return npins;
893}
894
895/**
896 * rza1_parse_pmx_function() - parse a pin mux sub-node
897 *
898 * @rza1_pctl: RZ/A1 pin controller device
899 * @np: of pmx sub-node
900 * @mux_confs: array of pin mux configurations to fill with parsed info
901 * @grpins: array of pin ids to mux
902 */
903static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
904 struct device_node *np,
905 struct rza1_mux_conf *mux_confs,
906 unsigned int *grpins)
907{
908 struct pinctrl_dev *pctldev = rza1_pctl->pctl;
909 char const *prop_name = "pinmux";
910 unsigned long *pin_configs;
911 unsigned int npin_configs;
912 struct property *of_pins;
913 unsigned int npins;
914 u8 pinmux_flags;
915 unsigned int i;
916 int ret;
917
918 of_pins = of_find_property(np, prop_name, NULL);
919 if (!of_pins) {
920 dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
921 return -ENOENT;
922 }
923 npins = of_pins->length / sizeof(u32);
924
925 /*
926 * Collect pin configuration properties: they apply to all pins in
927 * this sub-node
928 */
929 ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
930 &npin_configs);
931 if (ret) {
932 dev_err(rza1_pctl->dev,
933 "Unable to parse pin configuration options for %s\n",
934 np->name);
935 return ret;
936 }
937
938 /*
939 * Create a mask with pinmux flags from pin configuration;
940 * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
941 * specified in device tree.
942 */
943 pinmux_flags = 0;
944 for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
945 switch (pinconf_to_config_param(pin_configs[i])) {
946 case PIN_CONFIG_INPUT_ENABLE:
947 pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
948 break;
949 case PIN_CONFIG_OUTPUT:
950 pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
951 default:
952 break;
953
954 }
955
956 kfree(pin_configs);
957
958 /* Collect pin positions and their mux settings. */
959 for (i = 0; i < npins; ++i) {
960 u32 of_pinconf;
961 struct rza1_mux_conf *mux_conf = &mux_confs[i];
962
963 ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
964 if (ret)
965 return ret;
966
967 mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
968 mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
969 mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
970 mux_conf->mux_func = MUX_FUNC(of_pinconf);
971 mux_conf->mux_flags = pinmux_flags;
972
973 if (mux_conf->port >= RZA1_NPORTS ||
974 mux_conf->pin >= RZA1_PINS_PER_PORT) {
975 dev_err(rza1_pctl->dev,
976 "Wrong port %u pin %u for %s property\n",
977 mux_conf->port, mux_conf->pin, prop_name);
978 return -EINVAL;
979 }
980
981 grpins[i] = mux_conf->id;
982 }
983
984 return npins;
985}
986
987/**
988 * rza1_dt_node_to_map() - map a pin mux node to a function/group
989 *
990 * Parse and register a pin mux function.
991 *
992 * @pctldev: pin controller device
993 * @np: device tree node to parse
994 * @map: pointer to pin map (output)
995 * @num_maps: number of collected maps (output)
996 */
997static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
998 struct device_node *np,
999 struct pinctrl_map **map,
1000 unsigned int *num_maps)
1001{
1002 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1003 struct rza1_mux_conf *mux_confs, *mux_conf;
1004 unsigned int *grpins, *grpin;
1005 struct device_node *child;
1006 const char *grpname;
1007 const char **fngrps;
1008 int ret, npins;
1009
1010 npins = rza1_dt_node_pin_count(np);
1011 if (npins < 0) {
1012 dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
1013 return -EINVAL;
1014 }
1015
1016 /*
1017 * Functions are made of 1 group only;
1018 * in fact, functions and groups are identical for this pin controller
1019 * except that functions carry an array of per-pin mux configuration
1020 * settings.
1021 */
1022 mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
1023 GFP_KERNEL);
1024 grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
1025 GFP_KERNEL);
1026 fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
1027
1028 if (!mux_confs || !grpins || !fngrps)
1029 return -ENOMEM;
1030
1031 /*
1032 * Parse the pinmux node.
1033 * If the node does not contain "pinmux" property (-ENOENT)
1034 * that property shall be specified in all its children sub-nodes.
1035 */
1036 mux_conf = &mux_confs[0];
1037 grpin = &grpins[0];
1038
1039 ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
1040 if (ret == -ENOENT)
1041 for_each_child_of_node(np, child) {
1042 ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
1043 grpin);
1044 if (ret < 0)
1045 return ret;
1046
1047 grpin += ret;
1048 mux_conf += ret;
1049 }
1050 else if (ret < 0)
1051 return ret;
1052
1053 /* Register pin group and function name to pinctrl_generic */
1054 grpname = np->name;
1055 fngrps[0] = grpname;
1056
1057 mutex_lock(&rza1_pctl->mutex);
1058 ret = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
1059 NULL);
1060 if (ret) {
1061 mutex_unlock(&rza1_pctl->mutex);
1062 return ret;
1063 }
1064
1065 ret = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
1066 mux_confs);
1067 if (ret)
1068 goto remove_group;
1069 mutex_unlock(&rza1_pctl->mutex);
1070
1071 dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
1072 grpname, npins);
1073
1074 /* Create map where to retrieve function and mux settings from */
1075 *num_maps = 0;
1076 *map = kzalloc(sizeof(**map), GFP_KERNEL);
1077 if (!*map) {
1078 ret = -ENOMEM;
1079 goto remove_function;
1080 }
1081
1082 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1083 (*map)->data.mux.group = np->name;
1084 (*map)->data.mux.function = np->name;
1085 *num_maps = 1;
1086
1087 return 0;
1088
1089remove_function:
1090 mutex_lock(&rza1_pctl->mutex);
1091 pinmux_generic_remove_last_function(pctldev);
1092
1093remove_group:
1094 pinctrl_generic_remove_last_group(pctldev);
1095 mutex_unlock(&rza1_pctl->mutex);
1096
1097 dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
1098 grpname);
1099
1100 return ret;
1101}
1102
1103static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
1104 struct pinctrl_map *map, unsigned int num_maps)
1105{
1106 kfree(map);
1107}
1108
1109static const struct pinctrl_ops rza1_pinctrl_ops = {
1110 .get_groups_count = pinctrl_generic_get_group_count,
1111 .get_group_name = pinctrl_generic_get_group_name,
1112 .get_group_pins = pinctrl_generic_get_group_pins,
1113 .dt_node_to_map = rza1_dt_node_to_map,
1114 .dt_free_map = rza1_dt_free_map,
1115};
1116
1117/* ----------------------------------------------------------------------------
1118 * pinmux operations
1119 */
1120
1121/**
1122 * rza1_set_mux() - retrieve pins from a group and apply their mux settings
1123 *
1124 * @pctldev: pin controller device
1125 * @selector: function selector
1126 * @group: group selector
1127 */
1128static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
1129 unsigned int group)
1130{
1131 struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
1132 struct rza1_mux_conf *mux_confs;
1133 struct function_desc *func;
1134 struct group_desc *grp;
1135 int i;
1136
1137 grp = pinctrl_generic_get_group(pctldev, group);
1138 if (!grp)
1139 return -EINVAL;
1140
1141 func = pinmux_generic_get_function(pctldev, selector);
1142 if (!func)
1143 return -EINVAL;
1144
1145 mux_confs = (struct rza1_mux_conf *)func->data;
1146 for (i = 0; i < grp->num_pins; ++i) {
1147 int ret;
1148
1149 ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
1150 if (ret)
1151 return ret;
1152 }
1153
1154 return 0;
1155}
1156
b82bfae1 1157static const struct pinmux_ops rza1_pinmux_ops = {
5a49b644
JM		 1158 .get_functions_count = pinmux_generic_get_function_count,
1159 .get_function_name = pinmux_generic_get_function_name,
1160 .get_function_groups = pinmux_generic_get_function_groups,
1161 .set_mux = rza1_set_mux,
1162 .strict = true,
1163};
1164
1165/* ----------------------------------------------------------------------------
1166 * RZ/A1 pin controller driver operations
1167 */
1168
1169static unsigned int rza1_count_gpio_chips(struct device_node *np)
1170{
1171 struct device_node *child;
1172 unsigned int count = 0;
1173
1174 for_each_child_of_node(np, child) {
1175 if (!of_property_read_bool(child, "gpio-controller"))
1176 continue;
1177
1178 count++;
1179 }
1180
1181 return count;
1182}
1183
1184/**
1185 * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
1186 *
1187 * The gpio controller subnode shall provide a "gpio-ranges" list property as
1188 * defined by gpio device tree binding documentation.
1189 *
1190 * @rza1_pctl: RZ/A1 pin controller device
1191 * @np: of gpio-controller node
1192 * @chip: gpio chip to register to gpiolib
1193 * @range: pin range to register to pinctrl core
1194 */
1195static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
1196 struct device_node *np,
1197 struct gpio_chip *chip,
1198 struct pinctrl_gpio_range *range)
1199{
1200 const char *list_name = "gpio-ranges";
1201 struct of_phandle_args of_args;
1202 unsigned int gpioport;
1203 u32 pinctrl_base;
1204 int ret;
1205
1206 ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
1207 if (ret) {
1208 dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
1209 list_name);
1210 return ret;
1211 }
1212
1213 /*
1214 * Find out on which port this gpio-chip maps to by inspecting the
1215 * second argument of the "gpio-ranges" property.
1216 */
1217 pinctrl_base = of_args.args[1];
1218 gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
faaaba06 1219 if (gpioport >= RZA1_NPORTS) {
5a49b644
JM		 1220 dev_err(rza1_pctl->dev,
1221 "Invalid values in property %s\n", list_name);
1222 return -EINVAL;
1223 }
1224
1225 *chip = rza1_gpiochip_template;
1226 chip->base = -1;
cb715d0a
JM		 1227 chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%s",
1228 np->name);
5a49b644
JM		 1229 chip->ngpio = of_args.args[2];
1230 chip->of_node = np;
1231 chip->parent = rza1_pctl->dev;
1232
1233 range->id = gpioport;
1234 range->name = chip->label;
1235 range->pin_base = range->base = pinctrl_base;
1236 range->npins = of_args.args[2];
1237 range->gc = chip;
1238
1239 ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
1240 &rza1_pctl->ports[gpioport]);
1241 if (ret)
1242 return ret;
1243
1244 pinctrl_add_gpio_range(rza1_pctl->pctl, range);
1245
1246 dev_info(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
1247 chip->label, chip->ngpio);
1248
1249 return 0;
1250}
1251
1252/**
1253 * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
1254 *
1255 * @rza1_pctl: RZ/A1 pin controller device
1256 */
1257static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
1258{
1259 struct device_node *np = rza1_pctl->dev->of_node;
1260 struct pinctrl_gpio_range *gpio_ranges;
1261 struct gpio_chip *gpio_chips;
1262 struct device_node *child;
1263 unsigned int ngpiochips;
1264 unsigned int i;
1265 int ret;
1266
1267 ngpiochips = rza1_count_gpio_chips(np);
1268 if (ngpiochips == 0) {
1269 dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
1270 return 0;
1271 }
1272
1273 gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1274 sizeof(*gpio_chips), GFP_KERNEL);
1275 gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
1276 sizeof(*gpio_ranges), GFP_KERNEL);
1277 if (!gpio_chips || !gpio_ranges)
1278 return -ENOMEM;
1279
1280 i = 0;
1281 for_each_child_of_node(np, child) {
1282 if (!of_property_read_bool(child, "gpio-controller"))
1283 continue;
1284
1285 ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
1286 &gpio_ranges[i]);
1287 if (ret)
1288 goto gpiochip_remove;
1289
1290 ++i;
1291 }
1292
1293 dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
1294
1295 return 0;
1296
1297gpiochip_remove:
1298 for (; i > 0; i--)
1299 devm_gpiochip_remove(rza1_pctl->dev, &gpio_chips[i - 1]);
1300
1301 return ret;
1302}
1303
1304/**
1305 * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
1306 * them to pinctrl and gpio cores.
1307 *
1308 * @rza1_pctl: RZ/A1 pin controller device
1309 */
1310static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
1311{
1312 struct pinctrl_pin_desc *pins;
1313 struct rza1_port *ports;
1314 unsigned int i;
1315 int ret;
1316
1317 pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
1318 GFP_KERNEL);
1319 ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
1320 GFP_KERNEL);
1321 if (!pins || !ports)
1322 return -ENOMEM;
1323
1324 rza1_pctl->pins = pins;
1325 rza1_pctl->desc.pins = pins;
1326 rza1_pctl->desc.npins = RZA1_NPINS;
1327 rza1_pctl->ports = ports;
1328
1329 for (i = 0; i < RZA1_NPINS; ++i) {
1330 unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
1331 unsigned int port = RZA1_PIN_ID_TO_PORT(i);
1332
1333 pins[i].number = i;
1334 pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
1335 "P%u-%u", port, pin);
1336
1337 if (i % RZA1_PINS_PER_PORT == 0) {
1338 /*
1339 * Setup ports;
1340 * they provide per-port lock and logical base address.
1341 */
1342 unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
1343
1344 ports[port_id].id = port_id;
1345 ports[port_id].base = rza1_pctl->base;
1346 ports[port_id].pins = &pins[i];
1347 spin_lock_init(&ports[port_id].lock);
1348 }
1349 }
1350
1351 ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
1352 rza1_pctl, &rza1_pctl->pctl);
1353 if (ret) {
1354 dev_err(rza1_pctl->dev,
1355 "RZ/A1 pin controller registration failed\n");
1356 return ret;
1357 }
1358
1359 ret = pinctrl_enable(rza1_pctl->pctl);
1360 if (ret) {
1361 dev_err(rza1_pctl->dev,
1362 "RZ/A1 pin controller failed to start\n");
1363 return ret;
1364 }
1365
1366 ret = rza1_gpio_register(rza1_pctl);
1367 if (ret) {
1368 dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
1369 return ret;
1370 }
1371
1372 return 0;
1373}
1374
1375static int rza1_pinctrl_probe(struct platform_device *pdev)
1376{
1377 struct rza1_pinctrl *rza1_pctl;
1378 struct resource *res;
1379 int ret;
1380
1381 rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
1382 if (!rza1_pctl)
1383 return -ENOMEM;
1384
1385 rza1_pctl->dev = &pdev->dev;
1386
1387 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5a49b644
JM		 1388 rza1_pctl->base = devm_ioremap_resource(&pdev->dev, res);
1389 if (IS_ERR(rza1_pctl->base))
1390 return PTR_ERR(rza1_pctl->base);
1391
1392 mutex_init(&rza1_pctl->mutex);
1393
1394 platform_set_drvdata(pdev, rza1_pctl);
1395
1396 rza1_pctl->desc.name = DRIVER_NAME;
1397 rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
1398 rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
1399 rza1_pctl->desc.owner = THIS_MODULE;
1400 rza1_pctl->data = of_device_get_match_data(&pdev->dev);
1401
1402 ret = rza1_pinctrl_register(rza1_pctl);
1403 if (ret)
1404 return ret;
1405
1406 dev_info(&pdev->dev,
1407 "RZ/A1 pin controller and gpio successfully registered\n");
1408
1409 return 0;
1410}
1411
1412static const struct of_device_id rza1_pinctrl_of_match[] = {
1413 {
039bc58e 1414 /* RZ/A1H, RZ/A1M */
5a49b644
JM		 1415 .compatible = "renesas,r7s72100-ports",
1416 .data = &rza1h_pmx_conf,
1417 },
039bc58e
CB		 1418 {
1419 /* RZ/A1L */
1420 .compatible = "renesas,r7s72102-ports",
1421 .data = &rza1l_pmx_conf,
1422 },
5a49b644
JM		 1423 { }
1424};
1425
1426static struct platform_driver rza1_pinctrl_driver = {
1427 .driver = {
1428 .name = DRIVER_NAME,
1429 .of_match_table = rza1_pinctrl_of_match,
1430 },
1431 .probe = rza1_pinctrl_probe,
1432};
1433
1434static int __init rza1_pinctrl_init(void)
1435{
1436 return platform_driver_register(&rza1_pinctrl_driver);
1437}
1438core_initcall(rza1_pinctrl_init);
1439
1440MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
1441MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
1442MODULE_LICENSE("GPL v2");
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