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8b8b091b TL |
1 | /* |
2 | * Generic device tree based pinctrl driver for one register per pin | |
3 | * type pinmux controllers | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/list.h> | |
3e6cee17 TL |
18 | #include <linux/interrupt.h> |
19 | ||
20 | #include <linux/irqchip/chained_irq.h> | |
8b8b091b TL |
21 | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_address.h> | |
3e6cee17 | 25 | #include <linux/of_irq.h> |
8b8b091b TL |
26 | |
27 | #include <linux/pinctrl/pinctrl.h> | |
28 | #include <linux/pinctrl/pinmux.h> | |
9dddb4df | 29 | #include <linux/pinctrl/pinconf-generic.h> |
8b8b091b | 30 | |
dc7743aa TL |
31 | #include <linux/platform_data/pinctrl-single.h> |
32 | ||
8b8b091b | 33 | #include "core.h" |
4622215f | 34 | #include "devicetree.h" |
9dddb4df | 35 | #include "pinconf.h" |
571aec4d | 36 | #include "pinmux.h" |
8b8b091b TL |
37 | |
38 | #define DRIVER_NAME "pinctrl-single" | |
8b8b091b TL |
39 | #define PCS_OFF_DISABLED ~0U |
40 | ||
8b8b091b TL |
41 | /** |
42 | * struct pcs_func_vals - mux function register offset and value pair | |
43 | * @reg: register virtual address | |
44 | * @val: register value | |
45 | */ | |
46 | struct pcs_func_vals { | |
47 | void __iomem *reg; | |
48 | unsigned val; | |
9e605cb6 | 49 | unsigned mask; |
8b8b091b TL |
50 | }; |
51 | ||
9dddb4df HZ |
52 | /** |
53 | * struct pcs_conf_vals - pinconf parameter, pinconf register offset | |
54 | * and value, enable, disable, mask | |
55 | * @param: config parameter | |
56 | * @val: user input bits in the pinconf register | |
57 | * @enable: enable bits in the pinconf register | |
58 | * @disable: disable bits in the pinconf register | |
59 | * @mask: mask bits in the register value | |
60 | */ | |
61 | struct pcs_conf_vals { | |
62 | enum pin_config_param param; | |
63 | unsigned val; | |
64 | unsigned enable; | |
65 | unsigned disable; | |
66 | unsigned mask; | |
67 | }; | |
68 | ||
69 | /** | |
70 | * struct pcs_conf_type - pinconf property name, pinconf param pair | |
71 | * @name: property name in DTS file | |
72 | * @param: config parameter | |
73 | */ | |
74 | struct pcs_conf_type { | |
75 | const char *name; | |
76 | enum pin_config_param param; | |
77 | }; | |
78 | ||
8b8b091b TL |
79 | /** |
80 | * struct pcs_function - pinctrl function | |
81 | * @name: pinctrl function name | |
82 | * @vals: register and vals array | |
83 | * @nvals: number of entries in vals array | |
84 | * @pgnames: array of pingroup names the function uses | |
85 | * @npgnames: number of pingroup names the function uses | |
86 | * @node: list node | |
87 | */ | |
88 | struct pcs_function { | |
89 | const char *name; | |
90 | struct pcs_func_vals *vals; | |
91 | unsigned nvals; | |
92 | const char **pgnames; | |
93 | int npgnames; | |
9dddb4df HZ |
94 | struct pcs_conf_vals *conf; |
95 | int nconfs; | |
8b8b091b TL |
96 | struct list_head node; |
97 | }; | |
98 | ||
a1a277eb HZ |
99 | /** |
100 | * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function | |
101 | * @offset: offset base of pins | |
102 | * @npins: number pins with the same mux value of gpio function | |
103 | * @gpiofunc: mux value of gpio function | |
104 | * @node: list node | |
105 | */ | |
106 | struct pcs_gpiofunc_range { | |
107 | unsigned offset; | |
108 | unsigned npins; | |
109 | unsigned gpiofunc; | |
110 | struct list_head node; | |
111 | }; | |
112 | ||
8b8b091b TL |
113 | /** |
114 | * struct pcs_data - wrapper for data needed by pinctrl framework | |
115 | * @pa: pindesc array | |
116 | * @cur: index to current element | |
117 | * | |
118 | * REVISIT: We should be able to drop this eventually by adding | |
119 | * support for registering pins individually in the pinctrl | |
120 | * framework for those drivers that don't need a static array. | |
121 | */ | |
122 | struct pcs_data { | |
123 | struct pinctrl_pin_desc *pa; | |
124 | int cur; | |
125 | }; | |
126 | ||
02e483f6 TL |
127 | /** |
128 | * struct pcs_soc_data - SoC specific settings | |
129 | * @flags: initial SoC specific PCS_FEAT_xxx values | |
3e6cee17 TL |
130 | * @irq: optional interrupt for the controller |
131 | * @irq_enable_mask: optional SoC specific interrupt enable mask | |
132 | * @irq_status_mask: optional SoC specific interrupt status mask | |
dc7743aa | 133 | * @rearm: optional SoC specific wake-up rearm function |
02e483f6 TL |
134 | */ |
135 | struct pcs_soc_data { | |
136 | unsigned flags; | |
3e6cee17 TL |
137 | int irq; |
138 | unsigned irq_enable_mask; | |
139 | unsigned irq_status_mask; | |
dc7743aa | 140 | void (*rearm)(void); |
02e483f6 TL |
141 | }; |
142 | ||
8b8b091b TL |
143 | /** |
144 | * struct pcs_device - pinctrl device instance | |
145 | * @res: resources | |
146 | * @base: virtual address of the controller | |
88a1dbde | 147 | * @saved_vals: saved values for the controller |
8b8b091b TL |
148 | * @size: size of the ioremapped area |
149 | * @dev: device entry | |
4622215f | 150 | * @np: device tree node |
8b8b091b | 151 | * @pctl: pin controller device |
02e483f6 | 152 | * @flags: mask of PCS_FEAT_xxx values |
4622215f TL |
153 | * @missing_nr_pinctrl_cells: for legacy binding, may go away |
154 | * @socdata: soc specific data | |
3e6cee17 | 155 | * @lock: spinlock for register access |
8b8b091b TL |
156 | * @mutex: mutex protecting the lists |
157 | * @width: bits per mux register | |
158 | * @fmask: function register mask | |
159 | * @fshift: function register shift | |
160 | * @foff: value to turn mux off | |
161 | * @fmax: max number of functions in fmask | |
4622215f TL |
162 | * @bits_per_mux: number of bits per mux |
163 | * @bits_per_pin: number of bits per pin | |
8b8b091b | 164 | * @pins: physical pins on the SoC |
a1a277eb | 165 | * @gpiofuncs: list of gpio functions |
3e6cee17 TL |
166 | * @irqs: list of interrupt registers |
167 | * @chip: chip container for this instance | |
168 | * @domain: IRQ domain for this instance | |
8b8b091b TL |
169 | * @desc: pin controller descriptor |
170 | * @read: register read function to use | |
171 | * @write: register write function to use | |
172 | */ | |
173 | struct pcs_device { | |
174 | struct resource *res; | |
175 | void __iomem *base; | |
88a1dbde | 176 | void *saved_vals; |
8b8b091b TL |
177 | unsigned size; |
178 | struct device *dev; | |
4622215f | 179 | struct device_node *np; |
8b8b091b | 180 | struct pinctrl_dev *pctl; |
02e483f6 | 181 | unsigned flags; |
88a1dbde | 182 | #define PCS_CONTEXT_LOSS_OFF (1 << 3) |
3e6cee17 TL |
183 | #define PCS_QUIRK_SHARED_IRQ (1 << 2) |
184 | #define PCS_FEAT_IRQ (1 << 1) | |
02e483f6 | 185 | #define PCS_FEAT_PINCONF (1 << 0) |
4622215f | 186 | struct property *missing_nr_pinctrl_cells; |
3e6cee17 TL |
187 | struct pcs_soc_data socdata; |
188 | raw_spinlock_t lock; | |
8b8b091b TL |
189 | struct mutex mutex; |
190 | unsigned width; | |
191 | unsigned fmask; | |
192 | unsigned fshift; | |
193 | unsigned foff; | |
194 | unsigned fmax; | |
9e605cb6 | 195 | bool bits_per_mux; |
4e7e8017 | 196 | unsigned bits_per_pin; |
8b8b091b | 197 | struct pcs_data pins; |
a1a277eb | 198 | struct list_head gpiofuncs; |
3e6cee17 TL |
199 | struct list_head irqs; |
200 | struct irq_chip chip; | |
201 | struct irq_domain *domain; | |
8b8b091b TL |
202 | struct pinctrl_desc desc; |
203 | unsigned (*read)(void __iomem *reg); | |
204 | void (*write)(unsigned val, void __iomem *reg); | |
205 | }; | |
206 | ||
3e6cee17 TL |
207 | #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) |
208 | #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) | |
02e483f6 TL |
209 | #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) |
210 | ||
9dddb4df HZ |
211 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, |
212 | unsigned long *config); | |
213 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, | |
03b054e9 | 214 | unsigned long *configs, unsigned num_configs); |
9dddb4df HZ |
215 | |
216 | static enum pin_config_param pcs_bias[] = { | |
217 | PIN_CONFIG_BIAS_PULL_DOWN, | |
218 | PIN_CONFIG_BIAS_PULL_UP, | |
219 | }; | |
220 | ||
3c177a16 SH |
221 | /* |
222 | * This lock class tells lockdep that irqchip core that this single | |
223 | * pinctrl can be in a different category than its parents, so it won't | |
224 | * report false recursion. | |
225 | */ | |
226 | static struct lock_class_key pcs_lock_class; | |
227 | ||
39c3fd58 AL |
228 | /* Class for the IRQ request mutex */ |
229 | static struct lock_class_key pcs_request_class; | |
230 | ||
8b8b091b TL |
231 | /* |
232 | * REVISIT: Reads and writes could eventually use regmap or something | |
233 | * generic. But at least on omaps, some mux registers are performance | |
234 | * critical as they may need to be remuxed every time before and after | |
235 | * idle. Adding tests for register access width for every read and | |
236 | * write like regmap is doing is not desired, and caching the registers | |
237 | * does not help in this case. | |
238 | */ | |
239 | ||
240 | static unsigned __maybe_unused pcs_readb(void __iomem *reg) | |
241 | { | |
242 | return readb(reg); | |
243 | } | |
244 | ||
245 | static unsigned __maybe_unused pcs_readw(void __iomem *reg) | |
246 | { | |
247 | return readw(reg); | |
248 | } | |
249 | ||
250 | static unsigned __maybe_unused pcs_readl(void __iomem *reg) | |
251 | { | |
252 | return readl(reg); | |
253 | } | |
254 | ||
255 | static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) | |
256 | { | |
257 | writeb(val, reg); | |
258 | } | |
259 | ||
260 | static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) | |
261 | { | |
262 | writew(val, reg); | |
263 | } | |
264 | ||
265 | static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) | |
266 | { | |
267 | writel(val, reg); | |
268 | } | |
269 | ||
8b8b091b TL |
270 | static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, |
271 | struct seq_file *s, | |
e7ed6718 | 272 | unsigned pin) |
8b8b091b | 273 | { |
7d66ce7f | 274 | struct pcs_device *pcs; |
e7ed6718 | 275 | unsigned val, mux_bytes; |
223decc4 TL |
276 | unsigned long offset; |
277 | size_t pa; | |
7d66ce7f MP |
278 | |
279 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
280 | ||
e7ed6718 | 281 | mux_bytes = pcs->width / BITS_PER_BYTE; |
223decc4 TL |
282 | offset = pin * mux_bytes; |
283 | val = pcs->read(pcs->base + offset); | |
284 | pa = pcs->res->start + offset; | |
7d66ce7f | 285 | |
223decc4 | 286 | seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); |
8b8b091b TL |
287 | } |
288 | ||
289 | static void pcs_dt_free_map(struct pinctrl_dev *pctldev, | |
290 | struct pinctrl_map *map, unsigned num_maps) | |
291 | { | |
292 | struct pcs_device *pcs; | |
293 | ||
294 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
295 | devm_kfree(pcs->dev, map); | |
296 | } | |
297 | ||
298 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
299 | struct device_node *np_config, | |
300 | struct pinctrl_map **map, unsigned *num_maps); | |
301 | ||
022ab148 | 302 | static const struct pinctrl_ops pcs_pinctrl_ops = { |
caeb774e TL |
303 | .get_groups_count = pinctrl_generic_get_group_count, |
304 | .get_group_name = pinctrl_generic_get_group_name, | |
305 | .get_group_pins = pinctrl_generic_get_group_pins, | |
8b8b091b TL |
306 | .pin_dbg_show = pcs_pin_dbg_show, |
307 | .dt_node_to_map = pcs_dt_node_to_map, | |
308 | .dt_free_map = pcs_dt_free_map, | |
309 | }; | |
310 | ||
9dddb4df HZ |
311 | static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, |
312 | struct pcs_function **func) | |
313 | { | |
314 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); | |
315 | struct pin_desc *pdesc = pin_desc_get(pctldev, pin); | |
316 | const struct pinctrl_setting_mux *setting; | |
571aec4d | 317 | struct function_desc *function; |
9dddb4df HZ |
318 | unsigned fselector; |
319 | ||
320 | /* If pin is not described in DTS & enabled, mux_setting is NULL. */ | |
321 | setting = pdesc->mux_setting; | |
322 | if (!setting) | |
323 | return -ENOTSUPP; | |
324 | fselector = setting->func; | |
571aec4d TL |
325 | function = pinmux_generic_get_function(pctldev, fselector); |
326 | *func = function->data; | |
9dddb4df HZ |
327 | if (!(*func)) { |
328 | dev_err(pcs->dev, "%s could not find function%i\n", | |
329 | __func__, fselector); | |
330 | return -ENOTSUPP; | |
331 | } | |
332 | return 0; | |
333 | } | |
334 | ||
03e9f0ca | 335 | static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, |
8b8b091b TL |
336 | unsigned group) |
337 | { | |
338 | struct pcs_device *pcs; | |
571aec4d | 339 | struct function_desc *function; |
8b8b091b TL |
340 | struct pcs_function *func; |
341 | int i; | |
342 | ||
343 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
477ac771 HZ |
344 | /* If function mask is null, needn't enable it. */ |
345 | if (!pcs->fmask) | |
346 | return 0; | |
571aec4d TL |
347 | function = pinmux_generic_get_function(pctldev, fselector); |
348 | func = function->data; | |
8b8b091b TL |
349 | if (!func) |
350 | return -EINVAL; | |
351 | ||
352 | dev_dbg(pcs->dev, "enabling %s function%i\n", | |
353 | func->name, fselector); | |
354 | ||
355 | for (i = 0; i < func->nvals; i++) { | |
356 | struct pcs_func_vals *vals; | |
3e6cee17 | 357 | unsigned long flags; |
9e605cb6 | 358 | unsigned val, mask; |
8b8b091b TL |
359 | |
360 | vals = &func->vals[i]; | |
3e6cee17 | 361 | raw_spin_lock_irqsave(&pcs->lock, flags); |
8b8b091b | 362 | val = pcs->read(vals->reg); |
4e7e8017 MP |
363 | |
364 | if (pcs->bits_per_mux) | |
365 | mask = vals->mask; | |
9e605cb6 | 366 | else |
4e7e8017 | 367 | mask = pcs->fmask; |
9e605cb6 PU |
368 | |
369 | val &= ~mask; | |
370 | val |= (vals->val & mask); | |
8b8b091b | 371 | pcs->write(val, vals->reg); |
3e6cee17 | 372 | raw_spin_unlock_irqrestore(&pcs->lock, flags); |
8b8b091b TL |
373 | } |
374 | ||
375 | return 0; | |
376 | } | |
377 | ||
8b8b091b | 378 | static int pcs_request_gpio(struct pinctrl_dev *pctldev, |
a1a277eb | 379 | struct pinctrl_gpio_range *range, unsigned pin) |
8b8b091b | 380 | { |
a1a277eb HZ |
381 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
382 | struct pcs_gpiofunc_range *frange = NULL; | |
383 | struct list_head *pos, *tmp; | |
384 | int mux_bytes = 0; | |
385 | unsigned data; | |
386 | ||
477ac771 HZ |
387 | /* If function mask is null, return directly. */ |
388 | if (!pcs->fmask) | |
389 | return -ENOTSUPP; | |
390 | ||
a1a277eb HZ |
391 | list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { |
392 | frange = list_entry(pos, struct pcs_gpiofunc_range, node); | |
393 | if (pin >= frange->offset + frange->npins | |
394 | || pin < frange->offset) | |
395 | continue; | |
396 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
45dcb54f DL |
397 | |
398 | if (pcs->bits_per_mux) { | |
399 | int byte_num, offset, pin_shift; | |
400 | ||
401 | byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE; | |
402 | offset = (byte_num / mux_bytes) * mux_bytes; | |
403 | pin_shift = pin % (pcs->width / pcs->bits_per_pin) * | |
404 | pcs->bits_per_pin; | |
405 | ||
406 | data = pcs->read(pcs->base + offset); | |
407 | data &= ~(pcs->fmask << pin_shift); | |
408 | data |= frange->gpiofunc << pin_shift; | |
409 | pcs->write(data, pcs->base + offset); | |
410 | } else { | |
411 | data = pcs->read(pcs->base + pin * mux_bytes); | |
412 | data &= ~pcs->fmask; | |
413 | data |= frange->gpiofunc; | |
414 | pcs->write(data, pcs->base + pin * mux_bytes); | |
415 | } | |
a1a277eb HZ |
416 | break; |
417 | } | |
418 | return 0; | |
8b8b091b TL |
419 | } |
420 | ||
022ab148 | 421 | static const struct pinmux_ops pcs_pinmux_ops = { |
571aec4d TL |
422 | .get_functions_count = pinmux_generic_get_function_count, |
423 | .get_function_name = pinmux_generic_get_function_name, | |
424 | .get_function_groups = pinmux_generic_get_function_groups, | |
9e3a979f | 425 | .set_mux = pcs_set_mux, |
8b8b091b TL |
426 | .gpio_request_enable = pcs_request_gpio, |
427 | }; | |
428 | ||
9dddb4df HZ |
429 | /* Clear BIAS value */ |
430 | static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) | |
431 | { | |
432 | unsigned long config; | |
433 | int i; | |
434 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
435 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
03b054e9 | 436 | pcs_pinconf_set(pctldev, pin, &config, 1); |
9dddb4df HZ |
437 | } |
438 | } | |
439 | ||
440 | /* | |
441 | * Check whether PIN_CONFIG_BIAS_DISABLE is valid. | |
442 | * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. | |
443 | */ | |
444 | static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) | |
445 | { | |
446 | unsigned long config; | |
447 | int i; | |
448 | ||
449 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
450 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
451 | if (!pcs_pinconf_get(pctldev, pin, &config)) | |
452 | goto out; | |
453 | } | |
454 | return true; | |
455 | out: | |
456 | return false; | |
457 | } | |
458 | ||
8b8b091b TL |
459 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, |
460 | unsigned pin, unsigned long *config) | |
461 | { | |
9dddb4df HZ |
462 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
463 | struct pcs_function *func; | |
464 | enum pin_config_param param; | |
465 | unsigned offset = 0, data = 0, i, j, ret; | |
466 | ||
467 | ret = pcs_get_function(pctldev, pin, &func); | |
468 | if (ret) | |
469 | return ret; | |
470 | ||
471 | for (i = 0; i < func->nconfs; i++) { | |
472 | param = pinconf_to_config_param(*config); | |
473 | if (param == PIN_CONFIG_BIAS_DISABLE) { | |
474 | if (pcs_pinconf_bias_disable(pctldev, pin)) { | |
475 | *config = 0; | |
476 | return 0; | |
477 | } else { | |
478 | return -ENOTSUPP; | |
479 | } | |
480 | } else if (param != func->conf[i].param) { | |
481 | continue; | |
482 | } | |
483 | ||
484 | offset = pin * (pcs->width / BITS_PER_BYTE); | |
485 | data = pcs->read(pcs->base + offset) & func->conf[i].mask; | |
486 | switch (func->conf[i].param) { | |
487 | /* 4 parameters */ | |
488 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
489 | case PIN_CONFIG_BIAS_PULL_UP: | |
490 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
491 | if ((data != func->conf[i].enable) || | |
492 | (data == func->conf[i].disable)) | |
493 | return -ENOTSUPP; | |
494 | *config = 0; | |
495 | break; | |
496 | /* 2 parameters */ | |
497 | case PIN_CONFIG_INPUT_SCHMITT: | |
498 | for (j = 0; j < func->nconfs; j++) { | |
499 | switch (func->conf[j].param) { | |
500 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
501 | if (data != func->conf[j].enable) | |
502 | return -ENOTSUPP; | |
503 | break; | |
504 | default: | |
505 | break; | |
506 | } | |
507 | } | |
508 | *config = data; | |
509 | break; | |
510 | case PIN_CONFIG_DRIVE_STRENGTH: | |
511 | case PIN_CONFIG_SLEW_RATE: | |
4bd75477 | 512 | case PIN_CONFIG_LOW_POWER_MODE: |
9dddb4df HZ |
513 | default: |
514 | *config = data; | |
515 | break; | |
516 | } | |
517 | return 0; | |
518 | } | |
8b8b091b TL |
519 | return -ENOTSUPP; |
520 | } | |
521 | ||
522 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
523 | unsigned pin, unsigned long *configs, |
524 | unsigned num_configs) | |
8b8b091b | 525 | { |
9dddb4df HZ |
526 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
527 | struct pcs_function *func; | |
7cba5b3f | 528 | unsigned offset = 0, shift = 0, i, data, ret; |
58957d2e | 529 | u32 arg; |
03b054e9 | 530 | int j; |
9dddb4df HZ |
531 | |
532 | ret = pcs_get_function(pctldev, pin, &func); | |
533 | if (ret) | |
534 | return ret; | |
535 | ||
03b054e9 SY |
536 | for (j = 0; j < num_configs; j++) { |
537 | for (i = 0; i < func->nconfs; i++) { | |
538 | if (pinconf_to_config_param(configs[j]) | |
539 | != func->conf[i].param) | |
540 | continue; | |
541 | ||
9dddb4df HZ |
542 | offset = pin * (pcs->width / BITS_PER_BYTE); |
543 | data = pcs->read(pcs->base + offset); | |
03b054e9 | 544 | arg = pinconf_to_config_argument(configs[j]); |
9dddb4df HZ |
545 | switch (func->conf[i].param) { |
546 | /* 2 parameters */ | |
547 | case PIN_CONFIG_INPUT_SCHMITT: | |
548 | case PIN_CONFIG_DRIVE_STRENGTH: | |
549 | case PIN_CONFIG_SLEW_RATE: | |
4bd75477 | 550 | case PIN_CONFIG_LOW_POWER_MODE: |
9dddb4df | 551 | shift = ffs(func->conf[i].mask) - 1; |
9dddb4df HZ |
552 | data &= ~func->conf[i].mask; |
553 | data |= (arg << shift) & func->conf[i].mask; | |
554 | break; | |
555 | /* 4 parameters */ | |
556 | case PIN_CONFIG_BIAS_DISABLE: | |
557 | pcs_pinconf_clear_bias(pctldev, pin); | |
558 | break; | |
559 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
560 | case PIN_CONFIG_BIAS_PULL_UP: | |
7cba5b3f | 561 | if (arg) |
9dddb4df HZ |
562 | pcs_pinconf_clear_bias(pctldev, pin); |
563 | /* fall through */ | |
564 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
565 | data &= ~func->conf[i].mask; | |
7cba5b3f | 566 | if (arg) |
9dddb4df HZ |
567 | data |= func->conf[i].enable; |
568 | else | |
569 | data |= func->conf[i].disable; | |
570 | break; | |
571 | default: | |
572 | return -ENOTSUPP; | |
573 | } | |
574 | pcs->write(data, pcs->base + offset); | |
03b054e9 SY |
575 | |
576 | break; | |
9dddb4df | 577 | } |
03b054e9 SY |
578 | if (i >= func->nconfs) |
579 | return -ENOTSUPP; | |
580 | } /* for each config */ | |
581 | ||
582 | return 0; | |
8b8b091b TL |
583 | } |
584 | ||
585 | static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, | |
586 | unsigned group, unsigned long *config) | |
587 | { | |
9dddb4df HZ |
588 | const unsigned *pins; |
589 | unsigned npins, old = 0; | |
590 | int i, ret; | |
591 | ||
caeb774e | 592 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
593 | if (ret) |
594 | return ret; | |
595 | for (i = 0; i < npins; i++) { | |
596 | if (pcs_pinconf_get(pctldev, pins[i], config)) | |
597 | return -ENOTSUPP; | |
598 | /* configs do not match between two pins */ | |
599 | if (i && (old != *config)) | |
600 | return -ENOTSUPP; | |
601 | old = *config; | |
602 | } | |
603 | return 0; | |
8b8b091b TL |
604 | } |
605 | ||
606 | static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
607 | unsigned group, unsigned long *configs, |
608 | unsigned num_configs) | |
8b8b091b | 609 | { |
9dddb4df HZ |
610 | const unsigned *pins; |
611 | unsigned npins; | |
612 | int i, ret; | |
613 | ||
caeb774e | 614 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
615 | if (ret) |
616 | return ret; | |
617 | for (i = 0; i < npins; i++) { | |
03b054e9 | 618 | if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) |
9dddb4df HZ |
619 | return -ENOTSUPP; |
620 | } | |
621 | return 0; | |
8b8b091b TL |
622 | } |
623 | ||
624 | static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
9dddb4df | 625 | struct seq_file *s, unsigned pin) |
8b8b091b TL |
626 | { |
627 | } | |
628 | ||
629 | static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
630 | struct seq_file *s, unsigned selector) | |
631 | { | |
632 | } | |
633 | ||
9dddb4df HZ |
634 | static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, |
635 | struct seq_file *s, | |
636 | unsigned long config) | |
637 | { | |
638 | pinconf_generic_dump_config(pctldev, s, config); | |
639 | } | |
640 | ||
022ab148 | 641 | static const struct pinconf_ops pcs_pinconf_ops = { |
8b8b091b TL |
642 | .pin_config_get = pcs_pinconf_get, |
643 | .pin_config_set = pcs_pinconf_set, | |
644 | .pin_config_group_get = pcs_pinconf_group_get, | |
645 | .pin_config_group_set = pcs_pinconf_group_set, | |
646 | .pin_config_dbg_show = pcs_pinconf_dbg_show, | |
647 | .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, | |
9dddb4df | 648 | .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, |
a7bbdd7f | 649 | .is_generic = true, |
8b8b091b TL |
650 | }; |
651 | ||
652 | /** | |
653 | * pcs_add_pin() - add a pin to the static per controller pin array | |
654 | * @pcs: pcs driver instance | |
655 | * @offset: register offset from base | |
656 | */ | |
6f924b0b MP |
657 | static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, |
658 | unsigned pin_pos) | |
8b8b091b | 659 | { |
58968625 | 660 | struct pcs_soc_data *pcs_soc = &pcs->socdata; |
8b8b091b | 661 | struct pinctrl_pin_desc *pin; |
8b8b091b TL |
662 | int i; |
663 | ||
664 | i = pcs->pins.cur; | |
665 | if (i >= pcs->desc.npins) { | |
666 | dev_err(pcs->dev, "too many pins, max %i\n", | |
667 | pcs->desc.npins); | |
668 | return -ENOMEM; | |
669 | } | |
670 | ||
58968625 TL |
671 | if (pcs_soc->irq_enable_mask) { |
672 | unsigned val; | |
673 | ||
674 | val = pcs->read(pcs->base + offset); | |
675 | if (val & pcs_soc->irq_enable_mask) { | |
676 | dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", | |
677 | (unsigned long)pcs->res->start + offset, val); | |
678 | val &= ~pcs_soc->irq_enable_mask; | |
679 | pcs->write(val, pcs->base + offset); | |
680 | } | |
681 | } | |
682 | ||
8b8b091b | 683 | pin = &pcs->pins.pa[i]; |
8b8b091b TL |
684 | pin->number = i; |
685 | pcs->pins.cur++; | |
686 | ||
687 | return i; | |
688 | } | |
689 | ||
690 | /** | |
691 | * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver | |
692 | * @pcs: pcs driver instance | |
693 | * | |
694 | * In case of errors, resources are freed in pcs_free_resources. | |
695 | * | |
696 | * If your hardware needs holes in the address space, then just set | |
697 | * up multiple driver instances. | |
698 | */ | |
150632b0 | 699 | static int pcs_allocate_pin_table(struct pcs_device *pcs) |
8b8b091b TL |
700 | { |
701 | int mux_bytes, nr_pins, i; | |
6f924b0b | 702 | int num_pins_in_register = 0; |
8b8b091b TL |
703 | |
704 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
4e7e8017 MP |
705 | |
706 | if (pcs->bits_per_mux) { | |
707 | pcs->bits_per_pin = fls(pcs->fmask); | |
708 | nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; | |
6f924b0b | 709 | num_pins_in_register = pcs->width / pcs->bits_per_pin; |
4e7e8017 MP |
710 | } else { |
711 | nr_pins = pcs->size / mux_bytes; | |
712 | } | |
8b8b091b TL |
713 | |
714 | dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); | |
a86854d0 KC |
715 | pcs->pins.pa = devm_kcalloc(pcs->dev, |
716 | nr_pins, sizeof(*pcs->pins.pa), | |
8b8b091b TL |
717 | GFP_KERNEL); |
718 | if (!pcs->pins.pa) | |
719 | return -ENOMEM; | |
720 | ||
8b8b091b TL |
721 | pcs->desc.pins = pcs->pins.pa; |
722 | pcs->desc.npins = nr_pins; | |
723 | ||
724 | for (i = 0; i < pcs->desc.npins; i++) { | |
725 | unsigned offset; | |
726 | int res; | |
4e7e8017 | 727 | int byte_num; |
6f924b0b | 728 | int pin_pos = 0; |
8b8b091b | 729 | |
4e7e8017 MP |
730 | if (pcs->bits_per_mux) { |
731 | byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; | |
732 | offset = (byte_num / mux_bytes) * mux_bytes; | |
6f924b0b | 733 | pin_pos = i % num_pins_in_register; |
4e7e8017 MP |
734 | } else { |
735 | offset = i * mux_bytes; | |
736 | } | |
6f924b0b | 737 | res = pcs_add_pin(pcs, offset, pin_pos); |
8b8b091b TL |
738 | if (res < 0) { |
739 | dev_err(pcs->dev, "error adding pins: %i\n", res); | |
740 | return res; | |
741 | } | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
747 | /** | |
748 | * pcs_add_function() - adds a new function to the function list | |
749 | * @pcs: pcs driver instance | |
a4ab1086 | 750 | * @fcn: new function allocated |
8b8b091b TL |
751 | * @name: name of the function |
752 | * @vals: array of mux register value pairs used by the function | |
753 | * @nvals: number of mux register value pairs | |
754 | * @pgnames: array of pingroup names for the function | |
755 | * @npgnames: number of pingroup names | |
a4ab1086 TL |
756 | * |
757 | * Caller must take care of locking. | |
8b8b091b | 758 | */ |
a4ab1086 TL |
759 | static int pcs_add_function(struct pcs_device *pcs, |
760 | struct pcs_function **fcn, | |
761 | const char *name, | |
762 | struct pcs_func_vals *vals, | |
763 | unsigned int nvals, | |
764 | const char **pgnames, | |
765 | unsigned int npgnames) | |
8b8b091b TL |
766 | { |
767 | struct pcs_function *function; | |
a4ab1086 | 768 | int selector; |
8b8b091b TL |
769 | |
770 | function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); | |
771 | if (!function) | |
a4ab1086 | 772 | return -ENOMEM; |
8b8b091b | 773 | |
8b8b091b TL |
774 | function->vals = vals; |
775 | function->nvals = nvals; | |
8b8b091b | 776 | |
a4ab1086 TL |
777 | selector = pinmux_generic_add_function(pcs->pctl, name, |
778 | pgnames, npgnames, | |
779 | function); | |
780 | if (selector < 0) { | |
781 | devm_kfree(pcs->dev, function); | |
782 | *fcn = NULL; | |
783 | } else { | |
784 | *fcn = function; | |
785 | } | |
8b8b091b | 786 | |
a4ab1086 | 787 | return selector; |
8b8b091b TL |
788 | } |
789 | ||
8b8b091b TL |
790 | /** |
791 | * pcs_get_pin_by_offset() - get a pin index based on the register offset | |
792 | * @pcs: pcs driver instance | |
793 | * @offset: register offset from the base | |
794 | * | |
795 | * Note that this is OK as long as the pins are in a static array. | |
796 | */ | |
797 | static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) | |
798 | { | |
799 | unsigned index; | |
800 | ||
801 | if (offset >= pcs->size) { | |
802 | dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
803 | offset, pcs->size); | |
804 | return -EINVAL; | |
805 | } | |
806 | ||
4e7e8017 MP |
807 | if (pcs->bits_per_mux) |
808 | index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; | |
809 | else | |
810 | index = offset / (pcs->width / BITS_PER_BYTE); | |
8b8b091b TL |
811 | |
812 | return index; | |
813 | } | |
814 | ||
9dddb4df HZ |
815 | /* |
816 | * check whether data matches enable bits or disable bits | |
817 | * Return value: 1 for matching enable bits, 0 for matching disable bits, | |
818 | * and negative value for matching failure. | |
819 | */ | |
820 | static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) | |
821 | { | |
822 | int ret = -EINVAL; | |
823 | ||
824 | if (data == enable) | |
825 | ret = 1; | |
826 | else if (data == disable) | |
827 | ret = 0; | |
828 | return ret; | |
829 | } | |
830 | ||
831 | static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, | |
832 | unsigned value, unsigned enable, unsigned disable, | |
833 | unsigned mask) | |
834 | { | |
835 | (*conf)->param = param; | |
836 | (*conf)->val = value; | |
837 | (*conf)->enable = enable; | |
838 | (*conf)->disable = disable; | |
839 | (*conf)->mask = mask; | |
840 | (*conf)++; | |
841 | } | |
842 | ||
843 | static void add_setting(unsigned long **setting, enum pin_config_param param, | |
844 | unsigned arg) | |
845 | { | |
846 | **setting = pinconf_to_config_packed(param, arg); | |
847 | (*setting)++; | |
848 | } | |
849 | ||
850 | /* add pinconf setting with 2 parameters */ | |
851 | static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, | |
852 | const char *name, enum pin_config_param param, | |
853 | struct pcs_conf_vals **conf, unsigned long **settings) | |
854 | { | |
7cba5b3f | 855 | unsigned value[2], shift; |
9dddb4df HZ |
856 | int ret; |
857 | ||
858 | ret = of_property_read_u32_array(np, name, value, 2); | |
859 | if (ret) | |
860 | return; | |
861 | /* set value & mask */ | |
862 | value[0] &= value[1]; | |
7cba5b3f | 863 | shift = ffs(value[1]) - 1; |
9dddb4df HZ |
864 | /* skip enable & disable */ |
865 | add_config(conf, param, value[0], 0, 0, value[1]); | |
7cba5b3f | 866 | add_setting(settings, param, value[0] >> shift); |
9dddb4df HZ |
867 | } |
868 | ||
869 | /* add pinconf setting with 4 parameters */ | |
870 | static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, | |
871 | const char *name, enum pin_config_param param, | |
872 | struct pcs_conf_vals **conf, unsigned long **settings) | |
873 | { | |
874 | unsigned value[4]; | |
875 | int ret; | |
876 | ||
877 | /* value to set, enable, disable, mask */ | |
878 | ret = of_property_read_u32_array(np, name, value, 4); | |
879 | if (ret) | |
880 | return; | |
881 | if (!value[3]) { | |
882 | dev_err(pcs->dev, "mask field of the property can't be 0\n"); | |
883 | return; | |
884 | } | |
885 | value[0] &= value[3]; | |
886 | value[1] &= value[3]; | |
887 | value[2] &= value[3]; | |
888 | ret = pcs_config_match(value[0], value[1], value[2]); | |
889 | if (ret < 0) | |
890 | dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); | |
891 | add_config(conf, param, value[0], value[1], value[2], value[3]); | |
892 | add_setting(settings, param, ret); | |
893 | } | |
894 | ||
895 | static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, | |
896 | struct pcs_function *func, | |
897 | struct pinctrl_map **map) | |
898 | ||
899 | { | |
900 | struct pinctrl_map *m = *map; | |
901 | int i = 0, nconfs = 0; | |
902 | unsigned long *settings = NULL, *s = NULL; | |
903 | struct pcs_conf_vals *conf = NULL; | |
b582658a | 904 | static const struct pcs_conf_type prop2[] = { |
9dddb4df HZ |
905 | { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, |
906 | { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, | |
907 | { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, | |
4bd75477 | 908 | { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, |
9dddb4df | 909 | }; |
b582658a | 910 | static const struct pcs_conf_type prop4[] = { |
9dddb4df HZ |
911 | { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, |
912 | { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, | |
913 | { "pinctrl-single,input-schmitt-enable", | |
914 | PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, | |
915 | }; | |
916 | ||
917 | /* If pinconf isn't supported, don't parse properties in below. */ | |
02e483f6 | 918 | if (!PCS_HAS_PINCONF) |
9dddb4df HZ |
919 | return 0; |
920 | ||
921 | /* cacluate how much properties are supported in current node */ | |
922 | for (i = 0; i < ARRAY_SIZE(prop2); i++) { | |
923 | if (of_find_property(np, prop2[i].name, NULL)) | |
924 | nconfs++; | |
925 | } | |
926 | for (i = 0; i < ARRAY_SIZE(prop4); i++) { | |
927 | if (of_find_property(np, prop4[i].name, NULL)) | |
928 | nconfs++; | |
929 | } | |
930 | if (!nconfs) | |
931 | return 0; | |
932 | ||
a86854d0 KC |
933 | func->conf = devm_kcalloc(pcs->dev, |
934 | nconfs, sizeof(struct pcs_conf_vals), | |
9dddb4df HZ |
935 | GFP_KERNEL); |
936 | if (!func->conf) | |
937 | return -ENOMEM; | |
938 | func->nconfs = nconfs; | |
939 | conf = &(func->conf[0]); | |
940 | m++; | |
a86854d0 | 941 | settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long), |
9dddb4df HZ |
942 | GFP_KERNEL); |
943 | if (!settings) | |
944 | return -ENOMEM; | |
945 | s = &settings[0]; | |
946 | ||
947 | for (i = 0; i < ARRAY_SIZE(prop2); i++) | |
948 | pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, | |
949 | &conf, &s); | |
950 | for (i = 0; i < ARRAY_SIZE(prop4); i++) | |
951 | pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, | |
952 | &conf, &s); | |
953 | m->type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
954 | m->data.configs.group_or_pin = np->name; | |
955 | m->data.configs.configs = settings; | |
956 | m->data.configs.num_configs = nconfs; | |
957 | return 0; | |
958 | } | |
959 | ||
8b8b091b TL |
960 | /** |
961 | * smux_parse_one_pinctrl_entry() - parses a device tree mux entry | |
caeb774e | 962 | * @pctldev: pin controller device |
8b8b091b TL |
963 | * @pcs: pinctrl driver instance |
964 | * @np: device node of the mux entry | |
965 | * @map: map entry | |
9dddb4df | 966 | * @num_maps: number of map |
8b8b091b TL |
967 | * @pgnames: pingroup names |
968 | * | |
969 | * Note that this binding currently supports only sets of one register + value. | |
970 | * | |
971 | * Also note that this driver tries to avoid understanding pin and function | |
972 | * names because of the extra bloat they would cause especially in the case of | |
973 | * a large number of pins. This driver just sets what is specified for the board | |
974 | * in the .dts file. Further user space debugging tools can be developed to | |
975 | * decipher the pin and function names using debugfs. | |
976 | * | |
977 | * If you are concerned about the boot time, set up the static pins in | |
978 | * the bootloader, and only set up selected pins as device tree entries. | |
979 | */ | |
980 | static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, | |
981 | struct device_node *np, | |
982 | struct pinctrl_map **map, | |
9dddb4df | 983 | unsigned *num_maps, |
8b8b091b TL |
984 | const char **pgnames) |
985 | { | |
4622215f | 986 | const char *name = "pinctrl-single,pins"; |
8b8b091b | 987 | struct pcs_func_vals *vals; |
a4ab1086 TL |
988 | int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; |
989 | struct pcs_function *function = NULL; | |
8b8b091b | 990 | |
4622215f | 991 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc | 992 | if (rows <= 0) { |
059a6e63 | 993 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); |
de7416bc AH |
994 | return -EINVAL; |
995 | } | |
8b8b091b | 996 | |
a86854d0 | 997 | vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL); |
8b8b091b TL |
998 | if (!vals) |
999 | return -ENOMEM; | |
1000 | ||
a86854d0 | 1001 | pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL); |
8b8b091b TL |
1002 | if (!pins) |
1003 | goto free_vals; | |
1004 | ||
4622215f TL |
1005 | for (i = 0; i < rows; i++) { |
1006 | struct of_phandle_args pinctrl_spec; | |
1007 | unsigned int offset; | |
8b8b091b TL |
1008 | int pin; |
1009 | ||
4622215f TL |
1010 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
1011 | if (res) | |
1012 | return res; | |
1013 | ||
1014 | if (pinctrl_spec.args_count < 2) { | |
1015 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", | |
1016 | pinctrl_spec.args_count); | |
1017 | break; | |
1018 | } | |
1019 | ||
1020 | /* Index plus one value cell */ | |
1021 | offset = pinctrl_spec.args[0]; | |
8b8b091b | 1022 | vals[found].reg = pcs->base + offset; |
4622215f TL |
1023 | vals[found].val = pinctrl_spec.args[1]; |
1024 | ||
94f4e54c RH |
1025 | dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n", |
1026 | pinctrl_spec.np, offset, pinctrl_spec.args[1]); | |
8b8b091b TL |
1027 | |
1028 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1029 | if (pin < 0) { | |
1030 | dev_err(pcs->dev, | |
94f4e54c RH |
1031 | "could not add functions for %pOFn %ux\n", |
1032 | np, offset); | |
8b8b091b TL |
1033 | break; |
1034 | } | |
1035 | pins[found++] = pin; | |
1036 | } | |
1037 | ||
1038 | pgnames[0] = np->name; | |
a4ab1086 TL |
1039 | mutex_lock(&pcs->mutex); |
1040 | fsel = pcs_add_function(pcs, &function, np->name, vals, found, | |
1041 | pgnames, 1); | |
1042 | if (fsel < 0) { | |
1043 | res = fsel; | |
8b8b091b | 1044 | goto free_pins; |
712778d0 | 1045 | } |
8b8b091b | 1046 | |
a4ab1086 TL |
1047 | gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
1048 | if (gsel < 0) { | |
1049 | res = gsel; | |
8b8b091b | 1050 | goto free_function; |
a4ab1086 | 1051 | } |
8b8b091b TL |
1052 | |
1053 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1054 | (*map)->data.mux.group = np->name; | |
1055 | (*map)->data.mux.function = np->name; | |
1056 | ||
a4ab1086 | 1057 | if (PCS_HAS_PINCONF && function) { |
18442e65 WY |
1058 | res = pcs_parse_pinconf(pcs, np, function, map); |
1059 | if (res) | |
9dddb4df HZ |
1060 | goto free_pingroups; |
1061 | *num_maps = 2; | |
1062 | } else { | |
1063 | *num_maps = 1; | |
1064 | } | |
a4ab1086 TL |
1065 | mutex_unlock(&pcs->mutex); |
1066 | ||
8b8b091b TL |
1067 | return 0; |
1068 | ||
9dddb4df | 1069 | free_pingroups: |
a4ab1086 | 1070 | pinctrl_generic_remove_group(pcs->pctl, gsel); |
9dddb4df | 1071 | *num_maps = 1; |
8b8b091b | 1072 | free_function: |
a4ab1086 | 1073 | pinmux_generic_remove_function(pcs->pctl, fsel); |
8b8b091b | 1074 | free_pins: |
673ba5a0 | 1075 | mutex_unlock(&pcs->mutex); |
8b8b091b TL |
1076 | devm_kfree(pcs->dev, pins); |
1077 | ||
4e7e8017 MP |
1078 | free_vals: |
1079 | devm_kfree(pcs->dev, vals); | |
1080 | ||
1081 | return res; | |
1082 | } | |
1083 | ||
4e7e8017 MP |
1084 | static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, |
1085 | struct device_node *np, | |
1086 | struct pinctrl_map **map, | |
1087 | unsigned *num_maps, | |
1088 | const char **pgnames) | |
1089 | { | |
dd68a526 | 1090 | const char *name = "pinctrl-single,bits"; |
4e7e8017 | 1091 | struct pcs_func_vals *vals; |
a4ab1086 | 1092 | int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel; |
4e7e8017 | 1093 | int npins_in_row; |
a4ab1086 | 1094 | struct pcs_function *function = NULL; |
4e7e8017 | 1095 | |
22d5127e | 1096 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc AH |
1097 | if (rows <= 0) { |
1098 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); | |
1099 | return -EINVAL; | |
1100 | } | |
4e7e8017 | 1101 | |
4e7e8017 MP |
1102 | npins_in_row = pcs->width / pcs->bits_per_pin; |
1103 | ||
a86854d0 KC |
1104 | vals = devm_kzalloc(pcs->dev, |
1105 | array3_size(rows, npins_in_row, sizeof(*vals)), | |
1106 | GFP_KERNEL); | |
4e7e8017 MP |
1107 | if (!vals) |
1108 | return -ENOMEM; | |
1109 | ||
a86854d0 KC |
1110 | pins = devm_kzalloc(pcs->dev, |
1111 | array3_size(rows, npins_in_row, sizeof(*pins)), | |
1112 | GFP_KERNEL); | |
4e7e8017 MP |
1113 | if (!pins) |
1114 | goto free_vals; | |
1115 | ||
22d5127e TL |
1116 | for (i = 0; i < rows; i++) { |
1117 | struct of_phandle_args pinctrl_spec; | |
4e7e8017 MP |
1118 | unsigned offset, val; |
1119 | unsigned mask, bit_pos, val_pos, mask_pos, submask; | |
1120 | unsigned pin_num_from_lsb; | |
1121 | int pin; | |
1122 | ||
22d5127e TL |
1123 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
1124 | if (res) | |
1125 | return res; | |
1126 | ||
1127 | if (pinctrl_spec.args_count < 3) { | |
1128 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", | |
1129 | pinctrl_spec.args_count); | |
1130 | break; | |
1131 | } | |
1132 | ||
1133 | /* Index plus two value cells */ | |
1134 | offset = pinctrl_spec.args[0]; | |
1135 | val = pinctrl_spec.args[1]; | |
1136 | mask = pinctrl_spec.args[2]; | |
1137 | ||
94f4e54c RH |
1138 | dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n", |
1139 | pinctrl_spec.np, offset, val, mask); | |
4e7e8017 MP |
1140 | |
1141 | /* Parse pins in each row from LSB */ | |
1142 | while (mask) { | |
56b367c0 | 1143 | bit_pos = __ffs(mask); |
4e7e8017 | 1144 | pin_num_from_lsb = bit_pos / pcs->bits_per_pin; |
56b367c0 | 1145 | mask_pos = ((pcs->fmask) << bit_pos); |
4e7e8017 MP |
1146 | val_pos = val & mask_pos; |
1147 | submask = mask & mask_pos; | |
ad5d25fe TV |
1148 | |
1149 | if ((mask & mask_pos) == 0) { | |
1150 | dev_err(pcs->dev, | |
94f4e54c RH |
1151 | "Invalid mask for %pOFn at 0x%x\n", |
1152 | np, offset); | |
ad5d25fe TV |
1153 | break; |
1154 | } | |
1155 | ||
4e7e8017 MP |
1156 | mask &= ~mask_pos; |
1157 | ||
1158 | if (submask != mask_pos) { | |
1159 | dev_warn(pcs->dev, | |
94f4e54c RH |
1160 | "Invalid submask 0x%x for %pOFn at 0x%x\n", |
1161 | submask, np, offset); | |
4e7e8017 MP |
1162 | continue; |
1163 | } | |
1164 | ||
1165 | vals[found].mask = submask; | |
1166 | vals[found].reg = pcs->base + offset; | |
1167 | vals[found].val = val_pos; | |
1168 | ||
1169 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1170 | if (pin < 0) { | |
1171 | dev_err(pcs->dev, | |
94f4e54c RH |
1172 | "could not add functions for %pOFn %ux\n", |
1173 | np, offset); | |
4e7e8017 MP |
1174 | break; |
1175 | } | |
1176 | pins[found++] = pin + pin_num_from_lsb; | |
1177 | } | |
1178 | } | |
1179 | ||
1180 | pgnames[0] = np->name; | |
a4ab1086 TL |
1181 | mutex_lock(&pcs->mutex); |
1182 | fsel = pcs_add_function(pcs, &function, np->name, vals, found, | |
1183 | pgnames, 1); | |
1184 | if (fsel < 0) { | |
1185 | res = fsel; | |
4e7e8017 | 1186 | goto free_pins; |
712778d0 | 1187 | } |
4e7e8017 | 1188 | |
a4ab1086 TL |
1189 | gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
1190 | if (gsel < 0) { | |
1191 | res = gsel; | |
4e7e8017 | 1192 | goto free_function; |
a4ab1086 | 1193 | } |
4e7e8017 MP |
1194 | |
1195 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1196 | (*map)->data.mux.group = np->name; | |
1197 | (*map)->data.mux.function = np->name; | |
1198 | ||
02e483f6 | 1199 | if (PCS_HAS_PINCONF) { |
4e7e8017 MP |
1200 | dev_err(pcs->dev, "pinconf not supported\n"); |
1201 | goto free_pingroups; | |
1202 | } | |
1203 | ||
1204 | *num_maps = 1; | |
a4ab1086 TL |
1205 | mutex_unlock(&pcs->mutex); |
1206 | ||
4e7e8017 MP |
1207 | return 0; |
1208 | ||
1209 | free_pingroups: | |
a4ab1086 | 1210 | pinctrl_generic_remove_group(pcs->pctl, gsel); |
4e7e8017 MP |
1211 | *num_maps = 1; |
1212 | free_function: | |
a4ab1086 | 1213 | pinmux_generic_remove_function(pcs->pctl, fsel); |
4e7e8017 | 1214 | free_pins: |
673ba5a0 | 1215 | mutex_unlock(&pcs->mutex); |
4e7e8017 MP |
1216 | devm_kfree(pcs->dev, pins); |
1217 | ||
8b8b091b TL |
1218 | free_vals: |
1219 | devm_kfree(pcs->dev, vals); | |
1220 | ||
1221 | return res; | |
1222 | } | |
1223 | /** | |
1224 | * pcs_dt_node_to_map() - allocates and parses pinctrl maps | |
1225 | * @pctldev: pinctrl instance | |
1226 | * @np_config: device tree pinmux entry | |
1227 | * @map: array of map entries | |
1228 | * @num_maps: number of maps | |
1229 | */ | |
1230 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1231 | struct device_node *np_config, | |
1232 | struct pinctrl_map **map, unsigned *num_maps) | |
1233 | { | |
1234 | struct pcs_device *pcs; | |
1235 | const char **pgnames; | |
1236 | int ret; | |
1237 | ||
1238 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
1239 | ||
9dddb4df | 1240 | /* create 2 maps. One is for pinmux, and the other is for pinconf. */ |
a86854d0 | 1241 | *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL); |
00e79d12 | 1242 | if (!*map) |
8b8b091b TL |
1243 | return -ENOMEM; |
1244 | ||
1245 | *num_maps = 0; | |
1246 | ||
1247 | pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); | |
1248 | if (!pgnames) { | |
1249 | ret = -ENOMEM; | |
1250 | goto free_map; | |
1251 | } | |
1252 | ||
4e7e8017 MP |
1253 | if (pcs->bits_per_mux) { |
1254 | ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, | |
1255 | num_maps, pgnames); | |
1256 | if (ret < 0) { | |
94f4e54c RH |
1257 | dev_err(pcs->dev, "no pins entries for %pOFn\n", |
1258 | np_config); | |
4e7e8017 MP |
1259 | goto free_pgnames; |
1260 | } | |
1261 | } else { | |
1262 | ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, | |
1263 | num_maps, pgnames); | |
1264 | if (ret < 0) { | |
94f4e54c RH |
1265 | dev_err(pcs->dev, "no pins entries for %pOFn\n", |
1266 | np_config); | |
4e7e8017 MP |
1267 | goto free_pgnames; |
1268 | } | |
8b8b091b | 1269 | } |
8b8b091b TL |
1270 | |
1271 | return 0; | |
1272 | ||
1273 | free_pgnames: | |
1274 | devm_kfree(pcs->dev, pgnames); | |
1275 | free_map: | |
1276 | devm_kfree(pcs->dev, *map); | |
1277 | ||
1278 | return ret; | |
1279 | } | |
1280 | ||
3e6cee17 TL |
1281 | /** |
1282 | * pcs_irq_free() - free interrupt | |
1283 | * @pcs: pcs driver instance | |
1284 | */ | |
1285 | static void pcs_irq_free(struct pcs_device *pcs) | |
1286 | { | |
1287 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1288 | ||
1289 | if (pcs_soc->irq < 0) | |
1290 | return; | |
1291 | ||
1292 | if (pcs->domain) | |
1293 | irq_domain_remove(pcs->domain); | |
1294 | ||
1295 | if (PCS_QUIRK_HAS_SHARED_IRQ) | |
1296 | free_irq(pcs_soc->irq, pcs_soc); | |
1297 | else | |
1298 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1299 | } | |
1300 | ||
8b8b091b TL |
1301 | /** |
1302 | * pcs_free_resources() - free memory used by this driver | |
1303 | * @pcs: pcs driver instance | |
1304 | */ | |
1305 | static void pcs_free_resources(struct pcs_device *pcs) | |
1306 | { | |
3e6cee17 | 1307 | pcs_irq_free(pcs); |
f10a2585 | 1308 | pinctrl_unregister(pcs->pctl); |
caeb774e | 1309 | |
4622215f TL |
1310 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) |
1311 | if (pcs->missing_nr_pinctrl_cells) | |
1312 | of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); | |
1313 | #endif | |
8b8b091b TL |
1314 | } |
1315 | ||
a1a277eb HZ |
1316 | static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) |
1317 | { | |
1318 | const char *propname = "pinctrl-single,gpio-range"; | |
1319 | const char *cellname = "#pinctrl-single,gpio-range-cells"; | |
1320 | struct of_phandle_args gpiospec; | |
1321 | struct pcs_gpiofunc_range *range; | |
1322 | int ret, i; | |
1323 | ||
1324 | for (i = 0; ; i++) { | |
1325 | ret = of_parse_phandle_with_args(node, propname, cellname, | |
1326 | i, &gpiospec); | |
1327 | /* Do not treat it as error. Only treat it as end condition. */ | |
1328 | if (ret) { | |
1329 | ret = 0; | |
1330 | break; | |
1331 | } | |
1332 | range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); | |
1333 | if (!range) { | |
1334 | ret = -ENOMEM; | |
1335 | break; | |
1336 | } | |
1337 | range->offset = gpiospec.args[0]; | |
1338 | range->npins = gpiospec.args[1]; | |
1339 | range->gpiofunc = gpiospec.args[2]; | |
1340 | mutex_lock(&pcs->mutex); | |
1341 | list_add_tail(&range->node, &pcs->gpiofuncs); | |
1342 | mutex_unlock(&pcs->mutex); | |
1343 | } | |
1344 | return ret; | |
1345 | } | |
3e6cee17 TL |
1346 | /** |
1347 | * @reg: virtual address of interrupt register | |
1348 | * @hwirq: hardware irq number | |
1349 | * @irq: virtual irq number | |
1350 | * @node: list node | |
1351 | */ | |
1352 | struct pcs_interrupt { | |
1353 | void __iomem *reg; | |
1354 | irq_hw_number_t hwirq; | |
1355 | unsigned int irq; | |
1356 | struct list_head node; | |
1357 | }; | |
1358 | ||
1359 | /** | |
1360 | * pcs_irq_set() - enables or disables an interrupt | |
1361 | * | |
1362 | * Note that this currently assumes one interrupt per pinctrl | |
1363 | * register that is typically used for wake-up events. | |
1364 | */ | |
1365 | static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, | |
1366 | int irq, const bool enable) | |
1367 | { | |
1368 | struct pcs_device *pcs; | |
1369 | struct list_head *pos; | |
1370 | unsigned mask; | |
1371 | ||
1372 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1373 | list_for_each(pos, &pcs->irqs) { | |
1374 | struct pcs_interrupt *pcswi; | |
1375 | unsigned soc_mask; | |
1376 | ||
1377 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1378 | if (irq != pcswi->irq) | |
1379 | continue; | |
1380 | ||
1381 | soc_mask = pcs_soc->irq_enable_mask; | |
1382 | raw_spin_lock(&pcs->lock); | |
1383 | mask = pcs->read(pcswi->reg); | |
1384 | if (enable) | |
1385 | mask |= soc_mask; | |
1386 | else | |
1387 | mask &= ~soc_mask; | |
1388 | pcs->write(mask, pcswi->reg); | |
0ac3c0a4 TL |
1389 | |
1390 | /* flush posted write */ | |
1391 | mask = pcs->read(pcswi->reg); | |
3e6cee17 TL |
1392 | raw_spin_unlock(&pcs->lock); |
1393 | } | |
c9b3a7d2 RQ |
1394 | |
1395 | if (pcs_soc->rearm) | |
1396 | pcs_soc->rearm(); | |
3e6cee17 TL |
1397 | } |
1398 | ||
1399 | /** | |
1400 | * pcs_irq_mask() - mask pinctrl interrupt | |
1401 | * @d: interrupt data | |
1402 | */ | |
1403 | static void pcs_irq_mask(struct irq_data *d) | |
1404 | { | |
1405 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1406 | ||
1407 | pcs_irq_set(pcs_soc, d->irq, false); | |
1408 | } | |
1409 | ||
1410 | /** | |
1411 | * pcs_irq_unmask() - unmask pinctrl interrupt | |
1412 | * @d: interrupt data | |
1413 | */ | |
1414 | static void pcs_irq_unmask(struct irq_data *d) | |
1415 | { | |
1416 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1417 | ||
1418 | pcs_irq_set(pcs_soc, d->irq, true); | |
1419 | } | |
1420 | ||
1421 | /** | |
1422 | * pcs_irq_set_wake() - toggle the suspend and resume wake up | |
1423 | * @d: interrupt data | |
1424 | * @state: wake-up state | |
1425 | * | |
1426 | * Note that this should be called only for suspend and resume. | |
1427 | * For runtime PM, the wake-up events should be enabled by default. | |
1428 | */ | |
1429 | static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) | |
1430 | { | |
1431 | if (state) | |
1432 | pcs_irq_unmask(d); | |
1433 | else | |
1434 | pcs_irq_mask(d); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
1439 | /** | |
1440 | * pcs_irq_handle() - common interrupt handler | |
1441 | * @pcs_irq: interrupt data | |
1442 | * | |
1443 | * Note that this currently assumes we have one interrupt bit per | |
1444 | * mux register. This interrupt is typically used for wake-up events. | |
1445 | * For more complex interrupts different handlers can be specified. | |
1446 | */ | |
1447 | static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) | |
1448 | { | |
1449 | struct pcs_device *pcs; | |
1450 | struct list_head *pos; | |
1451 | int count = 0; | |
1452 | ||
1453 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1454 | list_for_each(pos, &pcs->irqs) { | |
1455 | struct pcs_interrupt *pcswi; | |
1456 | unsigned mask; | |
1457 | ||
1458 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1459 | raw_spin_lock(&pcs->lock); | |
1460 | mask = pcs->read(pcswi->reg); | |
1461 | raw_spin_unlock(&pcs->lock); | |
1462 | if (mask & pcs_soc->irq_status_mask) { | |
1463 | generic_handle_irq(irq_find_mapping(pcs->domain, | |
1464 | pcswi->hwirq)); | |
1465 | count++; | |
1466 | } | |
1467 | } | |
1468 | ||
1469 | return count; | |
1470 | } | |
1471 | ||
1472 | /** | |
1473 | * pcs_irq_handler() - handler for the shared interrupt case | |
1474 | * @irq: interrupt | |
1475 | * @d: data | |
1476 | * | |
1477 | * Use this for cases where multiple instances of | |
1478 | * pinctrl-single share a single interrupt like on omaps. | |
1479 | */ | |
1480 | static irqreturn_t pcs_irq_handler(int irq, void *d) | |
1481 | { | |
1482 | struct pcs_soc_data *pcs_soc = d; | |
1483 | ||
1484 | return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; | |
1485 | } | |
1486 | ||
1487 | /** | |
1488 | * pcs_irq_handle() - handler for the dedicated chained interrupt case | |
1489 | * @irq: interrupt | |
1490 | * @desc: interrupt descriptor | |
1491 | * | |
1492 | * Use this if you have a separate interrupt for each | |
1493 | * pinctrl-single instance. | |
1494 | */ | |
bd0b9ac4 | 1495 | static void pcs_irq_chain_handler(struct irq_desc *desc) |
3e6cee17 TL |
1496 | { |
1497 | struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); | |
1498 | struct irq_chip *chip; | |
3e6cee17 | 1499 | |
5663bb27 | 1500 | chip = irq_desc_get_chip(desc); |
3e6cee17 | 1501 | chained_irq_enter(chip, desc); |
849bfe06 | 1502 | pcs_irq_handle(pcs_soc); |
3e6cee17 TL |
1503 | /* REVISIT: export and add handle_bad_irq(irq, desc)? */ |
1504 | chained_irq_exit(chip, desc); | |
3e6cee17 TL |
1505 | } |
1506 | ||
1507 | static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1508 | irq_hw_number_t hwirq) | |
1509 | { | |
1510 | struct pcs_soc_data *pcs_soc = d->host_data; | |
1511 | struct pcs_device *pcs; | |
1512 | struct pcs_interrupt *pcswi; | |
1513 | ||
1514 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1515 | pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); | |
1516 | if (!pcswi) | |
1517 | return -ENOMEM; | |
1518 | ||
1519 | pcswi->reg = pcs->base + hwirq; | |
1520 | pcswi->hwirq = hwirq; | |
1521 | pcswi->irq = irq; | |
1522 | ||
1523 | mutex_lock(&pcs->mutex); | |
1524 | list_add_tail(&pcswi->node, &pcs->irqs); | |
1525 | mutex_unlock(&pcs->mutex); | |
1526 | ||
1527 | irq_set_chip_data(irq, pcs_soc); | |
1528 | irq_set_chip_and_handler(irq, &pcs->chip, | |
1529 | handle_level_irq); | |
39c3fd58 | 1530 | irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class); |
1b9c0fb3 | 1531 | irq_set_noprobe(irq); |
3e6cee17 TL |
1532 | |
1533 | return 0; | |
1534 | } | |
1535 | ||
e5b60953 | 1536 | static const struct irq_domain_ops pcs_irqdomain_ops = { |
3e6cee17 TL |
1537 | .map = pcs_irqdomain_map, |
1538 | .xlate = irq_domain_xlate_onecell, | |
1539 | }; | |
1540 | ||
1541 | /** | |
1542 | * pcs_irq_init_chained_handler() - set up a chained interrupt handler | |
1543 | * @pcs: pcs driver instance | |
1544 | * @np: device node pointer | |
1545 | */ | |
1546 | static int pcs_irq_init_chained_handler(struct pcs_device *pcs, | |
1547 | struct device_node *np) | |
1548 | { | |
1549 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1550 | const char *name = "pinctrl"; | |
1551 | int num_irqs; | |
1552 | ||
1553 | if (!pcs_soc->irq_enable_mask || | |
1554 | !pcs_soc->irq_status_mask) { | |
1555 | pcs_soc->irq = -1; | |
1556 | return -EINVAL; | |
1557 | } | |
1558 | ||
1559 | INIT_LIST_HEAD(&pcs->irqs); | |
1560 | pcs->chip.name = name; | |
1561 | pcs->chip.irq_ack = pcs_irq_mask; | |
1562 | pcs->chip.irq_mask = pcs_irq_mask; | |
1563 | pcs->chip.irq_unmask = pcs_irq_unmask; | |
1564 | pcs->chip.irq_set_wake = pcs_irq_set_wake; | |
1565 | ||
1566 | if (PCS_QUIRK_HAS_SHARED_IRQ) { | |
1567 | int res; | |
1568 | ||
1569 | res = request_irq(pcs_soc->irq, pcs_irq_handler, | |
c10372e6 GS |
1570 | IRQF_SHARED | IRQF_NO_SUSPEND | |
1571 | IRQF_NO_THREAD, | |
3e6cee17 TL |
1572 | name, pcs_soc); |
1573 | if (res) { | |
1574 | pcs_soc->irq = -1; | |
1575 | return res; | |
1576 | } | |
1577 | } else { | |
20d5d142 TG |
1578 | irq_set_chained_handler_and_data(pcs_soc->irq, |
1579 | pcs_irq_chain_handler, | |
1580 | pcs_soc); | |
3e6cee17 TL |
1581 | } |
1582 | ||
1583 | /* | |
1584 | * We can use the register offset as the hardirq | |
1585 | * number as irq_domain_add_simple maps them lazily. | |
1586 | * This way we can easily support more than one | |
1587 | * interrupt per function if needed. | |
1588 | */ | |
1589 | num_irqs = pcs->size; | |
1590 | ||
1591 | pcs->domain = irq_domain_add_simple(np, num_irqs, 0, | |
1592 | &pcs_irqdomain_ops, | |
1593 | pcs_soc); | |
1594 | if (!pcs->domain) { | |
1595 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1596 | return -EINVAL; | |
1597 | } | |
1598 | ||
1599 | return 0; | |
1600 | } | |
a1a277eb | 1601 | |
8cb440ab | 1602 | #ifdef CONFIG_PM |
88a1dbde K |
1603 | static int pcs_save_context(struct pcs_device *pcs) |
1604 | { | |
1605 | int i, mux_bytes; | |
1606 | u64 *regsl; | |
1607 | u32 *regsw; | |
1608 | u16 *regshw; | |
1609 | ||
1610 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
1611 | ||
7f57871f | 1612 | if (!pcs->saved_vals) { |
88a1dbde | 1613 | pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC); |
7f57871f CIK |
1614 | if (!pcs->saved_vals) |
1615 | return -ENOMEM; | |
1616 | } | |
88a1dbde K |
1617 | |
1618 | switch (pcs->width) { | |
1619 | case 64: | |
7d71b5f4 GU |
1620 | regsl = pcs->saved_vals; |
1621 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1622 | *regsl++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1623 | break; |
1624 | case 32: | |
7d71b5f4 GU |
1625 | regsw = pcs->saved_vals; |
1626 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1627 | *regsw++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1628 | break; |
1629 | case 16: | |
7d71b5f4 GU |
1630 | regshw = pcs->saved_vals; |
1631 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1632 | *regshw++ = pcs->read(pcs->base + i); | |
88a1dbde K |
1633 | break; |
1634 | } | |
1635 | ||
1636 | return 0; | |
1637 | } | |
1638 | ||
1639 | static void pcs_restore_context(struct pcs_device *pcs) | |
1640 | { | |
1641 | int i, mux_bytes; | |
1642 | u64 *regsl; | |
1643 | u32 *regsw; | |
1644 | u16 *regshw; | |
1645 | ||
1646 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
1647 | ||
1648 | switch (pcs->width) { | |
1649 | case 64: | |
7d71b5f4 GU |
1650 | regsl = pcs->saved_vals; |
1651 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1652 | pcs->write(*regsl++, pcs->base + i); | |
88a1dbde K |
1653 | break; |
1654 | case 32: | |
7d71b5f4 GU |
1655 | regsw = pcs->saved_vals; |
1656 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1657 | pcs->write(*regsw++, pcs->base + i); | |
88a1dbde K |
1658 | break; |
1659 | case 16: | |
7d71b5f4 GU |
1660 | regshw = pcs->saved_vals; |
1661 | for (i = 0; i < pcs->size; i += mux_bytes) | |
1662 | pcs->write(*regshw++, pcs->base + i); | |
88a1dbde K |
1663 | break; |
1664 | } | |
1665 | } | |
1666 | ||
0f9bc4bc HG |
1667 | static int pinctrl_single_suspend(struct platform_device *pdev, |
1668 | pm_message_t state) | |
1669 | { | |
1670 | struct pcs_device *pcs; | |
1671 | ||
1672 | pcs = platform_get_drvdata(pdev); | |
1673 | if (!pcs) | |
1674 | return -EINVAL; | |
1675 | ||
7f57871f CIK |
1676 | if (pcs->flags & PCS_CONTEXT_LOSS_OFF) { |
1677 | int ret; | |
1678 | ||
1679 | ret = pcs_save_context(pcs); | |
1680 | if (ret < 0) | |
1681 | return ret; | |
1682 | } | |
88a1dbde | 1683 | |
0f9bc4bc HG |
1684 | return pinctrl_force_sleep(pcs->pctl); |
1685 | } | |
1686 | ||
1687 | static int pinctrl_single_resume(struct platform_device *pdev) | |
1688 | { | |
1689 | struct pcs_device *pcs; | |
1690 | ||
1691 | pcs = platform_get_drvdata(pdev); | |
1692 | if (!pcs) | |
1693 | return -EINVAL; | |
1694 | ||
88a1dbde K |
1695 | if (pcs->flags & PCS_CONTEXT_LOSS_OFF) |
1696 | pcs_restore_context(pcs); | |
1697 | ||
0f9bc4bc HG |
1698 | return pinctrl_force_default(pcs->pctl); |
1699 | } | |
8cb440ab | 1700 | #endif |
0f9bc4bc | 1701 | |
4622215f TL |
1702 | /** |
1703 | * pcs_quirk_missing_pinctrl_cells - handle legacy binding | |
1704 | * @pcs: pinctrl driver instance | |
1705 | * @np: device tree node | |
1706 | * @cells: number of cells | |
1707 | * | |
1708 | * Handle legacy binding with no #pinctrl-cells. This should be | |
1709 | * always two pinctrl-single,bit-per-mux and one for others. | |
1710 | * At some point we may want to consider removing this. | |
1711 | */ | |
1712 | static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, | |
1713 | struct device_node *np, | |
1714 | int cells) | |
1715 | { | |
1716 | struct property *p; | |
1717 | const char *name = "#pinctrl-cells"; | |
1718 | int error; | |
1719 | u32 val; | |
1720 | ||
1721 | error = of_property_read_u32(np, name, &val); | |
1722 | if (!error) | |
1723 | return 0; | |
1724 | ||
1725 | dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", | |
1726 | name, cells); | |
1727 | ||
1728 | p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); | |
1729 | if (!p) | |
1730 | return -ENOMEM; | |
1731 | ||
1732 | p->length = sizeof(__be32); | |
1733 | p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); | |
1734 | if (!p->value) | |
1735 | return -ENOMEM; | |
1736 | *(__be32 *)p->value = cpu_to_be32(cells); | |
1737 | ||
1738 | p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); | |
1739 | if (!p->name) | |
1740 | return -ENOMEM; | |
1741 | ||
1742 | pcs->missing_nr_pinctrl_cells = p; | |
1743 | ||
1744 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) | |
1745 | error = of_add_property(np, pcs->missing_nr_pinctrl_cells); | |
1746 | #endif | |
1747 | ||
1748 | return error; | |
1749 | } | |
1750 | ||
150632b0 | 1751 | static int pcs_probe(struct platform_device *pdev) |
8b8b091b TL |
1752 | { |
1753 | struct device_node *np = pdev->dev.of_node; | |
dc7743aa | 1754 | struct pcs_pdata *pdata; |
8b8b091b TL |
1755 | struct resource *res; |
1756 | struct pcs_device *pcs; | |
02e483f6 | 1757 | const struct pcs_soc_data *soc; |
8b8b091b TL |
1758 | int ret; |
1759 | ||
1a8764f4 MY |
1760 | soc = of_device_get_match_data(&pdev->dev); |
1761 | if (WARN_ON(!soc)) | |
8b8b091b TL |
1762 | return -EINVAL; |
1763 | ||
1764 | pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); | |
a14aa271 | 1765 | if (!pcs) |
8b8b091b | 1766 | return -ENOMEM; |
a14aa271 | 1767 | |
8b8b091b | 1768 | pcs->dev = &pdev->dev; |
4622215f | 1769 | pcs->np = np; |
3e6cee17 | 1770 | raw_spin_lock_init(&pcs->lock); |
8b8b091b | 1771 | mutex_init(&pcs->mutex); |
a1a277eb | 1772 | INIT_LIST_HEAD(&pcs->gpiofuncs); |
02e483f6 | 1773 | pcs->flags = soc->flags; |
3e6cee17 | 1774 | memcpy(&pcs->socdata, soc, sizeof(*soc)); |
8b8b091b | 1775 | |
cd23604a TL |
1776 | ret = of_property_read_u32(np, "pinctrl-single,register-width", |
1777 | &pcs->width); | |
1778 | if (ret) { | |
1779 | dev_err(pcs->dev, "register width not specified\n"); | |
1780 | ||
1781 | return ret; | |
1782 | } | |
8b8b091b | 1783 | |
477ac771 HZ |
1784 | ret = of_property_read_u32(np, "pinctrl-single,function-mask", |
1785 | &pcs->fmask); | |
1786 | if (!ret) { | |
56b367c0 | 1787 | pcs->fshift = __ffs(pcs->fmask); |
477ac771 HZ |
1788 | pcs->fmax = pcs->fmask >> pcs->fshift; |
1789 | } else { | |
1790 | /* If mask property doesn't exist, function mux is invalid. */ | |
1791 | pcs->fmask = 0; | |
1792 | pcs->fshift = 0; | |
1793 | pcs->fmax = 0; | |
1794 | } | |
8b8b091b TL |
1795 | |
1796 | ret = of_property_read_u32(np, "pinctrl-single,function-off", | |
1797 | &pcs->foff); | |
1798 | if (ret) | |
1799 | pcs->foff = PCS_OFF_DISABLED; | |
1800 | ||
9e605cb6 PU |
1801 | pcs->bits_per_mux = of_property_read_bool(np, |
1802 | "pinctrl-single,bit-per-mux"); | |
4622215f TL |
1803 | ret = pcs_quirk_missing_pinctrl_cells(pcs, np, |
1804 | pcs->bits_per_mux ? 2 : 1); | |
1805 | if (ret) { | |
1806 | dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); | |
1807 | ||
1808 | return ret; | |
1809 | } | |
9e605cb6 | 1810 | |
8b8b091b TL |
1811 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1812 | if (!res) { | |
1813 | dev_err(pcs->dev, "could not get resource\n"); | |
1814 | return -ENODEV; | |
1815 | } | |
1816 | ||
1817 | pcs->res = devm_request_mem_region(pcs->dev, res->start, | |
1818 | resource_size(res), DRIVER_NAME); | |
1819 | if (!pcs->res) { | |
1820 | dev_err(pcs->dev, "could not get mem_region\n"); | |
1821 | return -EBUSY; | |
1822 | } | |
1823 | ||
1824 | pcs->size = resource_size(pcs->res); | |
1825 | pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); | |
1826 | if (!pcs->base) { | |
1827 | dev_err(pcs->dev, "could not ioremap\n"); | |
1828 | return -ENODEV; | |
1829 | } | |
1830 | ||
8b8b091b TL |
1831 | platform_set_drvdata(pdev, pcs); |
1832 | ||
1833 | switch (pcs->width) { | |
1834 | case 8: | |
1835 | pcs->read = pcs_readb; | |
1836 | pcs->write = pcs_writeb; | |
1837 | break; | |
1838 | case 16: | |
1839 | pcs->read = pcs_readw; | |
1840 | pcs->write = pcs_writew; | |
1841 | break; | |
1842 | case 32: | |
1843 | pcs->read = pcs_readl; | |
1844 | pcs->write = pcs_writel; | |
1845 | break; | |
1846 | default: | |
1847 | break; | |
1848 | } | |
1849 | ||
1850 | pcs->desc.name = DRIVER_NAME; | |
1851 | pcs->desc.pctlops = &pcs_pinctrl_ops; | |
1852 | pcs->desc.pmxops = &pcs_pinmux_ops; | |
02e483f6 | 1853 | if (PCS_HAS_PINCONF) |
a7bbdd7f | 1854 | pcs->desc.confops = &pcs_pinconf_ops; |
8b8b091b TL |
1855 | pcs->desc.owner = THIS_MODULE; |
1856 | ||
1857 | ret = pcs_allocate_pin_table(pcs); | |
1858 | if (ret < 0) | |
1859 | goto free; | |
1860 | ||
950b0d91 TL |
1861 | ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); |
1862 | if (ret) { | |
8b8b091b | 1863 | dev_err(pcs->dev, "could not register single pinctrl driver\n"); |
8b8b091b TL |
1864 | goto free; |
1865 | } | |
1866 | ||
a1a277eb HZ |
1867 | ret = pcs_add_gpio_func(np, pcs); |
1868 | if (ret < 0) | |
1869 | goto free; | |
1870 | ||
3e6cee17 TL |
1871 | pcs->socdata.irq = irq_of_parse_and_map(np, 0); |
1872 | if (pcs->socdata.irq) | |
1873 | pcs->flags |= PCS_FEAT_IRQ; | |
1874 | ||
dc7743aa TL |
1875 | /* We still need auxdata for some omaps for PRM interrupts */ |
1876 | pdata = dev_get_platdata(&pdev->dev); | |
1877 | if (pdata) { | |
1878 | if (pdata->rearm) | |
1879 | pcs->socdata.rearm = pdata->rearm; | |
1880 | if (pdata->irq) { | |
1881 | pcs->socdata.irq = pdata->irq; | |
1882 | pcs->flags |= PCS_FEAT_IRQ; | |
1883 | } | |
1884 | } | |
1885 | ||
3e6cee17 TL |
1886 | if (PCS_HAS_IRQ) { |
1887 | ret = pcs_irq_init_chained_handler(pcs, np); | |
1888 | if (ret < 0) | |
1889 | dev_warn(pcs->dev, "initialized with no interrupts\n"); | |
1890 | } | |
1891 | ||
c2584927 | 1892 | dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size); |
8b8b091b | 1893 | |
61187142 | 1894 | return pinctrl_enable(pcs->pctl); |
8b8b091b TL |
1895 | |
1896 | free: | |
1897 | pcs_free_resources(pcs); | |
1898 | ||
1899 | return ret; | |
1900 | } | |
1901 | ||
f90f54b3 | 1902 | static int pcs_remove(struct platform_device *pdev) |
8b8b091b TL |
1903 | { |
1904 | struct pcs_device *pcs = platform_get_drvdata(pdev); | |
1905 | ||
1906 | if (!pcs) | |
1907 | return 0; | |
1908 | ||
1909 | pcs_free_resources(pcs); | |
1910 | ||
1911 | return 0; | |
1912 | } | |
1913 | ||
3e6cee17 TL |
1914 | static const struct pcs_soc_data pinctrl_single_omap_wkup = { |
1915 | .flags = PCS_QUIRK_SHARED_IRQ, | |
1916 | .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ | |
1917 | .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ | |
1918 | }; | |
1919 | ||
31320bea | 1920 | static const struct pcs_soc_data pinctrl_single_dra7 = { |
31320bea NM |
1921 | .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ |
1922 | .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ | |
1923 | }; | |
1924 | ||
aa2293d8 | 1925 | static const struct pcs_soc_data pinctrl_single_am437x = { |
88a1dbde | 1926 | .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF, |
aa2293d8 K |
1927 | .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ |
1928 | .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ | |
1929 | }; | |
1930 | ||
02e483f6 TL |
1931 | static const struct pcs_soc_data pinctrl_single = { |
1932 | }; | |
1933 | ||
1934 | static const struct pcs_soc_data pinconf_single = { | |
1935 | .flags = PCS_FEAT_PINCONF, | |
1936 | }; | |
1937 | ||
baa9946e | 1938 | static const struct of_device_id pcs_of_match[] = { |
3e6cee17 TL |
1939 | { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, |
1940 | { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, | |
1941 | { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, | |
31320bea | 1942 | { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, |
aa2293d8 | 1943 | { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, |
02e483f6 TL |
1944 | { .compatible = "pinctrl-single", .data = &pinctrl_single }, |
1945 | { .compatible = "pinconf-single", .data = &pinconf_single }, | |
8b8b091b TL |
1946 | { }, |
1947 | }; | |
1948 | MODULE_DEVICE_TABLE(of, pcs_of_match); | |
1949 | ||
1950 | static struct platform_driver pcs_driver = { | |
1951 | .probe = pcs_probe, | |
2a36f086 | 1952 | .remove = pcs_remove, |
8b8b091b | 1953 | .driver = { |
8b8b091b TL |
1954 | .name = DRIVER_NAME, |
1955 | .of_match_table = pcs_of_match, | |
1956 | }, | |
0f9bc4bc HG |
1957 | #ifdef CONFIG_PM |
1958 | .suspend = pinctrl_single_suspend, | |
1959 | .resume = pinctrl_single_resume, | |
1960 | #endif | |
8b8b091b TL |
1961 | }; |
1962 | ||
1963 | module_platform_driver(pcs_driver); | |
1964 | ||
1965 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
1966 | MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); | |
1967 | MODULE_LICENSE("GPL v2"); |