]>
Commit | Line | Data |
---|---|---|
8b8b091b TL |
1 | /* |
2 | * Generic device tree based pinctrl driver for one register per pin | |
3 | * type pinmux controllers | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/list.h> | |
18 | ||
19 | #include <linux/of.h> | |
20 | #include <linux/of_device.h> | |
21 | #include <linux/of_address.h> | |
22 | ||
23 | #include <linux/pinctrl/pinctrl.h> | |
24 | #include <linux/pinctrl/pinmux.h> | |
25 | ||
26 | #include "core.h" | |
27 | ||
28 | #define DRIVER_NAME "pinctrl-single" | |
9e605cb6 PU |
29 | #define PCS_MUX_PINS_NAME "pinctrl-single,pins" |
30 | #define PCS_MUX_BITS_NAME "pinctrl-single,bits" | |
8b8b091b TL |
31 | #define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1) |
32 | #define PCS_OFF_DISABLED ~0U | |
33 | ||
34 | /** | |
35 | * struct pcs_pingroup - pingroups for a function | |
36 | * @np: pingroup device node pointer | |
37 | * @name: pingroup name | |
38 | * @gpins: array of the pins in the group | |
39 | * @ngpins: number of pins in the group | |
40 | * @node: list node | |
41 | */ | |
42 | struct pcs_pingroup { | |
43 | struct device_node *np; | |
44 | const char *name; | |
45 | int *gpins; | |
46 | int ngpins; | |
47 | struct list_head node; | |
48 | }; | |
49 | ||
50 | /** | |
51 | * struct pcs_func_vals - mux function register offset and value pair | |
52 | * @reg: register virtual address | |
53 | * @val: register value | |
54 | */ | |
55 | struct pcs_func_vals { | |
56 | void __iomem *reg; | |
57 | unsigned val; | |
9e605cb6 | 58 | unsigned mask; |
8b8b091b TL |
59 | }; |
60 | ||
61 | /** | |
62 | * struct pcs_function - pinctrl function | |
63 | * @name: pinctrl function name | |
64 | * @vals: register and vals array | |
65 | * @nvals: number of entries in vals array | |
66 | * @pgnames: array of pingroup names the function uses | |
67 | * @npgnames: number of pingroup names the function uses | |
68 | * @node: list node | |
69 | */ | |
70 | struct pcs_function { | |
71 | const char *name; | |
72 | struct pcs_func_vals *vals; | |
73 | unsigned nvals; | |
74 | const char **pgnames; | |
75 | int npgnames; | |
76 | struct list_head node; | |
77 | }; | |
78 | ||
a1a277eb HZ |
79 | /** |
80 | * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function | |
81 | * @offset: offset base of pins | |
82 | * @npins: number pins with the same mux value of gpio function | |
83 | * @gpiofunc: mux value of gpio function | |
84 | * @node: list node | |
85 | */ | |
86 | struct pcs_gpiofunc_range { | |
87 | unsigned offset; | |
88 | unsigned npins; | |
89 | unsigned gpiofunc; | |
90 | struct list_head node; | |
91 | }; | |
92 | ||
8b8b091b TL |
93 | /** |
94 | * struct pcs_data - wrapper for data needed by pinctrl framework | |
95 | * @pa: pindesc array | |
96 | * @cur: index to current element | |
97 | * | |
98 | * REVISIT: We should be able to drop this eventually by adding | |
99 | * support for registering pins individually in the pinctrl | |
100 | * framework for those drivers that don't need a static array. | |
101 | */ | |
102 | struct pcs_data { | |
103 | struct pinctrl_pin_desc *pa; | |
104 | int cur; | |
105 | }; | |
106 | ||
107 | /** | |
108 | * struct pcs_name - register name for a pin | |
109 | * @name: name of the pinctrl register | |
110 | * | |
111 | * REVISIT: We may want to make names optional in the pinctrl | |
112 | * framework as some drivers may not care about pin names to | |
113 | * avoid kernel bloat. The pin names can be deciphered by user | |
114 | * space tools using debugfs based on the register address and | |
115 | * SoC packaging information. | |
116 | */ | |
117 | struct pcs_name { | |
118 | char name[PCS_REG_NAME_LEN]; | |
119 | }; | |
120 | ||
121 | /** | |
122 | * struct pcs_device - pinctrl device instance | |
123 | * @res: resources | |
124 | * @base: virtual address of the controller | |
125 | * @size: size of the ioremapped area | |
126 | * @dev: device entry | |
127 | * @pctl: pin controller device | |
128 | * @mutex: mutex protecting the lists | |
129 | * @width: bits per mux register | |
130 | * @fmask: function register mask | |
131 | * @fshift: function register shift | |
132 | * @foff: value to turn mux off | |
133 | * @fmax: max number of functions in fmask | |
134 | * @names: array of register names for pins | |
135 | * @pins: physical pins on the SoC | |
136 | * @pgtree: pingroup index radix tree | |
137 | * @ftree: function index radix tree | |
138 | * @pingroups: list of pingroups | |
139 | * @functions: list of functions | |
a1a277eb | 140 | * @gpiofuncs: list of gpio functions |
8b8b091b TL |
141 | * @ngroups: number of pingroups |
142 | * @nfuncs: number of functions | |
143 | * @desc: pin controller descriptor | |
144 | * @read: register read function to use | |
145 | * @write: register write function to use | |
146 | */ | |
147 | struct pcs_device { | |
148 | struct resource *res; | |
149 | void __iomem *base; | |
150 | unsigned size; | |
151 | struct device *dev; | |
152 | struct pinctrl_dev *pctl; | |
153 | struct mutex mutex; | |
154 | unsigned width; | |
155 | unsigned fmask; | |
156 | unsigned fshift; | |
157 | unsigned foff; | |
158 | unsigned fmax; | |
9e605cb6 | 159 | bool bits_per_mux; |
8b8b091b TL |
160 | struct pcs_name *names; |
161 | struct pcs_data pins; | |
162 | struct radix_tree_root pgtree; | |
163 | struct radix_tree_root ftree; | |
164 | struct list_head pingroups; | |
165 | struct list_head functions; | |
a1a277eb | 166 | struct list_head gpiofuncs; |
8b8b091b TL |
167 | unsigned ngroups; |
168 | unsigned nfuncs; | |
169 | struct pinctrl_desc desc; | |
170 | unsigned (*read)(void __iomem *reg); | |
171 | void (*write)(unsigned val, void __iomem *reg); | |
172 | }; | |
173 | ||
174 | /* | |
175 | * REVISIT: Reads and writes could eventually use regmap or something | |
176 | * generic. But at least on omaps, some mux registers are performance | |
177 | * critical as they may need to be remuxed every time before and after | |
178 | * idle. Adding tests for register access width for every read and | |
179 | * write like regmap is doing is not desired, and caching the registers | |
180 | * does not help in this case. | |
181 | */ | |
182 | ||
183 | static unsigned __maybe_unused pcs_readb(void __iomem *reg) | |
184 | { | |
185 | return readb(reg); | |
186 | } | |
187 | ||
188 | static unsigned __maybe_unused pcs_readw(void __iomem *reg) | |
189 | { | |
190 | return readw(reg); | |
191 | } | |
192 | ||
193 | static unsigned __maybe_unused pcs_readl(void __iomem *reg) | |
194 | { | |
195 | return readl(reg); | |
196 | } | |
197 | ||
198 | static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) | |
199 | { | |
200 | writeb(val, reg); | |
201 | } | |
202 | ||
203 | static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) | |
204 | { | |
205 | writew(val, reg); | |
206 | } | |
207 | ||
208 | static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) | |
209 | { | |
210 | writel(val, reg); | |
211 | } | |
212 | ||
213 | static int pcs_get_groups_count(struct pinctrl_dev *pctldev) | |
214 | { | |
215 | struct pcs_device *pcs; | |
216 | ||
217 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
218 | ||
219 | return pcs->ngroups; | |
220 | } | |
221 | ||
222 | static const char *pcs_get_group_name(struct pinctrl_dev *pctldev, | |
223 | unsigned gselector) | |
224 | { | |
225 | struct pcs_device *pcs; | |
226 | struct pcs_pingroup *group; | |
227 | ||
228 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
229 | group = radix_tree_lookup(&pcs->pgtree, gselector); | |
230 | if (!group) { | |
231 | dev_err(pcs->dev, "%s could not find pingroup%i\n", | |
232 | __func__, gselector); | |
233 | return NULL; | |
234 | } | |
235 | ||
236 | return group->name; | |
237 | } | |
238 | ||
239 | static int pcs_get_group_pins(struct pinctrl_dev *pctldev, | |
240 | unsigned gselector, | |
241 | const unsigned **pins, | |
242 | unsigned *npins) | |
243 | { | |
244 | struct pcs_device *pcs; | |
245 | struct pcs_pingroup *group; | |
246 | ||
247 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
248 | group = radix_tree_lookup(&pcs->pgtree, gselector); | |
249 | if (!group) { | |
250 | dev_err(pcs->dev, "%s could not find pingroup%i\n", | |
251 | __func__, gselector); | |
252 | return -EINVAL; | |
253 | } | |
254 | ||
255 | *pins = group->gpins; | |
256 | *npins = group->ngpins; | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, | |
262 | struct seq_file *s, | |
e7ed6718 | 263 | unsigned pin) |
8b8b091b | 264 | { |
7d66ce7f | 265 | struct pcs_device *pcs; |
e7ed6718 | 266 | unsigned val, mux_bytes; |
7d66ce7f MP |
267 | |
268 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
269 | ||
e7ed6718 HZ |
270 | mux_bytes = pcs->width / BITS_PER_BYTE; |
271 | val = pcs->read(pcs->base + pin * mux_bytes); | |
7d66ce7f MP |
272 | |
273 | seq_printf(s, "%08x %s " , val, DRIVER_NAME); | |
8b8b091b TL |
274 | } |
275 | ||
276 | static void pcs_dt_free_map(struct pinctrl_dev *pctldev, | |
277 | struct pinctrl_map *map, unsigned num_maps) | |
278 | { | |
279 | struct pcs_device *pcs; | |
280 | ||
281 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
282 | devm_kfree(pcs->dev, map); | |
283 | } | |
284 | ||
285 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
286 | struct device_node *np_config, | |
287 | struct pinctrl_map **map, unsigned *num_maps); | |
288 | ||
022ab148 | 289 | static const struct pinctrl_ops pcs_pinctrl_ops = { |
8b8b091b TL |
290 | .get_groups_count = pcs_get_groups_count, |
291 | .get_group_name = pcs_get_group_name, | |
292 | .get_group_pins = pcs_get_group_pins, | |
293 | .pin_dbg_show = pcs_pin_dbg_show, | |
294 | .dt_node_to_map = pcs_dt_node_to_map, | |
295 | .dt_free_map = pcs_dt_free_map, | |
296 | }; | |
297 | ||
298 | static int pcs_get_functions_count(struct pinctrl_dev *pctldev) | |
299 | { | |
300 | struct pcs_device *pcs; | |
301 | ||
302 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
303 | ||
304 | return pcs->nfuncs; | |
305 | } | |
306 | ||
307 | static const char *pcs_get_function_name(struct pinctrl_dev *pctldev, | |
308 | unsigned fselector) | |
309 | { | |
310 | struct pcs_device *pcs; | |
311 | struct pcs_function *func; | |
312 | ||
313 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
314 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
315 | if (!func) { | |
316 | dev_err(pcs->dev, "%s could not find function%i\n", | |
317 | __func__, fselector); | |
318 | return NULL; | |
319 | } | |
320 | ||
321 | return func->name; | |
322 | } | |
323 | ||
324 | static int pcs_get_function_groups(struct pinctrl_dev *pctldev, | |
325 | unsigned fselector, | |
326 | const char * const **groups, | |
327 | unsigned * const ngroups) | |
328 | { | |
329 | struct pcs_device *pcs; | |
330 | struct pcs_function *func; | |
331 | ||
332 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
333 | func = radix_tree_lookup(&pcs->ftree, fselector); | |
334 | if (!func) { | |
335 | dev_err(pcs->dev, "%s could not find function%i\n", | |
336 | __func__, fselector); | |
337 | return -EINVAL; | |
338 | } | |
339 | *groups = func->pgnames; | |
340 | *ngroups = func->npgnames; | |
341 | ||
342 | return 0; | |
343 | } | |
344 | ||
345 | static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, | |
346 | unsigned group) | |
347 | { | |
348 | struct pcs_device *pcs; | |
349 | struct pcs_function *func; | |
350 | int i; | |
351 | ||
352 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
477ac771 HZ |
353 | /* If function mask is null, needn't enable it. */ |
354 | if (!pcs->fmask) | |
355 | return 0; | |
8b8b091b TL |
356 | func = radix_tree_lookup(&pcs->ftree, fselector); |
357 | if (!func) | |
358 | return -EINVAL; | |
359 | ||
360 | dev_dbg(pcs->dev, "enabling %s function%i\n", | |
361 | func->name, fselector); | |
362 | ||
363 | for (i = 0; i < func->nvals; i++) { | |
364 | struct pcs_func_vals *vals; | |
9e605cb6 | 365 | unsigned val, mask; |
8b8b091b TL |
366 | |
367 | vals = &func->vals[i]; | |
368 | val = pcs->read(vals->reg); | |
9e605cb6 PU |
369 | if (!vals->mask) |
370 | mask = pcs->fmask; | |
371 | else | |
372 | mask = pcs->fmask & vals->mask; | |
373 | ||
374 | val &= ~mask; | |
375 | val |= (vals->val & mask); | |
8b8b091b TL |
376 | pcs->write(val, vals->reg); |
377 | } | |
378 | ||
379 | return 0; | |
380 | } | |
381 | ||
382 | static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector, | |
383 | unsigned group) | |
384 | { | |
385 | struct pcs_device *pcs; | |
386 | struct pcs_function *func; | |
387 | int i; | |
388 | ||
389 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
477ac771 HZ |
390 | /* If function mask is null, needn't disable it. */ |
391 | if (!pcs->fmask) | |
392 | return; | |
393 | ||
8b8b091b TL |
394 | func = radix_tree_lookup(&pcs->ftree, fselector); |
395 | if (!func) { | |
396 | dev_err(pcs->dev, "%s could not find function%i\n", | |
397 | __func__, fselector); | |
398 | return; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Ignore disable if function-off is not specified. Some hardware | |
403 | * does not have clearly defined disable function. For pin specific | |
404 | * off modes, you can use alternate named states as described in | |
405 | * pinctrl-bindings.txt. | |
406 | */ | |
407 | if (pcs->foff == PCS_OFF_DISABLED) { | |
408 | dev_dbg(pcs->dev, "ignoring disable for %s function%i\n", | |
409 | func->name, fselector); | |
410 | return; | |
411 | } | |
412 | ||
413 | dev_dbg(pcs->dev, "disabling function%i %s\n", | |
414 | fselector, func->name); | |
415 | ||
416 | for (i = 0; i < func->nvals; i++) { | |
417 | struct pcs_func_vals *vals; | |
418 | unsigned val; | |
419 | ||
420 | vals = &func->vals[i]; | |
421 | val = pcs->read(vals->reg); | |
422 | val &= ~pcs->fmask; | |
423 | val |= pcs->foff << pcs->fshift; | |
424 | pcs->write(val, vals->reg); | |
425 | } | |
426 | } | |
427 | ||
428 | static int pcs_request_gpio(struct pinctrl_dev *pctldev, | |
a1a277eb | 429 | struct pinctrl_gpio_range *range, unsigned pin) |
8b8b091b | 430 | { |
a1a277eb HZ |
431 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
432 | struct pcs_gpiofunc_range *frange = NULL; | |
433 | struct list_head *pos, *tmp; | |
434 | int mux_bytes = 0; | |
435 | unsigned data; | |
436 | ||
477ac771 HZ |
437 | /* If function mask is null, return directly. */ |
438 | if (!pcs->fmask) | |
439 | return -ENOTSUPP; | |
440 | ||
a1a277eb HZ |
441 | list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { |
442 | frange = list_entry(pos, struct pcs_gpiofunc_range, node); | |
443 | if (pin >= frange->offset + frange->npins | |
444 | || pin < frange->offset) | |
445 | continue; | |
446 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
447 | data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; | |
448 | data |= frange->gpiofunc; | |
449 | pcs->write(data, pcs->base + pin * mux_bytes); | |
450 | break; | |
451 | } | |
452 | return 0; | |
8b8b091b TL |
453 | } |
454 | ||
022ab148 | 455 | static const struct pinmux_ops pcs_pinmux_ops = { |
8b8b091b TL |
456 | .get_functions_count = pcs_get_functions_count, |
457 | .get_function_name = pcs_get_function_name, | |
458 | .get_function_groups = pcs_get_function_groups, | |
459 | .enable = pcs_enable, | |
460 | .disable = pcs_disable, | |
461 | .gpio_request_enable = pcs_request_gpio, | |
462 | }; | |
463 | ||
464 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, | |
465 | unsigned pin, unsigned long *config) | |
466 | { | |
467 | return -ENOTSUPP; | |
468 | } | |
469 | ||
470 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, | |
471 | unsigned pin, unsigned long config) | |
472 | { | |
473 | return -ENOTSUPP; | |
474 | } | |
475 | ||
476 | static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, | |
477 | unsigned group, unsigned long *config) | |
478 | { | |
479 | return -ENOTSUPP; | |
480 | } | |
481 | ||
482 | static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, | |
483 | unsigned group, unsigned long config) | |
484 | { | |
485 | return -ENOTSUPP; | |
486 | } | |
487 | ||
488 | static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
489 | struct seq_file *s, unsigned offset) | |
490 | { | |
491 | } | |
492 | ||
493 | static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
494 | struct seq_file *s, unsigned selector) | |
495 | { | |
496 | } | |
497 | ||
022ab148 | 498 | static const struct pinconf_ops pcs_pinconf_ops = { |
8b8b091b TL |
499 | .pin_config_get = pcs_pinconf_get, |
500 | .pin_config_set = pcs_pinconf_set, | |
501 | .pin_config_group_get = pcs_pinconf_group_get, | |
502 | .pin_config_group_set = pcs_pinconf_group_set, | |
503 | .pin_config_dbg_show = pcs_pinconf_dbg_show, | |
504 | .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, | |
505 | }; | |
506 | ||
507 | /** | |
508 | * pcs_add_pin() - add a pin to the static per controller pin array | |
509 | * @pcs: pcs driver instance | |
510 | * @offset: register offset from base | |
511 | */ | |
150632b0 | 512 | static int pcs_add_pin(struct pcs_device *pcs, unsigned offset) |
8b8b091b TL |
513 | { |
514 | struct pinctrl_pin_desc *pin; | |
515 | struct pcs_name *pn; | |
516 | int i; | |
517 | ||
518 | i = pcs->pins.cur; | |
519 | if (i >= pcs->desc.npins) { | |
520 | dev_err(pcs->dev, "too many pins, max %i\n", | |
521 | pcs->desc.npins); | |
522 | return -ENOMEM; | |
523 | } | |
524 | ||
525 | pin = &pcs->pins.pa[i]; | |
526 | pn = &pcs->names[i]; | |
527 | sprintf(pn->name, "%lx", | |
528 | (unsigned long)pcs->res->start + offset); | |
529 | pin->name = pn->name; | |
530 | pin->number = i; | |
531 | pcs->pins.cur++; | |
532 | ||
533 | return i; | |
534 | } | |
535 | ||
536 | /** | |
537 | * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver | |
538 | * @pcs: pcs driver instance | |
539 | * | |
540 | * In case of errors, resources are freed in pcs_free_resources. | |
541 | * | |
542 | * If your hardware needs holes in the address space, then just set | |
543 | * up multiple driver instances. | |
544 | */ | |
150632b0 | 545 | static int pcs_allocate_pin_table(struct pcs_device *pcs) |
8b8b091b TL |
546 | { |
547 | int mux_bytes, nr_pins, i; | |
548 | ||
549 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
550 | nr_pins = pcs->size / mux_bytes; | |
551 | ||
552 | dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); | |
553 | pcs->pins.pa = devm_kzalloc(pcs->dev, | |
554 | sizeof(*pcs->pins.pa) * nr_pins, | |
555 | GFP_KERNEL); | |
556 | if (!pcs->pins.pa) | |
557 | return -ENOMEM; | |
558 | ||
559 | pcs->names = devm_kzalloc(pcs->dev, | |
560 | sizeof(struct pcs_name) * nr_pins, | |
561 | GFP_KERNEL); | |
562 | if (!pcs->names) | |
563 | return -ENOMEM; | |
564 | ||
565 | pcs->desc.pins = pcs->pins.pa; | |
566 | pcs->desc.npins = nr_pins; | |
567 | ||
568 | for (i = 0; i < pcs->desc.npins; i++) { | |
569 | unsigned offset; | |
570 | int res; | |
571 | ||
572 | offset = i * mux_bytes; | |
573 | res = pcs_add_pin(pcs, offset); | |
574 | if (res < 0) { | |
575 | dev_err(pcs->dev, "error adding pins: %i\n", res); | |
576 | return res; | |
577 | } | |
578 | } | |
579 | ||
580 | return 0; | |
581 | } | |
582 | ||
583 | /** | |
584 | * pcs_add_function() - adds a new function to the function list | |
585 | * @pcs: pcs driver instance | |
586 | * @np: device node of the mux entry | |
587 | * @name: name of the function | |
588 | * @vals: array of mux register value pairs used by the function | |
589 | * @nvals: number of mux register value pairs | |
590 | * @pgnames: array of pingroup names for the function | |
591 | * @npgnames: number of pingroup names | |
592 | */ | |
593 | static struct pcs_function *pcs_add_function(struct pcs_device *pcs, | |
594 | struct device_node *np, | |
595 | const char *name, | |
596 | struct pcs_func_vals *vals, | |
597 | unsigned nvals, | |
598 | const char **pgnames, | |
599 | unsigned npgnames) | |
600 | { | |
601 | struct pcs_function *function; | |
602 | ||
603 | function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); | |
604 | if (!function) | |
605 | return NULL; | |
606 | ||
607 | function->name = name; | |
608 | function->vals = vals; | |
609 | function->nvals = nvals; | |
610 | function->pgnames = pgnames; | |
611 | function->npgnames = npgnames; | |
612 | ||
613 | mutex_lock(&pcs->mutex); | |
614 | list_add_tail(&function->node, &pcs->functions); | |
615 | radix_tree_insert(&pcs->ftree, pcs->nfuncs, function); | |
616 | pcs->nfuncs++; | |
617 | mutex_unlock(&pcs->mutex); | |
618 | ||
619 | return function; | |
620 | } | |
621 | ||
622 | static void pcs_remove_function(struct pcs_device *pcs, | |
623 | struct pcs_function *function) | |
624 | { | |
625 | int i; | |
626 | ||
627 | mutex_lock(&pcs->mutex); | |
628 | for (i = 0; i < pcs->nfuncs; i++) { | |
629 | struct pcs_function *found; | |
630 | ||
631 | found = radix_tree_lookup(&pcs->ftree, i); | |
632 | if (found == function) | |
633 | radix_tree_delete(&pcs->ftree, i); | |
634 | } | |
635 | list_del(&function->node); | |
636 | mutex_unlock(&pcs->mutex); | |
637 | } | |
638 | ||
639 | /** | |
640 | * pcs_add_pingroup() - add a pingroup to the pingroup list | |
641 | * @pcs: pcs driver instance | |
642 | * @np: device node of the mux entry | |
643 | * @name: name of the pingroup | |
644 | * @gpins: array of the pins that belong to the group | |
645 | * @ngpins: number of pins in the group | |
646 | */ | |
647 | static int pcs_add_pingroup(struct pcs_device *pcs, | |
648 | struct device_node *np, | |
649 | const char *name, | |
650 | int *gpins, | |
651 | int ngpins) | |
652 | { | |
653 | struct pcs_pingroup *pingroup; | |
654 | ||
655 | pingroup = devm_kzalloc(pcs->dev, sizeof(*pingroup), GFP_KERNEL); | |
656 | if (!pingroup) | |
657 | return -ENOMEM; | |
658 | ||
659 | pingroup->name = name; | |
660 | pingroup->np = np; | |
661 | pingroup->gpins = gpins; | |
662 | pingroup->ngpins = ngpins; | |
663 | ||
664 | mutex_lock(&pcs->mutex); | |
665 | list_add_tail(&pingroup->node, &pcs->pingroups); | |
666 | radix_tree_insert(&pcs->pgtree, pcs->ngroups, pingroup); | |
667 | pcs->ngroups++; | |
668 | mutex_unlock(&pcs->mutex); | |
669 | ||
670 | return 0; | |
671 | } | |
672 | ||
673 | /** | |
674 | * pcs_get_pin_by_offset() - get a pin index based on the register offset | |
675 | * @pcs: pcs driver instance | |
676 | * @offset: register offset from the base | |
677 | * | |
678 | * Note that this is OK as long as the pins are in a static array. | |
679 | */ | |
680 | static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) | |
681 | { | |
682 | unsigned index; | |
683 | ||
684 | if (offset >= pcs->size) { | |
685 | dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
686 | offset, pcs->size); | |
687 | return -EINVAL; | |
688 | } | |
689 | ||
690 | index = offset / (pcs->width / BITS_PER_BYTE); | |
691 | ||
692 | return index; | |
693 | } | |
694 | ||
695 | /** | |
696 | * smux_parse_one_pinctrl_entry() - parses a device tree mux entry | |
697 | * @pcs: pinctrl driver instance | |
698 | * @np: device node of the mux entry | |
699 | * @map: map entry | |
700 | * @pgnames: pingroup names | |
701 | * | |
702 | * Note that this binding currently supports only sets of one register + value. | |
703 | * | |
704 | * Also note that this driver tries to avoid understanding pin and function | |
705 | * names because of the extra bloat they would cause especially in the case of | |
706 | * a large number of pins. This driver just sets what is specified for the board | |
707 | * in the .dts file. Further user space debugging tools can be developed to | |
708 | * decipher the pin and function names using debugfs. | |
709 | * | |
710 | * If you are concerned about the boot time, set up the static pins in | |
711 | * the bootloader, and only set up selected pins as device tree entries. | |
712 | */ | |
713 | static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, | |
714 | struct device_node *np, | |
715 | struct pinctrl_map **map, | |
716 | const char **pgnames) | |
717 | { | |
718 | struct pcs_func_vals *vals; | |
719 | const __be32 *mux; | |
9e605cb6 | 720 | int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM; |
8b8b091b TL |
721 | struct pcs_function *function; |
722 | ||
9e605cb6 PU |
723 | if (pcs->bits_per_mux) { |
724 | params = 3; | |
725 | mux = of_get_property(np, PCS_MUX_BITS_NAME, &size); | |
726 | } else { | |
727 | params = 2; | |
728 | mux = of_get_property(np, PCS_MUX_PINS_NAME, &size); | |
729 | } | |
730 | ||
731 | if (!mux) { | |
732 | dev_err(pcs->dev, "no valid property for %s\n", np->name); | |
733 | return -EINVAL; | |
734 | } | |
735 | ||
736 | if (size < (sizeof(*mux) * params)) { | |
737 | dev_err(pcs->dev, "bad data for %s\n", np->name); | |
8b8b091b TL |
738 | return -EINVAL; |
739 | } | |
740 | ||
741 | size /= sizeof(*mux); /* Number of elements in array */ | |
9e605cb6 | 742 | rows = size / params; |
8b8b091b TL |
743 | |
744 | vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); | |
745 | if (!vals) | |
746 | return -ENOMEM; | |
747 | ||
748 | pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); | |
749 | if (!pins) | |
750 | goto free_vals; | |
751 | ||
752 | while (index < size) { | |
753 | unsigned offset, val; | |
754 | int pin; | |
755 | ||
756 | offset = be32_to_cpup(mux + index++); | |
757 | val = be32_to_cpup(mux + index++); | |
758 | vals[found].reg = pcs->base + offset; | |
759 | vals[found].val = val; | |
9e605cb6 PU |
760 | if (params == 3) { |
761 | val = be32_to_cpup(mux + index++); | |
762 | vals[found].mask = val; | |
763 | } | |
8b8b091b TL |
764 | |
765 | pin = pcs_get_pin_by_offset(pcs, offset); | |
766 | if (pin < 0) { | |
767 | dev_err(pcs->dev, | |
768 | "could not add functions for %s %ux\n", | |
769 | np->name, offset); | |
770 | break; | |
771 | } | |
772 | pins[found++] = pin; | |
773 | } | |
774 | ||
775 | pgnames[0] = np->name; | |
776 | function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); | |
777 | if (!function) | |
778 | goto free_pins; | |
779 | ||
780 | res = pcs_add_pingroup(pcs, np, np->name, pins, found); | |
781 | if (res < 0) | |
782 | goto free_function; | |
783 | ||
784 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
785 | (*map)->data.mux.group = np->name; | |
786 | (*map)->data.mux.function = np->name; | |
787 | ||
788 | return 0; | |
789 | ||
790 | free_function: | |
791 | pcs_remove_function(pcs, function); | |
792 | ||
793 | free_pins: | |
794 | devm_kfree(pcs->dev, pins); | |
795 | ||
796 | free_vals: | |
797 | devm_kfree(pcs->dev, vals); | |
798 | ||
799 | return res; | |
800 | } | |
801 | /** | |
802 | * pcs_dt_node_to_map() - allocates and parses pinctrl maps | |
803 | * @pctldev: pinctrl instance | |
804 | * @np_config: device tree pinmux entry | |
805 | * @map: array of map entries | |
806 | * @num_maps: number of maps | |
807 | */ | |
808 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
809 | struct device_node *np_config, | |
810 | struct pinctrl_map **map, unsigned *num_maps) | |
811 | { | |
812 | struct pcs_device *pcs; | |
813 | const char **pgnames; | |
814 | int ret; | |
815 | ||
816 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
817 | ||
818 | *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); | |
00e79d12 | 819 | if (!*map) |
8b8b091b TL |
820 | return -ENOMEM; |
821 | ||
822 | *num_maps = 0; | |
823 | ||
824 | pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); | |
825 | if (!pgnames) { | |
826 | ret = -ENOMEM; | |
827 | goto free_map; | |
828 | } | |
829 | ||
830 | ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); | |
831 | if (ret < 0) { | |
832 | dev_err(pcs->dev, "no pins entries for %s\n", | |
833 | np_config->name); | |
834 | goto free_pgnames; | |
835 | } | |
836 | *num_maps = 1; | |
837 | ||
838 | return 0; | |
839 | ||
840 | free_pgnames: | |
841 | devm_kfree(pcs->dev, pgnames); | |
842 | free_map: | |
843 | devm_kfree(pcs->dev, *map); | |
844 | ||
845 | return ret; | |
846 | } | |
847 | ||
848 | /** | |
849 | * pcs_free_funcs() - free memory used by functions | |
850 | * @pcs: pcs driver instance | |
851 | */ | |
852 | static void pcs_free_funcs(struct pcs_device *pcs) | |
853 | { | |
854 | struct list_head *pos, *tmp; | |
855 | int i; | |
856 | ||
857 | mutex_lock(&pcs->mutex); | |
858 | for (i = 0; i < pcs->nfuncs; i++) { | |
859 | struct pcs_function *func; | |
860 | ||
861 | func = radix_tree_lookup(&pcs->ftree, i); | |
862 | if (!func) | |
863 | continue; | |
864 | radix_tree_delete(&pcs->ftree, i); | |
865 | } | |
866 | list_for_each_safe(pos, tmp, &pcs->functions) { | |
867 | struct pcs_function *function; | |
868 | ||
869 | function = list_entry(pos, struct pcs_function, node); | |
870 | list_del(&function->node); | |
871 | } | |
872 | mutex_unlock(&pcs->mutex); | |
873 | } | |
874 | ||
875 | /** | |
876 | * pcs_free_pingroups() - free memory used by pingroups | |
877 | * @pcs: pcs driver instance | |
878 | */ | |
879 | static void pcs_free_pingroups(struct pcs_device *pcs) | |
880 | { | |
881 | struct list_head *pos, *tmp; | |
882 | int i; | |
883 | ||
884 | mutex_lock(&pcs->mutex); | |
885 | for (i = 0; i < pcs->ngroups; i++) { | |
886 | struct pcs_pingroup *pingroup; | |
887 | ||
888 | pingroup = radix_tree_lookup(&pcs->pgtree, i); | |
889 | if (!pingroup) | |
890 | continue; | |
891 | radix_tree_delete(&pcs->pgtree, i); | |
892 | } | |
893 | list_for_each_safe(pos, tmp, &pcs->pingroups) { | |
894 | struct pcs_pingroup *pingroup; | |
895 | ||
896 | pingroup = list_entry(pos, struct pcs_pingroup, node); | |
897 | list_del(&pingroup->node); | |
898 | } | |
899 | mutex_unlock(&pcs->mutex); | |
900 | } | |
901 | ||
902 | /** | |
903 | * pcs_free_resources() - free memory used by this driver | |
904 | * @pcs: pcs driver instance | |
905 | */ | |
906 | static void pcs_free_resources(struct pcs_device *pcs) | |
907 | { | |
908 | if (pcs->pctl) | |
909 | pinctrl_unregister(pcs->pctl); | |
910 | ||
911 | pcs_free_funcs(pcs); | |
912 | pcs_free_pingroups(pcs); | |
913 | } | |
914 | ||
915 | #define PCS_GET_PROP_U32(name, reg, err) \ | |
916 | do { \ | |
917 | ret = of_property_read_u32(np, name, reg); \ | |
918 | if (ret) { \ | |
919 | dev_err(pcs->dev, err); \ | |
920 | return ret; \ | |
921 | } \ | |
922 | } while (0); | |
923 | ||
924 | static struct of_device_id pcs_of_match[]; | |
925 | ||
a1a277eb HZ |
926 | static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) |
927 | { | |
928 | const char *propname = "pinctrl-single,gpio-range"; | |
929 | const char *cellname = "#pinctrl-single,gpio-range-cells"; | |
930 | struct of_phandle_args gpiospec; | |
931 | struct pcs_gpiofunc_range *range; | |
932 | int ret, i; | |
933 | ||
934 | for (i = 0; ; i++) { | |
935 | ret = of_parse_phandle_with_args(node, propname, cellname, | |
936 | i, &gpiospec); | |
937 | /* Do not treat it as error. Only treat it as end condition. */ | |
938 | if (ret) { | |
939 | ret = 0; | |
940 | break; | |
941 | } | |
942 | range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); | |
943 | if (!range) { | |
944 | ret = -ENOMEM; | |
945 | break; | |
946 | } | |
947 | range->offset = gpiospec.args[0]; | |
948 | range->npins = gpiospec.args[1]; | |
949 | range->gpiofunc = gpiospec.args[2]; | |
950 | mutex_lock(&pcs->mutex); | |
951 | list_add_tail(&range->node, &pcs->gpiofuncs); | |
952 | mutex_unlock(&pcs->mutex); | |
953 | } | |
954 | return ret; | |
955 | } | |
956 | ||
150632b0 | 957 | static int pcs_probe(struct platform_device *pdev) |
8b8b091b TL |
958 | { |
959 | struct device_node *np = pdev->dev.of_node; | |
960 | const struct of_device_id *match; | |
961 | struct resource *res; | |
962 | struct pcs_device *pcs; | |
963 | int ret; | |
964 | ||
965 | match = of_match_device(pcs_of_match, &pdev->dev); | |
966 | if (!match) | |
967 | return -EINVAL; | |
968 | ||
969 | pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); | |
970 | if (!pcs) { | |
971 | dev_err(&pdev->dev, "could not allocate\n"); | |
972 | return -ENOMEM; | |
973 | } | |
974 | pcs->dev = &pdev->dev; | |
975 | mutex_init(&pcs->mutex); | |
976 | INIT_LIST_HEAD(&pcs->pingroups); | |
977 | INIT_LIST_HEAD(&pcs->functions); | |
a1a277eb | 978 | INIT_LIST_HEAD(&pcs->gpiofuncs); |
8b8b091b TL |
979 | |
980 | PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, | |
981 | "register width not specified\n"); | |
982 | ||
477ac771 HZ |
983 | ret = of_property_read_u32(np, "pinctrl-single,function-mask", |
984 | &pcs->fmask); | |
985 | if (!ret) { | |
986 | pcs->fshift = ffs(pcs->fmask) - 1; | |
987 | pcs->fmax = pcs->fmask >> pcs->fshift; | |
988 | } else { | |
989 | /* If mask property doesn't exist, function mux is invalid. */ | |
990 | pcs->fmask = 0; | |
991 | pcs->fshift = 0; | |
992 | pcs->fmax = 0; | |
993 | } | |
8b8b091b TL |
994 | |
995 | ret = of_property_read_u32(np, "pinctrl-single,function-off", | |
996 | &pcs->foff); | |
997 | if (ret) | |
998 | pcs->foff = PCS_OFF_DISABLED; | |
999 | ||
9e605cb6 PU |
1000 | pcs->bits_per_mux = of_property_read_bool(np, |
1001 | "pinctrl-single,bit-per-mux"); | |
1002 | ||
8b8b091b TL |
1003 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1004 | if (!res) { | |
1005 | dev_err(pcs->dev, "could not get resource\n"); | |
1006 | return -ENODEV; | |
1007 | } | |
1008 | ||
1009 | pcs->res = devm_request_mem_region(pcs->dev, res->start, | |
1010 | resource_size(res), DRIVER_NAME); | |
1011 | if (!pcs->res) { | |
1012 | dev_err(pcs->dev, "could not get mem_region\n"); | |
1013 | return -EBUSY; | |
1014 | } | |
1015 | ||
1016 | pcs->size = resource_size(pcs->res); | |
1017 | pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); | |
1018 | if (!pcs->base) { | |
1019 | dev_err(pcs->dev, "could not ioremap\n"); | |
1020 | return -ENODEV; | |
1021 | } | |
1022 | ||
1023 | INIT_RADIX_TREE(&pcs->pgtree, GFP_KERNEL); | |
1024 | INIT_RADIX_TREE(&pcs->ftree, GFP_KERNEL); | |
1025 | platform_set_drvdata(pdev, pcs); | |
1026 | ||
1027 | switch (pcs->width) { | |
1028 | case 8: | |
1029 | pcs->read = pcs_readb; | |
1030 | pcs->write = pcs_writeb; | |
1031 | break; | |
1032 | case 16: | |
1033 | pcs->read = pcs_readw; | |
1034 | pcs->write = pcs_writew; | |
1035 | break; | |
1036 | case 32: | |
1037 | pcs->read = pcs_readl; | |
1038 | pcs->write = pcs_writel; | |
1039 | break; | |
1040 | default: | |
1041 | break; | |
1042 | } | |
1043 | ||
1044 | pcs->desc.name = DRIVER_NAME; | |
1045 | pcs->desc.pctlops = &pcs_pinctrl_ops; | |
1046 | pcs->desc.pmxops = &pcs_pinmux_ops; | |
1047 | pcs->desc.confops = &pcs_pinconf_ops; | |
1048 | pcs->desc.owner = THIS_MODULE; | |
1049 | ||
1050 | ret = pcs_allocate_pin_table(pcs); | |
1051 | if (ret < 0) | |
1052 | goto free; | |
1053 | ||
1054 | pcs->pctl = pinctrl_register(&pcs->desc, pcs->dev, pcs); | |
1055 | if (!pcs->pctl) { | |
1056 | dev_err(pcs->dev, "could not register single pinctrl driver\n"); | |
1057 | ret = -EINVAL; | |
1058 | goto free; | |
1059 | } | |
1060 | ||
a1a277eb HZ |
1061 | ret = pcs_add_gpio_func(np, pcs); |
1062 | if (ret < 0) | |
1063 | goto free; | |
1064 | ||
8b8b091b TL |
1065 | dev_info(pcs->dev, "%i pins at pa %p size %u\n", |
1066 | pcs->desc.npins, pcs->base, pcs->size); | |
1067 | ||
1068 | return 0; | |
1069 | ||
1070 | free: | |
1071 | pcs_free_resources(pcs); | |
1072 | ||
1073 | return ret; | |
1074 | } | |
1075 | ||
f90f54b3 | 1076 | static int pcs_remove(struct platform_device *pdev) |
8b8b091b TL |
1077 | { |
1078 | struct pcs_device *pcs = platform_get_drvdata(pdev); | |
1079 | ||
1080 | if (!pcs) | |
1081 | return 0; | |
1082 | ||
1083 | pcs_free_resources(pcs); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
99688ed7 | 1088 | static struct of_device_id pcs_of_match[] = { |
8b8b091b TL |
1089 | { .compatible = DRIVER_NAME, }, |
1090 | { }, | |
1091 | }; | |
1092 | MODULE_DEVICE_TABLE(of, pcs_of_match); | |
1093 | ||
1094 | static struct platform_driver pcs_driver = { | |
1095 | .probe = pcs_probe, | |
2a36f086 | 1096 | .remove = pcs_remove, |
8b8b091b TL |
1097 | .driver = { |
1098 | .owner = THIS_MODULE, | |
1099 | .name = DRIVER_NAME, | |
1100 | .of_match_table = pcs_of_match, | |
1101 | }, | |
1102 | }; | |
1103 | ||
1104 | module_platform_driver(pcs_driver); | |
1105 | ||
1106 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
1107 | MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); | |
1108 | MODULE_LICENSE("GPL v2"); |