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8b8b091b TL |
1 | /* |
2 | * Generic device tree based pinctrl driver for one register per pin | |
3 | * type pinmux controllers | |
4 | * | |
5 | * Copyright (C) 2012 Texas Instruments, Inc. | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/init.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/slab.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/list.h> | |
3e6cee17 TL |
18 | #include <linux/interrupt.h> |
19 | ||
20 | #include <linux/irqchip/chained_irq.h> | |
8b8b091b TL |
21 | |
22 | #include <linux/of.h> | |
23 | #include <linux/of_device.h> | |
24 | #include <linux/of_address.h> | |
3e6cee17 | 25 | #include <linux/of_irq.h> |
8b8b091b TL |
26 | |
27 | #include <linux/pinctrl/pinctrl.h> | |
28 | #include <linux/pinctrl/pinmux.h> | |
9dddb4df | 29 | #include <linux/pinctrl/pinconf-generic.h> |
8b8b091b | 30 | |
dc7743aa TL |
31 | #include <linux/platform_data/pinctrl-single.h> |
32 | ||
8b8b091b | 33 | #include "core.h" |
4622215f | 34 | #include "devicetree.h" |
9dddb4df | 35 | #include "pinconf.h" |
571aec4d | 36 | #include "pinmux.h" |
8b8b091b TL |
37 | |
38 | #define DRIVER_NAME "pinctrl-single" | |
8b8b091b TL |
39 | #define PCS_OFF_DISABLED ~0U |
40 | ||
8b8b091b TL |
41 | /** |
42 | * struct pcs_func_vals - mux function register offset and value pair | |
43 | * @reg: register virtual address | |
44 | * @val: register value | |
45 | */ | |
46 | struct pcs_func_vals { | |
47 | void __iomem *reg; | |
48 | unsigned val; | |
9e605cb6 | 49 | unsigned mask; |
8b8b091b TL |
50 | }; |
51 | ||
9dddb4df HZ |
52 | /** |
53 | * struct pcs_conf_vals - pinconf parameter, pinconf register offset | |
54 | * and value, enable, disable, mask | |
55 | * @param: config parameter | |
56 | * @val: user input bits in the pinconf register | |
57 | * @enable: enable bits in the pinconf register | |
58 | * @disable: disable bits in the pinconf register | |
59 | * @mask: mask bits in the register value | |
60 | */ | |
61 | struct pcs_conf_vals { | |
62 | enum pin_config_param param; | |
63 | unsigned val; | |
64 | unsigned enable; | |
65 | unsigned disable; | |
66 | unsigned mask; | |
67 | }; | |
68 | ||
69 | /** | |
70 | * struct pcs_conf_type - pinconf property name, pinconf param pair | |
71 | * @name: property name in DTS file | |
72 | * @param: config parameter | |
73 | */ | |
74 | struct pcs_conf_type { | |
75 | const char *name; | |
76 | enum pin_config_param param; | |
77 | }; | |
78 | ||
8b8b091b TL |
79 | /** |
80 | * struct pcs_function - pinctrl function | |
81 | * @name: pinctrl function name | |
82 | * @vals: register and vals array | |
83 | * @nvals: number of entries in vals array | |
84 | * @pgnames: array of pingroup names the function uses | |
85 | * @npgnames: number of pingroup names the function uses | |
86 | * @node: list node | |
87 | */ | |
88 | struct pcs_function { | |
89 | const char *name; | |
90 | struct pcs_func_vals *vals; | |
91 | unsigned nvals; | |
92 | const char **pgnames; | |
93 | int npgnames; | |
9dddb4df HZ |
94 | struct pcs_conf_vals *conf; |
95 | int nconfs; | |
8b8b091b TL |
96 | struct list_head node; |
97 | }; | |
98 | ||
a1a277eb HZ |
99 | /** |
100 | * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function | |
101 | * @offset: offset base of pins | |
102 | * @npins: number pins with the same mux value of gpio function | |
103 | * @gpiofunc: mux value of gpio function | |
104 | * @node: list node | |
105 | */ | |
106 | struct pcs_gpiofunc_range { | |
107 | unsigned offset; | |
108 | unsigned npins; | |
109 | unsigned gpiofunc; | |
110 | struct list_head node; | |
111 | }; | |
112 | ||
8b8b091b TL |
113 | /** |
114 | * struct pcs_data - wrapper for data needed by pinctrl framework | |
115 | * @pa: pindesc array | |
116 | * @cur: index to current element | |
117 | * | |
118 | * REVISIT: We should be able to drop this eventually by adding | |
119 | * support for registering pins individually in the pinctrl | |
120 | * framework for those drivers that don't need a static array. | |
121 | */ | |
122 | struct pcs_data { | |
123 | struct pinctrl_pin_desc *pa; | |
124 | int cur; | |
125 | }; | |
126 | ||
02e483f6 TL |
127 | /** |
128 | * struct pcs_soc_data - SoC specific settings | |
129 | * @flags: initial SoC specific PCS_FEAT_xxx values | |
3e6cee17 TL |
130 | * @irq: optional interrupt for the controller |
131 | * @irq_enable_mask: optional SoC specific interrupt enable mask | |
132 | * @irq_status_mask: optional SoC specific interrupt status mask | |
dc7743aa | 133 | * @rearm: optional SoC specific wake-up rearm function |
02e483f6 TL |
134 | */ |
135 | struct pcs_soc_data { | |
136 | unsigned flags; | |
3e6cee17 TL |
137 | int irq; |
138 | unsigned irq_enable_mask; | |
139 | unsigned irq_status_mask; | |
dc7743aa | 140 | void (*rearm)(void); |
02e483f6 TL |
141 | }; |
142 | ||
8b8b091b TL |
143 | /** |
144 | * struct pcs_device - pinctrl device instance | |
145 | * @res: resources | |
146 | * @base: virtual address of the controller | |
147 | * @size: size of the ioremapped area | |
148 | * @dev: device entry | |
4622215f | 149 | * @np: device tree node |
8b8b091b | 150 | * @pctl: pin controller device |
02e483f6 | 151 | * @flags: mask of PCS_FEAT_xxx values |
4622215f TL |
152 | * @missing_nr_pinctrl_cells: for legacy binding, may go away |
153 | * @socdata: soc specific data | |
3e6cee17 | 154 | * @lock: spinlock for register access |
8b8b091b TL |
155 | * @mutex: mutex protecting the lists |
156 | * @width: bits per mux register | |
157 | * @fmask: function register mask | |
158 | * @fshift: function register shift | |
159 | * @foff: value to turn mux off | |
160 | * @fmax: max number of functions in fmask | |
4622215f TL |
161 | * @bits_per_mux: number of bits per mux |
162 | * @bits_per_pin: number of bits per pin | |
8b8b091b | 163 | * @pins: physical pins on the SoC |
a1a277eb | 164 | * @gpiofuncs: list of gpio functions |
3e6cee17 TL |
165 | * @irqs: list of interrupt registers |
166 | * @chip: chip container for this instance | |
167 | * @domain: IRQ domain for this instance | |
8b8b091b TL |
168 | * @desc: pin controller descriptor |
169 | * @read: register read function to use | |
170 | * @write: register write function to use | |
171 | */ | |
172 | struct pcs_device { | |
173 | struct resource *res; | |
174 | void __iomem *base; | |
175 | unsigned size; | |
176 | struct device *dev; | |
4622215f | 177 | struct device_node *np; |
8b8b091b | 178 | struct pinctrl_dev *pctl; |
02e483f6 | 179 | unsigned flags; |
3e6cee17 TL |
180 | #define PCS_QUIRK_SHARED_IRQ (1 << 2) |
181 | #define PCS_FEAT_IRQ (1 << 1) | |
02e483f6 | 182 | #define PCS_FEAT_PINCONF (1 << 0) |
4622215f | 183 | struct property *missing_nr_pinctrl_cells; |
3e6cee17 TL |
184 | struct pcs_soc_data socdata; |
185 | raw_spinlock_t lock; | |
8b8b091b TL |
186 | struct mutex mutex; |
187 | unsigned width; | |
188 | unsigned fmask; | |
189 | unsigned fshift; | |
190 | unsigned foff; | |
191 | unsigned fmax; | |
9e605cb6 | 192 | bool bits_per_mux; |
4e7e8017 | 193 | unsigned bits_per_pin; |
8b8b091b | 194 | struct pcs_data pins; |
a1a277eb | 195 | struct list_head gpiofuncs; |
3e6cee17 TL |
196 | struct list_head irqs; |
197 | struct irq_chip chip; | |
198 | struct irq_domain *domain; | |
8b8b091b TL |
199 | struct pinctrl_desc desc; |
200 | unsigned (*read)(void __iomem *reg); | |
201 | void (*write)(unsigned val, void __iomem *reg); | |
202 | }; | |
203 | ||
3e6cee17 TL |
204 | #define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ) |
205 | #define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ) | |
02e483f6 TL |
206 | #define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF) |
207 | ||
9dddb4df HZ |
208 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, |
209 | unsigned long *config); | |
210 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, | |
03b054e9 | 211 | unsigned long *configs, unsigned num_configs); |
9dddb4df HZ |
212 | |
213 | static enum pin_config_param pcs_bias[] = { | |
214 | PIN_CONFIG_BIAS_PULL_DOWN, | |
215 | PIN_CONFIG_BIAS_PULL_UP, | |
216 | }; | |
217 | ||
3c177a16 SH |
218 | /* |
219 | * This lock class tells lockdep that irqchip core that this single | |
220 | * pinctrl can be in a different category than its parents, so it won't | |
221 | * report false recursion. | |
222 | */ | |
223 | static struct lock_class_key pcs_lock_class; | |
224 | ||
8b8b091b TL |
225 | /* |
226 | * REVISIT: Reads and writes could eventually use regmap or something | |
227 | * generic. But at least on omaps, some mux registers are performance | |
228 | * critical as they may need to be remuxed every time before and after | |
229 | * idle. Adding tests for register access width for every read and | |
230 | * write like regmap is doing is not desired, and caching the registers | |
231 | * does not help in this case. | |
232 | */ | |
233 | ||
234 | static unsigned __maybe_unused pcs_readb(void __iomem *reg) | |
235 | { | |
236 | return readb(reg); | |
237 | } | |
238 | ||
239 | static unsigned __maybe_unused pcs_readw(void __iomem *reg) | |
240 | { | |
241 | return readw(reg); | |
242 | } | |
243 | ||
244 | static unsigned __maybe_unused pcs_readl(void __iomem *reg) | |
245 | { | |
246 | return readl(reg); | |
247 | } | |
248 | ||
249 | static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg) | |
250 | { | |
251 | writeb(val, reg); | |
252 | } | |
253 | ||
254 | static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg) | |
255 | { | |
256 | writew(val, reg); | |
257 | } | |
258 | ||
259 | static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg) | |
260 | { | |
261 | writel(val, reg); | |
262 | } | |
263 | ||
8b8b091b TL |
264 | static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev, |
265 | struct seq_file *s, | |
e7ed6718 | 266 | unsigned pin) |
8b8b091b | 267 | { |
7d66ce7f | 268 | struct pcs_device *pcs; |
e7ed6718 | 269 | unsigned val, mux_bytes; |
223decc4 TL |
270 | unsigned long offset; |
271 | size_t pa; | |
7d66ce7f MP |
272 | |
273 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
274 | ||
e7ed6718 | 275 | mux_bytes = pcs->width / BITS_PER_BYTE; |
223decc4 TL |
276 | offset = pin * mux_bytes; |
277 | val = pcs->read(pcs->base + offset); | |
278 | pa = pcs->res->start + offset; | |
7d66ce7f | 279 | |
223decc4 | 280 | seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME); |
8b8b091b TL |
281 | } |
282 | ||
283 | static void pcs_dt_free_map(struct pinctrl_dev *pctldev, | |
284 | struct pinctrl_map *map, unsigned num_maps) | |
285 | { | |
286 | struct pcs_device *pcs; | |
287 | ||
288 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
289 | devm_kfree(pcs->dev, map); | |
290 | } | |
291 | ||
292 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
293 | struct device_node *np_config, | |
294 | struct pinctrl_map **map, unsigned *num_maps); | |
295 | ||
022ab148 | 296 | static const struct pinctrl_ops pcs_pinctrl_ops = { |
caeb774e TL |
297 | .get_groups_count = pinctrl_generic_get_group_count, |
298 | .get_group_name = pinctrl_generic_get_group_name, | |
299 | .get_group_pins = pinctrl_generic_get_group_pins, | |
8b8b091b TL |
300 | .pin_dbg_show = pcs_pin_dbg_show, |
301 | .dt_node_to_map = pcs_dt_node_to_map, | |
302 | .dt_free_map = pcs_dt_free_map, | |
303 | }; | |
304 | ||
9dddb4df HZ |
305 | static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin, |
306 | struct pcs_function **func) | |
307 | { | |
308 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); | |
309 | struct pin_desc *pdesc = pin_desc_get(pctldev, pin); | |
310 | const struct pinctrl_setting_mux *setting; | |
571aec4d | 311 | struct function_desc *function; |
9dddb4df HZ |
312 | unsigned fselector; |
313 | ||
314 | /* If pin is not described in DTS & enabled, mux_setting is NULL. */ | |
315 | setting = pdesc->mux_setting; | |
316 | if (!setting) | |
317 | return -ENOTSUPP; | |
318 | fselector = setting->func; | |
571aec4d TL |
319 | function = pinmux_generic_get_function(pctldev, fselector); |
320 | *func = function->data; | |
9dddb4df HZ |
321 | if (!(*func)) { |
322 | dev_err(pcs->dev, "%s could not find function%i\n", | |
323 | __func__, fselector); | |
324 | return -ENOTSUPP; | |
325 | } | |
326 | return 0; | |
327 | } | |
328 | ||
03e9f0ca | 329 | static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector, |
8b8b091b TL |
330 | unsigned group) |
331 | { | |
332 | struct pcs_device *pcs; | |
571aec4d | 333 | struct function_desc *function; |
8b8b091b TL |
334 | struct pcs_function *func; |
335 | int i; | |
336 | ||
337 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
477ac771 HZ |
338 | /* If function mask is null, needn't enable it. */ |
339 | if (!pcs->fmask) | |
340 | return 0; | |
571aec4d TL |
341 | function = pinmux_generic_get_function(pctldev, fselector); |
342 | func = function->data; | |
8b8b091b TL |
343 | if (!func) |
344 | return -EINVAL; | |
345 | ||
346 | dev_dbg(pcs->dev, "enabling %s function%i\n", | |
347 | func->name, fselector); | |
348 | ||
349 | for (i = 0; i < func->nvals; i++) { | |
350 | struct pcs_func_vals *vals; | |
3e6cee17 | 351 | unsigned long flags; |
9e605cb6 | 352 | unsigned val, mask; |
8b8b091b TL |
353 | |
354 | vals = &func->vals[i]; | |
3e6cee17 | 355 | raw_spin_lock_irqsave(&pcs->lock, flags); |
8b8b091b | 356 | val = pcs->read(vals->reg); |
4e7e8017 MP |
357 | |
358 | if (pcs->bits_per_mux) | |
359 | mask = vals->mask; | |
9e605cb6 | 360 | else |
4e7e8017 | 361 | mask = pcs->fmask; |
9e605cb6 PU |
362 | |
363 | val &= ~mask; | |
364 | val |= (vals->val & mask); | |
8b8b091b | 365 | pcs->write(val, vals->reg); |
3e6cee17 | 366 | raw_spin_unlock_irqrestore(&pcs->lock, flags); |
8b8b091b TL |
367 | } |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
8b8b091b | 372 | static int pcs_request_gpio(struct pinctrl_dev *pctldev, |
a1a277eb | 373 | struct pinctrl_gpio_range *range, unsigned pin) |
8b8b091b | 374 | { |
a1a277eb HZ |
375 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
376 | struct pcs_gpiofunc_range *frange = NULL; | |
377 | struct list_head *pos, *tmp; | |
378 | int mux_bytes = 0; | |
379 | unsigned data; | |
380 | ||
477ac771 HZ |
381 | /* If function mask is null, return directly. */ |
382 | if (!pcs->fmask) | |
383 | return -ENOTSUPP; | |
384 | ||
a1a277eb HZ |
385 | list_for_each_safe(pos, tmp, &pcs->gpiofuncs) { |
386 | frange = list_entry(pos, struct pcs_gpiofunc_range, node); | |
387 | if (pin >= frange->offset + frange->npins | |
388 | || pin < frange->offset) | |
389 | continue; | |
390 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
391 | data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask; | |
392 | data |= frange->gpiofunc; | |
393 | pcs->write(data, pcs->base + pin * mux_bytes); | |
394 | break; | |
395 | } | |
396 | return 0; | |
8b8b091b TL |
397 | } |
398 | ||
022ab148 | 399 | static const struct pinmux_ops pcs_pinmux_ops = { |
571aec4d TL |
400 | .get_functions_count = pinmux_generic_get_function_count, |
401 | .get_function_name = pinmux_generic_get_function_name, | |
402 | .get_function_groups = pinmux_generic_get_function_groups, | |
9e3a979f | 403 | .set_mux = pcs_set_mux, |
8b8b091b TL |
404 | .gpio_request_enable = pcs_request_gpio, |
405 | }; | |
406 | ||
9dddb4df HZ |
407 | /* Clear BIAS value */ |
408 | static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin) | |
409 | { | |
410 | unsigned long config; | |
411 | int i; | |
412 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
413 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
03b054e9 | 414 | pcs_pinconf_set(pctldev, pin, &config, 1); |
9dddb4df HZ |
415 | } |
416 | } | |
417 | ||
418 | /* | |
419 | * Check whether PIN_CONFIG_BIAS_DISABLE is valid. | |
420 | * It's depend on that PULL_DOWN & PULL_UP configs are all invalid. | |
421 | */ | |
422 | static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin) | |
423 | { | |
424 | unsigned long config; | |
425 | int i; | |
426 | ||
427 | for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) { | |
428 | config = pinconf_to_config_packed(pcs_bias[i], 0); | |
429 | if (!pcs_pinconf_get(pctldev, pin, &config)) | |
430 | goto out; | |
431 | } | |
432 | return true; | |
433 | out: | |
434 | return false; | |
435 | } | |
436 | ||
8b8b091b TL |
437 | static int pcs_pinconf_get(struct pinctrl_dev *pctldev, |
438 | unsigned pin, unsigned long *config) | |
439 | { | |
9dddb4df HZ |
440 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
441 | struct pcs_function *func; | |
442 | enum pin_config_param param; | |
443 | unsigned offset = 0, data = 0, i, j, ret; | |
444 | ||
445 | ret = pcs_get_function(pctldev, pin, &func); | |
446 | if (ret) | |
447 | return ret; | |
448 | ||
449 | for (i = 0; i < func->nconfs; i++) { | |
450 | param = pinconf_to_config_param(*config); | |
451 | if (param == PIN_CONFIG_BIAS_DISABLE) { | |
452 | if (pcs_pinconf_bias_disable(pctldev, pin)) { | |
453 | *config = 0; | |
454 | return 0; | |
455 | } else { | |
456 | return -ENOTSUPP; | |
457 | } | |
458 | } else if (param != func->conf[i].param) { | |
459 | continue; | |
460 | } | |
461 | ||
462 | offset = pin * (pcs->width / BITS_PER_BYTE); | |
463 | data = pcs->read(pcs->base + offset) & func->conf[i].mask; | |
464 | switch (func->conf[i].param) { | |
465 | /* 4 parameters */ | |
466 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
467 | case PIN_CONFIG_BIAS_PULL_UP: | |
468 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
469 | if ((data != func->conf[i].enable) || | |
470 | (data == func->conf[i].disable)) | |
471 | return -ENOTSUPP; | |
472 | *config = 0; | |
473 | break; | |
474 | /* 2 parameters */ | |
475 | case PIN_CONFIG_INPUT_SCHMITT: | |
476 | for (j = 0; j < func->nconfs; j++) { | |
477 | switch (func->conf[j].param) { | |
478 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
479 | if (data != func->conf[j].enable) | |
480 | return -ENOTSUPP; | |
481 | break; | |
482 | default: | |
483 | break; | |
484 | } | |
485 | } | |
486 | *config = data; | |
487 | break; | |
488 | case PIN_CONFIG_DRIVE_STRENGTH: | |
489 | case PIN_CONFIG_SLEW_RATE: | |
4bd75477 | 490 | case PIN_CONFIG_LOW_POWER_MODE: |
9dddb4df HZ |
491 | default: |
492 | *config = data; | |
493 | break; | |
494 | } | |
495 | return 0; | |
496 | } | |
8b8b091b TL |
497 | return -ENOTSUPP; |
498 | } | |
499 | ||
500 | static int pcs_pinconf_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
501 | unsigned pin, unsigned long *configs, |
502 | unsigned num_configs) | |
8b8b091b | 503 | { |
9dddb4df HZ |
504 | struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev); |
505 | struct pcs_function *func; | |
7cba5b3f | 506 | unsigned offset = 0, shift = 0, i, data, ret; |
58957d2e | 507 | u32 arg; |
03b054e9 | 508 | int j; |
9dddb4df HZ |
509 | |
510 | ret = pcs_get_function(pctldev, pin, &func); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
03b054e9 SY |
514 | for (j = 0; j < num_configs; j++) { |
515 | for (i = 0; i < func->nconfs; i++) { | |
516 | if (pinconf_to_config_param(configs[j]) | |
517 | != func->conf[i].param) | |
518 | continue; | |
519 | ||
9dddb4df HZ |
520 | offset = pin * (pcs->width / BITS_PER_BYTE); |
521 | data = pcs->read(pcs->base + offset); | |
03b054e9 | 522 | arg = pinconf_to_config_argument(configs[j]); |
9dddb4df HZ |
523 | switch (func->conf[i].param) { |
524 | /* 2 parameters */ | |
525 | case PIN_CONFIG_INPUT_SCHMITT: | |
526 | case PIN_CONFIG_DRIVE_STRENGTH: | |
527 | case PIN_CONFIG_SLEW_RATE: | |
4bd75477 | 528 | case PIN_CONFIG_LOW_POWER_MODE: |
9dddb4df | 529 | shift = ffs(func->conf[i].mask) - 1; |
9dddb4df HZ |
530 | data &= ~func->conf[i].mask; |
531 | data |= (arg << shift) & func->conf[i].mask; | |
532 | break; | |
533 | /* 4 parameters */ | |
534 | case PIN_CONFIG_BIAS_DISABLE: | |
535 | pcs_pinconf_clear_bias(pctldev, pin); | |
536 | break; | |
537 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
538 | case PIN_CONFIG_BIAS_PULL_UP: | |
7cba5b3f | 539 | if (arg) |
9dddb4df HZ |
540 | pcs_pinconf_clear_bias(pctldev, pin); |
541 | /* fall through */ | |
542 | case PIN_CONFIG_INPUT_SCHMITT_ENABLE: | |
543 | data &= ~func->conf[i].mask; | |
7cba5b3f | 544 | if (arg) |
9dddb4df HZ |
545 | data |= func->conf[i].enable; |
546 | else | |
547 | data |= func->conf[i].disable; | |
548 | break; | |
549 | default: | |
550 | return -ENOTSUPP; | |
551 | } | |
552 | pcs->write(data, pcs->base + offset); | |
03b054e9 SY |
553 | |
554 | break; | |
9dddb4df | 555 | } |
03b054e9 SY |
556 | if (i >= func->nconfs) |
557 | return -ENOTSUPP; | |
558 | } /* for each config */ | |
559 | ||
560 | return 0; | |
8b8b091b TL |
561 | } |
562 | ||
563 | static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, | |
564 | unsigned group, unsigned long *config) | |
565 | { | |
9dddb4df HZ |
566 | const unsigned *pins; |
567 | unsigned npins, old = 0; | |
568 | int i, ret; | |
569 | ||
caeb774e | 570 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
571 | if (ret) |
572 | return ret; | |
573 | for (i = 0; i < npins; i++) { | |
574 | if (pcs_pinconf_get(pctldev, pins[i], config)) | |
575 | return -ENOTSUPP; | |
576 | /* configs do not match between two pins */ | |
577 | if (i && (old != *config)) | |
578 | return -ENOTSUPP; | |
579 | old = *config; | |
580 | } | |
581 | return 0; | |
8b8b091b TL |
582 | } |
583 | ||
584 | static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, | |
03b054e9 SY |
585 | unsigned group, unsigned long *configs, |
586 | unsigned num_configs) | |
8b8b091b | 587 | { |
9dddb4df HZ |
588 | const unsigned *pins; |
589 | unsigned npins; | |
590 | int i, ret; | |
591 | ||
caeb774e | 592 | ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); |
9dddb4df HZ |
593 | if (ret) |
594 | return ret; | |
595 | for (i = 0; i < npins; i++) { | |
03b054e9 | 596 | if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs)) |
9dddb4df HZ |
597 | return -ENOTSUPP; |
598 | } | |
599 | return 0; | |
8b8b091b TL |
600 | } |
601 | ||
602 | static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
9dddb4df | 603 | struct seq_file *s, unsigned pin) |
8b8b091b TL |
604 | { |
605 | } | |
606 | ||
607 | static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | |
608 | struct seq_file *s, unsigned selector) | |
609 | { | |
610 | } | |
611 | ||
9dddb4df HZ |
612 | static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, |
613 | struct seq_file *s, | |
614 | unsigned long config) | |
615 | { | |
616 | pinconf_generic_dump_config(pctldev, s, config); | |
617 | } | |
618 | ||
022ab148 | 619 | static const struct pinconf_ops pcs_pinconf_ops = { |
8b8b091b TL |
620 | .pin_config_get = pcs_pinconf_get, |
621 | .pin_config_set = pcs_pinconf_set, | |
622 | .pin_config_group_get = pcs_pinconf_group_get, | |
623 | .pin_config_group_set = pcs_pinconf_group_set, | |
624 | .pin_config_dbg_show = pcs_pinconf_dbg_show, | |
625 | .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, | |
9dddb4df | 626 | .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show, |
a7bbdd7f | 627 | .is_generic = true, |
8b8b091b TL |
628 | }; |
629 | ||
630 | /** | |
631 | * pcs_add_pin() - add a pin to the static per controller pin array | |
632 | * @pcs: pcs driver instance | |
633 | * @offset: register offset from base | |
634 | */ | |
6f924b0b MP |
635 | static int pcs_add_pin(struct pcs_device *pcs, unsigned offset, |
636 | unsigned pin_pos) | |
8b8b091b | 637 | { |
58968625 | 638 | struct pcs_soc_data *pcs_soc = &pcs->socdata; |
8b8b091b | 639 | struct pinctrl_pin_desc *pin; |
8b8b091b TL |
640 | int i; |
641 | ||
642 | i = pcs->pins.cur; | |
643 | if (i >= pcs->desc.npins) { | |
644 | dev_err(pcs->dev, "too many pins, max %i\n", | |
645 | pcs->desc.npins); | |
646 | return -ENOMEM; | |
647 | } | |
648 | ||
58968625 TL |
649 | if (pcs_soc->irq_enable_mask) { |
650 | unsigned val; | |
651 | ||
652 | val = pcs->read(pcs->base + offset); | |
653 | if (val & pcs_soc->irq_enable_mask) { | |
654 | dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n", | |
655 | (unsigned long)pcs->res->start + offset, val); | |
656 | val &= ~pcs_soc->irq_enable_mask; | |
657 | pcs->write(val, pcs->base + offset); | |
658 | } | |
659 | } | |
660 | ||
8b8b091b | 661 | pin = &pcs->pins.pa[i]; |
8b8b091b TL |
662 | pin->number = i; |
663 | pcs->pins.cur++; | |
664 | ||
665 | return i; | |
666 | } | |
667 | ||
668 | /** | |
669 | * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver | |
670 | * @pcs: pcs driver instance | |
671 | * | |
672 | * In case of errors, resources are freed in pcs_free_resources. | |
673 | * | |
674 | * If your hardware needs holes in the address space, then just set | |
675 | * up multiple driver instances. | |
676 | */ | |
150632b0 | 677 | static int pcs_allocate_pin_table(struct pcs_device *pcs) |
8b8b091b TL |
678 | { |
679 | int mux_bytes, nr_pins, i; | |
6f924b0b | 680 | int num_pins_in_register = 0; |
8b8b091b TL |
681 | |
682 | mux_bytes = pcs->width / BITS_PER_BYTE; | |
4e7e8017 MP |
683 | |
684 | if (pcs->bits_per_mux) { | |
685 | pcs->bits_per_pin = fls(pcs->fmask); | |
686 | nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin; | |
6f924b0b | 687 | num_pins_in_register = pcs->width / pcs->bits_per_pin; |
4e7e8017 MP |
688 | } else { |
689 | nr_pins = pcs->size / mux_bytes; | |
690 | } | |
8b8b091b TL |
691 | |
692 | dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins); | |
693 | pcs->pins.pa = devm_kzalloc(pcs->dev, | |
694 | sizeof(*pcs->pins.pa) * nr_pins, | |
695 | GFP_KERNEL); | |
696 | if (!pcs->pins.pa) | |
697 | return -ENOMEM; | |
698 | ||
8b8b091b TL |
699 | pcs->desc.pins = pcs->pins.pa; |
700 | pcs->desc.npins = nr_pins; | |
701 | ||
702 | for (i = 0; i < pcs->desc.npins; i++) { | |
703 | unsigned offset; | |
704 | int res; | |
4e7e8017 | 705 | int byte_num; |
6f924b0b | 706 | int pin_pos = 0; |
8b8b091b | 707 | |
4e7e8017 MP |
708 | if (pcs->bits_per_mux) { |
709 | byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE; | |
710 | offset = (byte_num / mux_bytes) * mux_bytes; | |
6f924b0b | 711 | pin_pos = i % num_pins_in_register; |
4e7e8017 MP |
712 | } else { |
713 | offset = i * mux_bytes; | |
714 | } | |
6f924b0b | 715 | res = pcs_add_pin(pcs, offset, pin_pos); |
8b8b091b TL |
716 | if (res < 0) { |
717 | dev_err(pcs->dev, "error adding pins: %i\n", res); | |
718 | return res; | |
719 | } | |
720 | } | |
721 | ||
722 | return 0; | |
723 | } | |
724 | ||
725 | /** | |
726 | * pcs_add_function() - adds a new function to the function list | |
727 | * @pcs: pcs driver instance | |
728 | * @np: device node of the mux entry | |
729 | * @name: name of the function | |
730 | * @vals: array of mux register value pairs used by the function | |
731 | * @nvals: number of mux register value pairs | |
732 | * @pgnames: array of pingroup names for the function | |
733 | * @npgnames: number of pingroup names | |
734 | */ | |
735 | static struct pcs_function *pcs_add_function(struct pcs_device *pcs, | |
736 | struct device_node *np, | |
737 | const char *name, | |
738 | struct pcs_func_vals *vals, | |
739 | unsigned nvals, | |
740 | const char **pgnames, | |
741 | unsigned npgnames) | |
742 | { | |
743 | struct pcs_function *function; | |
571aec4d | 744 | int res; |
8b8b091b TL |
745 | |
746 | function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL); | |
747 | if (!function) | |
748 | return NULL; | |
749 | ||
8b8b091b TL |
750 | function->vals = vals; |
751 | function->nvals = nvals; | |
8b8b091b | 752 | |
571aec4d TL |
753 | res = pinmux_generic_add_function(pcs->pctl, name, |
754 | pgnames, npgnames, | |
755 | function); | |
756 | if (res) | |
757 | return NULL; | |
8b8b091b TL |
758 | |
759 | return function; | |
760 | } | |
761 | ||
8b8b091b TL |
762 | /** |
763 | * pcs_get_pin_by_offset() - get a pin index based on the register offset | |
764 | * @pcs: pcs driver instance | |
765 | * @offset: register offset from the base | |
766 | * | |
767 | * Note that this is OK as long as the pins are in a static array. | |
768 | */ | |
769 | static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset) | |
770 | { | |
771 | unsigned index; | |
772 | ||
773 | if (offset >= pcs->size) { | |
774 | dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n", | |
775 | offset, pcs->size); | |
776 | return -EINVAL; | |
777 | } | |
778 | ||
4e7e8017 MP |
779 | if (pcs->bits_per_mux) |
780 | index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin; | |
781 | else | |
782 | index = offset / (pcs->width / BITS_PER_BYTE); | |
8b8b091b TL |
783 | |
784 | return index; | |
785 | } | |
786 | ||
9dddb4df HZ |
787 | /* |
788 | * check whether data matches enable bits or disable bits | |
789 | * Return value: 1 for matching enable bits, 0 for matching disable bits, | |
790 | * and negative value for matching failure. | |
791 | */ | |
792 | static int pcs_config_match(unsigned data, unsigned enable, unsigned disable) | |
793 | { | |
794 | int ret = -EINVAL; | |
795 | ||
796 | if (data == enable) | |
797 | ret = 1; | |
798 | else if (data == disable) | |
799 | ret = 0; | |
800 | return ret; | |
801 | } | |
802 | ||
803 | static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param, | |
804 | unsigned value, unsigned enable, unsigned disable, | |
805 | unsigned mask) | |
806 | { | |
807 | (*conf)->param = param; | |
808 | (*conf)->val = value; | |
809 | (*conf)->enable = enable; | |
810 | (*conf)->disable = disable; | |
811 | (*conf)->mask = mask; | |
812 | (*conf)++; | |
813 | } | |
814 | ||
815 | static void add_setting(unsigned long **setting, enum pin_config_param param, | |
816 | unsigned arg) | |
817 | { | |
818 | **setting = pinconf_to_config_packed(param, arg); | |
819 | (*setting)++; | |
820 | } | |
821 | ||
822 | /* add pinconf setting with 2 parameters */ | |
823 | static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np, | |
824 | const char *name, enum pin_config_param param, | |
825 | struct pcs_conf_vals **conf, unsigned long **settings) | |
826 | { | |
7cba5b3f | 827 | unsigned value[2], shift; |
9dddb4df HZ |
828 | int ret; |
829 | ||
830 | ret = of_property_read_u32_array(np, name, value, 2); | |
831 | if (ret) | |
832 | return; | |
833 | /* set value & mask */ | |
834 | value[0] &= value[1]; | |
7cba5b3f | 835 | shift = ffs(value[1]) - 1; |
9dddb4df HZ |
836 | /* skip enable & disable */ |
837 | add_config(conf, param, value[0], 0, 0, value[1]); | |
7cba5b3f | 838 | add_setting(settings, param, value[0] >> shift); |
9dddb4df HZ |
839 | } |
840 | ||
841 | /* add pinconf setting with 4 parameters */ | |
842 | static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np, | |
843 | const char *name, enum pin_config_param param, | |
844 | struct pcs_conf_vals **conf, unsigned long **settings) | |
845 | { | |
846 | unsigned value[4]; | |
847 | int ret; | |
848 | ||
849 | /* value to set, enable, disable, mask */ | |
850 | ret = of_property_read_u32_array(np, name, value, 4); | |
851 | if (ret) | |
852 | return; | |
853 | if (!value[3]) { | |
854 | dev_err(pcs->dev, "mask field of the property can't be 0\n"); | |
855 | return; | |
856 | } | |
857 | value[0] &= value[3]; | |
858 | value[1] &= value[3]; | |
859 | value[2] &= value[3]; | |
860 | ret = pcs_config_match(value[0], value[1], value[2]); | |
861 | if (ret < 0) | |
862 | dev_dbg(pcs->dev, "failed to match enable or disable bits\n"); | |
863 | add_config(conf, param, value[0], value[1], value[2], value[3]); | |
864 | add_setting(settings, param, ret); | |
865 | } | |
866 | ||
867 | static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np, | |
868 | struct pcs_function *func, | |
869 | struct pinctrl_map **map) | |
870 | ||
871 | { | |
872 | struct pinctrl_map *m = *map; | |
873 | int i = 0, nconfs = 0; | |
874 | unsigned long *settings = NULL, *s = NULL; | |
875 | struct pcs_conf_vals *conf = NULL; | |
876 | struct pcs_conf_type prop2[] = { | |
877 | { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, }, | |
878 | { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, }, | |
879 | { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, }, | |
4bd75477 | 880 | { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, }, |
9dddb4df HZ |
881 | }; |
882 | struct pcs_conf_type prop4[] = { | |
883 | { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, }, | |
884 | { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, }, | |
885 | { "pinctrl-single,input-schmitt-enable", | |
886 | PIN_CONFIG_INPUT_SCHMITT_ENABLE, }, | |
887 | }; | |
888 | ||
889 | /* If pinconf isn't supported, don't parse properties in below. */ | |
02e483f6 | 890 | if (!PCS_HAS_PINCONF) |
9dddb4df HZ |
891 | return 0; |
892 | ||
893 | /* cacluate how much properties are supported in current node */ | |
894 | for (i = 0; i < ARRAY_SIZE(prop2); i++) { | |
895 | if (of_find_property(np, prop2[i].name, NULL)) | |
896 | nconfs++; | |
897 | } | |
898 | for (i = 0; i < ARRAY_SIZE(prop4); i++) { | |
899 | if (of_find_property(np, prop4[i].name, NULL)) | |
900 | nconfs++; | |
901 | } | |
902 | if (!nconfs) | |
903 | return 0; | |
904 | ||
905 | func->conf = devm_kzalloc(pcs->dev, | |
906 | sizeof(struct pcs_conf_vals) * nconfs, | |
907 | GFP_KERNEL); | |
908 | if (!func->conf) | |
909 | return -ENOMEM; | |
910 | func->nconfs = nconfs; | |
911 | conf = &(func->conf[0]); | |
912 | m++; | |
913 | settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs, | |
914 | GFP_KERNEL); | |
915 | if (!settings) | |
916 | return -ENOMEM; | |
917 | s = &settings[0]; | |
918 | ||
919 | for (i = 0; i < ARRAY_SIZE(prop2); i++) | |
920 | pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param, | |
921 | &conf, &s); | |
922 | for (i = 0; i < ARRAY_SIZE(prop4); i++) | |
923 | pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param, | |
924 | &conf, &s); | |
925 | m->type = PIN_MAP_TYPE_CONFIGS_GROUP; | |
926 | m->data.configs.group_or_pin = np->name; | |
927 | m->data.configs.configs = settings; | |
928 | m->data.configs.num_configs = nconfs; | |
929 | return 0; | |
930 | } | |
931 | ||
8b8b091b TL |
932 | /** |
933 | * smux_parse_one_pinctrl_entry() - parses a device tree mux entry | |
caeb774e | 934 | * @pctldev: pin controller device |
8b8b091b TL |
935 | * @pcs: pinctrl driver instance |
936 | * @np: device node of the mux entry | |
937 | * @map: map entry | |
9dddb4df | 938 | * @num_maps: number of map |
8b8b091b TL |
939 | * @pgnames: pingroup names |
940 | * | |
941 | * Note that this binding currently supports only sets of one register + value. | |
942 | * | |
943 | * Also note that this driver tries to avoid understanding pin and function | |
944 | * names because of the extra bloat they would cause especially in the case of | |
945 | * a large number of pins. This driver just sets what is specified for the board | |
946 | * in the .dts file. Further user space debugging tools can be developed to | |
947 | * decipher the pin and function names using debugfs. | |
948 | * | |
949 | * If you are concerned about the boot time, set up the static pins in | |
950 | * the bootloader, and only set up selected pins as device tree entries. | |
951 | */ | |
952 | static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, | |
953 | struct device_node *np, | |
954 | struct pinctrl_map **map, | |
9dddb4df | 955 | unsigned *num_maps, |
8b8b091b TL |
956 | const char **pgnames) |
957 | { | |
4622215f | 958 | const char *name = "pinctrl-single,pins"; |
8b8b091b | 959 | struct pcs_func_vals *vals; |
4622215f | 960 | int rows, *pins, found = 0, res = -ENOMEM, i; |
8b8b091b TL |
961 | struct pcs_function *function; |
962 | ||
4622215f | 963 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc | 964 | if (rows <= 0) { |
059a6e63 | 965 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); |
de7416bc AH |
966 | return -EINVAL; |
967 | } | |
8b8b091b TL |
968 | |
969 | vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL); | |
970 | if (!vals) | |
971 | return -ENOMEM; | |
972 | ||
973 | pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL); | |
974 | if (!pins) | |
975 | goto free_vals; | |
976 | ||
4622215f TL |
977 | for (i = 0; i < rows; i++) { |
978 | struct of_phandle_args pinctrl_spec; | |
979 | unsigned int offset; | |
8b8b091b TL |
980 | int pin; |
981 | ||
4622215f TL |
982 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
983 | if (res) | |
984 | return res; | |
985 | ||
986 | if (pinctrl_spec.args_count < 2) { | |
987 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", | |
988 | pinctrl_spec.args_count); | |
989 | break; | |
990 | } | |
991 | ||
992 | /* Index plus one value cell */ | |
993 | offset = pinctrl_spec.args[0]; | |
8b8b091b | 994 | vals[found].reg = pcs->base + offset; |
4622215f TL |
995 | vals[found].val = pinctrl_spec.args[1]; |
996 | ||
997 | dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n", | |
998 | pinctrl_spec.np->name, offset, pinctrl_spec.args[1]); | |
8b8b091b TL |
999 | |
1000 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1001 | if (pin < 0) { | |
1002 | dev_err(pcs->dev, | |
1003 | "could not add functions for %s %ux\n", | |
1004 | np->name, offset); | |
1005 | break; | |
1006 | } | |
1007 | pins[found++] = pin; | |
1008 | } | |
1009 | ||
1010 | pgnames[0] = np->name; | |
1011 | function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); | |
712778d0 DC |
1012 | if (!function) { |
1013 | res = -ENOMEM; | |
8b8b091b | 1014 | goto free_pins; |
712778d0 | 1015 | } |
8b8b091b | 1016 | |
caeb774e | 1017 | res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
8b8b091b TL |
1018 | if (res < 0) |
1019 | goto free_function; | |
1020 | ||
1021 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1022 | (*map)->data.mux.group = np->name; | |
1023 | (*map)->data.mux.function = np->name; | |
1024 | ||
02e483f6 | 1025 | if (PCS_HAS_PINCONF) { |
18442e65 WY |
1026 | res = pcs_parse_pinconf(pcs, np, function, map); |
1027 | if (res) | |
9dddb4df HZ |
1028 | goto free_pingroups; |
1029 | *num_maps = 2; | |
1030 | } else { | |
1031 | *num_maps = 1; | |
1032 | } | |
8b8b091b TL |
1033 | return 0; |
1034 | ||
9dddb4df | 1035 | free_pingroups: |
caeb774e | 1036 | pinctrl_generic_remove_last_group(pcs->pctl); |
9dddb4df | 1037 | *num_maps = 1; |
8b8b091b | 1038 | free_function: |
571aec4d | 1039 | pinmux_generic_remove_last_function(pcs->pctl); |
8b8b091b TL |
1040 | |
1041 | free_pins: | |
1042 | devm_kfree(pcs->dev, pins); | |
1043 | ||
4e7e8017 MP |
1044 | free_vals: |
1045 | devm_kfree(pcs->dev, vals); | |
1046 | ||
1047 | return res; | |
1048 | } | |
1049 | ||
4e7e8017 MP |
1050 | static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs, |
1051 | struct device_node *np, | |
1052 | struct pinctrl_map **map, | |
1053 | unsigned *num_maps, | |
1054 | const char **pgnames) | |
1055 | { | |
dd68a526 | 1056 | const char *name = "pinctrl-single,bits"; |
4e7e8017 | 1057 | struct pcs_func_vals *vals; |
22d5127e | 1058 | int rows, *pins, found = 0, res = -ENOMEM, i; |
4e7e8017 MP |
1059 | int npins_in_row; |
1060 | struct pcs_function *function; | |
1061 | ||
22d5127e | 1062 | rows = pinctrl_count_index_with_args(np, name); |
de7416bc AH |
1063 | if (rows <= 0) { |
1064 | dev_err(pcs->dev, "Invalid number of rows: %d\n", rows); | |
1065 | return -EINVAL; | |
1066 | } | |
4e7e8017 | 1067 | |
4e7e8017 MP |
1068 | npins_in_row = pcs->width / pcs->bits_per_pin; |
1069 | ||
1070 | vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row, | |
1071 | GFP_KERNEL); | |
1072 | if (!vals) | |
1073 | return -ENOMEM; | |
1074 | ||
1075 | pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row, | |
1076 | GFP_KERNEL); | |
1077 | if (!pins) | |
1078 | goto free_vals; | |
1079 | ||
22d5127e TL |
1080 | for (i = 0; i < rows; i++) { |
1081 | struct of_phandle_args pinctrl_spec; | |
4e7e8017 MP |
1082 | unsigned offset, val; |
1083 | unsigned mask, bit_pos, val_pos, mask_pos, submask; | |
1084 | unsigned pin_num_from_lsb; | |
1085 | int pin; | |
1086 | ||
22d5127e TL |
1087 | res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec); |
1088 | if (res) | |
1089 | return res; | |
1090 | ||
1091 | if (pinctrl_spec.args_count < 3) { | |
1092 | dev_err(pcs->dev, "invalid args_count for spec: %i\n", | |
1093 | pinctrl_spec.args_count); | |
1094 | break; | |
1095 | } | |
1096 | ||
1097 | /* Index plus two value cells */ | |
1098 | offset = pinctrl_spec.args[0]; | |
1099 | val = pinctrl_spec.args[1]; | |
1100 | mask = pinctrl_spec.args[2]; | |
1101 | ||
1102 | dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n", | |
1103 | pinctrl_spec.np->name, offset, val, mask); | |
4e7e8017 MP |
1104 | |
1105 | /* Parse pins in each row from LSB */ | |
1106 | while (mask) { | |
56b367c0 | 1107 | bit_pos = __ffs(mask); |
4e7e8017 | 1108 | pin_num_from_lsb = bit_pos / pcs->bits_per_pin; |
56b367c0 | 1109 | mask_pos = ((pcs->fmask) << bit_pos); |
4e7e8017 MP |
1110 | val_pos = val & mask_pos; |
1111 | submask = mask & mask_pos; | |
ad5d25fe TV |
1112 | |
1113 | if ((mask & mask_pos) == 0) { | |
1114 | dev_err(pcs->dev, | |
1115 | "Invalid mask for %s at 0x%x\n", | |
1116 | np->name, offset); | |
1117 | break; | |
1118 | } | |
1119 | ||
4e7e8017 MP |
1120 | mask &= ~mask_pos; |
1121 | ||
1122 | if (submask != mask_pos) { | |
1123 | dev_warn(pcs->dev, | |
1124 | "Invalid submask 0x%x for %s at 0x%x\n", | |
1125 | submask, np->name, offset); | |
1126 | continue; | |
1127 | } | |
1128 | ||
1129 | vals[found].mask = submask; | |
1130 | vals[found].reg = pcs->base + offset; | |
1131 | vals[found].val = val_pos; | |
1132 | ||
1133 | pin = pcs_get_pin_by_offset(pcs, offset); | |
1134 | if (pin < 0) { | |
1135 | dev_err(pcs->dev, | |
1136 | "could not add functions for %s %ux\n", | |
1137 | np->name, offset); | |
1138 | break; | |
1139 | } | |
1140 | pins[found++] = pin + pin_num_from_lsb; | |
1141 | } | |
1142 | } | |
1143 | ||
1144 | pgnames[0] = np->name; | |
1145 | function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1); | |
712778d0 DC |
1146 | if (!function) { |
1147 | res = -ENOMEM; | |
4e7e8017 | 1148 | goto free_pins; |
712778d0 | 1149 | } |
4e7e8017 | 1150 | |
caeb774e | 1151 | res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs); |
4e7e8017 MP |
1152 | if (res < 0) |
1153 | goto free_function; | |
1154 | ||
1155 | (*map)->type = PIN_MAP_TYPE_MUX_GROUP; | |
1156 | (*map)->data.mux.group = np->name; | |
1157 | (*map)->data.mux.function = np->name; | |
1158 | ||
02e483f6 | 1159 | if (PCS_HAS_PINCONF) { |
4e7e8017 MP |
1160 | dev_err(pcs->dev, "pinconf not supported\n"); |
1161 | goto free_pingroups; | |
1162 | } | |
1163 | ||
1164 | *num_maps = 1; | |
1165 | return 0; | |
1166 | ||
1167 | free_pingroups: | |
caeb774e | 1168 | pinctrl_generic_remove_last_group(pcs->pctl); |
4e7e8017 MP |
1169 | *num_maps = 1; |
1170 | free_function: | |
571aec4d | 1171 | pinmux_generic_remove_last_function(pcs->pctl); |
4e7e8017 MP |
1172 | free_pins: |
1173 | devm_kfree(pcs->dev, pins); | |
1174 | ||
8b8b091b TL |
1175 | free_vals: |
1176 | devm_kfree(pcs->dev, vals); | |
1177 | ||
1178 | return res; | |
1179 | } | |
1180 | /** | |
1181 | * pcs_dt_node_to_map() - allocates and parses pinctrl maps | |
1182 | * @pctldev: pinctrl instance | |
1183 | * @np_config: device tree pinmux entry | |
1184 | * @map: array of map entries | |
1185 | * @num_maps: number of maps | |
1186 | */ | |
1187 | static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev, | |
1188 | struct device_node *np_config, | |
1189 | struct pinctrl_map **map, unsigned *num_maps) | |
1190 | { | |
1191 | struct pcs_device *pcs; | |
1192 | const char **pgnames; | |
1193 | int ret; | |
1194 | ||
1195 | pcs = pinctrl_dev_get_drvdata(pctldev); | |
1196 | ||
9dddb4df HZ |
1197 | /* create 2 maps. One is for pinmux, and the other is for pinconf. */ |
1198 | *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL); | |
00e79d12 | 1199 | if (!*map) |
8b8b091b TL |
1200 | return -ENOMEM; |
1201 | ||
1202 | *num_maps = 0; | |
1203 | ||
1204 | pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL); | |
1205 | if (!pgnames) { | |
1206 | ret = -ENOMEM; | |
1207 | goto free_map; | |
1208 | } | |
1209 | ||
4e7e8017 MP |
1210 | if (pcs->bits_per_mux) { |
1211 | ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map, | |
1212 | num_maps, pgnames); | |
1213 | if (ret < 0) { | |
1214 | dev_err(pcs->dev, "no pins entries for %s\n", | |
1215 | np_config->name); | |
1216 | goto free_pgnames; | |
1217 | } | |
1218 | } else { | |
1219 | ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, | |
1220 | num_maps, pgnames); | |
1221 | if (ret < 0) { | |
1222 | dev_err(pcs->dev, "no pins entries for %s\n", | |
1223 | np_config->name); | |
1224 | goto free_pgnames; | |
1225 | } | |
8b8b091b | 1226 | } |
8b8b091b TL |
1227 | |
1228 | return 0; | |
1229 | ||
1230 | free_pgnames: | |
1231 | devm_kfree(pcs->dev, pgnames); | |
1232 | free_map: | |
1233 | devm_kfree(pcs->dev, *map); | |
1234 | ||
1235 | return ret; | |
1236 | } | |
1237 | ||
3e6cee17 TL |
1238 | /** |
1239 | * pcs_irq_free() - free interrupt | |
1240 | * @pcs: pcs driver instance | |
1241 | */ | |
1242 | static void pcs_irq_free(struct pcs_device *pcs) | |
1243 | { | |
1244 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1245 | ||
1246 | if (pcs_soc->irq < 0) | |
1247 | return; | |
1248 | ||
1249 | if (pcs->domain) | |
1250 | irq_domain_remove(pcs->domain); | |
1251 | ||
1252 | if (PCS_QUIRK_HAS_SHARED_IRQ) | |
1253 | free_irq(pcs_soc->irq, pcs_soc); | |
1254 | else | |
1255 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1256 | } | |
1257 | ||
8b8b091b TL |
1258 | /** |
1259 | * pcs_free_resources() - free memory used by this driver | |
1260 | * @pcs: pcs driver instance | |
1261 | */ | |
1262 | static void pcs_free_resources(struct pcs_device *pcs) | |
1263 | { | |
3e6cee17 | 1264 | pcs_irq_free(pcs); |
f10a2585 | 1265 | pinctrl_unregister(pcs->pctl); |
caeb774e | 1266 | |
4622215f TL |
1267 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) |
1268 | if (pcs->missing_nr_pinctrl_cells) | |
1269 | of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells); | |
1270 | #endif | |
8b8b091b TL |
1271 | } |
1272 | ||
baa9946e | 1273 | static const struct of_device_id pcs_of_match[]; |
8b8b091b | 1274 | |
a1a277eb HZ |
1275 | static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs) |
1276 | { | |
1277 | const char *propname = "pinctrl-single,gpio-range"; | |
1278 | const char *cellname = "#pinctrl-single,gpio-range-cells"; | |
1279 | struct of_phandle_args gpiospec; | |
1280 | struct pcs_gpiofunc_range *range; | |
1281 | int ret, i; | |
1282 | ||
1283 | for (i = 0; ; i++) { | |
1284 | ret = of_parse_phandle_with_args(node, propname, cellname, | |
1285 | i, &gpiospec); | |
1286 | /* Do not treat it as error. Only treat it as end condition. */ | |
1287 | if (ret) { | |
1288 | ret = 0; | |
1289 | break; | |
1290 | } | |
1291 | range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL); | |
1292 | if (!range) { | |
1293 | ret = -ENOMEM; | |
1294 | break; | |
1295 | } | |
1296 | range->offset = gpiospec.args[0]; | |
1297 | range->npins = gpiospec.args[1]; | |
1298 | range->gpiofunc = gpiospec.args[2]; | |
1299 | mutex_lock(&pcs->mutex); | |
1300 | list_add_tail(&range->node, &pcs->gpiofuncs); | |
1301 | mutex_unlock(&pcs->mutex); | |
1302 | } | |
1303 | return ret; | |
1304 | } | |
3e6cee17 TL |
1305 | /** |
1306 | * @reg: virtual address of interrupt register | |
1307 | * @hwirq: hardware irq number | |
1308 | * @irq: virtual irq number | |
1309 | * @node: list node | |
1310 | */ | |
1311 | struct pcs_interrupt { | |
1312 | void __iomem *reg; | |
1313 | irq_hw_number_t hwirq; | |
1314 | unsigned int irq; | |
1315 | struct list_head node; | |
1316 | }; | |
1317 | ||
1318 | /** | |
1319 | * pcs_irq_set() - enables or disables an interrupt | |
1320 | * | |
1321 | * Note that this currently assumes one interrupt per pinctrl | |
1322 | * register that is typically used for wake-up events. | |
1323 | */ | |
1324 | static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc, | |
1325 | int irq, const bool enable) | |
1326 | { | |
1327 | struct pcs_device *pcs; | |
1328 | struct list_head *pos; | |
1329 | unsigned mask; | |
1330 | ||
1331 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1332 | list_for_each(pos, &pcs->irqs) { | |
1333 | struct pcs_interrupt *pcswi; | |
1334 | unsigned soc_mask; | |
1335 | ||
1336 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1337 | if (irq != pcswi->irq) | |
1338 | continue; | |
1339 | ||
1340 | soc_mask = pcs_soc->irq_enable_mask; | |
1341 | raw_spin_lock(&pcs->lock); | |
1342 | mask = pcs->read(pcswi->reg); | |
1343 | if (enable) | |
1344 | mask |= soc_mask; | |
1345 | else | |
1346 | mask &= ~soc_mask; | |
1347 | pcs->write(mask, pcswi->reg); | |
0ac3c0a4 TL |
1348 | |
1349 | /* flush posted write */ | |
1350 | mask = pcs->read(pcswi->reg); | |
3e6cee17 TL |
1351 | raw_spin_unlock(&pcs->lock); |
1352 | } | |
c9b3a7d2 RQ |
1353 | |
1354 | if (pcs_soc->rearm) | |
1355 | pcs_soc->rearm(); | |
3e6cee17 TL |
1356 | } |
1357 | ||
1358 | /** | |
1359 | * pcs_irq_mask() - mask pinctrl interrupt | |
1360 | * @d: interrupt data | |
1361 | */ | |
1362 | static void pcs_irq_mask(struct irq_data *d) | |
1363 | { | |
1364 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1365 | ||
1366 | pcs_irq_set(pcs_soc, d->irq, false); | |
1367 | } | |
1368 | ||
1369 | /** | |
1370 | * pcs_irq_unmask() - unmask pinctrl interrupt | |
1371 | * @d: interrupt data | |
1372 | */ | |
1373 | static void pcs_irq_unmask(struct irq_data *d) | |
1374 | { | |
1375 | struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d); | |
1376 | ||
1377 | pcs_irq_set(pcs_soc, d->irq, true); | |
1378 | } | |
1379 | ||
1380 | /** | |
1381 | * pcs_irq_set_wake() - toggle the suspend and resume wake up | |
1382 | * @d: interrupt data | |
1383 | * @state: wake-up state | |
1384 | * | |
1385 | * Note that this should be called only for suspend and resume. | |
1386 | * For runtime PM, the wake-up events should be enabled by default. | |
1387 | */ | |
1388 | static int pcs_irq_set_wake(struct irq_data *d, unsigned int state) | |
1389 | { | |
1390 | if (state) | |
1391 | pcs_irq_unmask(d); | |
1392 | else | |
1393 | pcs_irq_mask(d); | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | /** | |
1399 | * pcs_irq_handle() - common interrupt handler | |
1400 | * @pcs_irq: interrupt data | |
1401 | * | |
1402 | * Note that this currently assumes we have one interrupt bit per | |
1403 | * mux register. This interrupt is typically used for wake-up events. | |
1404 | * For more complex interrupts different handlers can be specified. | |
1405 | */ | |
1406 | static int pcs_irq_handle(struct pcs_soc_data *pcs_soc) | |
1407 | { | |
1408 | struct pcs_device *pcs; | |
1409 | struct list_head *pos; | |
1410 | int count = 0; | |
1411 | ||
1412 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1413 | list_for_each(pos, &pcs->irqs) { | |
1414 | struct pcs_interrupt *pcswi; | |
1415 | unsigned mask; | |
1416 | ||
1417 | pcswi = list_entry(pos, struct pcs_interrupt, node); | |
1418 | raw_spin_lock(&pcs->lock); | |
1419 | mask = pcs->read(pcswi->reg); | |
1420 | raw_spin_unlock(&pcs->lock); | |
1421 | if (mask & pcs_soc->irq_status_mask) { | |
1422 | generic_handle_irq(irq_find_mapping(pcs->domain, | |
1423 | pcswi->hwirq)); | |
1424 | count++; | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | return count; | |
1429 | } | |
1430 | ||
1431 | /** | |
1432 | * pcs_irq_handler() - handler for the shared interrupt case | |
1433 | * @irq: interrupt | |
1434 | * @d: data | |
1435 | * | |
1436 | * Use this for cases where multiple instances of | |
1437 | * pinctrl-single share a single interrupt like on omaps. | |
1438 | */ | |
1439 | static irqreturn_t pcs_irq_handler(int irq, void *d) | |
1440 | { | |
1441 | struct pcs_soc_data *pcs_soc = d; | |
1442 | ||
1443 | return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE; | |
1444 | } | |
1445 | ||
1446 | /** | |
1447 | * pcs_irq_handle() - handler for the dedicated chained interrupt case | |
1448 | * @irq: interrupt | |
1449 | * @desc: interrupt descriptor | |
1450 | * | |
1451 | * Use this if you have a separate interrupt for each | |
1452 | * pinctrl-single instance. | |
1453 | */ | |
bd0b9ac4 | 1454 | static void pcs_irq_chain_handler(struct irq_desc *desc) |
3e6cee17 TL |
1455 | { |
1456 | struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc); | |
1457 | struct irq_chip *chip; | |
3e6cee17 | 1458 | |
5663bb27 | 1459 | chip = irq_desc_get_chip(desc); |
3e6cee17 | 1460 | chained_irq_enter(chip, desc); |
849bfe06 | 1461 | pcs_irq_handle(pcs_soc); |
3e6cee17 TL |
1462 | /* REVISIT: export and add handle_bad_irq(irq, desc)? */ |
1463 | chained_irq_exit(chip, desc); | |
1464 | ||
1465 | return; | |
1466 | } | |
1467 | ||
1468 | static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq, | |
1469 | irq_hw_number_t hwirq) | |
1470 | { | |
1471 | struct pcs_soc_data *pcs_soc = d->host_data; | |
1472 | struct pcs_device *pcs; | |
1473 | struct pcs_interrupt *pcswi; | |
1474 | ||
1475 | pcs = container_of(pcs_soc, struct pcs_device, socdata); | |
1476 | pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL); | |
1477 | if (!pcswi) | |
1478 | return -ENOMEM; | |
1479 | ||
1480 | pcswi->reg = pcs->base + hwirq; | |
1481 | pcswi->hwirq = hwirq; | |
1482 | pcswi->irq = irq; | |
1483 | ||
1484 | mutex_lock(&pcs->mutex); | |
1485 | list_add_tail(&pcswi->node, &pcs->irqs); | |
1486 | mutex_unlock(&pcs->mutex); | |
1487 | ||
1488 | irq_set_chip_data(irq, pcs_soc); | |
1489 | irq_set_chip_and_handler(irq, &pcs->chip, | |
1490 | handle_level_irq); | |
3c177a16 | 1491 | irq_set_lockdep_class(irq, &pcs_lock_class); |
1b9c0fb3 | 1492 | irq_set_noprobe(irq); |
3e6cee17 TL |
1493 | |
1494 | return 0; | |
1495 | } | |
1496 | ||
e5b60953 | 1497 | static const struct irq_domain_ops pcs_irqdomain_ops = { |
3e6cee17 TL |
1498 | .map = pcs_irqdomain_map, |
1499 | .xlate = irq_domain_xlate_onecell, | |
1500 | }; | |
1501 | ||
1502 | /** | |
1503 | * pcs_irq_init_chained_handler() - set up a chained interrupt handler | |
1504 | * @pcs: pcs driver instance | |
1505 | * @np: device node pointer | |
1506 | */ | |
1507 | static int pcs_irq_init_chained_handler(struct pcs_device *pcs, | |
1508 | struct device_node *np) | |
1509 | { | |
1510 | struct pcs_soc_data *pcs_soc = &pcs->socdata; | |
1511 | const char *name = "pinctrl"; | |
1512 | int num_irqs; | |
1513 | ||
1514 | if (!pcs_soc->irq_enable_mask || | |
1515 | !pcs_soc->irq_status_mask) { | |
1516 | pcs_soc->irq = -1; | |
1517 | return -EINVAL; | |
1518 | } | |
1519 | ||
1520 | INIT_LIST_HEAD(&pcs->irqs); | |
1521 | pcs->chip.name = name; | |
1522 | pcs->chip.irq_ack = pcs_irq_mask; | |
1523 | pcs->chip.irq_mask = pcs_irq_mask; | |
1524 | pcs->chip.irq_unmask = pcs_irq_unmask; | |
1525 | pcs->chip.irq_set_wake = pcs_irq_set_wake; | |
1526 | ||
1527 | if (PCS_QUIRK_HAS_SHARED_IRQ) { | |
1528 | int res; | |
1529 | ||
1530 | res = request_irq(pcs_soc->irq, pcs_irq_handler, | |
c10372e6 GS |
1531 | IRQF_SHARED | IRQF_NO_SUSPEND | |
1532 | IRQF_NO_THREAD, | |
3e6cee17 TL |
1533 | name, pcs_soc); |
1534 | if (res) { | |
1535 | pcs_soc->irq = -1; | |
1536 | return res; | |
1537 | } | |
1538 | } else { | |
20d5d142 TG |
1539 | irq_set_chained_handler_and_data(pcs_soc->irq, |
1540 | pcs_irq_chain_handler, | |
1541 | pcs_soc); | |
3e6cee17 TL |
1542 | } |
1543 | ||
1544 | /* | |
1545 | * We can use the register offset as the hardirq | |
1546 | * number as irq_domain_add_simple maps them lazily. | |
1547 | * This way we can easily support more than one | |
1548 | * interrupt per function if needed. | |
1549 | */ | |
1550 | num_irqs = pcs->size; | |
1551 | ||
1552 | pcs->domain = irq_domain_add_simple(np, num_irqs, 0, | |
1553 | &pcs_irqdomain_ops, | |
1554 | pcs_soc); | |
1555 | if (!pcs->domain) { | |
1556 | irq_set_chained_handler(pcs_soc->irq, NULL); | |
1557 | return -EINVAL; | |
1558 | } | |
1559 | ||
1560 | return 0; | |
1561 | } | |
a1a277eb | 1562 | |
8cb440ab | 1563 | #ifdef CONFIG_PM |
0f9bc4bc HG |
1564 | static int pinctrl_single_suspend(struct platform_device *pdev, |
1565 | pm_message_t state) | |
1566 | { | |
1567 | struct pcs_device *pcs; | |
1568 | ||
1569 | pcs = platform_get_drvdata(pdev); | |
1570 | if (!pcs) | |
1571 | return -EINVAL; | |
1572 | ||
1573 | return pinctrl_force_sleep(pcs->pctl); | |
1574 | } | |
1575 | ||
1576 | static int pinctrl_single_resume(struct platform_device *pdev) | |
1577 | { | |
1578 | struct pcs_device *pcs; | |
1579 | ||
1580 | pcs = platform_get_drvdata(pdev); | |
1581 | if (!pcs) | |
1582 | return -EINVAL; | |
1583 | ||
1584 | return pinctrl_force_default(pcs->pctl); | |
1585 | } | |
8cb440ab | 1586 | #endif |
0f9bc4bc | 1587 | |
4622215f TL |
1588 | /** |
1589 | * pcs_quirk_missing_pinctrl_cells - handle legacy binding | |
1590 | * @pcs: pinctrl driver instance | |
1591 | * @np: device tree node | |
1592 | * @cells: number of cells | |
1593 | * | |
1594 | * Handle legacy binding with no #pinctrl-cells. This should be | |
1595 | * always two pinctrl-single,bit-per-mux and one for others. | |
1596 | * At some point we may want to consider removing this. | |
1597 | */ | |
1598 | static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs, | |
1599 | struct device_node *np, | |
1600 | int cells) | |
1601 | { | |
1602 | struct property *p; | |
1603 | const char *name = "#pinctrl-cells"; | |
1604 | int error; | |
1605 | u32 val; | |
1606 | ||
1607 | error = of_property_read_u32(np, name, &val); | |
1608 | if (!error) | |
1609 | return 0; | |
1610 | ||
1611 | dev_warn(pcs->dev, "please update dts to use %s = <%i>\n", | |
1612 | name, cells); | |
1613 | ||
1614 | p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL); | |
1615 | if (!p) | |
1616 | return -ENOMEM; | |
1617 | ||
1618 | p->length = sizeof(__be32); | |
1619 | p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL); | |
1620 | if (!p->value) | |
1621 | return -ENOMEM; | |
1622 | *(__be32 *)p->value = cpu_to_be32(cells); | |
1623 | ||
1624 | p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL); | |
1625 | if (!p->name) | |
1626 | return -ENOMEM; | |
1627 | ||
1628 | pcs->missing_nr_pinctrl_cells = p; | |
1629 | ||
1630 | #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE) | |
1631 | error = of_add_property(np, pcs->missing_nr_pinctrl_cells); | |
1632 | #endif | |
1633 | ||
1634 | return error; | |
1635 | } | |
1636 | ||
150632b0 | 1637 | static int pcs_probe(struct platform_device *pdev) |
8b8b091b TL |
1638 | { |
1639 | struct device_node *np = pdev->dev.of_node; | |
1640 | const struct of_device_id *match; | |
dc7743aa | 1641 | struct pcs_pdata *pdata; |
8b8b091b TL |
1642 | struct resource *res; |
1643 | struct pcs_device *pcs; | |
02e483f6 | 1644 | const struct pcs_soc_data *soc; |
8b8b091b TL |
1645 | int ret; |
1646 | ||
1647 | match = of_match_device(pcs_of_match, &pdev->dev); | |
1648 | if (!match) | |
1649 | return -EINVAL; | |
1650 | ||
1651 | pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL); | |
1652 | if (!pcs) { | |
1653 | dev_err(&pdev->dev, "could not allocate\n"); | |
1654 | return -ENOMEM; | |
1655 | } | |
1656 | pcs->dev = &pdev->dev; | |
4622215f | 1657 | pcs->np = np; |
3e6cee17 | 1658 | raw_spin_lock_init(&pcs->lock); |
8b8b091b | 1659 | mutex_init(&pcs->mutex); |
a1a277eb | 1660 | INIT_LIST_HEAD(&pcs->gpiofuncs); |
02e483f6 TL |
1661 | soc = match->data; |
1662 | pcs->flags = soc->flags; | |
3e6cee17 | 1663 | memcpy(&pcs->socdata, soc, sizeof(*soc)); |
8b8b091b | 1664 | |
cd23604a TL |
1665 | ret = of_property_read_u32(np, "pinctrl-single,register-width", |
1666 | &pcs->width); | |
1667 | if (ret) { | |
1668 | dev_err(pcs->dev, "register width not specified\n"); | |
1669 | ||
1670 | return ret; | |
1671 | } | |
8b8b091b | 1672 | |
477ac771 HZ |
1673 | ret = of_property_read_u32(np, "pinctrl-single,function-mask", |
1674 | &pcs->fmask); | |
1675 | if (!ret) { | |
56b367c0 | 1676 | pcs->fshift = __ffs(pcs->fmask); |
477ac771 HZ |
1677 | pcs->fmax = pcs->fmask >> pcs->fshift; |
1678 | } else { | |
1679 | /* If mask property doesn't exist, function mux is invalid. */ | |
1680 | pcs->fmask = 0; | |
1681 | pcs->fshift = 0; | |
1682 | pcs->fmax = 0; | |
1683 | } | |
8b8b091b TL |
1684 | |
1685 | ret = of_property_read_u32(np, "pinctrl-single,function-off", | |
1686 | &pcs->foff); | |
1687 | if (ret) | |
1688 | pcs->foff = PCS_OFF_DISABLED; | |
1689 | ||
9e605cb6 PU |
1690 | pcs->bits_per_mux = of_property_read_bool(np, |
1691 | "pinctrl-single,bit-per-mux"); | |
4622215f TL |
1692 | ret = pcs_quirk_missing_pinctrl_cells(pcs, np, |
1693 | pcs->bits_per_mux ? 2 : 1); | |
1694 | if (ret) { | |
1695 | dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n"); | |
1696 | ||
1697 | return ret; | |
1698 | } | |
9e605cb6 | 1699 | |
8b8b091b TL |
1700 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1701 | if (!res) { | |
1702 | dev_err(pcs->dev, "could not get resource\n"); | |
1703 | return -ENODEV; | |
1704 | } | |
1705 | ||
1706 | pcs->res = devm_request_mem_region(pcs->dev, res->start, | |
1707 | resource_size(res), DRIVER_NAME); | |
1708 | if (!pcs->res) { | |
1709 | dev_err(pcs->dev, "could not get mem_region\n"); | |
1710 | return -EBUSY; | |
1711 | } | |
1712 | ||
1713 | pcs->size = resource_size(pcs->res); | |
1714 | pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size); | |
1715 | if (!pcs->base) { | |
1716 | dev_err(pcs->dev, "could not ioremap\n"); | |
1717 | return -ENODEV; | |
1718 | } | |
1719 | ||
8b8b091b TL |
1720 | platform_set_drvdata(pdev, pcs); |
1721 | ||
1722 | switch (pcs->width) { | |
1723 | case 8: | |
1724 | pcs->read = pcs_readb; | |
1725 | pcs->write = pcs_writeb; | |
1726 | break; | |
1727 | case 16: | |
1728 | pcs->read = pcs_readw; | |
1729 | pcs->write = pcs_writew; | |
1730 | break; | |
1731 | case 32: | |
1732 | pcs->read = pcs_readl; | |
1733 | pcs->write = pcs_writel; | |
1734 | break; | |
1735 | default: | |
1736 | break; | |
1737 | } | |
1738 | ||
1739 | pcs->desc.name = DRIVER_NAME; | |
1740 | pcs->desc.pctlops = &pcs_pinctrl_ops; | |
1741 | pcs->desc.pmxops = &pcs_pinmux_ops; | |
02e483f6 | 1742 | if (PCS_HAS_PINCONF) |
a7bbdd7f | 1743 | pcs->desc.confops = &pcs_pinconf_ops; |
8b8b091b TL |
1744 | pcs->desc.owner = THIS_MODULE; |
1745 | ||
1746 | ret = pcs_allocate_pin_table(pcs); | |
1747 | if (ret < 0) | |
1748 | goto free; | |
1749 | ||
950b0d91 TL |
1750 | ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl); |
1751 | if (ret) { | |
8b8b091b | 1752 | dev_err(pcs->dev, "could not register single pinctrl driver\n"); |
8b8b091b TL |
1753 | goto free; |
1754 | } | |
1755 | ||
a1a277eb HZ |
1756 | ret = pcs_add_gpio_func(np, pcs); |
1757 | if (ret < 0) | |
1758 | goto free; | |
1759 | ||
3e6cee17 TL |
1760 | pcs->socdata.irq = irq_of_parse_and_map(np, 0); |
1761 | if (pcs->socdata.irq) | |
1762 | pcs->flags |= PCS_FEAT_IRQ; | |
1763 | ||
dc7743aa TL |
1764 | /* We still need auxdata for some omaps for PRM interrupts */ |
1765 | pdata = dev_get_platdata(&pdev->dev); | |
1766 | if (pdata) { | |
1767 | if (pdata->rearm) | |
1768 | pcs->socdata.rearm = pdata->rearm; | |
1769 | if (pdata->irq) { | |
1770 | pcs->socdata.irq = pdata->irq; | |
1771 | pcs->flags |= PCS_FEAT_IRQ; | |
1772 | } | |
1773 | } | |
1774 | ||
3e6cee17 TL |
1775 | if (PCS_HAS_IRQ) { |
1776 | ret = pcs_irq_init_chained_handler(pcs, np); | |
1777 | if (ret < 0) | |
1778 | dev_warn(pcs->dev, "initialized with no interrupts\n"); | |
1779 | } | |
1780 | ||
8b8b091b TL |
1781 | dev_info(pcs->dev, "%i pins at pa %p size %u\n", |
1782 | pcs->desc.npins, pcs->base, pcs->size); | |
1783 | ||
61187142 | 1784 | return pinctrl_enable(pcs->pctl); |
8b8b091b TL |
1785 | |
1786 | free: | |
1787 | pcs_free_resources(pcs); | |
1788 | ||
1789 | return ret; | |
1790 | } | |
1791 | ||
f90f54b3 | 1792 | static int pcs_remove(struct platform_device *pdev) |
8b8b091b TL |
1793 | { |
1794 | struct pcs_device *pcs = platform_get_drvdata(pdev); | |
1795 | ||
1796 | if (!pcs) | |
1797 | return 0; | |
1798 | ||
1799 | pcs_free_resources(pcs); | |
1800 | ||
1801 | return 0; | |
1802 | } | |
1803 | ||
3e6cee17 TL |
1804 | static const struct pcs_soc_data pinctrl_single_omap_wkup = { |
1805 | .flags = PCS_QUIRK_SHARED_IRQ, | |
1806 | .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */ | |
1807 | .irq_status_mask = (1 << 15), /* OMAP_WAKEUP_EVENT */ | |
1808 | }; | |
1809 | ||
31320bea | 1810 | static const struct pcs_soc_data pinctrl_single_dra7 = { |
31320bea NM |
1811 | .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */ |
1812 | .irq_status_mask = (1 << 25), /* WAKEUPEVENT */ | |
1813 | }; | |
1814 | ||
aa2293d8 K |
1815 | static const struct pcs_soc_data pinctrl_single_am437x = { |
1816 | .flags = PCS_QUIRK_SHARED_IRQ, | |
1817 | .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */ | |
1818 | .irq_status_mask = (1 << 30), /* OMAP_WAKEUP_EVENT */ | |
1819 | }; | |
1820 | ||
02e483f6 TL |
1821 | static const struct pcs_soc_data pinctrl_single = { |
1822 | }; | |
1823 | ||
1824 | static const struct pcs_soc_data pinconf_single = { | |
1825 | .flags = PCS_FEAT_PINCONF, | |
1826 | }; | |
1827 | ||
baa9946e | 1828 | static const struct of_device_id pcs_of_match[] = { |
3e6cee17 TL |
1829 | { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup }, |
1830 | { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup }, | |
1831 | { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup }, | |
31320bea | 1832 | { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 }, |
aa2293d8 | 1833 | { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x }, |
02e483f6 TL |
1834 | { .compatible = "pinctrl-single", .data = &pinctrl_single }, |
1835 | { .compatible = "pinconf-single", .data = &pinconf_single }, | |
8b8b091b TL |
1836 | { }, |
1837 | }; | |
1838 | MODULE_DEVICE_TABLE(of, pcs_of_match); | |
1839 | ||
1840 | static struct platform_driver pcs_driver = { | |
1841 | .probe = pcs_probe, | |
2a36f086 | 1842 | .remove = pcs_remove, |
8b8b091b | 1843 | .driver = { |
8b8b091b TL |
1844 | .name = DRIVER_NAME, |
1845 | .of_match_table = pcs_of_match, | |
1846 | }, | |
0f9bc4bc HG |
1847 | #ifdef CONFIG_PM |
1848 | .suspend = pinctrl_single_suspend, | |
1849 | .resume = pinctrl_single_resume, | |
1850 | #endif | |
8b8b091b TL |
1851 | }; |
1852 | ||
1853 | module_platform_driver(pcs_driver); | |
1854 | ||
1855 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
1856 | MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver"); | |
1857 | MODULE_LICENSE("GPL v2"); |