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Merge tag 'trace-4.1-tracefs' of git://git.kernel.org/pub/scm/linux/kernel/git/rosted...
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / pinctrl-st.c
CommitLineData
701016c0
SK		 1/*
2 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
3 * Authors:
4 * Srinivas Kandagatla <srinivas.kandagatla@st.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/err.h>
15#include <linux/io.h>
16#include <linux/of.h>
727b0f71 17#include <linux/of_irq.h>
701016c0
SK		 18#include <linux/of_gpio.h>
19#include <linux/of_address.h>
20#include <linux/regmap.h>
21#include <linux/mfd/syscon.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/platform_device.h>
26#include "core.h"
27
28/* PIO Block registers */
29/* PIO output */
30#define REG_PIO_POUT 0x00
31/* Set bits of POUT */
32#define REG_PIO_SET_POUT 0x04
33/* Clear bits of POUT */
34#define REG_PIO_CLR_POUT 0x08
35/* PIO input */
36#define REG_PIO_PIN 0x10
37/* PIO configuration */
38#define REG_PIO_PC(n) (0x20 + (n) * 0x10)
39/* Set bits of PC[2:0] */
40#define REG_PIO_SET_PC(n) (0x24 + (n) * 0x10)
41/* Clear bits of PC[2:0] */
42#define REG_PIO_CLR_PC(n) (0x28 + (n) * 0x10)
43/* PIO input comparison */
44#define REG_PIO_PCOMP 0x50
45/* Set bits of PCOMP */
46#define REG_PIO_SET_PCOMP 0x54
47/* Clear bits of PCOMP */
48#define REG_PIO_CLR_PCOMP 0x58
49/* PIO input comparison mask */
50#define REG_PIO_PMASK 0x60
51/* Set bits of PMASK */
52#define REG_PIO_SET_PMASK 0x64
53/* Clear bits of PMASK */
54#define REG_PIO_CLR_PMASK 0x68
55
56#define ST_GPIO_DIRECTION_BIDIR 0x1
57#define ST_GPIO_DIRECTION_OUT 0x2
58#define ST_GPIO_DIRECTION_IN 0x4
59
60/**
61 * Packed style retime configuration.
62 * There are two registers cfg0 and cfg1 in this style for each bank.
63 * Each field in this register is 8 bit corresponding to 8 pins in the bank.
64 */
65#define RT_P_CFGS_PER_BANK 2
66#define RT_P_CFG0_CLK1NOTCLK0_FIELD(reg) REG_FIELD(reg, 0, 7)
67#define RT_P_CFG0_DELAY_0_FIELD(reg) REG_FIELD(reg, 16, 23)
68#define RT_P_CFG0_DELAY_1_FIELD(reg) REG_FIELD(reg, 24, 31)
69#define RT_P_CFG1_INVERTCLK_FIELD(reg) REG_FIELD(reg, 0, 7)
70#define RT_P_CFG1_RETIME_FIELD(reg) REG_FIELD(reg, 8, 15)
71#define RT_P_CFG1_CLKNOTDATA_FIELD(reg) REG_FIELD(reg, 16, 23)
72#define RT_P_CFG1_DOUBLE_EDGE_FIELD(reg) REG_FIELD(reg, 24, 31)
73
74/**
75 * Dedicated style retime Configuration register
76 * each register is dedicated per pin.
77 */
78#define RT_D_CFGS_PER_BANK 8
79#define RT_D_CFG_CLK_SHIFT 0
80#define RT_D_CFG_CLK_MASK (0x3 << 0)
81#define RT_D_CFG_CLKNOTDATA_SHIFT 2
82#define RT_D_CFG_CLKNOTDATA_MASK BIT(2)
83#define RT_D_CFG_DELAY_SHIFT 3
84#define RT_D_CFG_DELAY_MASK (0xf << 3)
85#define RT_D_CFG_DELAY_INNOTOUT_SHIFT 7
86#define RT_D_CFG_DELAY_INNOTOUT_MASK BIT(7)
87#define RT_D_CFG_DOUBLE_EDGE_SHIFT 8
88#define RT_D_CFG_DOUBLE_EDGE_MASK BIT(8)
89#define RT_D_CFG_INVERTCLK_SHIFT 9
90#define RT_D_CFG_INVERTCLK_MASK BIT(9)
91#define RT_D_CFG_RETIME_SHIFT 10
92#define RT_D_CFG_RETIME_MASK BIT(10)
93
94/*
95 * Pinconf is represented in an opaque unsigned long variable.
96 * Below is the bit allocation details for each possible configuration.
97 * All the bit fields can be encapsulated into four variables
98 * (direction, retime-type, retime-clk, retime-delay)
99 *
100 * +----------------+
101 *[31:28]| reserved-3 |
102 * +----------------+-------------
103 *[27] | oe | |
104 * +----------------+ v
105 *[26] | pu | [Direction ]
106 * +----------------+ ^
107 *[25] | od | |
108 * +----------------+-------------
109 *[24] | reserved-2 |
110 * +----------------+-------------
111 *[23] | retime | |
112 * +----------------+ |
113 *[22] | retime-invclk | |
114 * +----------------+ v
115 *[21] |retime-clknotdat| [Retime-type ]
116 * +----------------+ ^
117 *[20] | retime-de | |
118 * +----------------+-------------
119 *[19:18]| retime-clk |------>[Retime-Clk ]
120 * +----------------+
121 *[17:16]| reserved-1 |
122 * +----------------+
123 *[15..0]| retime-delay |------>[Retime Delay]
124 * +----------------+
125 */
126
127#define ST_PINCONF_UNPACK(conf, param)\
128 ((conf >> ST_PINCONF_ ##param ##_SHIFT) \
129 & ST_PINCONF_ ##param ##_MASK)
130
131#define ST_PINCONF_PACK(conf, val, param) (conf |=\
132 ((val & ST_PINCONF_ ##param ##_MASK) << \
133 ST_PINCONF_ ##param ##_SHIFT))
134
135/* Output enable */
136#define ST_PINCONF_OE_MASK 0x1
137#define ST_PINCONF_OE_SHIFT 27
138#define ST_PINCONF_OE BIT(27)
139#define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE)
140#define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
141
142/* Pull Up */
143#define ST_PINCONF_PU_MASK 0x1
144#define ST_PINCONF_PU_SHIFT 26
145#define ST_PINCONF_PU BIT(26)
146#define ST_PINCONF_UNPACK_PU(conf) ST_PINCONF_UNPACK(conf, PU)
147#define ST_PINCONF_PACK_PU(conf) ST_PINCONF_PACK(conf, 1, PU)
148
149/* Open Drain */
150#define ST_PINCONF_OD_MASK 0x1
151#define ST_PINCONF_OD_SHIFT 25
152#define ST_PINCONF_OD BIT(25)
153#define ST_PINCONF_UNPACK_OD(conf) ST_PINCONF_UNPACK(conf, OD)
154#define ST_PINCONF_PACK_OD(conf) ST_PINCONF_PACK(conf, 1, OD)
155
156#define ST_PINCONF_RT_MASK 0x1
157#define ST_PINCONF_RT_SHIFT 23
158#define ST_PINCONF_RT BIT(23)
159#define ST_PINCONF_UNPACK_RT(conf) ST_PINCONF_UNPACK(conf, RT)
160#define ST_PINCONF_PACK_RT(conf) ST_PINCONF_PACK(conf, 1, RT)
161
162#define ST_PINCONF_RT_INVERTCLK_MASK 0x1
163#define ST_PINCONF_RT_INVERTCLK_SHIFT 22
164#define ST_PINCONF_RT_INVERTCLK BIT(22)
165#define ST_PINCONF_UNPACK_RT_INVERTCLK(conf) \
166 ST_PINCONF_UNPACK(conf, RT_INVERTCLK)
167#define ST_PINCONF_PACK_RT_INVERTCLK(conf) \
168 ST_PINCONF_PACK(conf, 1, RT_INVERTCLK)
169
170#define ST_PINCONF_RT_CLKNOTDATA_MASK 0x1
171#define ST_PINCONF_RT_CLKNOTDATA_SHIFT 21
172#define ST_PINCONF_RT_CLKNOTDATA BIT(21)
173#define ST_PINCONF_UNPACK_RT_CLKNOTDATA(conf) \
174 ST_PINCONF_UNPACK(conf, RT_CLKNOTDATA)
175#define ST_PINCONF_PACK_RT_CLKNOTDATA(conf) \
176 ST_PINCONF_PACK(conf, 1, RT_CLKNOTDATA)
177
178#define ST_PINCONF_RT_DOUBLE_EDGE_MASK 0x1
179#define ST_PINCONF_RT_DOUBLE_EDGE_SHIFT 20
180#define ST_PINCONF_RT_DOUBLE_EDGE BIT(20)
181#define ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(conf) \
182 ST_PINCONF_UNPACK(conf, RT_DOUBLE_EDGE)
183#define ST_PINCONF_PACK_RT_DOUBLE_EDGE(conf) \
184 ST_PINCONF_PACK(conf, 1, RT_DOUBLE_EDGE)
185
186#define ST_PINCONF_RT_CLK_MASK 0x3
187#define ST_PINCONF_RT_CLK_SHIFT 18
188#define ST_PINCONF_RT_CLK BIT(18)
189#define ST_PINCONF_UNPACK_RT_CLK(conf) ST_PINCONF_UNPACK(conf, RT_CLK)
190#define ST_PINCONF_PACK_RT_CLK(conf, val) ST_PINCONF_PACK(conf, val, RT_CLK)
191
192/* RETIME_DELAY in Pico Secs */
193#define ST_PINCONF_RT_DELAY_MASK 0xffff
194#define ST_PINCONF_RT_DELAY_SHIFT 0
195#define ST_PINCONF_UNPACK_RT_DELAY(conf) ST_PINCONF_UNPACK(conf, RT_DELAY)
196#define ST_PINCONF_PACK_RT_DELAY(conf, val) \
197 ST_PINCONF_PACK(conf, val, RT_DELAY)
198
199#define ST_GPIO_PINS_PER_BANK (8)
200#define OF_GPIO_ARGS_MIN (4)
201#define OF_RT_ARGS_MIN (2)
202
203#define gpio_range_to_bank(chip) \
204 container_of(chip, struct st_gpio_bank, range)
205
206#define gpio_chip_to_bank(chip) \
207 container_of(chip, struct st_gpio_bank, gpio_chip)
208
209
210enum st_retime_style {
211 st_retime_style_none,
212 st_retime_style_packed,
213 st_retime_style_dedicated,
214};
215
216struct st_retime_dedicated {
217 struct regmap_field *rt[ST_GPIO_PINS_PER_BANK];
218};
219
220struct st_retime_packed {
221 struct regmap_field *clk1notclk0;
222 struct regmap_field *delay_0;
223 struct regmap_field *delay_1;
224 struct regmap_field *invertclk;
225 struct regmap_field *retime;
226 struct regmap_field *clknotdata;
227 struct regmap_field *double_edge;
228};
229
230struct st_pio_control {
231 u32 rt_pin_mask;
232 struct regmap_field *alt, *oe, *pu, *od;
233 /* retiming */
234 union {
235 struct st_retime_packed rt_p;
236 struct st_retime_dedicated rt_d;
237 } rt;
238};
239
240struct st_pctl_data {
a4bc1f57
MC		 241 const enum st_retime_style rt_style;
242 const unsigned int *input_delays;
243 const int ninput_delays;
244 const unsigned int *output_delays;
245 const int noutput_delays;
701016c0 246 /* register offset information */
a4bc1f57 247 const int alt, oe, pu, od, rt;
701016c0
SK		 248};
249
250struct st_pinconf {
251 int pin;
252 const char *name;
253 unsigned long config;
254 int altfunc;
255};
256
257struct st_pmx_func {
258 const char *name;
259 const char **groups;
260 unsigned ngroups;
261};
262
263struct st_pctl_group {
264 const char *name;
265 unsigned int *pins;
266 unsigned npins;
267 struct st_pinconf *pin_conf;
268};
269
155795b9
SK		 270/*
271 * Edge triggers are not supported at hardware level, it is supported by
272 * software by exploiting the level trigger support in hardware.
273 * Software uses a virtual register (EDGE_CONF) for edge trigger configuration
274 * of each gpio pin in a GPIO bank.
275 *
276 * Each bank has a 32 bit EDGE_CONF register which is divided in to 8 parts of
277 * 4-bits. Each 4-bit space is allocated for each pin in a gpio bank.
278 *
279 * bit allocation per pin is:
280 * Bits: [0 - 3] | [4 - 7] [8 - 11] ... ... ... ... [ 28 - 31]
281 * --------------------------------------------------------
282 * | pin-0 | pin-2 | pin-3 | ... ... ... ... | pin -7 |
283 * --------------------------------------------------------
284 *
285 * A pin can have one of following the values in its edge configuration field.
286 *
287 * ------- ----------------------------
288 * [0-3] - Description
289 * ------- ----------------------------
290 * 0000 - No edge IRQ.
291 * 0001 - Falling edge IRQ.
292 * 0010 - Rising edge IRQ.
293 * 0011 - Rising and Falling edge IRQ.
294 * ------- ----------------------------
295 */
296
297#define ST_IRQ_EDGE_CONF_BITS_PER_PIN 4
298#define ST_IRQ_EDGE_MASK 0xf
299#define ST_IRQ_EDGE_FALLING BIT(0)
300#define ST_IRQ_EDGE_RISING BIT(1)
301#define ST_IRQ_EDGE_BOTH (BIT(0) | BIT(1))
302
303#define ST_IRQ_RISING_EDGE_CONF(pin) \
304 (ST_IRQ_EDGE_RISING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
305
306#define ST_IRQ_FALLING_EDGE_CONF(pin) \
307 (ST_IRQ_EDGE_FALLING << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
308
309#define ST_IRQ_BOTH_EDGE_CONF(pin) \
310 (ST_IRQ_EDGE_BOTH << (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN))
311
312#define ST_IRQ_EDGE_CONF(conf, pin) \
313 (conf >> (pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN) & ST_IRQ_EDGE_MASK)
314
701016c0
SK		 315struct st_gpio_bank {
316 struct gpio_chip gpio_chip;
317 struct pinctrl_gpio_range range;
318 void __iomem *base;
319 struct st_pio_control pc;
155795b9
SK		 320 unsigned long irq_edge_conf;
321 spinlock_t lock;
701016c0
SK		 322};
323
324struct st_pinctrl {
325 struct device *dev;
326 struct pinctrl_dev *pctl;
327 struct st_gpio_bank *banks;
328 int nbanks;
329 struct st_pmx_func *functions;
330 int nfunctions;
331 struct st_pctl_group *groups;
332 int ngroups;
333 struct regmap *regmap;
334 const struct st_pctl_data *data;
727b0f71 335 void __iomem *irqmux_base;
701016c0
SK		 336};
337
338/* SOC specific data */
339/* STiH415 data */
a4bc1f57
MC		 340static const unsigned int stih415_input_delays[] = {0, 500, 1000, 1500};
341static const unsigned int stih415_output_delays[] = {0, 1000, 2000, 3000};
701016c0
SK		 342
343#define STIH415_PCTRL_COMMON_DATA \
344 .rt_style = st_retime_style_packed, \
345 .input_delays = stih415_input_delays, \
3b02dad2 346 .ninput_delays = ARRAY_SIZE(stih415_input_delays), \
701016c0 347 .output_delays = stih415_output_delays, \
3b02dad2 348 .noutput_delays = ARRAY_SIZE(stih415_output_delays)
701016c0
SK		 349
350static const struct st_pctl_data stih415_sbc_data = {
351 STIH415_PCTRL_COMMON_DATA,
352 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 16,
353};
354
355static const struct st_pctl_data stih415_front_data = {
356 STIH415_PCTRL_COMMON_DATA,
357 .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 16,
358};
359
360static const struct st_pctl_data stih415_rear_data = {
361 STIH415_PCTRL_COMMON_DATA,
362 .alt = 0, .oe = 6, .pu = 8, .od = 10, .rt = 38,
363};
364
365static const struct st_pctl_data stih415_left_data = {
366 STIH415_PCTRL_COMMON_DATA,
367 .alt = 0, .oe = 3, .pu = 4, .od = 5, .rt = 6,
368};
369
370static const struct st_pctl_data stih415_right_data = {
371 STIH415_PCTRL_COMMON_DATA,
372 .alt = 0, .oe = 5, .pu = 7, .od = 9, .rt = 11,
373};
374
375/* STiH416 data */
a4bc1f57
MC		 376static const unsigned int stih416_delays[] = {0, 300, 500, 750, 1000, 1250,
377 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250 };
701016c0
SK		 378
379static const struct st_pctl_data stih416_data = {
380 .rt_style = st_retime_style_dedicated,
381 .input_delays = stih416_delays,
88430acf 382 .ninput_delays = ARRAY_SIZE(stih416_delays),
701016c0 383 .output_delays = stih416_delays,
88430acf 384 .noutput_delays = ARRAY_SIZE(stih416_delays),
701016c0
SK		 385 .alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
386};
387
7ce717db
GC		 388static const struct st_pctl_data stih407_flashdata = {
389 .rt_style = st_retime_style_none,
390 .input_delays = stih416_delays,
391 .ninput_delays = ARRAY_SIZE(stih416_delays),
392 .output_delays = stih416_delays,
393 .noutput_delays = ARRAY_SIZE(stih416_delays),
394 .alt = 0,
395 .oe = -1, /* Not Available */
396 .pu = -1, /* Not Available */
397 .od = 60,
398 .rt = 100,
399};
400
701016c0
SK		 401/* Low level functions.. */
402static inline int st_gpio_bank(int gpio)
403{
404 return gpio/ST_GPIO_PINS_PER_BANK;
405}
406
407static inline int st_gpio_pin(int gpio)
408{
409 return gpio%ST_GPIO_PINS_PER_BANK;
410}
411
412static void st_pinconf_set_config(struct st_pio_control *pc,
413 int pin, unsigned long config)
414{
415 struct regmap_field *output_enable = pc->oe;
416 struct regmap_field *pull_up = pc->pu;
417 struct regmap_field *open_drain = pc->od;
418 unsigned int oe_value, pu_value, od_value;
419 unsigned long mask = BIT(pin);
420
4e6a609f
GC		 421 if (output_enable) {
422 regmap_field_read(output_enable, &oe_value);
423 oe_value &= ~mask;
424 if (config & ST_PINCONF_OE)
425 oe_value |= mask;
426 regmap_field_write(output_enable, oe_value);
427 }
428
429 if (pull_up) {
430 regmap_field_read(pull_up, &pu_value);
431 pu_value &= ~mask;
432 if (config & ST_PINCONF_PU)
433 pu_value |= mask;
434 regmap_field_write(pull_up, pu_value);
435 }
436
437 if (open_drain) {
438 regmap_field_read(open_drain, &od_value);
439 od_value &= ~mask;
440 if (config & ST_PINCONF_OD)
441 od_value |= mask;
442 regmap_field_write(open_drain, od_value);
443 }
701016c0
SK		 444}
445
446static void st_pctl_set_function(struct st_pio_control *pc,
447 int pin_id, int function)
448{
449 struct regmap_field *alt = pc->alt;
450 unsigned int val;
451 int pin = st_gpio_pin(pin_id);
452 int offset = pin * 4;
453
4e6a609f
GC		 454 if (!alt)
455 return;
456
701016c0
SK		 457 regmap_field_read(alt, &val);
458 val &= ~(0xf << offset);
459 val |= function << offset;
460 regmap_field_write(alt, val);
461}
462
463static unsigned long st_pinconf_delay_to_bit(unsigned int delay,
464 const struct st_pctl_data *data, unsigned long config)
465{
a4bc1f57 466 const unsigned int *delay_times;
701016c0
SK		 467 int num_delay_times, i, closest_index = -1;
468 unsigned int closest_divergence = UINT_MAX;
469
470 if (ST_PINCONF_UNPACK_OE(config)) {
471 delay_times = data->output_delays;
472 num_delay_times = data->noutput_delays;
473 } else {
474 delay_times = data->input_delays;
475 num_delay_times = data->ninput_delays;
476 }
477
478 for (i = 0; i < num_delay_times; i++) {
479 unsigned int divergence = abs(delay - delay_times[i]);
480
481 if (divergence == 0)
482 return i;
483
484 if (divergence < closest_divergence) {
485 closest_divergence = divergence;
486 closest_index = i;
487 }
488 }
489
490 pr_warn("Attempt to set delay %d, closest available %d\n",
491 delay, delay_times[closest_index]);
492
493 return closest_index;
494}
495
496static unsigned long st_pinconf_bit_to_delay(unsigned int index,
497 const struct st_pctl_data *data, unsigned long output)
498{
a4bc1f57 499 const unsigned int *delay_times;
701016c0
SK		 500 int num_delay_times;
501
502 if (output) {
503 delay_times = data->output_delays;
504 num_delay_times = data->noutput_delays;
505 } else {
506 delay_times = data->input_delays;
507 num_delay_times = data->ninput_delays;
508 }
509
510 if (index < num_delay_times) {
511 return delay_times[index];
512 } else {
513 pr_warn("Delay not found in/out delay list\n");
514 return 0;
515 }
516}
517
518static void st_regmap_field_bit_set_clear_pin(struct regmap_field *field,
519 int enable, int pin)
520{
521 unsigned int val = 0;
522
523 regmap_field_read(field, &val);
524 if (enable)
525 val |= BIT(pin);
526 else
527 val &= ~BIT(pin);
528 regmap_field_write(field, val);
529}
530
531static void st_pinconf_set_retime_packed(struct st_pinctrl *info,
532 struct st_pio_control *pc, unsigned long config, int pin)
533{
534 const struct st_pctl_data *data = info->data;
535 struct st_retime_packed *rt_p = &pc->rt.rt_p;
536 unsigned int delay;
537
538 st_regmap_field_bit_set_clear_pin(rt_p->clk1notclk0,
539 ST_PINCONF_UNPACK_RT_CLK(config), pin);
540
541 st_regmap_field_bit_set_clear_pin(rt_p->clknotdata,
542 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config), pin);
543
544 st_regmap_field_bit_set_clear_pin(rt_p->double_edge,
545 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config), pin);
546
547 st_regmap_field_bit_set_clear_pin(rt_p->invertclk,
548 ST_PINCONF_UNPACK_RT_INVERTCLK(config), pin);
549
550 st_regmap_field_bit_set_clear_pin(rt_p->retime,
551 ST_PINCONF_UNPACK_RT(config), pin);
552
553 delay = st_pinconf_delay_to_bit(ST_PINCONF_UNPACK_RT_DELAY(config),
554 data, config);
555 /* 2 bit delay, lsb */
556 st_regmap_field_bit_set_clear_pin(rt_p->delay_0, delay & 0x1, pin);
557 /* 2 bit delay, msb */
558 st_regmap_field_bit_set_clear_pin(rt_p->delay_1, delay & 0x2, pin);
559
560}
561
562static void st_pinconf_set_retime_dedicated(struct st_pinctrl *info,
563 struct st_pio_control *pc, unsigned long config, int pin)
564{
565 int input = ST_PINCONF_UNPACK_OE(config) ? 0 : 1;
566 int clk = ST_PINCONF_UNPACK_RT_CLK(config);
567 int clknotdata = ST_PINCONF_UNPACK_RT_CLKNOTDATA(config);
568 int double_edge = ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config);
569 int invertclk = ST_PINCONF_UNPACK_RT_INVERTCLK(config);
570 int retime = ST_PINCONF_UNPACK_RT(config);
571
572 unsigned long delay = st_pinconf_delay_to_bit(
573 ST_PINCONF_UNPACK_RT_DELAY(config),
574 info->data, config);
575 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
576
577 unsigned long retime_config =
578 ((clk) << RT_D_CFG_CLK_SHIFT) |
579 ((delay) << RT_D_CFG_DELAY_SHIFT) |
580 ((input) << RT_D_CFG_DELAY_INNOTOUT_SHIFT) |
581 ((retime) << RT_D_CFG_RETIME_SHIFT) |
582 ((clknotdata) << RT_D_CFG_CLKNOTDATA_SHIFT) |
583 ((invertclk) << RT_D_CFG_INVERTCLK_SHIFT) |
584 ((double_edge) << RT_D_CFG_DOUBLE_EDGE_SHIFT);
585
586 regmap_field_write(rt_d->rt[pin], retime_config);
587}
588
589static void st_pinconf_get_direction(struct st_pio_control *pc,
590 int pin, unsigned long *config)
591{
592 unsigned int oe_value, pu_value, od_value;
593
4e6a609f
GC		 594 if (pc->oe) {
595 regmap_field_read(pc->oe, &oe_value);
596 if (oe_value & BIT(pin))
597 ST_PINCONF_PACK_OE(*config);
598 }
701016c0 599
4e6a609f
GC		 600 if (pc->pu) {
601 regmap_field_read(pc->pu, &pu_value);
602 if (pu_value & BIT(pin))
603 ST_PINCONF_PACK_PU(*config);
604 }
701016c0 605
4e6a609f
GC		 606 if (pc->od) {
607 regmap_field_read(pc->od, &od_value);
608 if (od_value & BIT(pin))
609 ST_PINCONF_PACK_OD(*config);
610 }
701016c0
SK		 611}
612
613static int st_pinconf_get_retime_packed(struct st_pinctrl *info,
614 struct st_pio_control *pc, int pin, unsigned long *config)
615{
616 const struct st_pctl_data *data = info->data;
617 struct st_retime_packed *rt_p = &pc->rt.rt_p;
618 unsigned int delay_bits, delay, delay0, delay1, val;
619 int output = ST_PINCONF_UNPACK_OE(*config);
620
621 if (!regmap_field_read(rt_p->retime, &val) && (val & BIT(pin)))
622 ST_PINCONF_PACK_RT(*config);
623
624 if (!regmap_field_read(rt_p->clk1notclk0, &val) && (val & BIT(pin)))
625 ST_PINCONF_PACK_RT_CLK(*config, 1);
626
627 if (!regmap_field_read(rt_p->clknotdata, &val) && (val & BIT(pin)))
628 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
629
630 if (!regmap_field_read(rt_p->double_edge, &val) && (val & BIT(pin)))
631 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
632
633 if (!regmap_field_read(rt_p->invertclk, &val) && (val & BIT(pin)))
634 ST_PINCONF_PACK_RT_INVERTCLK(*config);
635
636 regmap_field_read(rt_p->delay_0, &delay0);
637 regmap_field_read(rt_p->delay_1, &delay1);
638 delay_bits = (((delay1 & BIT(pin)) ? 1 : 0) << 1) |
639 (((delay0 & BIT(pin)) ? 1 : 0));
640 delay = st_pinconf_bit_to_delay(delay_bits, data, output);
641 ST_PINCONF_PACK_RT_DELAY(*config, delay);
642
643 return 0;
644}
645
646static int st_pinconf_get_retime_dedicated(struct st_pinctrl *info,
647 struct st_pio_control *pc, int pin, unsigned long *config)
648{
649 unsigned int value;
650 unsigned long delay_bits, delay, rt_clk;
651 int output = ST_PINCONF_UNPACK_OE(*config);
652 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
653
654 regmap_field_read(rt_d->rt[pin], &value);
655
656 rt_clk = (value & RT_D_CFG_CLK_MASK) >> RT_D_CFG_CLK_SHIFT;
657 ST_PINCONF_PACK_RT_CLK(*config, rt_clk);
658
659 delay_bits = (value & RT_D_CFG_DELAY_MASK) >> RT_D_CFG_DELAY_SHIFT;
660 delay = st_pinconf_bit_to_delay(delay_bits, info->data, output);
661 ST_PINCONF_PACK_RT_DELAY(*config, delay);
662
663 if (value & RT_D_CFG_CLKNOTDATA_MASK)
664 ST_PINCONF_PACK_RT_CLKNOTDATA(*config);
665
666 if (value & RT_D_CFG_DOUBLE_EDGE_MASK)
667 ST_PINCONF_PACK_RT_DOUBLE_EDGE(*config);
668
669 if (value & RT_D_CFG_INVERTCLK_MASK)
670 ST_PINCONF_PACK_RT_INVERTCLK(*config);
671
672 if (value & RT_D_CFG_RETIME_MASK)
673 ST_PINCONF_PACK_RT(*config);
674
675 return 0;
676}
677
678/* GPIO related functions */
679
680static inline void __st_gpio_set(struct st_gpio_bank *bank,
681 unsigned offset, int value)
682{
683 if (value)
684 writel(BIT(offset), bank->base + REG_PIO_SET_POUT);
685 else
686 writel(BIT(offset), bank->base + REG_PIO_CLR_POUT);
687}
688
689static void st_gpio_direction(struct st_gpio_bank *bank,
690 unsigned int gpio, unsigned int direction)
691{
692 int offset = st_gpio_pin(gpio);
693 int i = 0;
694 /**
695 * There are three configuration registers (PIOn_PC0, PIOn_PC1
696 * and PIOn_PC2) for each port. These are used to configure the
697 * PIO port pins. Each pin can be configured as an input, output,
698 * bidirectional, or alternative function pin. Three bits, one bit
699 * from each of the three registers, configure the corresponding bit of
700 * the port. Valid bit settings is:
701 *
702 * PC2 PC1 PC0 Direction.
703 * 0 0 0 [Input Weak pull-up]
704 * 0 0 or 1 1 [Bidirection]
705 * 0 1 0 [Output]
706 * 1 0 0 [Input]
707 *
708 * PIOn_SET_PC and PIOn_CLR_PC registers are used to set and clear bits
709 * individually.
710 */
711 for (i = 0; i <= 2; i++) {
712 if (direction & BIT(i))
713 writel(BIT(offset), bank->base + REG_PIO_SET_PC(i));
714 else
715 writel(BIT(offset), bank->base + REG_PIO_CLR_PC(i));
716 }
717}
718
719static int st_gpio_request(struct gpio_chip *chip, unsigned offset)
720{
721 return pinctrl_request_gpio(chip->base + offset);
722}
723
724static void st_gpio_free(struct gpio_chip *chip, unsigned offset)
725{
726 pinctrl_free_gpio(chip->base + offset);
727}
728
729static int st_gpio_get(struct gpio_chip *chip, unsigned offset)
730{
731 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
732
733 return !!(readl(bank->base + REG_PIO_PIN) & BIT(offset));
734}
735
736static void st_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
737{
738 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
739 __st_gpio_set(bank, offset, value);
740}
741
742static int st_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
743{
744 pinctrl_gpio_direction_input(chip->base + offset);
745
746 return 0;
747}
748
749static int st_gpio_direction_output(struct gpio_chip *chip,
750 unsigned offset, int value)
751{
752 struct st_gpio_bank *bank = gpio_chip_to_bank(chip);
753
754 __st_gpio_set(bank, offset, value);
755 pinctrl_gpio_direction_output(chip->base + offset);
756
757 return 0;
758}
759
760static int st_gpio_xlate(struct gpio_chip *gc,
761 const struct of_phandle_args *gpiospec, u32 *flags)
762{
763 if (WARN_ON(gc->of_gpio_n_cells < 1))
764 return -EINVAL;
765
766 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
767 return -EINVAL;
768
769 if (gpiospec->args[0] > gc->ngpio)
770 return -EINVAL;
771
772 return gpiospec->args[0];
773}
774
775/* Pinctrl Groups */
776static int st_pctl_get_groups_count(struct pinctrl_dev *pctldev)
777{
778 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
779
780 return info->ngroups;
781}
782
783static const char *st_pctl_get_group_name(struct pinctrl_dev *pctldev,
784 unsigned selector)
785{
786 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
787
788 return info->groups[selector].name;
789}
790
791static int st_pctl_get_group_pins(struct pinctrl_dev *pctldev,
792 unsigned selector, const unsigned **pins, unsigned *npins)
793{
794 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
795
796 if (selector >= info->ngroups)
797 return -EINVAL;
798
799 *pins = info->groups[selector].pins;
800 *npins = info->groups[selector].npins;
801
802 return 0;
803}
804
805static const inline struct st_pctl_group *st_pctl_find_group_by_name(
806 const struct st_pinctrl *info, const char *name)
807{
808 int i;
809
810 for (i = 0; i < info->ngroups; i++) {
811 if (!strcmp(info->groups[i].name, name))
812 return &info->groups[i];
813 }
814
815 return NULL;
816}
817
818static int st_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
819 struct device_node *np, struct pinctrl_map **map, unsigned *num_maps)
820{
821 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
822 const struct st_pctl_group *grp;
823 struct pinctrl_map *new_map;
824 struct device_node *parent;
825 int map_num, i;
826
827 grp = st_pctl_find_group_by_name(info, np->name);
828 if (!grp) {
829 dev_err(info->dev, "unable to find group for node %s\n",
830 np->name);
831 return -EINVAL;
832 }
833
834 map_num = grp->npins + 1;
835 new_map = devm_kzalloc(pctldev->dev,
836 sizeof(*new_map) * map_num, GFP_KERNEL);
837 if (!new_map)
838 return -ENOMEM;
839
840 parent = of_get_parent(np);
841 if (!parent) {
842 devm_kfree(pctldev->dev, new_map);
843 return -EINVAL;
844 }
845
846 *map = new_map;
847 *num_maps = map_num;
848 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
849 new_map[0].data.mux.function = parent->name;
850 new_map[0].data.mux.group = np->name;
851 of_node_put(parent);
852
853 /* create config map per pin */
854 new_map++;
855 for (i = 0; i < grp->npins; i++) {
856 new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
857 new_map[i].data.configs.group_or_pin =
858 pin_get_name(pctldev, grp->pins[i]);
859 new_map[i].data.configs.configs = &grp->pin_conf[i].config;
860 new_map[i].data.configs.num_configs = 1;
861 }
862 dev_info(pctldev->dev, "maps: function %s group %s num %d\n",
863 (*map)->data.mux.function, grp->name, map_num);
864
865 return 0;
866}
867
868static void st_pctl_dt_free_map(struct pinctrl_dev *pctldev,
869 struct pinctrl_map *map, unsigned num_maps)
870{
871}
872
873static struct pinctrl_ops st_pctlops = {
874 .get_groups_count = st_pctl_get_groups_count,
875 .get_group_pins = st_pctl_get_group_pins,
876 .get_group_name = st_pctl_get_group_name,
877 .dt_node_to_map = st_pctl_dt_node_to_map,
878 .dt_free_map = st_pctl_dt_free_map,
879};
880
881/* Pinmux */
882static int st_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
883{
884 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
885
886 return info->nfunctions;
887}
888
ef75bfd5 889static const char *st_pmx_get_fname(struct pinctrl_dev *pctldev,
701016c0
SK		 890 unsigned selector)
891{
892 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
893
894 return info->functions[selector].name;
895}
896
897static int st_pmx_get_groups(struct pinctrl_dev *pctldev,
898 unsigned selector, const char * const **grps, unsigned * const ngrps)
899{
900 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
901 *grps = info->functions[selector].groups;
902 *ngrps = info->functions[selector].ngroups;
903
904 return 0;
905}
906
907static struct st_pio_control *st_get_pio_control(
908 struct pinctrl_dev *pctldev, int pin)
909{
910 struct pinctrl_gpio_range *range =
911 pinctrl_find_gpio_range_from_pin(pctldev, pin);
912 struct st_gpio_bank *bank = gpio_range_to_bank(range);
913
914 return &bank->pc;
915}
916
03e9f0ca
LW		 917static int st_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
918 unsigned group)
701016c0
SK		 919{
920 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
921 struct st_pinconf *conf = info->groups[group].pin_conf;
922 struct st_pio_control *pc;
923 int i;
924
925 for (i = 0; i < info->groups[group].npins; i++) {
926 pc = st_get_pio_control(pctldev, conf[i].pin);
927 st_pctl_set_function(pc, conf[i].pin, conf[i].altfunc);
928 }
929
930 return 0;
931}
932
701016c0
SK		 933static int st_pmx_set_gpio_direction(struct pinctrl_dev *pctldev,
934 struct pinctrl_gpio_range *range, unsigned gpio,
935 bool input)
936{
937 struct st_gpio_bank *bank = gpio_range_to_bank(range);
938 /*
939 * When a PIO bank is used in its primary function mode (altfunc = 0)
940 * Output Enable (OE), Open Drain(OD), and Pull Up (PU)
941 * for the primary PIO functions are driven by the related PIO block
942 */
943 st_pctl_set_function(&bank->pc, gpio, 0);
944 st_gpio_direction(bank, gpio, input ?
945 ST_GPIO_DIRECTION_IN : ST_GPIO_DIRECTION_OUT);
946
947 return 0;
948}
949
950static struct pinmux_ops st_pmxops = {
951 .get_functions_count = st_pmx_get_funcs_count,
952 .get_function_name = st_pmx_get_fname,
953 .get_function_groups = st_pmx_get_groups,
03e9f0ca 954 .set_mux = st_pmx_set_mux,
701016c0
SK		 955 .gpio_set_direction = st_pmx_set_gpio_direction,
956};
957
958/* Pinconf */
959static void st_pinconf_get_retime(struct st_pinctrl *info,
960 struct st_pio_control *pc, int pin, unsigned long *config)
961{
962 if (info->data->rt_style == st_retime_style_packed)
963 st_pinconf_get_retime_packed(info, pc, pin, config);
964 else if (info->data->rt_style == st_retime_style_dedicated)
965 if ((BIT(pin) & pc->rt_pin_mask))
966 st_pinconf_get_retime_dedicated(info, pc,
967 pin, config);
968}
969
970static void st_pinconf_set_retime(struct st_pinctrl *info,
971 struct st_pio_control *pc, int pin, unsigned long config)
972{
973 if (info->data->rt_style == st_retime_style_packed)
974 st_pinconf_set_retime_packed(info, pc, config, pin);
975 else if (info->data->rt_style == st_retime_style_dedicated)
976 if ((BIT(pin) & pc->rt_pin_mask))
977 st_pinconf_set_retime_dedicated(info, pc,
978 config, pin);
979}
980
03b054e9
SY		 981static int st_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin_id,
982 unsigned long *configs, unsigned num_configs)
701016c0
SK		 983{
984 int pin = st_gpio_pin(pin_id);
985 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
986 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
03b054e9 987 int i;
701016c0 988
03b054e9
SY		 989 for (i = 0; i < num_configs; i++) {
990 st_pinconf_set_config(pc, pin, configs[i]);
991 st_pinconf_set_retime(info, pc, pin, configs[i]);
992 } /* for each config */
701016c0
SK		 993
994 return 0;
995}
996
997static int st_pinconf_get(struct pinctrl_dev *pctldev,
998 unsigned pin_id, unsigned long *config)
999{
1000 int pin = st_gpio_pin(pin_id);
1001 struct st_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
1002 struct st_pio_control *pc = st_get_pio_control(pctldev, pin_id);
1003
1004 *config = 0;
1005 st_pinconf_get_direction(pc, pin, config);
1006 st_pinconf_get_retime(info, pc, pin, config);
1007
1008 return 0;
1009}
1010
1011static void st_pinconf_dbg_show(struct pinctrl_dev *pctldev,
1012 struct seq_file *s, unsigned pin_id)
1013{
1014 unsigned long config;
701016c0 1015
96d16c30
FV		 1016 mutex_unlock(&pctldev->mutex);
1017 st_pinconf_get(pctldev, pin_id, &config);
1018 mutex_lock(&pctldev->mutex);
701016c0
SK		 1019 seq_printf(s, "[OE:%ld,PU:%ld,OD:%ld]\n"
1020 "\t\t[retime:%ld,invclk:%ld,clknotdat:%ld,"
1021 "de:%ld,rt-clk:%ld,rt-delay:%ld]",
1022 ST_PINCONF_UNPACK_OE(config),
1023 ST_PINCONF_UNPACK_PU(config),
1024 ST_PINCONF_UNPACK_OD(config),
1025 ST_PINCONF_UNPACK_RT(config),
1026 ST_PINCONF_UNPACK_RT_INVERTCLK(config),
1027 ST_PINCONF_UNPACK_RT_CLKNOTDATA(config),
1028 ST_PINCONF_UNPACK_RT_DOUBLE_EDGE(config),
1029 ST_PINCONF_UNPACK_RT_CLK(config),
1030 ST_PINCONF_UNPACK_RT_DELAY(config));
1031}
1032
1033static struct pinconf_ops st_confops = {
1034 .pin_config_get = st_pinconf_get,
1035 .pin_config_set = st_pinconf_set,
1036 .pin_config_dbg_show = st_pinconf_dbg_show,
1037};
1038
1039static void st_pctl_dt_child_count(struct st_pinctrl *info,
1040 struct device_node *np)
1041{
1042 struct device_node *child;
1043 for_each_child_of_node(np, child) {
1044 if (of_property_read_bool(child, "gpio-controller")) {
1045 info->nbanks++;
1046 } else {
1047 info->nfunctions++;
1048 info->ngroups += of_get_child_count(child);
1049 }
1050 }
1051}
1052
1053static int st_pctl_dt_setup_retime_packed(struct st_pinctrl *info,
1054 int bank, struct st_pio_control *pc)
1055{
1056 struct device *dev = info->dev;
1057 struct regmap *rm = info->regmap;
1058 const struct st_pctl_data *data = info->data;
1059 /* 2 registers per bank */
1060 int reg = (data->rt + bank * RT_P_CFGS_PER_BANK) * 4;
1061 struct st_retime_packed *rt_p = &pc->rt.rt_p;
1062 /* cfg0 */
1063 struct reg_field clk1notclk0 = RT_P_CFG0_CLK1NOTCLK0_FIELD(reg);
1064 struct reg_field delay_0 = RT_P_CFG0_DELAY_0_FIELD(reg);
1065 struct reg_field delay_1 = RT_P_CFG0_DELAY_1_FIELD(reg);
1066 /* cfg1 */
1067 struct reg_field invertclk = RT_P_CFG1_INVERTCLK_FIELD(reg + 4);
1068 struct reg_field retime = RT_P_CFG1_RETIME_FIELD(reg + 4);
1069 struct reg_field clknotdata = RT_P_CFG1_CLKNOTDATA_FIELD(reg + 4);
1070 struct reg_field double_edge = RT_P_CFG1_DOUBLE_EDGE_FIELD(reg + 4);
1071
1072 rt_p->clk1notclk0 = devm_regmap_field_alloc(dev, rm, clk1notclk0);
1073 rt_p->delay_0 = devm_regmap_field_alloc(dev, rm, delay_0);
1074 rt_p->delay_1 = devm_regmap_field_alloc(dev, rm, delay_1);
1075 rt_p->invertclk = devm_regmap_field_alloc(dev, rm, invertclk);
1076 rt_p->retime = devm_regmap_field_alloc(dev, rm, retime);
1077 rt_p->clknotdata = devm_regmap_field_alloc(dev, rm, clknotdata);
1078 rt_p->double_edge = devm_regmap_field_alloc(dev, rm, double_edge);
1079
1080 if (IS_ERR(rt_p->clk1notclk0) || IS_ERR(rt_p->delay_0) ||
1081 IS_ERR(rt_p->delay_1) || IS_ERR(rt_p->invertclk) ||
1082 IS_ERR(rt_p->retime) || IS_ERR(rt_p->clknotdata) ||
1083 IS_ERR(rt_p->double_edge))
1084 return -EINVAL;
1085
1086 return 0;
1087}
1088
1089static int st_pctl_dt_setup_retime_dedicated(struct st_pinctrl *info,
1090 int bank, struct st_pio_control *pc)
1091{
1092 struct device *dev = info->dev;
1093 struct regmap *rm = info->regmap;
1094 const struct st_pctl_data *data = info->data;
1095 /* 8 registers per bank */
1096 int reg_offset = (data->rt + bank * RT_D_CFGS_PER_BANK) * 4;
1097 struct st_retime_dedicated *rt_d = &pc->rt.rt_d;
1098 unsigned int j;
1099 u32 pin_mask = pc->rt_pin_mask;
1100
1101 for (j = 0; j < RT_D_CFGS_PER_BANK; j++) {
1102 if (BIT(j) & pin_mask) {
1103 struct reg_field reg = REG_FIELD(reg_offset, 0, 31);
1104 rt_d->rt[j] = devm_regmap_field_alloc(dev, rm, reg);
1105 if (IS_ERR(rt_d->rt[j]))
1106 return -EINVAL;
1107 reg_offset += 4;
1108 }
1109 }
1110 return 0;
1111}
1112
1113static int st_pctl_dt_setup_retime(struct st_pinctrl *info,
1114 int bank, struct st_pio_control *pc)
1115{
1116 const struct st_pctl_data *data = info->data;
1117 if (data->rt_style == st_retime_style_packed)
1118 return st_pctl_dt_setup_retime_packed(info, bank, pc);
1119 else if (data->rt_style == st_retime_style_dedicated)
1120 return st_pctl_dt_setup_retime_dedicated(info, bank, pc);
1121
1122 return -EINVAL;
1123}
1124
4e6a609f
GC		 1125
1126static struct regmap_field *st_pc_get_value(struct device *dev,
1127 struct regmap *regmap, int bank,
1128 int data, int lsb, int msb)
1129{
1130 struct reg_field reg = REG_FIELD((data + bank) * 4, lsb, msb);
1131
1132 if (data < 0)
1133 return NULL;
1134
1135 return devm_regmap_field_alloc(dev, regmap, reg);
1136}
1137
1138static void st_parse_syscfgs(struct st_pinctrl *info, int bank,
1139 struct device_node *np)
701016c0
SK		 1140{
1141 const struct st_pctl_data *data = info->data;
1142 /**
1143 * For a given shared register like OE/PU/OD, there are 8 bits per bank
1144 * 0:7 belongs to bank0, 8:15 belongs to bank1 ...
1145 * So each register is shared across 4 banks.
1146 */
1147 int lsb = (bank%4) * ST_GPIO_PINS_PER_BANK;
1148 int msb = lsb + ST_GPIO_PINS_PER_BANK - 1;
701016c0
SK		 1149 struct st_pio_control *pc = &info->banks[bank].pc;
1150 struct device *dev = info->dev;
1151 struct regmap *regmap = info->regmap;
1152
4e6a609f
GC		 1153 pc->alt = st_pc_get_value(dev, regmap, bank, data->alt, 0, 31);
1154 pc->oe = st_pc_get_value(dev, regmap, bank/4, data->oe, lsb, msb);
1155 pc->pu = st_pc_get_value(dev, regmap, bank/4, data->pu, lsb, msb);
1156 pc->od = st_pc_get_value(dev, regmap, bank/4, data->od, lsb, msb);
701016c0
SK		 1157
1158 /* retime avaiable for all pins by default */
1159 pc->rt_pin_mask = 0xff;
1160 of_property_read_u32(np, "st,retime-pin-mask", &pc->rt_pin_mask);
1161 st_pctl_dt_setup_retime(info, bank, pc);
1162
4e6a609f 1163 return;
701016c0
SK		 1164}
1165
1166/*
1167 * Each pin is represented in of the below forms.
1168 * <bank offset mux direction rt_type rt_delay rt_clk>
1169 */
1170static int st_pctl_dt_parse_groups(struct device_node *np,
1171 struct st_pctl_group *grp, struct st_pinctrl *info, int idx)
1172{
1173 /* bank pad direction val altfunction */
1174 const __be32 *list;
1175 struct property *pp;
1176 struct st_pinconf *conf;
701016c0 1177 struct device_node *pins;
701016c0
SK		 1178 int i = 0, npins = 0, nr_props;
1179
1180 pins = of_get_child_by_name(np, "st,pins");
1181 if (!pins)
1182 return -ENODATA;
1183
1184 for_each_property_of_node(pins, pp) {
1185 /* Skip those we do not want to proceed */
1186 if (!strcmp(pp->name, "name"))
1187 continue;
1188
1189 if (pp && (pp->length/sizeof(__be32)) >= OF_GPIO_ARGS_MIN) {
1190 npins++;
1191 } else {
1192 pr_warn("Invalid st,pins in %s node\n", np->name);
1193 return -EINVAL;
1194 }
1195 }
1196
1197 grp->npins = npins;
1198 grp->name = np->name;
1199 grp->pins = devm_kzalloc(info->dev, npins * sizeof(u32), GFP_KERNEL);
1200 grp->pin_conf = devm_kzalloc(info->dev,
1201 npins * sizeof(*conf), GFP_KERNEL);
1202
1203 if (!grp->pins || !grp->pin_conf)
1204 return -ENOMEM;
1205
1206 /* <bank offset mux direction rt_type rt_delay rt_clk> */
1207 for_each_property_of_node(pins, pp) {
1208 if (!strcmp(pp->name, "name"))
1209 continue;
1210 nr_props = pp->length/sizeof(u32);
1211 list = pp->value;
1212 conf = &grp->pin_conf[i];
1213
1214 /* bank & offset */
1f978217
RS		 1215 be32_to_cpup(list++);
1216 be32_to_cpup(list++);
701016c0
SK		 1217 conf->pin = of_get_named_gpio(pins, pp->name, 0);
1218 conf->name = pp->name;
1219 grp->pins[i] = conf->pin;
1220 /* mux */
1221 conf->altfunc = be32_to_cpup(list++);
1222 conf->config = 0;
1223 /* direction */
1224 conf->config |= be32_to_cpup(list++);
1225 /* rt_type rt_delay rt_clk */
1226 if (nr_props >= OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN) {
1227 /* rt_type */
1228 conf->config |= be32_to_cpup(list++);
1229 /* rt_delay */
1230 conf->config |= be32_to_cpup(list++);
1231 /* rt_clk */
1232 if (nr_props > OF_GPIO_ARGS_MIN + OF_RT_ARGS_MIN)
1233 conf->config |= be32_to_cpup(list++);
1234 }
1235 i++;
1236 }
1237 of_node_put(pins);
1238
1239 return 0;
1240}
1241
1242static int st_pctl_parse_functions(struct device_node *np,
1243 struct st_pinctrl *info, u32 index, int *grp_index)
1244{
1245 struct device_node *child;
1246 struct st_pmx_func *func;
1247 struct st_pctl_group *grp;
1248 int ret, i;
1249
1250 func = &info->functions[index];
1251 func->name = np->name;
1252 func->ngroups = of_get_child_count(np);
8b0c107c 1253 if (func->ngroups == 0) {
701016c0
SK		 1254 dev_err(info->dev, "No groups defined\n");
1255 return -EINVAL;
1256 }
1257 func->groups = devm_kzalloc(info->dev,
1258 func->ngroups * sizeof(char *), GFP_KERNEL);
1259 if (!func->groups)
1260 return -ENOMEM;
1261
1262 i = 0;
1263 for_each_child_of_node(np, child) {
1264 func->groups[i] = child->name;
1265 grp = &info->groups[*grp_index];
1266 *grp_index += 1;
1267 ret = st_pctl_dt_parse_groups(child, grp, info, i++);
1268 if (ret)
1269 return ret;
1270 }
1271 dev_info(info->dev, "Function[%d\t name:%s,\tgroups:%d]\n",
1272 index, func->name, func->ngroups);
1273
1274 return 0;
1275}
1276
727b0f71
SK		 1277static void st_gpio_irq_mask(struct irq_data *d)
1278{
130cbe30
LW		 1279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1280 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
727b0f71
SK		 1281
1282 writel(BIT(d->hwirq), bank->base + REG_PIO_CLR_PMASK);
1283}
1284
1285static void st_gpio_irq_unmask(struct irq_data *d)
1286{
130cbe30
LW		 1287 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1288 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
727b0f71
SK		 1289
1290 writel(BIT(d->hwirq), bank->base + REG_PIO_SET_PMASK);
1291}
1292
727b0f71
SK		 1293static int st_gpio_irq_set_type(struct irq_data *d, unsigned type)
1294{
130cbe30
LW		 1295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1296 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
727b0f71
SK		 1297 unsigned long flags;
1298 int comp, pin = d->hwirq;
1299 u32 val;
155795b9 1300 u32 pin_edge_conf = 0;
727b0f71
SK		 1301
1302 switch (type) {
1303 case IRQ_TYPE_LEVEL_HIGH:
1304 comp = 0;
1305 break;
155795b9
SK		 1306 case IRQ_TYPE_EDGE_FALLING:
1307 comp = 0;
1308 pin_edge_conf = ST_IRQ_FALLING_EDGE_CONF(pin);
1309 break;
727b0f71
SK		 1310 case IRQ_TYPE_LEVEL_LOW:
1311 comp = 1;
1312 break;
155795b9
SK		 1313 case IRQ_TYPE_EDGE_RISING:
1314 comp = 1;
1315 pin_edge_conf = ST_IRQ_RISING_EDGE_CONF(pin);
1316 break;
1317 case IRQ_TYPE_EDGE_BOTH:
1318 comp = st_gpio_get(&bank->gpio_chip, pin);
1319 pin_edge_conf = ST_IRQ_BOTH_EDGE_CONF(pin);
1320 break;
727b0f71
SK		 1321 default:
1322 return -EINVAL;
1323 }
1324
155795b9
SK		 1325 spin_lock_irqsave(&bank->lock, flags);
1326 bank->irq_edge_conf &= ~(ST_IRQ_EDGE_MASK << (
1327 pin * ST_IRQ_EDGE_CONF_BITS_PER_PIN));
1328 bank->irq_edge_conf |= pin_edge_conf;
1329 spin_unlock_irqrestore(&bank->lock, flags);
1330
727b0f71
SK		 1331 val = readl(bank->base + REG_PIO_PCOMP);
1332 val &= ~BIT(pin);
1333 val |= (comp << pin);
1334 writel(val, bank->base + REG_PIO_PCOMP);
1335
1336 return 0;
1337}
1338
155795b9
SK		 1339/*
1340 * As edge triggers are not supported at hardware level, it is supported by
1341 * software by exploiting the level trigger support in hardware.
1342 *
1343 * Steps for detection raising edge interrupt in software.
1344 *
1345 * Step 1: CONFIGURE pin to detect level LOW interrupts.
1346 *
1347 * Step 2: DETECT level LOW interrupt and in irqmux/gpio bank interrupt handler,
1348 * if the value of pin is low, then CONFIGURE pin for level HIGH interrupt.
1349 * IGNORE calling the actual interrupt handler for the pin at this stage.
1350 *
1351 * Step 3: DETECT level HIGH interrupt and in irqmux/gpio-bank interrupt handler
1352 * if the value of pin is HIGH, CONFIGURE pin for level LOW interrupt and then
1353 * DISPATCH the interrupt to the interrupt handler of the pin.
1354 *
1355 * step-1 ________ __________
1356 * | | step - 3
1357 * | |
1358 * step -2 |_____|
1359 *
1360 * falling edge is also detected int the same way.
1361 *
1362 */
727b0f71
SK		 1363static void __gpio_irq_handler(struct st_gpio_bank *bank)
1364{
1365 unsigned long port_in, port_mask, port_comp, active_irqs;
155795b9
SK		 1366 unsigned long bank_edge_mask, flags;
1367 int n, val, ecfg;
1368
1369 spin_lock_irqsave(&bank->lock, flags);
1370 bank_edge_mask = bank->irq_edge_conf;
1371 spin_unlock_irqrestore(&bank->lock, flags);
727b0f71
SK		 1372
1373 for (;;) {
1374 port_in = readl(bank->base + REG_PIO_PIN);
1375 port_comp = readl(bank->base + REG_PIO_PCOMP);
1376 port_mask = readl(bank->base + REG_PIO_PMASK);
1377
1378 active_irqs = (port_in ^ port_comp) & port_mask;
1379
1380 if (active_irqs == 0)
1381 break;
1382
1383 for_each_set_bit(n, &active_irqs, BITS_PER_LONG) {
155795b9
SK		 1384 /* check if we are detecting fake edges ... */
1385 ecfg = ST_IRQ_EDGE_CONF(bank_edge_mask, n);
1386
1387 if (ecfg) {
1388 /* edge detection. */
1389 val = st_gpio_get(&bank->gpio_chip, n);
1390
1391 writel(BIT(n),
1392 val ? bank->base + REG_PIO_SET_PCOMP :
1393 bank->base + REG_PIO_CLR_PCOMP);
1394
1395 if (ecfg != ST_IRQ_EDGE_BOTH &&
1396 !((ecfg & ST_IRQ_EDGE_FALLING) ^ val))
1397 continue;
1398 }
1399
130cbe30 1400 generic_handle_irq(irq_find_mapping(bank->gpio_chip.irqdomain, n));
727b0f71
SK		 1401 }
1402 }
1403}
1404
1405static void st_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1406{
1407 /* interrupt dedicated per bank */
1408 struct irq_chip *chip = irq_get_chip(irq);
130cbe30
LW		 1409 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1410 struct st_gpio_bank *bank = gpio_chip_to_bank(gc);
727b0f71
SK		 1411
1412 chained_irq_enter(chip, desc);
1413 __gpio_irq_handler(bank);
1414 chained_irq_exit(chip, desc);
1415}
1416
1417static void st_gpio_irqmux_handler(unsigned irq, struct irq_desc *desc)
1418{
1419 struct irq_chip *chip = irq_get_chip(irq);
1420 struct st_pinctrl *info = irq_get_handler_data(irq);
1421 unsigned long status;
1422 int n;
1423
1424 chained_irq_enter(chip, desc);
1425
1426 status = readl(info->irqmux_base);
1427
7a2deccf 1428 for_each_set_bit(n, &status, info->nbanks)
727b0f71
SK		 1429 __gpio_irq_handler(&info->banks[n]);
1430
1431 chained_irq_exit(chip, desc);
1432}
1433
701016c0
SK		 1434static struct gpio_chip st_gpio_template = {
1435 .request = st_gpio_request,
1436 .free = st_gpio_free,
1437 .get = st_gpio_get,
1438 .set = st_gpio_set,
1439 .direction_input = st_gpio_direction_input,
1440 .direction_output = st_gpio_direction_output,
1441 .ngpio = ST_GPIO_PINS_PER_BANK,
1442 .of_gpio_n_cells = 1,
1443 .of_xlate = st_gpio_xlate,
727b0f71
SK		 1444};
1445
1446static struct irq_chip st_gpio_irqchip = {
1447 .name = "GPIO",
fce7fcc7 1448 .irq_disable = st_gpio_irq_mask,
727b0f71
SK		 1449 .irq_mask = st_gpio_irq_mask,
1450 .irq_unmask = st_gpio_irq_unmask,
1451 .irq_set_type = st_gpio_irq_set_type,
8708ebca 1452 .flags = IRQCHIP_SKIP_SET_WAKE,
701016c0
SK		 1453};
1454
1455static int st_gpiolib_register_bank(struct st_pinctrl *info,
1456 int bank_nr, struct device_node *np)
1457{
1458 struct st_gpio_bank *bank = &info->banks[bank_nr];
1459 struct pinctrl_gpio_range *range = &bank->range;
1460 struct device *dev = info->dev;
1461 int bank_num = of_alias_get_id(np, "gpio");
727b0f71 1462 struct resource res, irq_res;
130cbe30 1463 int gpio_irq = 0, err;
701016c0
SK		 1464
1465 if (of_address_to_resource(np, 0, &res))
1466 return -ENODEV;
1467
656445f3
SK		 1468 bank->base = devm_ioremap_resource(dev, &res);
1469 if (IS_ERR(bank->base))
1470 return PTR_ERR(bank->base);
701016c0
SK		 1471
1472 bank->gpio_chip = st_gpio_template;
1473 bank->gpio_chip.base = bank_num * ST_GPIO_PINS_PER_BANK;
1474 bank->gpio_chip.ngpio = ST_GPIO_PINS_PER_BANK;
1475 bank->gpio_chip.of_node = np;
130cbe30 1476 bank->gpio_chip.dev = dev;
155795b9 1477 spin_lock_init(&bank->lock);
701016c0
SK		 1478
1479 of_property_read_string(np, "st,bank-name", &range->name);
1480 bank->gpio_chip.label = range->name;
1481
1482 range->id = bank_num;
1483 range->pin_base = range->base = range->id * ST_GPIO_PINS_PER_BANK;
1484 range->npins = bank->gpio_chip.ngpio;
1485 range->gc = &bank->gpio_chip;
1486 err = gpiochip_add(&bank->gpio_chip);
1487 if (err) {
1488 dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_num);
1489 return err;
1490 }
1491 dev_info(dev, "%s bank added.\n", range->name);
1492
727b0f71
SK		 1493 /**
1494 * GPIO bank can have one of the two possible types of
1495 * interrupt-wirings.
1496 *
1497 * First type is via irqmux, single interrupt is used by multiple
1498 * gpio banks. This reduces number of overall interrupts numbers
1499 * required. All these banks belong to a single pincontroller.
1500 * _________
1501 * | |----> [gpio-bank (n) ]
1502 * | |----> [gpio-bank (n + 1)]
1503 * [irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
1504 * | |----> [gpio-bank (... )]
1505 * |_________|----> [gpio-bank (n + 7)]
1506 *
1507 * Second type has a dedicated interrupt per each gpio bank.
1508 *
1509 * [irqN]----> [gpio-bank (n)]
1510 */
1511
bcca9220 1512 if (of_irq_to_resource(np, 0, &irq_res)) {
727b0f71 1513 gpio_irq = irq_res.start;
130cbe30
LW		 1514 gpiochip_set_chained_irqchip(&bank->gpio_chip, &st_gpio_irqchip,
1515 gpio_irq, st_gpio_irq_handler);
727b0f71
SK		 1516 }
1517
2e537276 1518 if (info->irqmux_base || gpio_irq > 0) {
130cbe30
LW		 1519 err = gpiochip_irqchip_add(&bank->gpio_chip, &st_gpio_irqchip,
1520 0, handle_simple_irq,
1521 IRQ_TYPE_LEVEL_LOW);
1522 if (err) {
7471725f 1523 gpiochip_remove(&bank->gpio_chip);
130cbe30
LW		 1524 dev_info(dev, "could not add irqchip\n");
1525 return err;
727b0f71 1526 }
727b0f71
SK		 1527 } else {
1528 dev_info(dev, "No IRQ support for %s bank\n", np->full_name);
1529 }
1530
701016c0
SK		 1531 return 0;
1532}
1533
1534static struct of_device_id st_pctl_of_match[] = {
1535 { .compatible = "st,stih415-sbc-pinctrl", .data = &stih415_sbc_data },
1536 { .compatible = "st,stih415-rear-pinctrl", .data = &stih415_rear_data },
1537 { .compatible = "st,stih415-left-pinctrl", .data = &stih415_left_data },
1538 { .compatible = "st,stih415-right-pinctrl",
1539 .data = &stih415_right_data },
1540 { .compatible = "st,stih415-front-pinctrl",
1541 .data = &stih415_front_data },
1542 { .compatible = "st,stih416-sbc-pinctrl", .data = &stih416_data},
1543 { .compatible = "st,stih416-front-pinctrl", .data = &stih416_data},
1544 { .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
1545 { .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
1546 { .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
7ce717db
GC		 1547 { .compatible = "st,stih407-sbc-pinctrl", .data = &stih416_data},
1548 { .compatible = "st,stih407-front-pinctrl", .data = &stih416_data},
1549 { .compatible = "st,stih407-rear-pinctrl", .data = &stih416_data},
1550 { .compatible = "st,stih407-flash-pinctrl", .data = &stih407_flashdata},
701016c0
SK		 1551 { /* sentinel */ }
1552};
1553
1554static int st_pctl_probe_dt(struct platform_device *pdev,
1555 struct pinctrl_desc *pctl_desc, struct st_pinctrl *info)
1556{
1557 int ret = 0;
1558 int i = 0, j = 0, k = 0, bank;
1559 struct pinctrl_pin_desc *pdesc;
1560 struct device_node *np = pdev->dev.of_node;
1561 struct device_node *child;
1562 int grp_index = 0;
727b0f71
SK		 1563 int irq = 0;
1564 struct resource *res;
701016c0
SK		 1565
1566 st_pctl_dt_child_count(info, np);
1567 if (!info->nbanks) {
1568 dev_err(&pdev->dev, "you need atleast one gpio bank\n");
1569 return -EINVAL;
1570 }
1571
1572 dev_info(&pdev->dev, "nbanks = %d\n", info->nbanks);
1573 dev_info(&pdev->dev, "nfunctions = %d\n", info->nfunctions);
1574 dev_info(&pdev->dev, "ngroups = %d\n", info->ngroups);
1575
1576 info->functions = devm_kzalloc(&pdev->dev,
1577 info->nfunctions * sizeof(*info->functions), GFP_KERNEL);
1578
1579 info->groups = devm_kzalloc(&pdev->dev,
1580 info->ngroups * sizeof(*info->groups) , GFP_KERNEL);
1581
1582 info->banks = devm_kzalloc(&pdev->dev,
1583 info->nbanks * sizeof(*info->banks), GFP_KERNEL);
1584
1585 if (!info->functions || !info->groups || !info->banks)
1586 return -ENOMEM;
1587
1588 info->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
5c75acdc 1589 if (IS_ERR(info->regmap)) {
701016c0 1590 dev_err(info->dev, "No syscfg phandle specified\n");
5c75acdc 1591 return PTR_ERR(info->regmap);
701016c0
SK		 1592 }
1593 info->data = of_match_node(st_pctl_of_match, np)->data;
1594
727b0f71
SK		 1595 irq = platform_get_irq(pdev, 0);
1596
1597 if (irq > 0) {
1598 res = platform_get_resource_byname(pdev,
1599 IORESOURCE_MEM, "irqmux");
1600 info->irqmux_base = devm_ioremap_resource(&pdev->dev, res);
1601
1602 if (IS_ERR(info->irqmux_base))
1603 return PTR_ERR(info->irqmux_base);
1604
1605 irq_set_chained_handler(irq, st_gpio_irqmux_handler);
1606 irq_set_handler_data(irq, info);
1607
1608 }
1609
701016c0
SK		 1610 pctl_desc->npins = info->nbanks * ST_GPIO_PINS_PER_BANK;
1611 pdesc = devm_kzalloc(&pdev->dev,
1612 sizeof(*pdesc) * pctl_desc->npins, GFP_KERNEL);
1613 if (!pdesc)
1614 return -ENOMEM;
1615
1616 pctl_desc->pins = pdesc;
1617
1618 bank = 0;
1619 for_each_child_of_node(np, child) {
1620 if (of_property_read_bool(child, "gpio-controller")) {
1621 const char *bank_name = NULL;
1622 ret = st_gpiolib_register_bank(info, bank, child);
1623 if (ret)
1624 return ret;
1625
1626 k = info->banks[bank].range.pin_base;
1627 bank_name = info->banks[bank].range.name;
1628 for (j = 0; j < ST_GPIO_PINS_PER_BANK; j++, k++) {
1629 pdesc->number = k;
1630 pdesc->name = kasprintf(GFP_KERNEL, "%s[%d]",
1631 bank_name, j);
1632 pdesc++;
1633 }
1634 st_parse_syscfgs(info, bank, child);
1635 bank++;
1636 } else {
1637 ret = st_pctl_parse_functions(child, info,
1638 i++, &grp_index);
1639 if (ret) {
1640 dev_err(&pdev->dev, "No functions found.\n");
1641 return ret;
1642 }
1643 }
1644 }
1645
1646 return 0;
1647}
1648
1649static int st_pctl_probe(struct platform_device *pdev)
1650{
1651 struct st_pinctrl *info;
1652 struct pinctrl_desc *pctl_desc;
1653 int ret, i;
1654
1655 if (!pdev->dev.of_node) {
1656 dev_err(&pdev->dev, "device node not found.\n");
1657 return -EINVAL;
1658 }
1659
1660 pctl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctl_desc), GFP_KERNEL);
1661 if (!pctl_desc)
1662 return -ENOMEM;
1663
1664 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
1665 if (!info)
1666 return -ENOMEM;
1667
1668 info->dev = &pdev->dev;
1669 platform_set_drvdata(pdev, info);
1670 ret = st_pctl_probe_dt(pdev, pctl_desc, info);
1671 if (ret)
1672 return ret;
1673
c9dd66b7
SK		 1674 pctl_desc->owner = THIS_MODULE;
1675 pctl_desc->pctlops = &st_pctlops;
1676 pctl_desc->pmxops = &st_pmxops;
1677 pctl_desc->confops = &st_confops;
701016c0
SK		 1678 pctl_desc->name = dev_name(&pdev->dev);
1679
1680 info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info);
5c75acdc 1681 if (!info->pctl) {
701016c0 1682 dev_err(&pdev->dev, "Failed pinctrl registration\n");
5c75acdc 1683 return -EINVAL;
701016c0
SK		 1684 }
1685
1686 for (i = 0; i < info->nbanks; i++)
1687 pinctrl_add_gpio_range(info->pctl, &info->banks[i].range);
1688
1689 return 0;
1690}
1691
1692static struct platform_driver st_pctl_driver = {
1693 .driver = {
1694 .name = "st-pinctrl",
539fde59 1695 .of_match_table = st_pctl_of_match,
701016c0
SK		 1696 },
1697 .probe = st_pctl_probe,
1698};
1699
1700static int __init st_pctl_init(void)
1701{
1702 return platform_driver_register(&st_pctl_driver);
1703}
1704arch_initcall(st_pctl_init);
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