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pinctrl-sx150x: Use handle_bad_irq instead of handle_edge_irq
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / pinctrl-sx150x.c
CommitLineData
9e80f906
NA		 1/*
2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
6 *
7 * Driver for Semtech SX150X I2C GPIO Expanders
8 *
9 * Author: Gregory Bean <gbean@codeaurora.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 and
13 * only version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
0db0f26c 21#include <linux/regmap.h>
9e80f906
NA		 22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/mutex.h>
27#include <linux/slab.h>
28#include <linux/of.h>
e3ba8120 29#include <linux/of_device.h>
9e80f906
NA		 30#include <linux/gpio.h>
31#include <linux/pinctrl/machine.h>
32#include <linux/pinctrl/pinconf.h>
33#include <linux/pinctrl/pinctrl.h>
34#include <linux/pinctrl/pinmux.h>
35#include <linux/pinctrl/pinconf-generic.h>
36
37#include "core.h"
38#include "pinconf.h"
39#include "pinctrl-utils.h"
40
41/* The chip models of sx150x */
42enum {
43 SX150X_123 = 0,
44 SX150X_456,
45 SX150X_789,
46};
7d68a79a
AS		 47enum {
48 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
0db0f26c 49 SX150X_MAX_REGISTER = 0xad,
7d68a79a 50};
9e80f906
NA		 51
52struct sx150x_123_pri {
53 u8 reg_pld_mode;
54 u8 reg_pld_table0;
55 u8 reg_pld_table1;
56 u8 reg_pld_table2;
57 u8 reg_pld_table3;
58 u8 reg_pld_table4;
59 u8 reg_advance;
60};
61
62struct sx150x_456_pri {
63 u8 reg_pld_mode;
64 u8 reg_pld_table0;
65 u8 reg_pld_table1;
66 u8 reg_pld_table2;
67 u8 reg_pld_table3;
68 u8 reg_pld_table4;
69 u8 reg_advance;
70};
71
72struct sx150x_789_pri {
73 u8 reg_drain;
74 u8 reg_polarity;
75 u8 reg_clock;
76 u8 reg_misc;
77 u8 reg_reset;
78 u8 ngpios;
79};
80
81struct sx150x_device_data {
82 u8 model;
83 u8 reg_pullup;
84 u8 reg_pulldn;
85 u8 reg_dir;
86 u8 reg_data;
87 u8 reg_irq_mask;
88 u8 reg_irq_src;
89 u8 reg_sense;
90 u8 ngpios;
91 union {
92 struct sx150x_123_pri x123;
93 struct sx150x_456_pri x456;
94 struct sx150x_789_pri x789;
95 } pri;
96 const struct pinctrl_pin_desc *pins;
97 unsigned int npins;
98};
99
100struct sx150x_pinctrl {
101 struct device *dev;
102 struct i2c_client *client;
103 struct pinctrl_dev *pctldev;
104 struct pinctrl_desc pinctrl_desc;
105 struct gpio_chip gpio;
106 struct irq_chip irq_chip;
0db0f26c 107 struct regmap *regmap;
9e80f906 108 struct {
9e80f906
NA		 109 u32 sense;
110 u32 masked;
9e80f906
NA		 111 } irq;
112 struct mutex lock;
113 const struct sx150x_device_data *data;
114};
115
116static const struct pinctrl_pin_desc sx150x_8_pins[] = {
117 PINCTRL_PIN(0, "gpio0"),
118 PINCTRL_PIN(1, "gpio1"),
119 PINCTRL_PIN(2, "gpio2"),
120 PINCTRL_PIN(3, "gpio3"),
121 PINCTRL_PIN(4, "gpio4"),
122 PINCTRL_PIN(5, "gpio5"),
123 PINCTRL_PIN(6, "gpio6"),
124 PINCTRL_PIN(7, "gpio7"),
125 PINCTRL_PIN(8, "oscio"),
126};
127
128static const struct pinctrl_pin_desc sx150x_16_pins[] = {
129 PINCTRL_PIN(0, "gpio0"),
130 PINCTRL_PIN(1, "gpio1"),
131 PINCTRL_PIN(2, "gpio2"),
132 PINCTRL_PIN(3, "gpio3"),
133 PINCTRL_PIN(4, "gpio4"),
134 PINCTRL_PIN(5, "gpio5"),
135 PINCTRL_PIN(6, "gpio6"),
136 PINCTRL_PIN(7, "gpio7"),
137 PINCTRL_PIN(8, "gpio8"),
138 PINCTRL_PIN(9, "gpio9"),
139 PINCTRL_PIN(10, "gpio10"),
140 PINCTRL_PIN(11, "gpio11"),
141 PINCTRL_PIN(12, "gpio12"),
142 PINCTRL_PIN(13, "gpio13"),
143 PINCTRL_PIN(14, "gpio14"),
144 PINCTRL_PIN(15, "gpio15"),
145 PINCTRL_PIN(16, "oscio"),
146};
147
148static const struct sx150x_device_data sx1508q_device_data = {
149 .model = SX150X_789,
150 .reg_pullup = 0x03,
151 .reg_pulldn = 0x04,
152 .reg_dir = 0x07,
153 .reg_data = 0x08,
154 .reg_irq_mask = 0x09,
155 .reg_irq_src = 0x0c,
156 .reg_sense = 0x0b,
157 .pri.x789 = {
158 .reg_drain = 0x05,
159 .reg_polarity = 0x06,
160 .reg_clock = 0x0f,
161 .reg_misc = 0x10,
162 .reg_reset = 0x7d,
163 },
164 .ngpios = 8,
165 .pins = sx150x_8_pins,
166 .npins = ARRAY_SIZE(sx150x_8_pins),
167};
168
169static const struct sx150x_device_data sx1509q_device_data = {
170 .model = SX150X_789,
6489677f
AS		 171 .reg_pullup = 0x06,
172 .reg_pulldn = 0x08,
173 .reg_dir = 0x0e,
174 .reg_data = 0x10,
175 .reg_irq_mask = 0x12,
176 .reg_irq_src = 0x18,
177 .reg_sense = 0x14,
9e80f906 178 .pri.x789 = {
6489677f
AS		 179 .reg_drain = 0x0a,
180 .reg_polarity = 0x0c,
9e80f906
NA		 181 .reg_clock = 0x1e,
182 .reg_misc = 0x1f,
183 .reg_reset = 0x7d,
184 },
185 .ngpios = 16,
186 .pins = sx150x_16_pins,
187 .npins = ARRAY_SIZE(sx150x_16_pins),
188};
189
190static const struct sx150x_device_data sx1506q_device_data = {
191 .model = SX150X_456,
6489677f
AS		 192 .reg_pullup = 0x04,
193 .reg_pulldn = 0x06,
194 .reg_dir = 0x02,
195 .reg_data = 0x00,
196 .reg_irq_mask = 0x08,
197 .reg_irq_src = 0x0e,
198 .reg_sense = 0x0a,
9e80f906 199 .pri.x456 = {
6489677f
AS		 200 .reg_pld_mode = 0x20,
201 .reg_pld_table0 = 0x22,
202 .reg_pld_table1 = 0x24,
203 .reg_pld_table2 = 0x26,
204 .reg_pld_table3 = 0x28,
205 .reg_pld_table4 = 0x2a,
9e80f906
NA		 206 .reg_advance = 0xad,
207 },
208 .ngpios = 16,
209 .pins = sx150x_16_pins,
210 .npins = 16, /* oscio not available */
211};
212
213static const struct sx150x_device_data sx1502q_device_data = {
214 .model = SX150X_123,
215 .reg_pullup = 0x02,
216 .reg_pulldn = 0x03,
217 .reg_dir = 0x01,
218 .reg_data = 0x00,
219 .reg_irq_mask = 0x05,
220 .reg_irq_src = 0x08,
221 .reg_sense = 0x07,
222 .pri.x123 = {
223 .reg_pld_mode = 0x10,
224 .reg_pld_table0 = 0x11,
225 .reg_pld_table1 = 0x12,
226 .reg_pld_table2 = 0x13,
227 .reg_pld_table3 = 0x14,
228 .reg_pld_table4 = 0x15,
229 .reg_advance = 0xad,
230 },
231 .ngpios = 8,
232 .pins = sx150x_8_pins,
233 .npins = 8, /* oscio not available */
234};
235
6697546d
AS		 236static const struct sx150x_device_data sx1503q_device_data = {
237 .model = SX150X_123,
6489677f
AS		 238 .reg_pullup = 0x04,
239 .reg_pulldn = 0x06,
240 .reg_dir = 0x02,
241 .reg_data = 0x00,
242 .reg_irq_mask = 0x08,
243 .reg_irq_src = 0x0e,
244 .reg_sense = 0x0a,
6697546d 245 .pri.x123 = {
6489677f
AS		 246 .reg_pld_mode = 0x20,
247 .reg_pld_table0 = 0x22,
248 .reg_pld_table1 = 0x24,
249 .reg_pld_table2 = 0x26,
250 .reg_pld_table3 = 0x28,
251 .reg_pld_table4 = 0x2a,
6697546d
AS		 252 .reg_advance = 0xad,
253 },
254 .ngpios = 16,
255 .pins = sx150x_16_pins,
256 .npins = 16, /* oscio not available */
257};
258
9e80f906
NA		 259static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
260{
261 return 0;
262}
263
264static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
265 unsigned int group)
266{
267 return NULL;
268}
269
270static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
271 unsigned int group,
272 const unsigned int **pins,
273 unsigned int *num_pins)
274{
275 return -ENOTSUPP;
276}
277
278static const struct pinctrl_ops sx150x_pinctrl_ops = {
279 .get_groups_count = sx150x_pinctrl_get_groups_count,
280 .get_group_name = sx150x_pinctrl_get_group_name,
281 .get_group_pins = sx150x_pinctrl_get_group_pins,
282#ifdef CONFIG_OF
283 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
284 .dt_free_map = pinctrl_utils_free_map,
285#endif
286};
287
288static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
289{
290 if (pin >= pctl->data->npins)
291 return false;
292
293 /* OSCIO pin is only present in 789 devices */
294 if (pctl->data->model != SX150X_789)
295 return false;
296
297 return !strcmp(pctl->data->pins[pin].name, "oscio");
298}
299
300static int sx150x_gpio_get_direction(struct gpio_chip *chip,
301 unsigned int offset)
302{
303 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
6489677f
AS		 304 unsigned int value;
305 int ret;
9e80f906
NA		 306
307 if (sx150x_pin_is_oscio(pctl, offset))
308 return false;
309
6489677f
AS		 310 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
311 if (ret < 0)
312 return ret;
9e80f906 313
6489677f 314 return !!(value & BIT(offset));
9e80f906
NA		 315}
316
317static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
318{
319 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
6489677f
AS		 320 unsigned int value;
321 int ret;
9e80f906
NA		 322
323 if (sx150x_pin_is_oscio(pctl, offset))
324 return -EINVAL;
325
6489677f
AS		 326 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
327 if (ret < 0)
328 return ret;
9e80f906 329
6489677f 330 return !!(value & BIT(offset));
9e80f906
NA		 331}
332
333static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
334 unsigned int offset,
335 enum single_ended_mode mode)
336{
337 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
338 int ret;
339
340 switch (mode) {
341 case LINE_MODE_PUSH_PULL:
342 if (pctl->data->model != SX150X_789 ||
343 sx150x_pin_is_oscio(pctl, offset))
344 return 0;
345
6489677f
AS		 346 ret = regmap_write_bits(pctl->regmap,
347 pctl->data->pri.x789.reg_drain,
348 BIT(offset), 0);
9e80f906
NA		 349 break;
350
351 case LINE_MODE_OPEN_DRAIN:
352 if (pctl->data->model != SX150X_789 ||
353 sx150x_pin_is_oscio(pctl, offset))
354 return -ENOTSUPP;
355
6489677f
AS		 356 ret = regmap_write_bits(pctl->regmap,
357 pctl->data->pri.x789.reg_drain,
358 BIT(offset), BIT(offset));
9e80f906 359 break;
9e80f906 360 default:
d977a876
AS		 361 ret = -ENOTSUPP;
362 break;
9e80f906
NA		 363 }
364
d977a876 365 return ret;
9e80f906
NA		 366}
367
6489677f
AS		 368static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
369 int value)
370{
371 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
372 BIT(offset), value ? BIT(offset) : 0);
373}
374
ab5bd035
AS		 375static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
376 int value)
377{
378 return regmap_write(pctl->regmap,
379 pctl->data->pri.x789.reg_clock,
380 (value ? 0x1f : 0x10));
381}
382
9e80f906
NA		 383static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
384 int value)
385{
386 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
387
d977a876 388 if (sx150x_pin_is_oscio(pctl, offset))
ab5bd035 389 sx150x_gpio_oscio_set(pctl, value);
d977a876 390 else
6489677f 391 __sx150x_gpio_set(pctl, offset, value);
d977a876 392
9e80f906
NA		 393}
394
395static int sx150x_gpio_direction_input(struct gpio_chip *chip,
396 unsigned int offset)
397{
398 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
9e80f906
NA		 399
400 if (sx150x_pin_is_oscio(pctl, offset))
401 return -EINVAL;
402
d977a876
AS		 403 return regmap_write_bits(pctl->regmap,
404 pctl->data->reg_dir,
405 BIT(offset), BIT(offset));
9e80f906
NA		 406}
407
408static int sx150x_gpio_direction_output(struct gpio_chip *chip,
409 unsigned int offset, int value)
410{
411 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
d977a876 412 int ret;
9e80f906 413
ab5bd035
AS		 414 if (sx150x_pin_is_oscio(pctl, offset))
415 return sx150x_gpio_oscio_set(pctl, value);
9e80f906 416
d977a876
AS		 417 ret = __sx150x_gpio_set(pctl, offset, value);
418 if (ret < 0)
419 return ret;
9e80f906 420
d977a876
AS		 421 return regmap_write_bits(pctl->regmap,
422 pctl->data->reg_dir,
423 BIT(offset), 0);
9e80f906
NA		 424}
425
426static void sx150x_irq_mask(struct irq_data *d)
427{
428 struct sx150x_pinctrl *pctl =
429 gpiochip_get_data(irq_data_get_irq_chip_data(d));
430 unsigned int n = d->hwirq;
431
6489677f 432 pctl->irq.masked |= BIT(n);
9e80f906
NA		 433}
434
435static void sx150x_irq_unmask(struct irq_data *d)
436{
437 struct sx150x_pinctrl *pctl =
438 gpiochip_get_data(irq_data_get_irq_chip_data(d));
439 unsigned int n = d->hwirq;
440
6489677f 441 pctl->irq.masked &= ~BIT(n);
9e80f906
NA		 442}
443
444static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
445{
446 struct sx150x_pinctrl *pctl =
447 gpiochip_get_data(irq_data_get_irq_chip_data(d));
448 unsigned int n, val = 0;
449
450 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
451 return -EINVAL;
452
453 n = d->hwirq;
454
455 if (flow_type & IRQ_TYPE_EDGE_RISING)
456 val |= 0x1;
457 if (flow_type & IRQ_TYPE_EDGE_FALLING)
458 val |= 0x2;
459
460 pctl->irq.sense &= ~(3UL << (n * 2));
461 pctl->irq.sense |= val << (n * 2);
9e80f906
NA		 462 return 0;
463}
464
465static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
466{
467 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
05a90cc7 468 unsigned long n, status;
0db0f26c 469 unsigned int val;
05a90cc7 470 int err;
9e80f906 471
6489677f
AS		 472 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
473 if (err < 0)
474 return IRQ_NONE;
9e80f906 475
6489677f
AS		 476 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
477 if (err < 0)
478 return IRQ_NONE;
479
05a90cc7
AS		 480 status = val;
481 for_each_set_bit(n, &status, pctl->data->ngpios)
482 handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
9e80f906 483
05a90cc7 484 return IRQ_HANDLED;
9e80f906
NA		 485}
486
487static void sx150x_irq_bus_lock(struct irq_data *d)
488{
489 struct sx150x_pinctrl *pctl =
490 gpiochip_get_data(irq_data_get_irq_chip_data(d));
491
492 mutex_lock(&pctl->lock);
493}
494
495static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
496{
497 struct sx150x_pinctrl *pctl =
498 gpiochip_get_data(irq_data_get_irq_chip_data(d));
9e80f906 499
6489677f
AS		 500 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
501 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
9e80f906
NA		 502 mutex_unlock(&pctl->lock);
503}
504
505static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
506 unsigned long *config)
507{
508 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
509 unsigned int param = pinconf_to_config_param(*config);
510 int ret;
511 u32 arg;
6489677f 512 unsigned int data;
9e80f906
NA		 513
514 if (sx150x_pin_is_oscio(pctl, pin)) {
9e80f906
NA		 515 switch (param) {
516 case PIN_CONFIG_DRIVE_PUSH_PULL:
517 case PIN_CONFIG_OUTPUT:
0db0f26c
AS		 518 ret = regmap_read(pctl->regmap,
519 pctl->data->pri.x789.reg_clock,
520 &data);
9e80f906
NA		 521 if (ret < 0)
522 return ret;
523
524 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
525 arg = (data & 0x1f) ? 1 : 0;
526 else {
527 if ((data & 0x1f) == 0x1f)
528 arg = 1;
529 else if ((data & 0x1f) == 0x10)
530 arg = 0;
531 else
532 return -EINVAL;
533 }
534
535 break;
536 default:
537 return -ENOTSUPP;
538 }
539
540 goto out;
541 }
542
543 switch (param) {
544 case PIN_CONFIG_BIAS_PULL_DOWN:
6489677f
AS		 545 ret = regmap_read(pctl->regmap,
546 pctl->data->reg_pulldn,
547 &data);
548 data &= BIT(pin);
9e80f906
NA		 549
550 if (ret < 0)
551 return ret;
552
553 if (!ret)
554 return -EINVAL;
555
556 arg = 1;
557 break;
558
559 case PIN_CONFIG_BIAS_PULL_UP:
6489677f
AS		 560 ret = regmap_read(pctl->regmap,
561 pctl->data->reg_pullup,
562 &data);
563 data &= BIT(pin);
9e80f906
NA		 564
565 if (ret < 0)
566 return ret;
567
568 if (!ret)
569 return -EINVAL;
570
571 arg = 1;
572 break;
573
574 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
575 if (pctl->data->model != SX150X_789)
576 return -ENOTSUPP;
577
6489677f
AS		 578 ret = regmap_read(pctl->regmap,
579 pctl->data->pri.x789.reg_drain,
580 &data);
581 data &= BIT(pin);
9e80f906
NA		 582
583 if (ret < 0)
584 return ret;
585
6489677f 586 if (!data)
9e80f906
NA		 587 return -EINVAL;
588
589 arg = 1;
590 break;
591
592 case PIN_CONFIG_DRIVE_PUSH_PULL:
593 if (pctl->data->model != SX150X_789)
594 arg = true;
595 else {
6489677f
AS		 596 ret = regmap_read(pctl->regmap,
597 pctl->data->pri.x789.reg_drain,
598 &data);
599 data &= BIT(pin);
9e80f906
NA		 600
601 if (ret < 0)
602 return ret;
603
6489677f 604 if (data)
9e80f906
NA		 605 return -EINVAL;
606
607 arg = 1;
608 }
609 break;
610
611 case PIN_CONFIG_OUTPUT:
612 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
613 if (ret < 0)
614 return ret;
615
616 if (ret)
617 return -EINVAL;
618
619 ret = sx150x_gpio_get(&pctl->gpio, pin);
620 if (ret < 0)
621 return ret;
622
623 arg = ret;
624 break;
625
626 default:
627 return -ENOTSUPP;
628 }
629
630out:
631 *config = pinconf_to_config_packed(param, arg);
632
633 return 0;
634}
635
636static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
637 unsigned long *configs, unsigned int num_configs)
638{
639 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
640 enum pin_config_param param;
641 u32 arg;
642 int i;
643 int ret;
644
645 for (i = 0; i < num_configs; i++) {
646 param = pinconf_to_config_param(configs[i]);
647 arg = pinconf_to_config_argument(configs[i]);
648
649 if (sx150x_pin_is_oscio(pctl, pin)) {
650 if (param == PIN_CONFIG_OUTPUT) {
651 ret = sx150x_gpio_direction_output(&pctl->gpio,
652 pin, arg);
653 if (ret < 0)
654 return ret;
655
656 continue;
657 } else
658 return -ENOTSUPP;
659 }
660
661 switch (param) {
662 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
663 case PIN_CONFIG_BIAS_DISABLE:
6489677f
AS		 664 ret = regmap_write_bits(pctl->regmap,
665 pctl->data->reg_pulldn,
666 BIT(pin), 0);
9e80f906
NA		 667 if (ret < 0)
668 return ret;
669
6489677f
AS		 670 ret = regmap_write_bits(pctl->regmap,
671 pctl->data->reg_pullup,
672 BIT(pin), 0);
9e80f906
NA		 673 if (ret < 0)
674 return ret;
675
676 break;
677
678 case PIN_CONFIG_BIAS_PULL_UP:
6489677f
AS		 679 ret = regmap_write_bits(pctl->regmap,
680 pctl->data->reg_pullup,
681 BIT(pin), BIT(pin));
9e80f906
NA		 682 if (ret < 0)
683 return ret;
684
685 break;
686
687 case PIN_CONFIG_BIAS_PULL_DOWN:
6489677f
AS		 688 ret = regmap_write_bits(pctl->regmap,
689 pctl->data->reg_pulldn,
690 BIT(pin), BIT(pin));
9e80f906
NA		 691 if (ret < 0)
692 return ret;
693
694 break;
695
696 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
697 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
698 pin, LINE_MODE_OPEN_DRAIN);
699 if (ret < 0)
700 return ret;
701
702 break;
703
704 case PIN_CONFIG_DRIVE_PUSH_PULL:
705 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
706 pin, LINE_MODE_PUSH_PULL);
707 if (ret < 0)
708 return ret;
709
710 break;
711
712 case PIN_CONFIG_OUTPUT:
713 ret = sx150x_gpio_direction_output(&pctl->gpio,
714 pin, arg);
715 if (ret < 0)
716 return ret;
717
718 break;
719
720 default:
721 return -ENOTSUPP;
722 }
723 } /* for each config */
724
725 return 0;
726}
727
728static const struct pinconf_ops sx150x_pinconf_ops = {
729 .pin_config_get = sx150x_pinconf_get,
730 .pin_config_set = sx150x_pinconf_set,
731 .is_generic = true,
732};
733
734static const struct i2c_device_id sx150x_id[] = {
735 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
736 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
737 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
738 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
6697546d 739 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
9e80f906
NA		 740 {}
741};
742
743static const struct of_device_id sx150x_of_match[] = {
e3ba8120
AS		 744 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
745 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
746 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
747 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
6697546d 748 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
9e80f906
NA		 749 {},
750};
751
9e80f906
NA		 752static int sx150x_reset(struct sx150x_pinctrl *pctl)
753{
754 int err;
755
756 err = i2c_smbus_write_byte_data(pctl->client,
757 pctl->data->pri.x789.reg_reset,
758 0x12);
759 if (err < 0)
760 return err;
761
762 err = i2c_smbus_write_byte_data(pctl->client,
763 pctl->data->pri.x789.reg_reset,
764 0x34);
765 return err;
766}
767
310cdfa0
AS		 768static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
769{
770 u8 reg, value;
771
772 switch (pctl->data->model) {
773 case SX150X_789:
774 reg = pctl->data->pri.x789.reg_misc;
775 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
776 break;
777 case SX150X_456:
778 reg = pctl->data->pri.x456.reg_advance;
779 value = 0x00;
b30d31e4
AS		 780
781 /*
782 * Only SX1506 has RegAdvanced, SX1504/5 are expected
783 * to initialize this offset to zero
784 */
785 if (!reg)
786 return 0;
310cdfa0
AS		 787 break;
788 case SX150X_123:
789 reg = pctl->data->pri.x123.reg_advance;
790 value = 0x00;
791 break;
792 default:
793 WARN(1, "Unknown chip model %d\n", pctl->data->model);
794 return -EINVAL;
795 }
796
6489677f 797 return regmap_write(pctl->regmap, reg, value);
310cdfa0
AS		 798}
799
9e80f906
NA		 800static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
801{
6489677f
AS		 802 const u8 reg[] = {
803 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
804 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
805 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
806 };
9e80f906
NA		 807 int err;
808
809 if (pctl->data->model == SX150X_789 &&
810 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
811 err = sx150x_reset(pctl);
812 if (err < 0)
813 return err;
814 }
815
310cdfa0 816 err = sx150x_init_misc(pctl);
9e80f906
NA		 817 if (err < 0)
818 return err;
819
820 /* Set all pins to work in normal mode */
6489677f
AS		 821 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
822}
823
824static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
825 unsigned int reg)
826{
827 const struct sx150x_device_data *data = pctl->data;
828
829 if (reg == data->reg_sense) {
830 /*
831 * RegSense packs two bits of configuration per GPIO,
832 * so we'd need to read twice as many bits as there
833 * are GPIO in our chip
834 */
835 return 2 * data->ngpios;
836 } else if ((data->model == SX150X_789 &&
837 (reg == data->pri.x789.reg_misc ||
838 reg == data->pri.x789.reg_clock ||
839 reg == data->pri.x789.reg_reset))
840 ||
841 (data->model == SX150X_123 &&
842 reg == data->pri.x123.reg_advance)
843 ||
844 (data->model == SX150X_456 &&
845 reg == data->pri.x456.reg_advance)) {
846 return 8;
9e80f906 847 } else {
6489677f
AS		 848 return data->ngpios;
849 }
850}
851
852static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
853 unsigned int reg, unsigned int val)
854{
855 unsigned int a, b;
856 const struct sx150x_device_data *data = pctl->data;
857
858 /*
859 * Whereas SX1509 presents RegSense in a simple layout as such:
860 * reg [ f f e e d d c c ]
861 * reg + 1 [ b b a a 9 9 8 8 ]
862 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
863 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
864 *
865 * SX1503 and SX1506 deviate from that data layout, instead storing
866 * thier contents as follows:
867 *
868 * reg [ f f e e d d c c ]
869 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
870 * reg + 2 [ b b a a 9 9 8 8 ]
871 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
872 *
873 * so, taking that into account, we swap two
874 * inner bytes of a 4-byte result
875 */
876
877 if (reg == data->reg_sense &&
878 data->ngpios == 16 &&
879 (data->model == SX150X_123 ||
880 data->model == SX150X_456)) {
881 a = val & 0x00ff0000;
882 b = val & 0x0000ff00;
883
884 val &= 0xff0000ff;
885 val |= b << 8;
886 val |= a >> 8;
9e80f906
NA		 887 }
888
6489677f
AS		 889 return val;
890}
891
892/*
893 * In order to mask the differences between 16 and 8 bit expander
894 * devices we set up a sligthly ficticious regmap that pretends to be
895 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
896 * pair/quartet) registers and transparently reconstructs those
897 * registers via multiple I2C/SMBus reads
898 *
899 * This way the rest of the driver code, interfacing with the chip via
900 * regmap API, can work assuming that each GPIO pin is represented by
901 * a group of bits at an offset proportioan to GPIO number within a
902 * given register.
903 *
904 */
905static int sx150x_regmap_reg_read(void *context, unsigned int reg,
906 unsigned int *result)
907{
908 int ret, n;
909 struct sx150x_pinctrl *pctl = context;
910 struct i2c_client *i2c = pctl->client;
911 const int width = sx150x_regmap_reg_width(pctl, reg);
912 unsigned int idx, val;
913
914 /*
915 * There are four potential cases coverd by this function:
916 *
917 * 1) 8-pin chip, single configuration bit register
918 *
919 * This is trivial the code below just needs to read:
920 * reg [ 7 6 5 4 3 2 1 0 ]
921 *
922 * 2) 8-pin chip, double configuration bit register (RegSense)
923 *
924 * The read will be done as follows:
925 * reg [ 7 7 6 6 5 5 4 4 ]
926 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
927 *
928 * 3) 16-pin chip, single configuration bit register
929 *
930 * The read will be done as follows:
931 * reg [ f e d c b a 9 8 ]
932 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
933 *
934 * 4) 16-pin chip, double configuration bit register (RegSense)
935 *
936 * The read will be done as follows:
937 * reg [ f f e e d d c c ]
938 * reg + 1 [ b b a a 9 9 8 8 ]
939 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
940 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
941 */
942
943 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
944 val <<= 8;
945
946 ret = i2c_smbus_read_byte_data(i2c, idx);
947 if (ret < 0)
948 return ret;
949
950 val |= ret;
951 }
952
953 *result = sx150x_maybe_swizzle(pctl, reg, val);
954
955 return 0;
956}
957
958static int sx150x_regmap_reg_write(void *context, unsigned int reg,
959 unsigned int val)
960{
961 int ret, n;
962 struct sx150x_pinctrl *pctl = context;
963 struct i2c_client *i2c = pctl->client;
964 const int width = sx150x_regmap_reg_width(pctl, reg);
965
966 val = sx150x_maybe_swizzle(pctl, reg, val);
967
968 n = width - 8;
969 do {
970 const u8 byte = (val >> n) & 0xff;
971
972 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
973 if (ret < 0)
974 return ret;
975
976 reg++;
977 n -= 8;
978 } while (n >= 0);
979
9e80f906
NA		 980 return 0;
981}
982
0db0f26c
AS		 983static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
984{
985 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
986
6489677f 987 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
0db0f26c
AS		 988}
989
990const struct regmap_config sx150x_regmap_config = {
991 .reg_bits = 8,
6489677f 992 .val_bits = 32,
0db0f26c
AS		 993
994 .cache_type = REGCACHE_RBTREE,
995
6489677f
AS		 996 .reg_read = sx150x_regmap_reg_read,
997 .reg_write = sx150x_regmap_reg_write,
998
0db0f26c
AS		 999 .max_register = SX150X_MAX_REGISTER,
1000 .volatile_reg = sx150x_reg_volatile,
1001};
1002
9e80f906
NA		 1003static int sx150x_probe(struct i2c_client *client,
1004 const struct i2c_device_id *id)
1005{
1006 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1007 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1008 struct device *dev = &client->dev;
1009 struct sx150x_pinctrl *pctl;
1010 int ret;
1011
9e80f906
NA		 1012 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1013 return -ENOSYS;
1014
1015 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1016 if (!pctl)
1017 return -ENOMEM;
1018
0db0f26c
AS		 1019 i2c_set_clientdata(client, pctl);
1020
9e80f906
NA		 1021 pctl->dev = dev;
1022 pctl->client = client;
e3ba8120
AS		 1023
1024 if (dev->of_node)
1025 pctl->data = of_device_get_match_data(dev);
1026 else
1027 pctl->data = (struct sx150x_device_data *)id->driver_data;
1028
1029 if (!pctl->data)
1030 return -EINVAL;
9e80f906 1031
6489677f
AS		 1032 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1033 &sx150x_regmap_config);
0db0f26c
AS		 1034 if (IS_ERR(pctl->regmap)) {
1035 ret = PTR_ERR(pctl->regmap);
1036 dev_err(dev, "Failed to allocate register map: %d\n",
1037 ret);
1038 return ret;
1039 }
1040
9e80f906
NA		 1041 mutex_init(&pctl->lock);
1042
1043 ret = sx150x_init_hw(pctl);
1044 if (ret)
1045 return ret;
1046
1047 /* Register GPIO controller */
1048 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1049 pctl->gpio.base = -1;
1050 pctl->gpio.ngpio = pctl->data->npins;
1051 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1052 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1053 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1054 pctl->gpio.get = sx150x_gpio_get;
1055 pctl->gpio.set = sx150x_gpio_set;
1056 pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended;
1057 pctl->gpio.parent = dev;
1058#ifdef CONFIG_OF_GPIO
1059 pctl->gpio.of_node = dev->of_node;
1060#endif
1061 pctl->gpio.can_sleep = true;
1062
1063 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1064 if (ret)
1065 return ret;
1066
1067 /* Add Interrupt support if an irq is specified */
1068 if (client->irq > 0) {
1069 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1070 GFP_KERNEL);
1071 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1072 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1073 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1074 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1075 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1076
1077 pctl->irq.masked = ~0;
1078 pctl->irq.sense = 0;
9e80f906 1079
080c489d
AS		 1080 /*
1081 * Because sx150x_irq_threaded_fn invokes all of the
1082 * nested interrrupt handlers via handle_nested_irq,
1083 * any "handler" passed to gpiochip_irqchip_add()
1084 * below is going to be ignored, so the choice of the
1085 * function does not matter that much.
1086 *
1087 * We set it to handle_bad_irq to avoid confusion,
1088 * plus it will be instantly noticeable if it is ever
1089 * called (should not happen)
1090 */
9e80f906
NA		 1091 ret = gpiochip_irqchip_add(&pctl->gpio,
1092 &pctl->irq_chip, 0,
080c489d 1093 handle_bad_irq, IRQ_TYPE_NONE);
9e80f906
NA		 1094 if (ret) {
1095 dev_err(dev, "could not connect irqchip to gpiochip\n");
1096 return ret;
1097 }
1098
1099 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1100 sx150x_irq_thread_fn,
1101 IRQF_ONESHOT | IRQF_SHARED |
1102 IRQF_TRIGGER_FALLING,
1103 pctl->irq_chip.name, pctl);
1104 if (ret < 0)
1105 return ret;
1106 }
1107
1108 /* Pinctrl_desc */
1109 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1110 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1111 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1112 pctl->pinctrl_desc.pins = pctl->data->pins;
1113 pctl->pinctrl_desc.npins = pctl->data->npins;
1114 pctl->pinctrl_desc.owner = THIS_MODULE;
1115
1116 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl);
1117 if (IS_ERR(pctl->pctldev)) {
1118 dev_err(dev, "Failed to register pinctrl device\n");
1119 return PTR_ERR(pctl->pctldev);
1120 }
1121
1122 return 0;
1123}
1124
1125static struct i2c_driver sx150x_driver = {
1126 .driver = {
1127 .name = "sx150x-pinctrl",
1128 .of_match_table = of_match_ptr(sx150x_of_match),
1129 },
1130 .probe = sx150x_probe,
1131 .id_table = sx150x_id,
1132};
1133
1134static int __init sx150x_init(void)
1135{
1136 return i2c_add_driver(&sx150x_driver);
1137}
1138subsys_initcall(sx150x_init);
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