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pinctrl: sx150x: use correct registers for reg_sense (sx1502 and sx1508)
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / pinctrl-sx150x.c
CommitLineData
9e80f906
NA		 1/*
2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
6 *
7 * Driver for Semtech SX150X I2C GPIO Expanders
8 *
9 * Author: Gregory Bean <gbean@codeaurora.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 and
13 * only version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
0db0f26c 21#include <linux/regmap.h>
9e80f906
NA		 22#include <linux/i2c.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/mutex.h>
27#include <linux/slab.h>
28#include <linux/of.h>
e3ba8120 29#include <linux/of_device.h>
fc669d13 30#include <linux/gpio/driver.h>
9e80f906
NA		 31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinctrl.h>
33#include <linux/pinctrl/pinmux.h>
34#include <linux/pinctrl/pinconf-generic.h>
35
36#include "core.h"
37#include "pinconf.h"
38#include "pinctrl-utils.h"
39
40/* The chip models of sx150x */
41enum {
42 SX150X_123 = 0,
43 SX150X_456,
44 SX150X_789,
45};
7d68a79a
AS		 46enum {
47 SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
0db0f26c 48 SX150X_MAX_REGISTER = 0xad,
fd931f23
AS		 49 SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
50 SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
f9038d60
AS		 51 SX150X_789_RESET_KEY1 = 0x12,
52 SX150X_789_RESET_KEY2 = 0x34,
7d68a79a 53};
9e80f906
NA		 54
55struct sx150x_123_pri {
56 u8 reg_pld_mode;
57 u8 reg_pld_table0;
58 u8 reg_pld_table1;
59 u8 reg_pld_table2;
60 u8 reg_pld_table3;
61 u8 reg_pld_table4;
62 u8 reg_advance;
63};
64
65struct sx150x_456_pri {
66 u8 reg_pld_mode;
67 u8 reg_pld_table0;
68 u8 reg_pld_table1;
69 u8 reg_pld_table2;
70 u8 reg_pld_table3;
71 u8 reg_pld_table4;
72 u8 reg_advance;
73};
74
75struct sx150x_789_pri {
76 u8 reg_drain;
77 u8 reg_polarity;
78 u8 reg_clock;
79 u8 reg_misc;
80 u8 reg_reset;
81 u8 ngpios;
82};
83
84struct sx150x_device_data {
85 u8 model;
86 u8 reg_pullup;
87 u8 reg_pulldn;
88 u8 reg_dir;
89 u8 reg_data;
90 u8 reg_irq_mask;
91 u8 reg_irq_src;
92 u8 reg_sense;
93 u8 ngpios;
94 union {
95 struct sx150x_123_pri x123;
96 struct sx150x_456_pri x456;
97 struct sx150x_789_pri x789;
98 } pri;
99 const struct pinctrl_pin_desc *pins;
100 unsigned int npins;
101};
102
103struct sx150x_pinctrl {
104 struct device *dev;
105 struct i2c_client *client;
106 struct pinctrl_dev *pctldev;
107 struct pinctrl_desc pinctrl_desc;
108 struct gpio_chip gpio;
109 struct irq_chip irq_chip;
0db0f26c 110 struct regmap *regmap;
9e80f906 111 struct {
9e80f906
NA		 112 u32 sense;
113 u32 masked;
9e80f906
NA		 114 } irq;
115 struct mutex lock;
116 const struct sx150x_device_data *data;
117};
118
119static const struct pinctrl_pin_desc sx150x_8_pins[] = {
120 PINCTRL_PIN(0, "gpio0"),
121 PINCTRL_PIN(1, "gpio1"),
122 PINCTRL_PIN(2, "gpio2"),
123 PINCTRL_PIN(3, "gpio3"),
124 PINCTRL_PIN(4, "gpio4"),
125 PINCTRL_PIN(5, "gpio5"),
126 PINCTRL_PIN(6, "gpio6"),
127 PINCTRL_PIN(7, "gpio7"),
128 PINCTRL_PIN(8, "oscio"),
129};
130
131static const struct pinctrl_pin_desc sx150x_16_pins[] = {
132 PINCTRL_PIN(0, "gpio0"),
133 PINCTRL_PIN(1, "gpio1"),
134 PINCTRL_PIN(2, "gpio2"),
135 PINCTRL_PIN(3, "gpio3"),
136 PINCTRL_PIN(4, "gpio4"),
137 PINCTRL_PIN(5, "gpio5"),
138 PINCTRL_PIN(6, "gpio6"),
139 PINCTRL_PIN(7, "gpio7"),
140 PINCTRL_PIN(8, "gpio8"),
141 PINCTRL_PIN(9, "gpio9"),
142 PINCTRL_PIN(10, "gpio10"),
143 PINCTRL_PIN(11, "gpio11"),
144 PINCTRL_PIN(12, "gpio12"),
145 PINCTRL_PIN(13, "gpio13"),
146 PINCTRL_PIN(14, "gpio14"),
147 PINCTRL_PIN(15, "gpio15"),
148 PINCTRL_PIN(16, "oscio"),
149};
150
151static const struct sx150x_device_data sx1508q_device_data = {
152 .model = SX150X_789,
153 .reg_pullup = 0x03,
154 .reg_pulldn = 0x04,
155 .reg_dir = 0x07,
156 .reg_data = 0x08,
157 .reg_irq_mask = 0x09,
158 .reg_irq_src = 0x0c,
1663682c 159 .reg_sense = 0x0a,
9e80f906
NA		 160 .pri.x789 = {
161 .reg_drain = 0x05,
162 .reg_polarity = 0x06,
163 .reg_clock = 0x0f,
164 .reg_misc = 0x10,
165 .reg_reset = 0x7d,
166 },
167 .ngpios = 8,
168 .pins = sx150x_8_pins,
169 .npins = ARRAY_SIZE(sx150x_8_pins),
170};
171
172static const struct sx150x_device_data sx1509q_device_data = {
173 .model = SX150X_789,
6489677f
AS		 174 .reg_pullup = 0x06,
175 .reg_pulldn = 0x08,
176 .reg_dir = 0x0e,
177 .reg_data = 0x10,
178 .reg_irq_mask = 0x12,
179 .reg_irq_src = 0x18,
180 .reg_sense = 0x14,
9e80f906 181 .pri.x789 = {
6489677f
AS		 182 .reg_drain = 0x0a,
183 .reg_polarity = 0x0c,
9e80f906
NA		 184 .reg_clock = 0x1e,
185 .reg_misc = 0x1f,
186 .reg_reset = 0x7d,
187 },
188 .ngpios = 16,
189 .pins = sx150x_16_pins,
190 .npins = ARRAY_SIZE(sx150x_16_pins),
191};
192
193static const struct sx150x_device_data sx1506q_device_data = {
194 .model = SX150X_456,
6489677f
AS		 195 .reg_pullup = 0x04,
196 .reg_pulldn = 0x06,
197 .reg_dir = 0x02,
198 .reg_data = 0x00,
199 .reg_irq_mask = 0x08,
200 .reg_irq_src = 0x0e,
201 .reg_sense = 0x0a,
9e80f906 202 .pri.x456 = {
6489677f
AS		 203 .reg_pld_mode = 0x20,
204 .reg_pld_table0 = 0x22,
205 .reg_pld_table1 = 0x24,
206 .reg_pld_table2 = 0x26,
207 .reg_pld_table3 = 0x28,
208 .reg_pld_table4 = 0x2a,
9e80f906
NA		 209 .reg_advance = 0xad,
210 },
211 .ngpios = 16,
212 .pins = sx150x_16_pins,
213 .npins = 16, /* oscio not available */
214};
215
216static const struct sx150x_device_data sx1502q_device_data = {
217 .model = SX150X_123,
218 .reg_pullup = 0x02,
219 .reg_pulldn = 0x03,
220 .reg_dir = 0x01,
221 .reg_data = 0x00,
222 .reg_irq_mask = 0x05,
223 .reg_irq_src = 0x08,
1663682c 224 .reg_sense = 0x06,
9e80f906
NA		 225 .pri.x123 = {
226 .reg_pld_mode = 0x10,
227 .reg_pld_table0 = 0x11,
228 .reg_pld_table1 = 0x12,
229 .reg_pld_table2 = 0x13,
230 .reg_pld_table3 = 0x14,
231 .reg_pld_table4 = 0x15,
232 .reg_advance = 0xad,
233 },
234 .ngpios = 8,
235 .pins = sx150x_8_pins,
236 .npins = 8, /* oscio not available */
237};
238
6697546d
AS		 239static const struct sx150x_device_data sx1503q_device_data = {
240 .model = SX150X_123,
6489677f
AS		 241 .reg_pullup = 0x04,
242 .reg_pulldn = 0x06,
243 .reg_dir = 0x02,
244 .reg_data = 0x00,
245 .reg_irq_mask = 0x08,
246 .reg_irq_src = 0x0e,
247 .reg_sense = 0x0a,
6697546d 248 .pri.x123 = {
6489677f
AS		 249 .reg_pld_mode = 0x20,
250 .reg_pld_table0 = 0x22,
251 .reg_pld_table1 = 0x24,
252 .reg_pld_table2 = 0x26,
253 .reg_pld_table3 = 0x28,
254 .reg_pld_table4 = 0x2a,
6697546d
AS		 255 .reg_advance = 0xad,
256 },
257 .ngpios = 16,
258 .pins = sx150x_16_pins,
259 .npins = 16, /* oscio not available */
260};
261
9e80f906
NA		 262static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
263{
264 return 0;
265}
266
267static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
268 unsigned int group)
269{
270 return NULL;
271}
272
273static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
274 unsigned int group,
275 const unsigned int **pins,
276 unsigned int *num_pins)
277{
278 return -ENOTSUPP;
279}
280
281static const struct pinctrl_ops sx150x_pinctrl_ops = {
282 .get_groups_count = sx150x_pinctrl_get_groups_count,
283 .get_group_name = sx150x_pinctrl_get_group_name,
284 .get_group_pins = sx150x_pinctrl_get_group_pins,
285#ifdef CONFIG_OF
286 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
287 .dt_free_map = pinctrl_utils_free_map,
288#endif
289};
290
291static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
292{
293 if (pin >= pctl->data->npins)
294 return false;
295
296 /* OSCIO pin is only present in 789 devices */
297 if (pctl->data->model != SX150X_789)
298 return false;
299
300 return !strcmp(pctl->data->pins[pin].name, "oscio");
301}
302
303static int sx150x_gpio_get_direction(struct gpio_chip *chip,
304 unsigned int offset)
305{
306 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
6489677f
AS		 307 unsigned int value;
308 int ret;
9e80f906
NA		 309
310 if (sx150x_pin_is_oscio(pctl, offset))
311 return false;
312
6489677f
AS		 313 ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
314 if (ret < 0)
315 return ret;
9e80f906 316
6489677f 317 return !!(value & BIT(offset));
9e80f906
NA		 318}
319
320static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
321{
322 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
6489677f
AS		 323 unsigned int value;
324 int ret;
9e80f906
NA		 325
326 if (sx150x_pin_is_oscio(pctl, offset))
327 return -EINVAL;
328
6489677f
AS		 329 ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
330 if (ret < 0)
331 return ret;
9e80f906 332
6489677f 333 return !!(value & BIT(offset));
9e80f906
NA		 334}
335
336static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
337 unsigned int offset,
338 enum single_ended_mode mode)
339{
340 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
341 int ret;
342
343 switch (mode) {
344 case LINE_MODE_PUSH_PULL:
345 if (pctl->data->model != SX150X_789 ||
346 sx150x_pin_is_oscio(pctl, offset))
347 return 0;
348
6489677f
AS		 349 ret = regmap_write_bits(pctl->regmap,
350 pctl->data->pri.x789.reg_drain,
351 BIT(offset), 0);
9e80f906
NA		 352 break;
353
354 case LINE_MODE_OPEN_DRAIN:
355 if (pctl->data->model != SX150X_789 ||
356 sx150x_pin_is_oscio(pctl, offset))
357 return -ENOTSUPP;
358
6489677f
AS		 359 ret = regmap_write_bits(pctl->regmap,
360 pctl->data->pri.x789.reg_drain,
361 BIT(offset), BIT(offset));
9e80f906 362 break;
9e80f906 363 default:
d977a876
AS		 364 ret = -ENOTSUPP;
365 break;
9e80f906
NA		 366 }
367
d977a876 368 return ret;
9e80f906
NA		 369}
370
6489677f
AS		 371static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
372 int value)
373{
374 return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
375 BIT(offset), value ? BIT(offset) : 0);
376}
377
ab5bd035
AS		 378static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
379 int value)
380{
381 return regmap_write(pctl->regmap,
382 pctl->data->pri.x789.reg_clock,
383 (value ? 0x1f : 0x10));
384}
385
9e80f906 386static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
7bd47496 387 int value)
9e80f906
NA		 388{
389 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
390
d977a876 391 if (sx150x_pin_is_oscio(pctl, offset))
ab5bd035 392 sx150x_gpio_oscio_set(pctl, value);
d977a876 393 else
6489677f 394 __sx150x_gpio_set(pctl, offset, value);
d977a876 395
9e80f906
NA		 396}
397
ec61168b
PR		 398static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
399 unsigned long *mask,
400 unsigned long *bits)
401{
402 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
403
404 regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
405}
406
9e80f906 407static int sx150x_gpio_direction_input(struct gpio_chip *chip,
7bd47496 408 unsigned int offset)
9e80f906
NA		 409{
410 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
9e80f906
NA		 411
412 if (sx150x_pin_is_oscio(pctl, offset))
413 return -EINVAL;
414
d977a876
AS		 415 return regmap_write_bits(pctl->regmap,
416 pctl->data->reg_dir,
417 BIT(offset), BIT(offset));
9e80f906
NA		 418}
419
420static int sx150x_gpio_direction_output(struct gpio_chip *chip,
7bd47496 421 unsigned int offset, int value)
9e80f906
NA		 422{
423 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
d977a876 424 int ret;
9e80f906 425
ab5bd035
AS		 426 if (sx150x_pin_is_oscio(pctl, offset))
427 return sx150x_gpio_oscio_set(pctl, value);
9e80f906 428
d977a876
AS		 429 ret = __sx150x_gpio_set(pctl, offset, value);
430 if (ret < 0)
431 return ret;
9e80f906 432
d977a876
AS		 433 return regmap_write_bits(pctl->regmap,
434 pctl->data->reg_dir,
435 BIT(offset), 0);
9e80f906
NA		 436}
437
438static void sx150x_irq_mask(struct irq_data *d)
439{
440 struct sx150x_pinctrl *pctl =
441 gpiochip_get_data(irq_data_get_irq_chip_data(d));
442 unsigned int n = d->hwirq;
443
6489677f 444 pctl->irq.masked |= BIT(n);
9e80f906
NA		 445}
446
447static void sx150x_irq_unmask(struct irq_data *d)
448{
449 struct sx150x_pinctrl *pctl =
450 gpiochip_get_data(irq_data_get_irq_chip_data(d));
451 unsigned int n = d->hwirq;
452
6489677f 453 pctl->irq.masked &= ~BIT(n);
9e80f906
NA		 454}
455
fd931f23
AS		 456static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
457 unsigned int line, unsigned int sense)
458{
459 /*
460 * Every interrupt line is represented by two bits shifted
461 * proportionally to the line number
462 */
463 const unsigned int n = line * 2;
464 const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
465 SX150X_IRQ_TYPE_EDGE_FALLING) << n);
466
467 pctl->irq.sense &= mask;
468 pctl->irq.sense |= sense << n;
469}
470
9e80f906
NA		 471static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
472{
473 struct sx150x_pinctrl *pctl =
474 gpiochip_get_data(irq_data_get_irq_chip_data(d));
475 unsigned int n, val = 0;
476
477 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
478 return -EINVAL;
479
480 n = d->hwirq;
481
482 if (flow_type & IRQ_TYPE_EDGE_RISING)
fd931f23 483 val |= SX150X_IRQ_TYPE_EDGE_RISING;
9e80f906 484 if (flow_type & IRQ_TYPE_EDGE_FALLING)
fd931f23 485 val |= SX150X_IRQ_TYPE_EDGE_FALLING;
9e80f906 486
fd931f23 487 sx150x_irq_set_sense(pctl, n, val);
9e80f906
NA		 488 return 0;
489}
490
491static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
492{
493 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
05a90cc7 494 unsigned long n, status;
0db0f26c 495 unsigned int val;
05a90cc7 496 int err;
9e80f906 497
6489677f
AS		 498 err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
499 if (err < 0)
500 return IRQ_NONE;
9e80f906 501
6489677f
AS		 502 err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
503 if (err < 0)
504 return IRQ_NONE;
505
05a90cc7
AS		 506 status = val;
507 for_each_set_bit(n, &status, pctl->data->ngpios)
508 handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n));
9e80f906 509
05a90cc7 510 return IRQ_HANDLED;
9e80f906
NA		 511}
512
513static void sx150x_irq_bus_lock(struct irq_data *d)
514{
515 struct sx150x_pinctrl *pctl =
516 gpiochip_get_data(irq_data_get_irq_chip_data(d));
517
518 mutex_lock(&pctl->lock);
519}
520
521static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
522{
523 struct sx150x_pinctrl *pctl =
524 gpiochip_get_data(irq_data_get_irq_chip_data(d));
9e80f906 525
6489677f
AS		 526 regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
527 regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
9e80f906
NA		 528 mutex_unlock(&pctl->lock);
529}
530
531static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
532 unsigned long *config)
533{
534 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
535 unsigned int param = pinconf_to_config_param(*config);
536 int ret;
537 u32 arg;
6489677f 538 unsigned int data;
9e80f906
NA		 539
540 if (sx150x_pin_is_oscio(pctl, pin)) {
9e80f906
NA		 541 switch (param) {
542 case PIN_CONFIG_DRIVE_PUSH_PULL:
543 case PIN_CONFIG_OUTPUT:
0db0f26c
AS		 544 ret = regmap_read(pctl->regmap,
545 pctl->data->pri.x789.reg_clock,
546 &data);
9e80f906
NA		 547 if (ret < 0)
548 return ret;
549
550 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
551 arg = (data & 0x1f) ? 1 : 0;
552 else {
553 if ((data & 0x1f) == 0x1f)
554 arg = 1;
555 else if ((data & 0x1f) == 0x10)
556 arg = 0;
557 else
558 return -EINVAL;
559 }
560
561 break;
562 default:
563 return -ENOTSUPP;
564 }
565
566 goto out;
567 }
568
569 switch (param) {
570 case PIN_CONFIG_BIAS_PULL_DOWN:
6489677f
AS		 571 ret = regmap_read(pctl->regmap,
572 pctl->data->reg_pulldn,
573 &data);
574 data &= BIT(pin);
9e80f906
NA		 575
576 if (ret < 0)
577 return ret;
578
579 if (!ret)
580 return -EINVAL;
581
582 arg = 1;
583 break;
584
585 case PIN_CONFIG_BIAS_PULL_UP:
6489677f
AS		 586 ret = regmap_read(pctl->regmap,
587 pctl->data->reg_pullup,
588 &data);
589 data &= BIT(pin);
9e80f906
NA		 590
591 if (ret < 0)
592 return ret;
593
594 if (!ret)
595 return -EINVAL;
596
597 arg = 1;
598 break;
599
600 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
601 if (pctl->data->model != SX150X_789)
602 return -ENOTSUPP;
603
6489677f
AS		 604 ret = regmap_read(pctl->regmap,
605 pctl->data->pri.x789.reg_drain,
606 &data);
607 data &= BIT(pin);
9e80f906
NA		 608
609 if (ret < 0)
610 return ret;
611
6489677f 612 if (!data)
9e80f906
NA		 613 return -EINVAL;
614
615 arg = 1;
616 break;
617
618 case PIN_CONFIG_DRIVE_PUSH_PULL:
619 if (pctl->data->model != SX150X_789)
620 arg = true;
621 else {
6489677f
AS		 622 ret = regmap_read(pctl->regmap,
623 pctl->data->pri.x789.reg_drain,
624 &data);
625 data &= BIT(pin);
9e80f906
NA		 626
627 if (ret < 0)
628 return ret;
629
6489677f 630 if (data)
9e80f906
NA		 631 return -EINVAL;
632
633 arg = 1;
634 }
635 break;
636
637 case PIN_CONFIG_OUTPUT:
638 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
639 if (ret < 0)
640 return ret;
641
642 if (ret)
643 return -EINVAL;
644
645 ret = sx150x_gpio_get(&pctl->gpio, pin);
646 if (ret < 0)
647 return ret;
648
649 arg = ret;
650 break;
651
652 default:
653 return -ENOTSUPP;
654 }
655
656out:
657 *config = pinconf_to_config_packed(param, arg);
658
659 return 0;
660}
661
662static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
663 unsigned long *configs, unsigned int num_configs)
664{
665 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
666 enum pin_config_param param;
667 u32 arg;
668 int i;
669 int ret;
670
671 for (i = 0; i < num_configs; i++) {
672 param = pinconf_to_config_param(configs[i]);
673 arg = pinconf_to_config_argument(configs[i]);
674
675 if (sx150x_pin_is_oscio(pctl, pin)) {
676 if (param == PIN_CONFIG_OUTPUT) {
677 ret = sx150x_gpio_direction_output(&pctl->gpio,
678 pin, arg);
679 if (ret < 0)
680 return ret;
681
682 continue;
683 } else
684 return -ENOTSUPP;
685 }
686
687 switch (param) {
688 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
689 case PIN_CONFIG_BIAS_DISABLE:
6489677f
AS		 690 ret = regmap_write_bits(pctl->regmap,
691 pctl->data->reg_pulldn,
692 BIT(pin), 0);
9e80f906
NA		 693 if (ret < 0)
694 return ret;
695
6489677f
AS		 696 ret = regmap_write_bits(pctl->regmap,
697 pctl->data->reg_pullup,
698 BIT(pin), 0);
9e80f906
NA		 699 if (ret < 0)
700 return ret;
701
702 break;
703
704 case PIN_CONFIG_BIAS_PULL_UP:
6489677f
AS		 705 ret = regmap_write_bits(pctl->regmap,
706 pctl->data->reg_pullup,
707 BIT(pin), BIT(pin));
9e80f906
NA		 708 if (ret < 0)
709 return ret;
710
711 break;
712
713 case PIN_CONFIG_BIAS_PULL_DOWN:
6489677f
AS		 714 ret = regmap_write_bits(pctl->regmap,
715 pctl->data->reg_pulldn,
716 BIT(pin), BIT(pin));
9e80f906
NA		 717 if (ret < 0)
718 return ret;
719
720 break;
721
722 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
723 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
724 pin, LINE_MODE_OPEN_DRAIN);
725 if (ret < 0)
726 return ret;
727
728 break;
729
730 case PIN_CONFIG_DRIVE_PUSH_PULL:
731 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
732 pin, LINE_MODE_PUSH_PULL);
733 if (ret < 0)
734 return ret;
735
736 break;
737
738 case PIN_CONFIG_OUTPUT:
739 ret = sx150x_gpio_direction_output(&pctl->gpio,
740 pin, arg);
741 if (ret < 0)
742 return ret;
743
744 break;
745
746 default:
747 return -ENOTSUPP;
748 }
749 } /* for each config */
750
751 return 0;
752}
753
754static const struct pinconf_ops sx150x_pinconf_ops = {
755 .pin_config_get = sx150x_pinconf_get,
756 .pin_config_set = sx150x_pinconf_set,
757 .is_generic = true,
758};
759
760static const struct i2c_device_id sx150x_id[] = {
761 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
762 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
763 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
764 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
6697546d 765 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
9e80f906
NA		 766 {}
767};
768
769static const struct of_device_id sx150x_of_match[] = {
e3ba8120
AS		 770 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
771 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
772 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
773 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
6697546d 774 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
9e80f906
NA		 775 {},
776};
777
9e80f906
NA		 778static int sx150x_reset(struct sx150x_pinctrl *pctl)
779{
780 int err;
781
782 err = i2c_smbus_write_byte_data(pctl->client,
783 pctl->data->pri.x789.reg_reset,
f9038d60 784 SX150X_789_RESET_KEY1);
9e80f906
NA		 785 if (err < 0)
786 return err;
787
788 err = i2c_smbus_write_byte_data(pctl->client,
789 pctl->data->pri.x789.reg_reset,
f9038d60 790 SX150X_789_RESET_KEY2);
9e80f906
NA		 791 return err;
792}
793
310cdfa0
AS		 794static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
795{
796 u8 reg, value;
797
798 switch (pctl->data->model) {
799 case SX150X_789:
800 reg = pctl->data->pri.x789.reg_misc;
801 value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
802 break;
803 case SX150X_456:
804 reg = pctl->data->pri.x456.reg_advance;
805 value = 0x00;
b30d31e4
AS		 806
807 /*
808 * Only SX1506 has RegAdvanced, SX1504/5 are expected
809 * to initialize this offset to zero
810 */
811 if (!reg)
812 return 0;
310cdfa0
AS		 813 break;
814 case SX150X_123:
815 reg = pctl->data->pri.x123.reg_advance;
816 value = 0x00;
817 break;
818 default:
819 WARN(1, "Unknown chip model %d\n", pctl->data->model);
820 return -EINVAL;
821 }
822
6489677f 823 return regmap_write(pctl->regmap, reg, value);
310cdfa0
AS		 824}
825
9e80f906
NA		 826static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
827{
6489677f
AS		 828 const u8 reg[] = {
829 [SX150X_789] = pctl->data->pri.x789.reg_polarity,
830 [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
831 [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
832 };
9e80f906
NA		 833 int err;
834
835 if (pctl->data->model == SX150X_789 &&
836 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
837 err = sx150x_reset(pctl);
838 if (err < 0)
839 return err;
840 }
841
310cdfa0 842 err = sx150x_init_misc(pctl);
9e80f906
NA		 843 if (err < 0)
844 return err;
845
846 /* Set all pins to work in normal mode */
6489677f
AS		 847 return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
848}
849
850static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
851 unsigned int reg)
852{
853 const struct sx150x_device_data *data = pctl->data;
854
855 if (reg == data->reg_sense) {
856 /*
857 * RegSense packs two bits of configuration per GPIO,
858 * so we'd need to read twice as many bits as there
859 * are GPIO in our chip
860 */
861 return 2 * data->ngpios;
862 } else if ((data->model == SX150X_789 &&
863 (reg == data->pri.x789.reg_misc ||
864 reg == data->pri.x789.reg_clock ||
865 reg == data->pri.x789.reg_reset))
866 ||
867 (data->model == SX150X_123 &&
868 reg == data->pri.x123.reg_advance)
869 ||
870 (data->model == SX150X_456 &&
871 reg == data->pri.x456.reg_advance)) {
872 return 8;
9e80f906 873 } else {
6489677f
AS		 874 return data->ngpios;
875 }
876}
877
878static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
879 unsigned int reg, unsigned int val)
880{
881 unsigned int a, b;
882 const struct sx150x_device_data *data = pctl->data;
883
884 /*
885 * Whereas SX1509 presents RegSense in a simple layout as such:
886 * reg [ f f e e d d c c ]
887 * reg + 1 [ b b a a 9 9 8 8 ]
888 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
889 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
890 *
891 * SX1503 and SX1506 deviate from that data layout, instead storing
7bd47496 892 * their contents as follows:
6489677f
AS		 893 *
894 * reg [ f f e e d d c c ]
895 * reg + 1 [ 7 7 6 6 5 5 4 4 ]
896 * reg + 2 [ b b a a 9 9 8 8 ]
897 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
898 *
899 * so, taking that into account, we swap two
900 * inner bytes of a 4-byte result
901 */
902
903 if (reg == data->reg_sense &&
904 data->ngpios == 16 &&
905 (data->model == SX150X_123 ||
906 data->model == SX150X_456)) {
907 a = val & 0x00ff0000;
908 b = val & 0x0000ff00;
909
910 val &= 0xff0000ff;
911 val |= b << 8;
912 val |= a >> 8;
9e80f906
NA		 913 }
914
6489677f
AS		 915 return val;
916}
917
918/*
919 * In order to mask the differences between 16 and 8 bit expander
920 * devices we set up a sligthly ficticious regmap that pretends to be
921 * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh
922 * pair/quartet) registers and transparently reconstructs those
923 * registers via multiple I2C/SMBus reads
924 *
925 * This way the rest of the driver code, interfacing with the chip via
926 * regmap API, can work assuming that each GPIO pin is represented by
7bd47496 927 * a group of bits at an offset proportional to GPIO number within a
6489677f 928 * given register.
6489677f
AS		 929 */
930static int sx150x_regmap_reg_read(void *context, unsigned int reg,
931 unsigned int *result)
932{
933 int ret, n;
934 struct sx150x_pinctrl *pctl = context;
935 struct i2c_client *i2c = pctl->client;
936 const int width = sx150x_regmap_reg_width(pctl, reg);
937 unsigned int idx, val;
938
939 /*
7bd47496 940 * There are four potential cases covered by this function:
6489677f
AS		 941 *
942 * 1) 8-pin chip, single configuration bit register
943 *
944 * This is trivial the code below just needs to read:
945 * reg [ 7 6 5 4 3 2 1 0 ]
946 *
947 * 2) 8-pin chip, double configuration bit register (RegSense)
948 *
949 * The read will be done as follows:
950 * reg [ 7 7 6 6 5 5 4 4 ]
951 * reg + 1 [ 3 3 2 2 1 1 0 0 ]
952 *
953 * 3) 16-pin chip, single configuration bit register
954 *
955 * The read will be done as follows:
956 * reg [ f e d c b a 9 8 ]
957 * reg + 1 [ 7 6 5 4 3 2 1 0 ]
958 *
959 * 4) 16-pin chip, double configuration bit register (RegSense)
960 *
961 * The read will be done as follows:
962 * reg [ f f e e d d c c ]
963 * reg + 1 [ b b a a 9 9 8 8 ]
964 * reg + 2 [ 7 7 6 6 5 5 4 4 ]
965 * reg + 3 [ 3 3 2 2 1 1 0 0 ]
966 */
967
968 for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
969 val <<= 8;
970
971 ret = i2c_smbus_read_byte_data(i2c, idx);
972 if (ret < 0)
973 return ret;
974
975 val |= ret;
976 }
977
978 *result = sx150x_maybe_swizzle(pctl, reg, val);
979
980 return 0;
981}
982
983static int sx150x_regmap_reg_write(void *context, unsigned int reg,
984 unsigned int val)
985{
986 int ret, n;
987 struct sx150x_pinctrl *pctl = context;
988 struct i2c_client *i2c = pctl->client;
989 const int width = sx150x_regmap_reg_width(pctl, reg);
990
991 val = sx150x_maybe_swizzle(pctl, reg, val);
992
993 n = width - 8;
994 do {
995 const u8 byte = (val >> n) & 0xff;
996
997 ret = i2c_smbus_write_byte_data(i2c, reg, byte);
998 if (ret < 0)
999 return ret;
1000
1001 reg++;
1002 n -= 8;
1003 } while (n >= 0);
1004
9e80f906
NA		 1005 return 0;
1006}
1007
0db0f26c
AS		 1008static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1009{
1010 struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1011
6489677f 1012 return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
0db0f26c
AS		 1013}
1014
1015const struct regmap_config sx150x_regmap_config = {
1016 .reg_bits = 8,
6489677f 1017 .val_bits = 32,
0db0f26c
AS		 1018
1019 .cache_type = REGCACHE_RBTREE,
1020
6489677f
AS		 1021 .reg_read = sx150x_regmap_reg_read,
1022 .reg_write = sx150x_regmap_reg_write,
1023
0db0f26c
AS		 1024 .max_register = SX150X_MAX_REGISTER,
1025 .volatile_reg = sx150x_reg_volatile,
1026};
1027
9e80f906
NA		 1028static int sx150x_probe(struct i2c_client *client,
1029 const struct i2c_device_id *id)
1030{
1031 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1032 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1033 struct device *dev = &client->dev;
1034 struct sx150x_pinctrl *pctl;
1035 int ret;
1036
9e80f906
NA		 1037 if (!i2c_check_functionality(client->adapter, i2c_funcs))
1038 return -ENOSYS;
1039
1040 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1041 if (!pctl)
1042 return -ENOMEM;
1043
0db0f26c
AS		 1044 i2c_set_clientdata(client, pctl);
1045
9e80f906
NA		 1046 pctl->dev = dev;
1047 pctl->client = client;
e3ba8120
AS		 1048
1049 if (dev->of_node)
1050 pctl->data = of_device_get_match_data(dev);
1051 else
1052 pctl->data = (struct sx150x_device_data *)id->driver_data;
1053
1054 if (!pctl->data)
1055 return -EINVAL;
9e80f906 1056
6489677f
AS		 1057 pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1058 &sx150x_regmap_config);
0db0f26c
AS		 1059 if (IS_ERR(pctl->regmap)) {
1060 ret = PTR_ERR(pctl->regmap);
1061 dev_err(dev, "Failed to allocate register map: %d\n",
1062 ret);
1063 return ret;
1064 }
1065
9e80f906
NA		 1066 mutex_init(&pctl->lock);
1067
1068 ret = sx150x_init_hw(pctl);
1069 if (ret)
1070 return ret;
1071
1072 /* Register GPIO controller */
1073 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1074 pctl->gpio.base = -1;
1075 pctl->gpio.ngpio = pctl->data->npins;
1076 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1077 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1078 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1079 pctl->gpio.get = sx150x_gpio_get;
1080 pctl->gpio.set = sx150x_gpio_set;
1081 pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended;
1082 pctl->gpio.parent = dev;
1083#ifdef CONFIG_OF_GPIO
1084 pctl->gpio.of_node = dev->of_node;
1085#endif
1086 pctl->gpio.can_sleep = true;
ec61168b
PR		 1087 /*
1088 * Setting multiple pins is not safe when all pins are not
1089 * handled by the same regmap register. The oscio pin (present
1090 * on the SX150X_789 chips) lives in its own register, so
1091 * would require locking that is not in place at this time.
1092 */
1093 if (pctl->data->model != SX150X_789)
1094 pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
9e80f906
NA		 1095
1096 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1097 if (ret)
1098 return ret;
1099
1100 /* Add Interrupt support if an irq is specified */
1101 if (client->irq > 0) {
1102 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1103 GFP_KERNEL);
1104 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1105 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1106 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1107 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1108 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1109
1110 pctl->irq.masked = ~0;
1111 pctl->irq.sense = 0;
9e80f906 1112
080c489d
AS		 1113 /*
1114 * Because sx150x_irq_threaded_fn invokes all of the
1115 * nested interrrupt handlers via handle_nested_irq,
1116 * any "handler" passed to gpiochip_irqchip_add()
1117 * below is going to be ignored, so the choice of the
1118 * function does not matter that much.
1119 *
1120 * We set it to handle_bad_irq to avoid confusion,
1121 * plus it will be instantly noticeable if it is ever
1122 * called (should not happen)
1123 */
9e80f906
NA		 1124 ret = gpiochip_irqchip_add(&pctl->gpio,
1125 &pctl->irq_chip, 0,
080c489d 1126 handle_bad_irq, IRQ_TYPE_NONE);
9e80f906
NA		 1127 if (ret) {
1128 dev_err(dev, "could not connect irqchip to gpiochip\n");
1129 return ret;
1130 }
1131
1132 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1133 sx150x_irq_thread_fn,
1134 IRQF_ONESHOT | IRQF_SHARED |
1135 IRQF_TRIGGER_FALLING,
1136 pctl->irq_chip.name, pctl);
1137 if (ret < 0)
1138 return ret;
1139 }
1140
1141 /* Pinctrl_desc */
1142 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1143 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1144 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1145 pctl->pinctrl_desc.pins = pctl->data->pins;
1146 pctl->pinctrl_desc.npins = pctl->data->npins;
1147 pctl->pinctrl_desc.owner = THIS_MODULE;
1148
1149 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl);
1150 if (IS_ERR(pctl->pctldev)) {
1151 dev_err(dev, "Failed to register pinctrl device\n");
1152 return PTR_ERR(pctl->pctldev);
1153 }
1154
1155 return 0;
1156}
1157
1158static struct i2c_driver sx150x_driver = {
1159 .driver = {
1160 .name = "sx150x-pinctrl",
1161 .of_match_table = of_match_ptr(sx150x_of_match),
1162 },
1163 .probe = sx150x_probe,
1164 .id_table = sx150x_id,
1165};
1166
1167static int __init sx150x_init(void)
1168{
1169 return i2c_add_driver(&sx150x_driver);
1170}
1171subsys_initcall(sx150x_init);
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