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9e80f906 NA |
1 | /* |
2 | * Copyright (c) 2016, BayLibre, SAS. All rights reserved. | |
3 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
4 | * | |
5 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | |
6 | * | |
7 | * Driver for Semtech SX150X I2C GPIO Expanders | |
8 | * | |
9 | * Author: Gregory Bean <gbean@codeaurora.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 and | |
13 | * only version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | */ | |
20 | ||
21 | #include <linux/i2c.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/mutex.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/of.h> | |
e3ba8120 | 28 | #include <linux/of_device.h> |
9e80f906 NA |
29 | #include <linux/gpio.h> |
30 | #include <linux/pinctrl/machine.h> | |
31 | #include <linux/pinctrl/pinconf.h> | |
32 | #include <linux/pinctrl/pinctrl.h> | |
33 | #include <linux/pinctrl/pinmux.h> | |
34 | #include <linux/pinctrl/pinconf-generic.h> | |
35 | ||
36 | #include "core.h" | |
37 | #include "pinconf.h" | |
38 | #include "pinctrl-utils.h" | |
39 | ||
40 | /* The chip models of sx150x */ | |
41 | enum { | |
42 | SX150X_123 = 0, | |
43 | SX150X_456, | |
44 | SX150X_789, | |
45 | }; | |
7d68a79a AS |
46 | enum { |
47 | SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, | |
48 | }; | |
9e80f906 NA |
49 | |
50 | struct sx150x_123_pri { | |
51 | u8 reg_pld_mode; | |
52 | u8 reg_pld_table0; | |
53 | u8 reg_pld_table1; | |
54 | u8 reg_pld_table2; | |
55 | u8 reg_pld_table3; | |
56 | u8 reg_pld_table4; | |
57 | u8 reg_advance; | |
58 | }; | |
59 | ||
60 | struct sx150x_456_pri { | |
61 | u8 reg_pld_mode; | |
62 | u8 reg_pld_table0; | |
63 | u8 reg_pld_table1; | |
64 | u8 reg_pld_table2; | |
65 | u8 reg_pld_table3; | |
66 | u8 reg_pld_table4; | |
67 | u8 reg_advance; | |
68 | }; | |
69 | ||
70 | struct sx150x_789_pri { | |
71 | u8 reg_drain; | |
72 | u8 reg_polarity; | |
73 | u8 reg_clock; | |
74 | u8 reg_misc; | |
75 | u8 reg_reset; | |
76 | u8 ngpios; | |
77 | }; | |
78 | ||
79 | struct sx150x_device_data { | |
80 | u8 model; | |
81 | u8 reg_pullup; | |
82 | u8 reg_pulldn; | |
83 | u8 reg_dir; | |
84 | u8 reg_data; | |
85 | u8 reg_irq_mask; | |
86 | u8 reg_irq_src; | |
87 | u8 reg_sense; | |
88 | u8 ngpios; | |
89 | union { | |
90 | struct sx150x_123_pri x123; | |
91 | struct sx150x_456_pri x456; | |
92 | struct sx150x_789_pri x789; | |
93 | } pri; | |
94 | const struct pinctrl_pin_desc *pins; | |
95 | unsigned int npins; | |
96 | }; | |
97 | ||
98 | struct sx150x_pinctrl { | |
99 | struct device *dev; | |
100 | struct i2c_client *client; | |
101 | struct pinctrl_dev *pctldev; | |
102 | struct pinctrl_desc pinctrl_desc; | |
103 | struct gpio_chip gpio; | |
104 | struct irq_chip irq_chip; | |
105 | struct { | |
106 | int update; | |
107 | u32 sense; | |
108 | u32 masked; | |
109 | u32 dev_sense; | |
110 | u32 dev_masked; | |
111 | } irq; | |
112 | struct mutex lock; | |
113 | const struct sx150x_device_data *data; | |
114 | }; | |
115 | ||
116 | static const struct pinctrl_pin_desc sx150x_8_pins[] = { | |
117 | PINCTRL_PIN(0, "gpio0"), | |
118 | PINCTRL_PIN(1, "gpio1"), | |
119 | PINCTRL_PIN(2, "gpio2"), | |
120 | PINCTRL_PIN(3, "gpio3"), | |
121 | PINCTRL_PIN(4, "gpio4"), | |
122 | PINCTRL_PIN(5, "gpio5"), | |
123 | PINCTRL_PIN(6, "gpio6"), | |
124 | PINCTRL_PIN(7, "gpio7"), | |
125 | PINCTRL_PIN(8, "oscio"), | |
126 | }; | |
127 | ||
128 | static const struct pinctrl_pin_desc sx150x_16_pins[] = { | |
129 | PINCTRL_PIN(0, "gpio0"), | |
130 | PINCTRL_PIN(1, "gpio1"), | |
131 | PINCTRL_PIN(2, "gpio2"), | |
132 | PINCTRL_PIN(3, "gpio3"), | |
133 | PINCTRL_PIN(4, "gpio4"), | |
134 | PINCTRL_PIN(5, "gpio5"), | |
135 | PINCTRL_PIN(6, "gpio6"), | |
136 | PINCTRL_PIN(7, "gpio7"), | |
137 | PINCTRL_PIN(8, "gpio8"), | |
138 | PINCTRL_PIN(9, "gpio9"), | |
139 | PINCTRL_PIN(10, "gpio10"), | |
140 | PINCTRL_PIN(11, "gpio11"), | |
141 | PINCTRL_PIN(12, "gpio12"), | |
142 | PINCTRL_PIN(13, "gpio13"), | |
143 | PINCTRL_PIN(14, "gpio14"), | |
144 | PINCTRL_PIN(15, "gpio15"), | |
145 | PINCTRL_PIN(16, "oscio"), | |
146 | }; | |
147 | ||
148 | static const struct sx150x_device_data sx1508q_device_data = { | |
149 | .model = SX150X_789, | |
150 | .reg_pullup = 0x03, | |
151 | .reg_pulldn = 0x04, | |
152 | .reg_dir = 0x07, | |
153 | .reg_data = 0x08, | |
154 | .reg_irq_mask = 0x09, | |
155 | .reg_irq_src = 0x0c, | |
156 | .reg_sense = 0x0b, | |
157 | .pri.x789 = { | |
158 | .reg_drain = 0x05, | |
159 | .reg_polarity = 0x06, | |
160 | .reg_clock = 0x0f, | |
161 | .reg_misc = 0x10, | |
162 | .reg_reset = 0x7d, | |
163 | }, | |
164 | .ngpios = 8, | |
165 | .pins = sx150x_8_pins, | |
166 | .npins = ARRAY_SIZE(sx150x_8_pins), | |
167 | }; | |
168 | ||
169 | static const struct sx150x_device_data sx1509q_device_data = { | |
170 | .model = SX150X_789, | |
171 | .reg_pullup = 0x07, | |
172 | .reg_pulldn = 0x09, | |
173 | .reg_dir = 0x0f, | |
174 | .reg_data = 0x11, | |
175 | .reg_irq_mask = 0x13, | |
176 | .reg_irq_src = 0x19, | |
177 | .reg_sense = 0x17, | |
178 | .pri.x789 = { | |
179 | .reg_drain = 0x0b, | |
180 | .reg_polarity = 0x0d, | |
181 | .reg_clock = 0x1e, | |
182 | .reg_misc = 0x1f, | |
183 | .reg_reset = 0x7d, | |
184 | }, | |
185 | .ngpios = 16, | |
186 | .pins = sx150x_16_pins, | |
187 | .npins = ARRAY_SIZE(sx150x_16_pins), | |
188 | }; | |
189 | ||
190 | static const struct sx150x_device_data sx1506q_device_data = { | |
191 | .model = SX150X_456, | |
192 | .reg_pullup = 0x05, | |
193 | .reg_pulldn = 0x07, | |
194 | .reg_dir = 0x03, | |
195 | .reg_data = 0x01, | |
196 | .reg_irq_mask = 0x09, | |
197 | .reg_irq_src = 0x0f, | |
198 | .reg_sense = 0x0d, | |
199 | .pri.x456 = { | |
200 | .reg_pld_mode = 0x21, | |
201 | .reg_pld_table0 = 0x23, | |
202 | .reg_pld_table1 = 0x25, | |
203 | .reg_pld_table2 = 0x27, | |
204 | .reg_pld_table3 = 0x29, | |
205 | .reg_pld_table4 = 0x2b, | |
206 | .reg_advance = 0xad, | |
207 | }, | |
208 | .ngpios = 16, | |
209 | .pins = sx150x_16_pins, | |
210 | .npins = 16, /* oscio not available */ | |
211 | }; | |
212 | ||
213 | static const struct sx150x_device_data sx1502q_device_data = { | |
214 | .model = SX150X_123, | |
215 | .reg_pullup = 0x02, | |
216 | .reg_pulldn = 0x03, | |
217 | .reg_dir = 0x01, | |
218 | .reg_data = 0x00, | |
219 | .reg_irq_mask = 0x05, | |
220 | .reg_irq_src = 0x08, | |
221 | .reg_sense = 0x07, | |
222 | .pri.x123 = { | |
223 | .reg_pld_mode = 0x10, | |
224 | .reg_pld_table0 = 0x11, | |
225 | .reg_pld_table1 = 0x12, | |
226 | .reg_pld_table2 = 0x13, | |
227 | .reg_pld_table3 = 0x14, | |
228 | .reg_pld_table4 = 0x15, | |
229 | .reg_advance = 0xad, | |
230 | }, | |
231 | .ngpios = 8, | |
232 | .pins = sx150x_8_pins, | |
233 | .npins = 8, /* oscio not available */ | |
234 | }; | |
235 | ||
6697546d AS |
236 | static const struct sx150x_device_data sx1503q_device_data = { |
237 | .model = SX150X_123, | |
238 | .reg_pullup = 0x05, | |
239 | .reg_pulldn = 0x07, | |
240 | .reg_dir = 0x03, | |
241 | .reg_data = 0x01, | |
242 | .reg_irq_mask = 0x09, | |
243 | .reg_irq_src = 0x0f, | |
244 | .reg_sense = 0x07, | |
245 | .pri.x123 = { | |
246 | .reg_pld_mode = 0x10, | |
247 | .reg_pld_table0 = 0x11, | |
248 | .reg_pld_table1 = 0x12, | |
249 | .reg_pld_table2 = 0x13, | |
250 | .reg_pld_table3 = 0x14, | |
251 | .reg_pld_table4 = 0x15, | |
252 | .reg_advance = 0xad, | |
253 | }, | |
254 | .ngpios = 16, | |
255 | .pins = sx150x_16_pins, | |
256 | .npins = 16, /* oscio not available */ | |
257 | }; | |
258 | ||
9e80f906 NA |
259 | static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val) |
260 | { | |
261 | s32 err = i2c_smbus_write_byte_data(client, reg, val); | |
262 | ||
263 | if (err < 0) | |
264 | dev_warn(&client->dev, | |
265 | "i2c write fail: can't write %02x to %02x: %d\n", | |
266 | val, reg, err); | |
267 | return err; | |
268 | } | |
269 | ||
270 | static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val) | |
271 | { | |
272 | s32 err = i2c_smbus_read_byte_data(client, reg); | |
273 | ||
274 | if (err >= 0) | |
275 | *val = err; | |
276 | else | |
277 | dev_warn(&client->dev, | |
278 | "i2c read fail: can't read from %02x: %d\n", | |
279 | reg, err); | |
280 | return err; | |
281 | } | |
282 | ||
283 | /* | |
284 | * These utility functions solve the common problem of locating and setting | |
285 | * configuration bits. Configuration bits are grouped into registers | |
286 | * whose indexes increase downwards. For example, with eight-bit registers, | |
287 | * sixteen gpios would have their config bits grouped in the following order: | |
288 | * REGISTER N-1 [ f e d c b a 9 8 ] | |
289 | * N [ 7 6 5 4 3 2 1 0 ] | |
290 | * | |
291 | * For multi-bit configurations, the pattern gets wider: | |
292 | * REGISTER N-3 [ f f e e d d c c ] | |
293 | * N-2 [ b b a a 9 9 8 8 ] | |
294 | * N-1 [ 7 7 6 6 5 5 4 4 ] | |
295 | * N [ 3 3 2 2 1 1 0 0 ] | |
296 | * | |
297 | * Given the address of the starting register 'N', the index of the gpio | |
298 | * whose configuration we seek to change, and the width in bits of that | |
299 | * configuration, these functions allow us to locate the correct | |
300 | * register and mask the correct bits. | |
301 | */ | |
302 | static inline void sx150x_find_cfg(u8 offset, u8 width, | |
303 | u8 *reg, u8 *mask, u8 *shift) | |
304 | { | |
305 | *reg -= offset * width / 8; | |
306 | *mask = (1 << width) - 1; | |
307 | *shift = (offset * width) % 8; | |
308 | *mask <<= *shift; | |
309 | } | |
310 | ||
311 | static int sx150x_write_cfg(struct i2c_client *client, | |
312 | u8 offset, u8 width, u8 reg, u8 val) | |
313 | { | |
314 | u8 mask; | |
315 | u8 data; | |
316 | u8 shift; | |
317 | int err; | |
318 | ||
319 | sx150x_find_cfg(offset, width, ®, &mask, &shift); | |
320 | err = sx150x_i2c_read(client, reg, &data); | |
321 | if (err < 0) | |
322 | return err; | |
323 | ||
324 | data &= ~mask; | |
325 | data |= (val << shift) & mask; | |
326 | return sx150x_i2c_write(client, reg, data); | |
327 | } | |
328 | ||
329 | static int sx150x_read_cfg(struct i2c_client *client, | |
330 | u8 offset, u8 width, u8 reg) | |
331 | { | |
332 | u8 mask; | |
333 | u8 data; | |
334 | u8 shift; | |
335 | int err; | |
336 | ||
337 | sx150x_find_cfg(offset, width, ®, &mask, &shift); | |
338 | err = sx150x_i2c_read(client, reg, &data); | |
339 | if (err < 0) | |
340 | return err; | |
341 | ||
342 | return (data & mask); | |
343 | } | |
344 | ||
345 | static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
346 | { | |
347 | return 0; | |
348 | } | |
349 | ||
350 | static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
351 | unsigned int group) | |
352 | { | |
353 | return NULL; | |
354 | } | |
355 | ||
356 | static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
357 | unsigned int group, | |
358 | const unsigned int **pins, | |
359 | unsigned int *num_pins) | |
360 | { | |
361 | return -ENOTSUPP; | |
362 | } | |
363 | ||
364 | static const struct pinctrl_ops sx150x_pinctrl_ops = { | |
365 | .get_groups_count = sx150x_pinctrl_get_groups_count, | |
366 | .get_group_name = sx150x_pinctrl_get_group_name, | |
367 | .get_group_pins = sx150x_pinctrl_get_group_pins, | |
368 | #ifdef CONFIG_OF | |
369 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
370 | .dt_free_map = pinctrl_utils_free_map, | |
371 | #endif | |
372 | }; | |
373 | ||
374 | static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) | |
375 | { | |
376 | if (pin >= pctl->data->npins) | |
377 | return false; | |
378 | ||
379 | /* OSCIO pin is only present in 789 devices */ | |
380 | if (pctl->data->model != SX150X_789) | |
381 | return false; | |
382 | ||
383 | return !strcmp(pctl->data->pins[pin].name, "oscio"); | |
384 | } | |
385 | ||
386 | static int sx150x_gpio_get_direction(struct gpio_chip *chip, | |
387 | unsigned int offset) | |
388 | { | |
389 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
390 | int status; | |
391 | ||
392 | if (sx150x_pin_is_oscio(pctl, offset)) | |
393 | return false; | |
394 | ||
395 | status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_dir); | |
396 | if (status >= 0) | |
397 | status = !!status; | |
398 | ||
399 | return status; | |
400 | } | |
401 | ||
402 | static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
403 | { | |
404 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
405 | int status; | |
406 | ||
407 | if (sx150x_pin_is_oscio(pctl, offset)) | |
408 | return -EINVAL; | |
409 | ||
410 | status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_data); | |
411 | if (status >= 0) | |
412 | status = !!status; | |
413 | ||
414 | return status; | |
415 | } | |
416 | ||
417 | static int sx150x_gpio_set_single_ended(struct gpio_chip *chip, | |
418 | unsigned int offset, | |
419 | enum single_ended_mode mode) | |
420 | { | |
421 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
422 | int ret; | |
423 | ||
424 | switch (mode) { | |
425 | case LINE_MODE_PUSH_PULL: | |
426 | if (pctl->data->model != SX150X_789 || | |
427 | sx150x_pin_is_oscio(pctl, offset)) | |
428 | return 0; | |
429 | ||
430 | mutex_lock(&pctl->lock); | |
431 | ret = sx150x_write_cfg(pctl->client, offset, 1, | |
432 | pctl->data->pri.x789.reg_drain, | |
433 | 0); | |
434 | mutex_unlock(&pctl->lock); | |
435 | if (ret < 0) | |
436 | return ret; | |
437 | break; | |
438 | ||
439 | case LINE_MODE_OPEN_DRAIN: | |
440 | if (pctl->data->model != SX150X_789 || | |
441 | sx150x_pin_is_oscio(pctl, offset)) | |
442 | return -ENOTSUPP; | |
443 | ||
444 | mutex_lock(&pctl->lock); | |
445 | ret = sx150x_write_cfg(pctl->client, offset, 1, | |
446 | pctl->data->pri.x789.reg_drain, | |
447 | 1); | |
448 | mutex_unlock(&pctl->lock); | |
449 | if (ret < 0) | |
450 | return ret; | |
451 | break; | |
452 | ||
453 | default: | |
454 | return -ENOTSUPP; | |
455 | } | |
456 | ||
457 | return 0; | |
458 | } | |
459 | ||
460 | static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, | |
461 | int value) | |
462 | { | |
463 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
464 | ||
465 | if (sx150x_pin_is_oscio(pctl, offset)) { | |
466 | ||
467 | mutex_lock(&pctl->lock); | |
468 | sx150x_i2c_write(pctl->client, | |
469 | pctl->data->pri.x789.reg_clock, | |
470 | (value ? 0x1f : 0x10)); | |
471 | mutex_unlock(&pctl->lock); | |
472 | } else { | |
473 | mutex_lock(&pctl->lock); | |
474 | sx150x_write_cfg(pctl->client, offset, 1, | |
475 | pctl->data->reg_data, | |
476 | (value ? 1 : 0)); | |
477 | mutex_unlock(&pctl->lock); | |
478 | } | |
479 | } | |
480 | ||
481 | static int sx150x_gpio_direction_input(struct gpio_chip *chip, | |
482 | unsigned int offset) | |
483 | { | |
484 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
485 | int ret; | |
486 | ||
487 | if (sx150x_pin_is_oscio(pctl, offset)) | |
488 | return -EINVAL; | |
489 | ||
490 | mutex_lock(&pctl->lock); | |
491 | ret = sx150x_write_cfg(pctl->client, offset, 1, | |
492 | pctl->data->reg_dir, 1); | |
493 | mutex_unlock(&pctl->lock); | |
494 | ||
495 | return ret; | |
496 | } | |
497 | ||
498 | static int sx150x_gpio_direction_output(struct gpio_chip *chip, | |
499 | unsigned int offset, int value) | |
500 | { | |
501 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
502 | int status; | |
503 | ||
504 | if (sx150x_pin_is_oscio(pctl, offset)) { | |
505 | sx150x_gpio_set(chip, offset, value); | |
506 | return 0; | |
507 | } | |
508 | ||
509 | mutex_lock(&pctl->lock); | |
510 | status = sx150x_write_cfg(pctl->client, offset, 1, | |
511 | pctl->data->reg_data, | |
512 | (value ? 1 : 0)); | |
513 | if (status >= 0) | |
514 | status = sx150x_write_cfg(pctl->client, offset, 1, | |
515 | pctl->data->reg_dir, 0); | |
516 | mutex_unlock(&pctl->lock); | |
517 | ||
518 | return status; | |
519 | } | |
520 | ||
521 | static void sx150x_irq_mask(struct irq_data *d) | |
522 | { | |
523 | struct sx150x_pinctrl *pctl = | |
524 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
525 | unsigned int n = d->hwirq; | |
526 | ||
527 | pctl->irq.masked |= (1 << n); | |
528 | pctl->irq.update = n; | |
529 | } | |
530 | ||
531 | static void sx150x_irq_unmask(struct irq_data *d) | |
532 | { | |
533 | struct sx150x_pinctrl *pctl = | |
534 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
535 | unsigned int n = d->hwirq; | |
536 | ||
537 | pctl->irq.masked &= ~(1 << n); | |
538 | pctl->irq.update = n; | |
539 | } | |
540 | ||
541 | static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) | |
542 | { | |
543 | struct sx150x_pinctrl *pctl = | |
544 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
545 | unsigned int n, val = 0; | |
546 | ||
547 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
548 | return -EINVAL; | |
549 | ||
550 | n = d->hwirq; | |
551 | ||
552 | if (flow_type & IRQ_TYPE_EDGE_RISING) | |
553 | val |= 0x1; | |
554 | if (flow_type & IRQ_TYPE_EDGE_FALLING) | |
555 | val |= 0x2; | |
556 | ||
557 | pctl->irq.sense &= ~(3UL << (n * 2)); | |
558 | pctl->irq.sense |= val << (n * 2); | |
559 | pctl->irq.update = n; | |
560 | return 0; | |
561 | } | |
562 | ||
563 | static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) | |
564 | { | |
565 | struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; | |
566 | unsigned int nhandled = 0; | |
567 | unsigned int sub_irq; | |
568 | unsigned int n; | |
569 | s32 err; | |
570 | u8 val; | |
571 | int i; | |
572 | ||
573 | for (i = (pctl->data->ngpios / 8) - 1; i >= 0; --i) { | |
574 | err = sx150x_i2c_read(pctl->client, | |
575 | pctl->data->reg_irq_src - i, | |
576 | &val); | |
577 | if (err < 0) | |
578 | continue; | |
579 | ||
580 | err = sx150x_i2c_write(pctl->client, | |
581 | pctl->data->reg_irq_src - i, | |
582 | val); | |
583 | if (err < 0) | |
584 | continue; | |
585 | ||
586 | for (n = 0; n < 8; ++n) { | |
587 | if (val & (1 << n)) { | |
588 | sub_irq = irq_find_mapping( | |
589 | pctl->gpio.irqdomain, | |
590 | (i * 8) + n); | |
591 | handle_nested_irq(sub_irq); | |
592 | ++nhandled; | |
593 | } | |
594 | } | |
595 | } | |
596 | ||
597 | return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); | |
598 | } | |
599 | ||
600 | static void sx150x_irq_bus_lock(struct irq_data *d) | |
601 | { | |
602 | struct sx150x_pinctrl *pctl = | |
603 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
604 | ||
605 | mutex_lock(&pctl->lock); | |
606 | } | |
607 | ||
608 | static void sx150x_irq_bus_sync_unlock(struct irq_data *d) | |
609 | { | |
610 | struct sx150x_pinctrl *pctl = | |
611 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
612 | unsigned int n; | |
613 | ||
614 | if (pctl->irq.update < 0) | |
615 | goto out; | |
616 | ||
617 | n = pctl->irq.update; | |
618 | pctl->irq.update = -1; | |
619 | ||
620 | /* Avoid updates if nothing changed */ | |
621 | if (pctl->irq.dev_sense == pctl->irq.sense && | |
622 | pctl->irq.dev_masked == pctl->irq.masked) | |
623 | goto out; | |
624 | ||
625 | pctl->irq.dev_sense = pctl->irq.sense; | |
626 | pctl->irq.dev_masked = pctl->irq.masked; | |
627 | ||
628 | if (pctl->irq.masked & (1 << n)) { | |
629 | sx150x_write_cfg(pctl->client, n, 1, | |
630 | pctl->data->reg_irq_mask, 1); | |
631 | sx150x_write_cfg(pctl->client, n, 2, | |
632 | pctl->data->reg_sense, 0); | |
633 | } else { | |
634 | sx150x_write_cfg(pctl->client, n, 1, | |
635 | pctl->data->reg_irq_mask, 0); | |
636 | sx150x_write_cfg(pctl->client, n, 2, | |
637 | pctl->data->reg_sense, | |
638 | pctl->irq.sense >> (n * 2)); | |
639 | } | |
640 | out: | |
641 | mutex_unlock(&pctl->lock); | |
642 | } | |
643 | ||
644 | static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
645 | unsigned long *config) | |
646 | { | |
647 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
648 | unsigned int param = pinconf_to_config_param(*config); | |
649 | int ret; | |
650 | u32 arg; | |
651 | ||
652 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
653 | u8 data; | |
654 | ||
655 | switch (param) { | |
656 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
657 | case PIN_CONFIG_OUTPUT: | |
658 | mutex_lock(&pctl->lock); | |
659 | ret = sx150x_i2c_read(pctl->client, | |
660 | pctl->data->pri.x789.reg_clock, | |
661 | &data); | |
662 | mutex_unlock(&pctl->lock); | |
663 | ||
664 | if (ret < 0) | |
665 | return ret; | |
666 | ||
667 | if (param == PIN_CONFIG_DRIVE_PUSH_PULL) | |
668 | arg = (data & 0x1f) ? 1 : 0; | |
669 | else { | |
670 | if ((data & 0x1f) == 0x1f) | |
671 | arg = 1; | |
672 | else if ((data & 0x1f) == 0x10) | |
673 | arg = 0; | |
674 | else | |
675 | return -EINVAL; | |
676 | } | |
677 | ||
678 | break; | |
679 | default: | |
680 | return -ENOTSUPP; | |
681 | } | |
682 | ||
683 | goto out; | |
684 | } | |
685 | ||
686 | switch (param) { | |
687 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
688 | mutex_lock(&pctl->lock); | |
689 | ret = sx150x_read_cfg(pctl->client, pin, 1, | |
690 | pctl->data->reg_pulldn); | |
691 | mutex_unlock(&pctl->lock); | |
692 | ||
693 | if (ret < 0) | |
694 | return ret; | |
695 | ||
696 | if (!ret) | |
697 | return -EINVAL; | |
698 | ||
699 | arg = 1; | |
700 | break; | |
701 | ||
702 | case PIN_CONFIG_BIAS_PULL_UP: | |
703 | mutex_lock(&pctl->lock); | |
704 | ret = sx150x_read_cfg(pctl->client, pin, 1, | |
705 | pctl->data->reg_pullup); | |
706 | mutex_unlock(&pctl->lock); | |
707 | ||
708 | if (ret < 0) | |
709 | return ret; | |
710 | ||
711 | if (!ret) | |
712 | return -EINVAL; | |
713 | ||
714 | arg = 1; | |
715 | break; | |
716 | ||
717 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
718 | if (pctl->data->model != SX150X_789) | |
719 | return -ENOTSUPP; | |
720 | ||
721 | mutex_lock(&pctl->lock); | |
722 | ret = sx150x_read_cfg(pctl->client, pin, 1, | |
723 | pctl->data->pri.x789.reg_drain); | |
724 | mutex_unlock(&pctl->lock); | |
725 | ||
726 | if (ret < 0) | |
727 | return ret; | |
728 | ||
729 | if (!ret) | |
730 | return -EINVAL; | |
731 | ||
732 | arg = 1; | |
733 | break; | |
734 | ||
735 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
736 | if (pctl->data->model != SX150X_789) | |
737 | arg = true; | |
738 | else { | |
739 | mutex_lock(&pctl->lock); | |
740 | ret = sx150x_read_cfg(pctl->client, pin, 1, | |
741 | pctl->data->pri.x789.reg_drain); | |
742 | mutex_unlock(&pctl->lock); | |
743 | ||
744 | if (ret < 0) | |
745 | return ret; | |
746 | ||
747 | if (ret) | |
748 | return -EINVAL; | |
749 | ||
750 | arg = 1; | |
751 | } | |
752 | break; | |
753 | ||
754 | case PIN_CONFIG_OUTPUT: | |
755 | ret = sx150x_gpio_get_direction(&pctl->gpio, pin); | |
756 | if (ret < 0) | |
757 | return ret; | |
758 | ||
759 | if (ret) | |
760 | return -EINVAL; | |
761 | ||
762 | ret = sx150x_gpio_get(&pctl->gpio, pin); | |
763 | if (ret < 0) | |
764 | return ret; | |
765 | ||
766 | arg = ret; | |
767 | break; | |
768 | ||
769 | default: | |
770 | return -ENOTSUPP; | |
771 | } | |
772 | ||
773 | out: | |
774 | *config = pinconf_to_config_packed(param, arg); | |
775 | ||
776 | return 0; | |
777 | } | |
778 | ||
779 | static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
780 | unsigned long *configs, unsigned int num_configs) | |
781 | { | |
782 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
783 | enum pin_config_param param; | |
784 | u32 arg; | |
785 | int i; | |
786 | int ret; | |
787 | ||
788 | for (i = 0; i < num_configs; i++) { | |
789 | param = pinconf_to_config_param(configs[i]); | |
790 | arg = pinconf_to_config_argument(configs[i]); | |
791 | ||
792 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
793 | if (param == PIN_CONFIG_OUTPUT) { | |
794 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
795 | pin, arg); | |
796 | if (ret < 0) | |
797 | return ret; | |
798 | ||
799 | continue; | |
800 | } else | |
801 | return -ENOTSUPP; | |
802 | } | |
803 | ||
804 | switch (param) { | |
805 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
806 | case PIN_CONFIG_BIAS_DISABLE: | |
807 | mutex_lock(&pctl->lock); | |
808 | ret = sx150x_write_cfg(pctl->client, pin, 1, | |
809 | pctl->data->reg_pulldn, 0); | |
810 | mutex_unlock(&pctl->lock); | |
811 | if (ret < 0) | |
812 | return ret; | |
813 | ||
814 | mutex_lock(&pctl->lock); | |
815 | ret = sx150x_write_cfg(pctl->client, pin, 1, | |
816 | pctl->data->reg_pullup, 0); | |
817 | mutex_unlock(&pctl->lock); | |
818 | if (ret < 0) | |
819 | return ret; | |
820 | ||
821 | break; | |
822 | ||
823 | case PIN_CONFIG_BIAS_PULL_UP: | |
824 | mutex_lock(&pctl->lock); | |
825 | ret = sx150x_write_cfg(pctl->client, pin, 1, | |
826 | pctl->data->reg_pullup, | |
827 | 1); | |
828 | mutex_unlock(&pctl->lock); | |
829 | if (ret < 0) | |
830 | return ret; | |
831 | ||
832 | break; | |
833 | ||
834 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
835 | mutex_lock(&pctl->lock); | |
836 | ret = sx150x_write_cfg(pctl->client, pin, 1, | |
837 | pctl->data->reg_pulldn, | |
838 | 1); | |
839 | mutex_unlock(&pctl->lock); | |
840 | if (ret < 0) | |
841 | return ret; | |
842 | ||
843 | break; | |
844 | ||
845 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
846 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
847 | pin, LINE_MODE_OPEN_DRAIN); | |
848 | if (ret < 0) | |
849 | return ret; | |
850 | ||
851 | break; | |
852 | ||
853 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
854 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
855 | pin, LINE_MODE_PUSH_PULL); | |
856 | if (ret < 0) | |
857 | return ret; | |
858 | ||
859 | break; | |
860 | ||
861 | case PIN_CONFIG_OUTPUT: | |
862 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
863 | pin, arg); | |
864 | if (ret < 0) | |
865 | return ret; | |
866 | ||
867 | break; | |
868 | ||
869 | default: | |
870 | return -ENOTSUPP; | |
871 | } | |
872 | } /* for each config */ | |
873 | ||
874 | return 0; | |
875 | } | |
876 | ||
877 | static const struct pinconf_ops sx150x_pinconf_ops = { | |
878 | .pin_config_get = sx150x_pinconf_get, | |
879 | .pin_config_set = sx150x_pinconf_set, | |
880 | .is_generic = true, | |
881 | }; | |
882 | ||
883 | static const struct i2c_device_id sx150x_id[] = { | |
884 | {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, | |
885 | {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, | |
886 | {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, | |
887 | {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, | |
6697546d | 888 | {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, |
9e80f906 NA |
889 | {} |
890 | }; | |
891 | ||
892 | static const struct of_device_id sx150x_of_match[] = { | |
e3ba8120 AS |
893 | { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, |
894 | { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, | |
895 | { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, | |
896 | { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, | |
6697546d | 897 | { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, |
9e80f906 NA |
898 | {}, |
899 | }; | |
900 | ||
901 | static int sx150x_init_io(struct sx150x_pinctrl *pctl, u8 base, u16 cfg) | |
902 | { | |
903 | int err = 0; | |
904 | unsigned int n; | |
905 | ||
906 | for (n = 0; err >= 0 && n < (pctl->data->ngpios / 8); ++n) | |
907 | err = sx150x_i2c_write(pctl->client, base - n, cfg >> (n * 8)); | |
908 | return err; | |
909 | } | |
910 | ||
911 | static int sx150x_reset(struct sx150x_pinctrl *pctl) | |
912 | { | |
913 | int err; | |
914 | ||
915 | err = i2c_smbus_write_byte_data(pctl->client, | |
916 | pctl->data->pri.x789.reg_reset, | |
917 | 0x12); | |
918 | if (err < 0) | |
919 | return err; | |
920 | ||
921 | err = i2c_smbus_write_byte_data(pctl->client, | |
922 | pctl->data->pri.x789.reg_reset, | |
923 | 0x34); | |
924 | return err; | |
925 | } | |
926 | ||
310cdfa0 AS |
927 | static int sx150x_init_misc(struct sx150x_pinctrl *pctl) |
928 | { | |
929 | u8 reg, value; | |
930 | ||
931 | switch (pctl->data->model) { | |
932 | case SX150X_789: | |
933 | reg = pctl->data->pri.x789.reg_misc; | |
934 | value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; | |
935 | break; | |
936 | case SX150X_456: | |
937 | reg = pctl->data->pri.x456.reg_advance; | |
938 | value = 0x00; | |
939 | break; | |
940 | case SX150X_123: | |
941 | reg = pctl->data->pri.x123.reg_advance; | |
942 | value = 0x00; | |
943 | break; | |
944 | default: | |
945 | WARN(1, "Unknown chip model %d\n", pctl->data->model); | |
946 | return -EINVAL; | |
947 | } | |
948 | ||
949 | return sx150x_i2c_write(pctl->client, reg, value); | |
950 | } | |
951 | ||
9e80f906 NA |
952 | static int sx150x_init_hw(struct sx150x_pinctrl *pctl) |
953 | { | |
954 | int err; | |
955 | ||
956 | if (pctl->data->model == SX150X_789 && | |
957 | of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { | |
958 | err = sx150x_reset(pctl); | |
959 | if (err < 0) | |
960 | return err; | |
961 | } | |
962 | ||
310cdfa0 | 963 | err = sx150x_init_misc(pctl); |
9e80f906 NA |
964 | if (err < 0) |
965 | return err; | |
966 | ||
967 | /* Set all pins to work in normal mode */ | |
968 | if (pctl->data->model == SX150X_789) { | |
969 | err = sx150x_init_io(pctl, | |
970 | pctl->data->pri.x789.reg_polarity, | |
971 | 0); | |
972 | if (err < 0) | |
973 | return err; | |
974 | } else if (pctl->data->model == SX150X_456) { | |
975 | /* Set all pins to work in normal mode */ | |
976 | err = sx150x_init_io(pctl, | |
977 | pctl->data->pri.x456.reg_pld_mode, | |
978 | 0); | |
979 | if (err < 0) | |
980 | return err; | |
981 | } else { | |
982 | /* Set all pins to work in normal mode */ | |
983 | err = sx150x_init_io(pctl, | |
984 | pctl->data->pri.x123.reg_pld_mode, | |
985 | 0); | |
986 | if (err < 0) | |
987 | return err; | |
988 | } | |
989 | ||
990 | return 0; | |
991 | } | |
992 | ||
993 | static int sx150x_probe(struct i2c_client *client, | |
994 | const struct i2c_device_id *id) | |
995 | { | |
996 | static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | | |
997 | I2C_FUNC_SMBUS_WRITE_WORD_DATA; | |
998 | struct device *dev = &client->dev; | |
999 | struct sx150x_pinctrl *pctl; | |
1000 | int ret; | |
1001 | ||
9e80f906 NA |
1002 | if (!i2c_check_functionality(client->adapter, i2c_funcs)) |
1003 | return -ENOSYS; | |
1004 | ||
1005 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
1006 | if (!pctl) | |
1007 | return -ENOMEM; | |
1008 | ||
1009 | pctl->dev = dev; | |
1010 | pctl->client = client; | |
e3ba8120 AS |
1011 | |
1012 | if (dev->of_node) | |
1013 | pctl->data = of_device_get_match_data(dev); | |
1014 | else | |
1015 | pctl->data = (struct sx150x_device_data *)id->driver_data; | |
1016 | ||
1017 | if (!pctl->data) | |
1018 | return -EINVAL; | |
9e80f906 NA |
1019 | |
1020 | mutex_init(&pctl->lock); | |
1021 | ||
1022 | ret = sx150x_init_hw(pctl); | |
1023 | if (ret) | |
1024 | return ret; | |
1025 | ||
1026 | /* Register GPIO controller */ | |
1027 | pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); | |
1028 | pctl->gpio.base = -1; | |
1029 | pctl->gpio.ngpio = pctl->data->npins; | |
1030 | pctl->gpio.get_direction = sx150x_gpio_get_direction; | |
1031 | pctl->gpio.direction_input = sx150x_gpio_direction_input; | |
1032 | pctl->gpio.direction_output = sx150x_gpio_direction_output; | |
1033 | pctl->gpio.get = sx150x_gpio_get; | |
1034 | pctl->gpio.set = sx150x_gpio_set; | |
1035 | pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended; | |
1036 | pctl->gpio.parent = dev; | |
1037 | #ifdef CONFIG_OF_GPIO | |
1038 | pctl->gpio.of_node = dev->of_node; | |
1039 | #endif | |
1040 | pctl->gpio.can_sleep = true; | |
1041 | ||
1042 | ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); | |
1043 | if (ret) | |
1044 | return ret; | |
1045 | ||
1046 | /* Add Interrupt support if an irq is specified */ | |
1047 | if (client->irq > 0) { | |
1048 | pctl->irq_chip.name = devm_kstrdup(dev, client->name, | |
1049 | GFP_KERNEL); | |
1050 | pctl->irq_chip.irq_mask = sx150x_irq_mask; | |
1051 | pctl->irq_chip.irq_unmask = sx150x_irq_unmask; | |
1052 | pctl->irq_chip.irq_set_type = sx150x_irq_set_type; | |
1053 | pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; | |
1054 | pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; | |
1055 | ||
1056 | pctl->irq.masked = ~0; | |
1057 | pctl->irq.sense = 0; | |
1058 | pctl->irq.dev_masked = ~0; | |
1059 | pctl->irq.dev_sense = 0; | |
1060 | pctl->irq.update = -1; | |
1061 | ||
1062 | ret = gpiochip_irqchip_add(&pctl->gpio, | |
1063 | &pctl->irq_chip, 0, | |
1064 | handle_edge_irq, IRQ_TYPE_NONE); | |
1065 | if (ret) { | |
1066 | dev_err(dev, "could not connect irqchip to gpiochip\n"); | |
1067 | return ret; | |
1068 | } | |
1069 | ||
1070 | ret = devm_request_threaded_irq(dev, client->irq, NULL, | |
1071 | sx150x_irq_thread_fn, | |
1072 | IRQF_ONESHOT | IRQF_SHARED | | |
1073 | IRQF_TRIGGER_FALLING, | |
1074 | pctl->irq_chip.name, pctl); | |
1075 | if (ret < 0) | |
1076 | return ret; | |
1077 | } | |
1078 | ||
1079 | /* Pinctrl_desc */ | |
1080 | pctl->pinctrl_desc.name = "sx150x-pinctrl"; | |
1081 | pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; | |
1082 | pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; | |
1083 | pctl->pinctrl_desc.pins = pctl->data->pins; | |
1084 | pctl->pinctrl_desc.npins = pctl->data->npins; | |
1085 | pctl->pinctrl_desc.owner = THIS_MODULE; | |
1086 | ||
1087 | pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl); | |
1088 | if (IS_ERR(pctl->pctldev)) { | |
1089 | dev_err(dev, "Failed to register pinctrl device\n"); | |
1090 | return PTR_ERR(pctl->pctldev); | |
1091 | } | |
1092 | ||
1093 | return 0; | |
1094 | } | |
1095 | ||
1096 | static struct i2c_driver sx150x_driver = { | |
1097 | .driver = { | |
1098 | .name = "sx150x-pinctrl", | |
1099 | .of_match_table = of_match_ptr(sx150x_of_match), | |
1100 | }, | |
1101 | .probe = sx150x_probe, | |
1102 | .id_table = sx150x_id, | |
1103 | }; | |
1104 | ||
1105 | static int __init sx150x_init(void) | |
1106 | { | |
1107 | return i2c_add_driver(&sx150x_driver); | |
1108 | } | |
1109 | subsys_initcall(sx150x_init); |