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9e80f906 NA |
1 | /* |
2 | * Copyright (c) 2016, BayLibre, SAS. All rights reserved. | |
3 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
4 | * | |
5 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | |
6 | * | |
7 | * Driver for Semtech SX150X I2C GPIO Expanders | |
8 | * | |
9 | * Author: Gregory Bean <gbean@codeaurora.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 and | |
13 | * only version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | */ | |
20 | ||
0db0f26c | 21 | #include <linux/regmap.h> |
9e80f906 NA |
22 | #include <linux/i2c.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/of.h> | |
e3ba8120 | 29 | #include <linux/of_device.h> |
fc669d13 | 30 | #include <linux/gpio/driver.h> |
9e80f906 NA |
31 | #include <linux/pinctrl/pinconf.h> |
32 | #include <linux/pinctrl/pinctrl.h> | |
33 | #include <linux/pinctrl/pinmux.h> | |
34 | #include <linux/pinctrl/pinconf-generic.h> | |
35 | ||
36 | #include "core.h" | |
37 | #include "pinconf.h" | |
38 | #include "pinctrl-utils.h" | |
39 | ||
40 | /* The chip models of sx150x */ | |
41 | enum { | |
42 | SX150X_123 = 0, | |
43 | SX150X_456, | |
44 | SX150X_789, | |
45 | }; | |
7d68a79a AS |
46 | enum { |
47 | SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, | |
0db0f26c | 48 | SX150X_MAX_REGISTER = 0xad, |
fd931f23 AS |
49 | SX150X_IRQ_TYPE_EDGE_RISING = 0x1, |
50 | SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, | |
f9038d60 AS |
51 | SX150X_789_RESET_KEY1 = 0x12, |
52 | SX150X_789_RESET_KEY2 = 0x34, | |
7d68a79a | 53 | }; |
9e80f906 NA |
54 | |
55 | struct sx150x_123_pri { | |
56 | u8 reg_pld_mode; | |
57 | u8 reg_pld_table0; | |
58 | u8 reg_pld_table1; | |
59 | u8 reg_pld_table2; | |
60 | u8 reg_pld_table3; | |
61 | u8 reg_pld_table4; | |
62 | u8 reg_advance; | |
63 | }; | |
64 | ||
65 | struct sx150x_456_pri { | |
66 | u8 reg_pld_mode; | |
67 | u8 reg_pld_table0; | |
68 | u8 reg_pld_table1; | |
69 | u8 reg_pld_table2; | |
70 | u8 reg_pld_table3; | |
71 | u8 reg_pld_table4; | |
72 | u8 reg_advance; | |
73 | }; | |
74 | ||
75 | struct sx150x_789_pri { | |
76 | u8 reg_drain; | |
77 | u8 reg_polarity; | |
78 | u8 reg_clock; | |
79 | u8 reg_misc; | |
80 | u8 reg_reset; | |
81 | u8 ngpios; | |
82 | }; | |
83 | ||
84 | struct sx150x_device_data { | |
85 | u8 model; | |
86 | u8 reg_pullup; | |
87 | u8 reg_pulldn; | |
88 | u8 reg_dir; | |
89 | u8 reg_data; | |
90 | u8 reg_irq_mask; | |
91 | u8 reg_irq_src; | |
92 | u8 reg_sense; | |
93 | u8 ngpios; | |
94 | union { | |
95 | struct sx150x_123_pri x123; | |
96 | struct sx150x_456_pri x456; | |
97 | struct sx150x_789_pri x789; | |
98 | } pri; | |
99 | const struct pinctrl_pin_desc *pins; | |
100 | unsigned int npins; | |
101 | }; | |
102 | ||
103 | struct sx150x_pinctrl { | |
104 | struct device *dev; | |
105 | struct i2c_client *client; | |
106 | struct pinctrl_dev *pctldev; | |
107 | struct pinctrl_desc pinctrl_desc; | |
108 | struct gpio_chip gpio; | |
109 | struct irq_chip irq_chip; | |
0db0f26c | 110 | struct regmap *regmap; |
9e80f906 | 111 | struct { |
9e80f906 NA |
112 | u32 sense; |
113 | u32 masked; | |
9e80f906 NA |
114 | } irq; |
115 | struct mutex lock; | |
116 | const struct sx150x_device_data *data; | |
117 | }; | |
118 | ||
119 | static const struct pinctrl_pin_desc sx150x_8_pins[] = { | |
120 | PINCTRL_PIN(0, "gpio0"), | |
121 | PINCTRL_PIN(1, "gpio1"), | |
122 | PINCTRL_PIN(2, "gpio2"), | |
123 | PINCTRL_PIN(3, "gpio3"), | |
124 | PINCTRL_PIN(4, "gpio4"), | |
125 | PINCTRL_PIN(5, "gpio5"), | |
126 | PINCTRL_PIN(6, "gpio6"), | |
127 | PINCTRL_PIN(7, "gpio7"), | |
128 | PINCTRL_PIN(8, "oscio"), | |
129 | }; | |
130 | ||
131 | static const struct pinctrl_pin_desc sx150x_16_pins[] = { | |
132 | PINCTRL_PIN(0, "gpio0"), | |
133 | PINCTRL_PIN(1, "gpio1"), | |
134 | PINCTRL_PIN(2, "gpio2"), | |
135 | PINCTRL_PIN(3, "gpio3"), | |
136 | PINCTRL_PIN(4, "gpio4"), | |
137 | PINCTRL_PIN(5, "gpio5"), | |
138 | PINCTRL_PIN(6, "gpio6"), | |
139 | PINCTRL_PIN(7, "gpio7"), | |
140 | PINCTRL_PIN(8, "gpio8"), | |
141 | PINCTRL_PIN(9, "gpio9"), | |
142 | PINCTRL_PIN(10, "gpio10"), | |
143 | PINCTRL_PIN(11, "gpio11"), | |
144 | PINCTRL_PIN(12, "gpio12"), | |
145 | PINCTRL_PIN(13, "gpio13"), | |
146 | PINCTRL_PIN(14, "gpio14"), | |
147 | PINCTRL_PIN(15, "gpio15"), | |
148 | PINCTRL_PIN(16, "oscio"), | |
149 | }; | |
150 | ||
151 | static const struct sx150x_device_data sx1508q_device_data = { | |
152 | .model = SX150X_789, | |
153 | .reg_pullup = 0x03, | |
154 | .reg_pulldn = 0x04, | |
155 | .reg_dir = 0x07, | |
156 | .reg_data = 0x08, | |
157 | .reg_irq_mask = 0x09, | |
158 | .reg_irq_src = 0x0c, | |
159 | .reg_sense = 0x0b, | |
160 | .pri.x789 = { | |
161 | .reg_drain = 0x05, | |
162 | .reg_polarity = 0x06, | |
163 | .reg_clock = 0x0f, | |
164 | .reg_misc = 0x10, | |
165 | .reg_reset = 0x7d, | |
166 | }, | |
167 | .ngpios = 8, | |
168 | .pins = sx150x_8_pins, | |
169 | .npins = ARRAY_SIZE(sx150x_8_pins), | |
170 | }; | |
171 | ||
172 | static const struct sx150x_device_data sx1509q_device_data = { | |
173 | .model = SX150X_789, | |
6489677f AS |
174 | .reg_pullup = 0x06, |
175 | .reg_pulldn = 0x08, | |
176 | .reg_dir = 0x0e, | |
177 | .reg_data = 0x10, | |
178 | .reg_irq_mask = 0x12, | |
179 | .reg_irq_src = 0x18, | |
180 | .reg_sense = 0x14, | |
9e80f906 | 181 | .pri.x789 = { |
6489677f AS |
182 | .reg_drain = 0x0a, |
183 | .reg_polarity = 0x0c, | |
9e80f906 NA |
184 | .reg_clock = 0x1e, |
185 | .reg_misc = 0x1f, | |
186 | .reg_reset = 0x7d, | |
187 | }, | |
188 | .ngpios = 16, | |
189 | .pins = sx150x_16_pins, | |
190 | .npins = ARRAY_SIZE(sx150x_16_pins), | |
191 | }; | |
192 | ||
193 | static const struct sx150x_device_data sx1506q_device_data = { | |
194 | .model = SX150X_456, | |
6489677f AS |
195 | .reg_pullup = 0x04, |
196 | .reg_pulldn = 0x06, | |
197 | .reg_dir = 0x02, | |
198 | .reg_data = 0x00, | |
199 | .reg_irq_mask = 0x08, | |
200 | .reg_irq_src = 0x0e, | |
201 | .reg_sense = 0x0a, | |
9e80f906 | 202 | .pri.x456 = { |
6489677f AS |
203 | .reg_pld_mode = 0x20, |
204 | .reg_pld_table0 = 0x22, | |
205 | .reg_pld_table1 = 0x24, | |
206 | .reg_pld_table2 = 0x26, | |
207 | .reg_pld_table3 = 0x28, | |
208 | .reg_pld_table4 = 0x2a, | |
9e80f906 NA |
209 | .reg_advance = 0xad, |
210 | }, | |
211 | .ngpios = 16, | |
212 | .pins = sx150x_16_pins, | |
213 | .npins = 16, /* oscio not available */ | |
214 | }; | |
215 | ||
216 | static const struct sx150x_device_data sx1502q_device_data = { | |
217 | .model = SX150X_123, | |
218 | .reg_pullup = 0x02, | |
219 | .reg_pulldn = 0x03, | |
220 | .reg_dir = 0x01, | |
221 | .reg_data = 0x00, | |
222 | .reg_irq_mask = 0x05, | |
223 | .reg_irq_src = 0x08, | |
224 | .reg_sense = 0x07, | |
225 | .pri.x123 = { | |
226 | .reg_pld_mode = 0x10, | |
227 | .reg_pld_table0 = 0x11, | |
228 | .reg_pld_table1 = 0x12, | |
229 | .reg_pld_table2 = 0x13, | |
230 | .reg_pld_table3 = 0x14, | |
231 | .reg_pld_table4 = 0x15, | |
232 | .reg_advance = 0xad, | |
233 | }, | |
234 | .ngpios = 8, | |
235 | .pins = sx150x_8_pins, | |
236 | .npins = 8, /* oscio not available */ | |
237 | }; | |
238 | ||
6697546d AS |
239 | static const struct sx150x_device_data sx1503q_device_data = { |
240 | .model = SX150X_123, | |
6489677f AS |
241 | .reg_pullup = 0x04, |
242 | .reg_pulldn = 0x06, | |
243 | .reg_dir = 0x02, | |
244 | .reg_data = 0x00, | |
245 | .reg_irq_mask = 0x08, | |
246 | .reg_irq_src = 0x0e, | |
247 | .reg_sense = 0x0a, | |
6697546d | 248 | .pri.x123 = { |
6489677f AS |
249 | .reg_pld_mode = 0x20, |
250 | .reg_pld_table0 = 0x22, | |
251 | .reg_pld_table1 = 0x24, | |
252 | .reg_pld_table2 = 0x26, | |
253 | .reg_pld_table3 = 0x28, | |
254 | .reg_pld_table4 = 0x2a, | |
6697546d AS |
255 | .reg_advance = 0xad, |
256 | }, | |
257 | .ngpios = 16, | |
258 | .pins = sx150x_16_pins, | |
259 | .npins = 16, /* oscio not available */ | |
260 | }; | |
261 | ||
9e80f906 NA |
262 | static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
263 | { | |
264 | return 0; | |
265 | } | |
266 | ||
267 | static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
268 | unsigned int group) | |
269 | { | |
270 | return NULL; | |
271 | } | |
272 | ||
273 | static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
274 | unsigned int group, | |
275 | const unsigned int **pins, | |
276 | unsigned int *num_pins) | |
277 | { | |
278 | return -ENOTSUPP; | |
279 | } | |
280 | ||
281 | static const struct pinctrl_ops sx150x_pinctrl_ops = { | |
282 | .get_groups_count = sx150x_pinctrl_get_groups_count, | |
283 | .get_group_name = sx150x_pinctrl_get_group_name, | |
284 | .get_group_pins = sx150x_pinctrl_get_group_pins, | |
285 | #ifdef CONFIG_OF | |
286 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
287 | .dt_free_map = pinctrl_utils_free_map, | |
288 | #endif | |
289 | }; | |
290 | ||
291 | static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) | |
292 | { | |
293 | if (pin >= pctl->data->npins) | |
294 | return false; | |
295 | ||
296 | /* OSCIO pin is only present in 789 devices */ | |
297 | if (pctl->data->model != SX150X_789) | |
298 | return false; | |
299 | ||
300 | return !strcmp(pctl->data->pins[pin].name, "oscio"); | |
301 | } | |
302 | ||
303 | static int sx150x_gpio_get_direction(struct gpio_chip *chip, | |
304 | unsigned int offset) | |
305 | { | |
306 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
6489677f AS |
307 | unsigned int value; |
308 | int ret; | |
9e80f906 NA |
309 | |
310 | if (sx150x_pin_is_oscio(pctl, offset)) | |
311 | return false; | |
312 | ||
6489677f AS |
313 | ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); |
314 | if (ret < 0) | |
315 | return ret; | |
9e80f906 | 316 | |
6489677f | 317 | return !!(value & BIT(offset)); |
9e80f906 NA |
318 | } |
319 | ||
320 | static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
321 | { | |
322 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
6489677f AS |
323 | unsigned int value; |
324 | int ret; | |
9e80f906 NA |
325 | |
326 | if (sx150x_pin_is_oscio(pctl, offset)) | |
327 | return -EINVAL; | |
328 | ||
6489677f AS |
329 | ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); |
330 | if (ret < 0) | |
331 | return ret; | |
9e80f906 | 332 | |
6489677f | 333 | return !!(value & BIT(offset)); |
9e80f906 NA |
334 | } |
335 | ||
336 | static int sx150x_gpio_set_single_ended(struct gpio_chip *chip, | |
337 | unsigned int offset, | |
338 | enum single_ended_mode mode) | |
339 | { | |
340 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
341 | int ret; | |
342 | ||
343 | switch (mode) { | |
344 | case LINE_MODE_PUSH_PULL: | |
345 | if (pctl->data->model != SX150X_789 || | |
346 | sx150x_pin_is_oscio(pctl, offset)) | |
347 | return 0; | |
348 | ||
6489677f AS |
349 | ret = regmap_write_bits(pctl->regmap, |
350 | pctl->data->pri.x789.reg_drain, | |
351 | BIT(offset), 0); | |
9e80f906 NA |
352 | break; |
353 | ||
354 | case LINE_MODE_OPEN_DRAIN: | |
355 | if (pctl->data->model != SX150X_789 || | |
356 | sx150x_pin_is_oscio(pctl, offset)) | |
357 | return -ENOTSUPP; | |
358 | ||
6489677f AS |
359 | ret = regmap_write_bits(pctl->regmap, |
360 | pctl->data->pri.x789.reg_drain, | |
361 | BIT(offset), BIT(offset)); | |
9e80f906 | 362 | break; |
9e80f906 | 363 | default: |
d977a876 AS |
364 | ret = -ENOTSUPP; |
365 | break; | |
9e80f906 NA |
366 | } |
367 | ||
d977a876 | 368 | return ret; |
9e80f906 NA |
369 | } |
370 | ||
6489677f AS |
371 | static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, |
372 | int value) | |
373 | { | |
374 | return regmap_write_bits(pctl->regmap, pctl->data->reg_data, | |
375 | BIT(offset), value ? BIT(offset) : 0); | |
376 | } | |
377 | ||
ab5bd035 AS |
378 | static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, |
379 | int value) | |
380 | { | |
381 | return regmap_write(pctl->regmap, | |
382 | pctl->data->pri.x789.reg_clock, | |
383 | (value ? 0x1f : 0x10)); | |
384 | } | |
385 | ||
9e80f906 | 386 | static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, |
7bd47496 | 387 | int value) |
9e80f906 NA |
388 | { |
389 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
390 | ||
d977a876 | 391 | if (sx150x_pin_is_oscio(pctl, offset)) |
ab5bd035 | 392 | sx150x_gpio_oscio_set(pctl, value); |
d977a876 | 393 | else |
6489677f | 394 | __sx150x_gpio_set(pctl, offset, value); |
d977a876 | 395 | |
9e80f906 NA |
396 | } |
397 | ||
398 | static int sx150x_gpio_direction_input(struct gpio_chip *chip, | |
7bd47496 | 399 | unsigned int offset) |
9e80f906 NA |
400 | { |
401 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
9e80f906 NA |
402 | |
403 | if (sx150x_pin_is_oscio(pctl, offset)) | |
404 | return -EINVAL; | |
405 | ||
d977a876 AS |
406 | return regmap_write_bits(pctl->regmap, |
407 | pctl->data->reg_dir, | |
408 | BIT(offset), BIT(offset)); | |
9e80f906 NA |
409 | } |
410 | ||
411 | static int sx150x_gpio_direction_output(struct gpio_chip *chip, | |
7bd47496 | 412 | unsigned int offset, int value) |
9e80f906 NA |
413 | { |
414 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
d977a876 | 415 | int ret; |
9e80f906 | 416 | |
ab5bd035 AS |
417 | if (sx150x_pin_is_oscio(pctl, offset)) |
418 | return sx150x_gpio_oscio_set(pctl, value); | |
9e80f906 | 419 | |
d977a876 AS |
420 | ret = __sx150x_gpio_set(pctl, offset, value); |
421 | if (ret < 0) | |
422 | return ret; | |
9e80f906 | 423 | |
d977a876 AS |
424 | return regmap_write_bits(pctl->regmap, |
425 | pctl->data->reg_dir, | |
426 | BIT(offset), 0); | |
9e80f906 NA |
427 | } |
428 | ||
429 | static void sx150x_irq_mask(struct irq_data *d) | |
430 | { | |
431 | struct sx150x_pinctrl *pctl = | |
432 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
433 | unsigned int n = d->hwirq; | |
434 | ||
6489677f | 435 | pctl->irq.masked |= BIT(n); |
9e80f906 NA |
436 | } |
437 | ||
438 | static void sx150x_irq_unmask(struct irq_data *d) | |
439 | { | |
440 | struct sx150x_pinctrl *pctl = | |
441 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
442 | unsigned int n = d->hwirq; | |
443 | ||
6489677f | 444 | pctl->irq.masked &= ~BIT(n); |
9e80f906 NA |
445 | } |
446 | ||
fd931f23 AS |
447 | static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, |
448 | unsigned int line, unsigned int sense) | |
449 | { | |
450 | /* | |
451 | * Every interrupt line is represented by two bits shifted | |
452 | * proportionally to the line number | |
453 | */ | |
454 | const unsigned int n = line * 2; | |
455 | const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | | |
456 | SX150X_IRQ_TYPE_EDGE_FALLING) << n); | |
457 | ||
458 | pctl->irq.sense &= mask; | |
459 | pctl->irq.sense |= sense << n; | |
460 | } | |
461 | ||
9e80f906 NA |
462 | static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
463 | { | |
464 | struct sx150x_pinctrl *pctl = | |
465 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
466 | unsigned int n, val = 0; | |
467 | ||
468 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
469 | return -EINVAL; | |
470 | ||
471 | n = d->hwirq; | |
472 | ||
473 | if (flow_type & IRQ_TYPE_EDGE_RISING) | |
fd931f23 | 474 | val |= SX150X_IRQ_TYPE_EDGE_RISING; |
9e80f906 | 475 | if (flow_type & IRQ_TYPE_EDGE_FALLING) |
fd931f23 | 476 | val |= SX150X_IRQ_TYPE_EDGE_FALLING; |
9e80f906 | 477 | |
fd931f23 | 478 | sx150x_irq_set_sense(pctl, n, val); |
9e80f906 NA |
479 | return 0; |
480 | } | |
481 | ||
482 | static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) | |
483 | { | |
484 | struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; | |
05a90cc7 | 485 | unsigned long n, status; |
0db0f26c | 486 | unsigned int val; |
05a90cc7 | 487 | int err; |
9e80f906 | 488 | |
6489677f AS |
489 | err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); |
490 | if (err < 0) | |
491 | return IRQ_NONE; | |
9e80f906 | 492 | |
6489677f AS |
493 | err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); |
494 | if (err < 0) | |
495 | return IRQ_NONE; | |
496 | ||
05a90cc7 AS |
497 | status = val; |
498 | for_each_set_bit(n, &status, pctl->data->ngpios) | |
499 | handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n)); | |
9e80f906 | 500 | |
05a90cc7 | 501 | return IRQ_HANDLED; |
9e80f906 NA |
502 | } |
503 | ||
504 | static void sx150x_irq_bus_lock(struct irq_data *d) | |
505 | { | |
506 | struct sx150x_pinctrl *pctl = | |
507 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
508 | ||
509 | mutex_lock(&pctl->lock); | |
510 | } | |
511 | ||
512 | static void sx150x_irq_bus_sync_unlock(struct irq_data *d) | |
513 | { | |
514 | struct sx150x_pinctrl *pctl = | |
515 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
9e80f906 | 516 | |
6489677f AS |
517 | regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); |
518 | regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); | |
9e80f906 NA |
519 | mutex_unlock(&pctl->lock); |
520 | } | |
521 | ||
522 | static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
523 | unsigned long *config) | |
524 | { | |
525 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
526 | unsigned int param = pinconf_to_config_param(*config); | |
527 | int ret; | |
528 | u32 arg; | |
6489677f | 529 | unsigned int data; |
9e80f906 NA |
530 | |
531 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
9e80f906 NA |
532 | switch (param) { |
533 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
534 | case PIN_CONFIG_OUTPUT: | |
0db0f26c AS |
535 | ret = regmap_read(pctl->regmap, |
536 | pctl->data->pri.x789.reg_clock, | |
537 | &data); | |
9e80f906 NA |
538 | if (ret < 0) |
539 | return ret; | |
540 | ||
541 | if (param == PIN_CONFIG_DRIVE_PUSH_PULL) | |
542 | arg = (data & 0x1f) ? 1 : 0; | |
543 | else { | |
544 | if ((data & 0x1f) == 0x1f) | |
545 | arg = 1; | |
546 | else if ((data & 0x1f) == 0x10) | |
547 | arg = 0; | |
548 | else | |
549 | return -EINVAL; | |
550 | } | |
551 | ||
552 | break; | |
553 | default: | |
554 | return -ENOTSUPP; | |
555 | } | |
556 | ||
557 | goto out; | |
558 | } | |
559 | ||
560 | switch (param) { | |
561 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
6489677f AS |
562 | ret = regmap_read(pctl->regmap, |
563 | pctl->data->reg_pulldn, | |
564 | &data); | |
565 | data &= BIT(pin); | |
9e80f906 NA |
566 | |
567 | if (ret < 0) | |
568 | return ret; | |
569 | ||
570 | if (!ret) | |
571 | return -EINVAL; | |
572 | ||
573 | arg = 1; | |
574 | break; | |
575 | ||
576 | case PIN_CONFIG_BIAS_PULL_UP: | |
6489677f AS |
577 | ret = regmap_read(pctl->regmap, |
578 | pctl->data->reg_pullup, | |
579 | &data); | |
580 | data &= BIT(pin); | |
9e80f906 NA |
581 | |
582 | if (ret < 0) | |
583 | return ret; | |
584 | ||
585 | if (!ret) | |
586 | return -EINVAL; | |
587 | ||
588 | arg = 1; | |
589 | break; | |
590 | ||
591 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
592 | if (pctl->data->model != SX150X_789) | |
593 | return -ENOTSUPP; | |
594 | ||
6489677f AS |
595 | ret = regmap_read(pctl->regmap, |
596 | pctl->data->pri.x789.reg_drain, | |
597 | &data); | |
598 | data &= BIT(pin); | |
9e80f906 NA |
599 | |
600 | if (ret < 0) | |
601 | return ret; | |
602 | ||
6489677f | 603 | if (!data) |
9e80f906 NA |
604 | return -EINVAL; |
605 | ||
606 | arg = 1; | |
607 | break; | |
608 | ||
609 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
610 | if (pctl->data->model != SX150X_789) | |
611 | arg = true; | |
612 | else { | |
6489677f AS |
613 | ret = regmap_read(pctl->regmap, |
614 | pctl->data->pri.x789.reg_drain, | |
615 | &data); | |
616 | data &= BIT(pin); | |
9e80f906 NA |
617 | |
618 | if (ret < 0) | |
619 | return ret; | |
620 | ||
6489677f | 621 | if (data) |
9e80f906 NA |
622 | return -EINVAL; |
623 | ||
624 | arg = 1; | |
625 | } | |
626 | break; | |
627 | ||
628 | case PIN_CONFIG_OUTPUT: | |
629 | ret = sx150x_gpio_get_direction(&pctl->gpio, pin); | |
630 | if (ret < 0) | |
631 | return ret; | |
632 | ||
633 | if (ret) | |
634 | return -EINVAL; | |
635 | ||
636 | ret = sx150x_gpio_get(&pctl->gpio, pin); | |
637 | if (ret < 0) | |
638 | return ret; | |
639 | ||
640 | arg = ret; | |
641 | break; | |
642 | ||
643 | default: | |
644 | return -ENOTSUPP; | |
645 | } | |
646 | ||
647 | out: | |
648 | *config = pinconf_to_config_packed(param, arg); | |
649 | ||
650 | return 0; | |
651 | } | |
652 | ||
653 | static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
654 | unsigned long *configs, unsigned int num_configs) | |
655 | { | |
656 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
657 | enum pin_config_param param; | |
658 | u32 arg; | |
659 | int i; | |
660 | int ret; | |
661 | ||
662 | for (i = 0; i < num_configs; i++) { | |
663 | param = pinconf_to_config_param(configs[i]); | |
664 | arg = pinconf_to_config_argument(configs[i]); | |
665 | ||
666 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
667 | if (param == PIN_CONFIG_OUTPUT) { | |
668 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
669 | pin, arg); | |
670 | if (ret < 0) | |
671 | return ret; | |
672 | ||
673 | continue; | |
674 | } else | |
675 | return -ENOTSUPP; | |
676 | } | |
677 | ||
678 | switch (param) { | |
679 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
680 | case PIN_CONFIG_BIAS_DISABLE: | |
6489677f AS |
681 | ret = regmap_write_bits(pctl->regmap, |
682 | pctl->data->reg_pulldn, | |
683 | BIT(pin), 0); | |
9e80f906 NA |
684 | if (ret < 0) |
685 | return ret; | |
686 | ||
6489677f AS |
687 | ret = regmap_write_bits(pctl->regmap, |
688 | pctl->data->reg_pullup, | |
689 | BIT(pin), 0); | |
9e80f906 NA |
690 | if (ret < 0) |
691 | return ret; | |
692 | ||
693 | break; | |
694 | ||
695 | case PIN_CONFIG_BIAS_PULL_UP: | |
6489677f AS |
696 | ret = regmap_write_bits(pctl->regmap, |
697 | pctl->data->reg_pullup, | |
698 | BIT(pin), BIT(pin)); | |
9e80f906 NA |
699 | if (ret < 0) |
700 | return ret; | |
701 | ||
702 | break; | |
703 | ||
704 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
6489677f AS |
705 | ret = regmap_write_bits(pctl->regmap, |
706 | pctl->data->reg_pulldn, | |
707 | BIT(pin), BIT(pin)); | |
9e80f906 NA |
708 | if (ret < 0) |
709 | return ret; | |
710 | ||
711 | break; | |
712 | ||
713 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
714 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
715 | pin, LINE_MODE_OPEN_DRAIN); | |
716 | if (ret < 0) | |
717 | return ret; | |
718 | ||
719 | break; | |
720 | ||
721 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
722 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
723 | pin, LINE_MODE_PUSH_PULL); | |
724 | if (ret < 0) | |
725 | return ret; | |
726 | ||
727 | break; | |
728 | ||
729 | case PIN_CONFIG_OUTPUT: | |
730 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
731 | pin, arg); | |
732 | if (ret < 0) | |
733 | return ret; | |
734 | ||
735 | break; | |
736 | ||
737 | default: | |
738 | return -ENOTSUPP; | |
739 | } | |
740 | } /* for each config */ | |
741 | ||
742 | return 0; | |
743 | } | |
744 | ||
745 | static const struct pinconf_ops sx150x_pinconf_ops = { | |
746 | .pin_config_get = sx150x_pinconf_get, | |
747 | .pin_config_set = sx150x_pinconf_set, | |
748 | .is_generic = true, | |
749 | }; | |
750 | ||
751 | static const struct i2c_device_id sx150x_id[] = { | |
752 | {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, | |
753 | {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, | |
754 | {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, | |
755 | {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, | |
6697546d | 756 | {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, |
9e80f906 NA |
757 | {} |
758 | }; | |
759 | ||
760 | static const struct of_device_id sx150x_of_match[] = { | |
e3ba8120 AS |
761 | { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, |
762 | { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, | |
763 | { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, | |
764 | { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, | |
6697546d | 765 | { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, |
9e80f906 NA |
766 | {}, |
767 | }; | |
768 | ||
9e80f906 NA |
769 | static int sx150x_reset(struct sx150x_pinctrl *pctl) |
770 | { | |
771 | int err; | |
772 | ||
773 | err = i2c_smbus_write_byte_data(pctl->client, | |
774 | pctl->data->pri.x789.reg_reset, | |
f9038d60 | 775 | SX150X_789_RESET_KEY1); |
9e80f906 NA |
776 | if (err < 0) |
777 | return err; | |
778 | ||
779 | err = i2c_smbus_write_byte_data(pctl->client, | |
780 | pctl->data->pri.x789.reg_reset, | |
f9038d60 | 781 | SX150X_789_RESET_KEY2); |
9e80f906 NA |
782 | return err; |
783 | } | |
784 | ||
310cdfa0 AS |
785 | static int sx150x_init_misc(struct sx150x_pinctrl *pctl) |
786 | { | |
787 | u8 reg, value; | |
788 | ||
789 | switch (pctl->data->model) { | |
790 | case SX150X_789: | |
791 | reg = pctl->data->pri.x789.reg_misc; | |
792 | value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; | |
793 | break; | |
794 | case SX150X_456: | |
795 | reg = pctl->data->pri.x456.reg_advance; | |
796 | value = 0x00; | |
b30d31e4 AS |
797 | |
798 | /* | |
799 | * Only SX1506 has RegAdvanced, SX1504/5 are expected | |
800 | * to initialize this offset to zero | |
801 | */ | |
802 | if (!reg) | |
803 | return 0; | |
310cdfa0 AS |
804 | break; |
805 | case SX150X_123: | |
806 | reg = pctl->data->pri.x123.reg_advance; | |
807 | value = 0x00; | |
808 | break; | |
809 | default: | |
810 | WARN(1, "Unknown chip model %d\n", pctl->data->model); | |
811 | return -EINVAL; | |
812 | } | |
813 | ||
6489677f | 814 | return regmap_write(pctl->regmap, reg, value); |
310cdfa0 AS |
815 | } |
816 | ||
9e80f906 NA |
817 | static int sx150x_init_hw(struct sx150x_pinctrl *pctl) |
818 | { | |
6489677f AS |
819 | const u8 reg[] = { |
820 | [SX150X_789] = pctl->data->pri.x789.reg_polarity, | |
821 | [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, | |
822 | [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, | |
823 | }; | |
9e80f906 NA |
824 | int err; |
825 | ||
826 | if (pctl->data->model == SX150X_789 && | |
827 | of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { | |
828 | err = sx150x_reset(pctl); | |
829 | if (err < 0) | |
830 | return err; | |
831 | } | |
832 | ||
310cdfa0 | 833 | err = sx150x_init_misc(pctl); |
9e80f906 NA |
834 | if (err < 0) |
835 | return err; | |
836 | ||
837 | /* Set all pins to work in normal mode */ | |
6489677f AS |
838 | return regmap_write(pctl->regmap, reg[pctl->data->model], 0); |
839 | } | |
840 | ||
841 | static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, | |
842 | unsigned int reg) | |
843 | { | |
844 | const struct sx150x_device_data *data = pctl->data; | |
845 | ||
846 | if (reg == data->reg_sense) { | |
847 | /* | |
848 | * RegSense packs two bits of configuration per GPIO, | |
849 | * so we'd need to read twice as many bits as there | |
850 | * are GPIO in our chip | |
851 | */ | |
852 | return 2 * data->ngpios; | |
853 | } else if ((data->model == SX150X_789 && | |
854 | (reg == data->pri.x789.reg_misc || | |
855 | reg == data->pri.x789.reg_clock || | |
856 | reg == data->pri.x789.reg_reset)) | |
857 | || | |
858 | (data->model == SX150X_123 && | |
859 | reg == data->pri.x123.reg_advance) | |
860 | || | |
861 | (data->model == SX150X_456 && | |
862 | reg == data->pri.x456.reg_advance)) { | |
863 | return 8; | |
9e80f906 | 864 | } else { |
6489677f AS |
865 | return data->ngpios; |
866 | } | |
867 | } | |
868 | ||
869 | static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, | |
870 | unsigned int reg, unsigned int val) | |
871 | { | |
872 | unsigned int a, b; | |
873 | const struct sx150x_device_data *data = pctl->data; | |
874 | ||
875 | /* | |
876 | * Whereas SX1509 presents RegSense in a simple layout as such: | |
877 | * reg [ f f e e d d c c ] | |
878 | * reg + 1 [ b b a a 9 9 8 8 ] | |
879 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] | |
880 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
881 | * | |
882 | * SX1503 and SX1506 deviate from that data layout, instead storing | |
7bd47496 | 883 | * their contents as follows: |
6489677f AS |
884 | * |
885 | * reg [ f f e e d d c c ] | |
886 | * reg + 1 [ 7 7 6 6 5 5 4 4 ] | |
887 | * reg + 2 [ b b a a 9 9 8 8 ] | |
888 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
889 | * | |
890 | * so, taking that into account, we swap two | |
891 | * inner bytes of a 4-byte result | |
892 | */ | |
893 | ||
894 | if (reg == data->reg_sense && | |
895 | data->ngpios == 16 && | |
896 | (data->model == SX150X_123 || | |
897 | data->model == SX150X_456)) { | |
898 | a = val & 0x00ff0000; | |
899 | b = val & 0x0000ff00; | |
900 | ||
901 | val &= 0xff0000ff; | |
902 | val |= b << 8; | |
903 | val |= a >> 8; | |
9e80f906 NA |
904 | } |
905 | ||
6489677f AS |
906 | return val; |
907 | } | |
908 | ||
909 | /* | |
910 | * In order to mask the differences between 16 and 8 bit expander | |
911 | * devices we set up a sligthly ficticious regmap that pretends to be | |
912 | * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh | |
913 | * pair/quartet) registers and transparently reconstructs those | |
914 | * registers via multiple I2C/SMBus reads | |
915 | * | |
916 | * This way the rest of the driver code, interfacing with the chip via | |
917 | * regmap API, can work assuming that each GPIO pin is represented by | |
7bd47496 | 918 | * a group of bits at an offset proportional to GPIO number within a |
6489677f | 919 | * given register. |
6489677f AS |
920 | */ |
921 | static int sx150x_regmap_reg_read(void *context, unsigned int reg, | |
922 | unsigned int *result) | |
923 | { | |
924 | int ret, n; | |
925 | struct sx150x_pinctrl *pctl = context; | |
926 | struct i2c_client *i2c = pctl->client; | |
927 | const int width = sx150x_regmap_reg_width(pctl, reg); | |
928 | unsigned int idx, val; | |
929 | ||
930 | /* | |
7bd47496 | 931 | * There are four potential cases covered by this function: |
6489677f AS |
932 | * |
933 | * 1) 8-pin chip, single configuration bit register | |
934 | * | |
935 | * This is trivial the code below just needs to read: | |
936 | * reg [ 7 6 5 4 3 2 1 0 ] | |
937 | * | |
938 | * 2) 8-pin chip, double configuration bit register (RegSense) | |
939 | * | |
940 | * The read will be done as follows: | |
941 | * reg [ 7 7 6 6 5 5 4 4 ] | |
942 | * reg + 1 [ 3 3 2 2 1 1 0 0 ] | |
943 | * | |
944 | * 3) 16-pin chip, single configuration bit register | |
945 | * | |
946 | * The read will be done as follows: | |
947 | * reg [ f e d c b a 9 8 ] | |
948 | * reg + 1 [ 7 6 5 4 3 2 1 0 ] | |
949 | * | |
950 | * 4) 16-pin chip, double configuration bit register (RegSense) | |
951 | * | |
952 | * The read will be done as follows: | |
953 | * reg [ f f e e d d c c ] | |
954 | * reg + 1 [ b b a a 9 9 8 8 ] | |
955 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] | |
956 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
957 | */ | |
958 | ||
959 | for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { | |
960 | val <<= 8; | |
961 | ||
962 | ret = i2c_smbus_read_byte_data(i2c, idx); | |
963 | if (ret < 0) | |
964 | return ret; | |
965 | ||
966 | val |= ret; | |
967 | } | |
968 | ||
969 | *result = sx150x_maybe_swizzle(pctl, reg, val); | |
970 | ||
971 | return 0; | |
972 | } | |
973 | ||
974 | static int sx150x_regmap_reg_write(void *context, unsigned int reg, | |
975 | unsigned int val) | |
976 | { | |
977 | int ret, n; | |
978 | struct sx150x_pinctrl *pctl = context; | |
979 | struct i2c_client *i2c = pctl->client; | |
980 | const int width = sx150x_regmap_reg_width(pctl, reg); | |
981 | ||
982 | val = sx150x_maybe_swizzle(pctl, reg, val); | |
983 | ||
984 | n = width - 8; | |
985 | do { | |
986 | const u8 byte = (val >> n) & 0xff; | |
987 | ||
988 | ret = i2c_smbus_write_byte_data(i2c, reg, byte); | |
989 | if (ret < 0) | |
990 | return ret; | |
991 | ||
992 | reg++; | |
993 | n -= 8; | |
994 | } while (n >= 0); | |
995 | ||
9e80f906 NA |
996 | return 0; |
997 | } | |
998 | ||
0db0f26c AS |
999 | static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) |
1000 | { | |
1001 | struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); | |
1002 | ||
6489677f | 1003 | return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; |
0db0f26c AS |
1004 | } |
1005 | ||
1006 | const struct regmap_config sx150x_regmap_config = { | |
1007 | .reg_bits = 8, | |
6489677f | 1008 | .val_bits = 32, |
0db0f26c AS |
1009 | |
1010 | .cache_type = REGCACHE_RBTREE, | |
1011 | ||
6489677f AS |
1012 | .reg_read = sx150x_regmap_reg_read, |
1013 | .reg_write = sx150x_regmap_reg_write, | |
1014 | ||
0db0f26c AS |
1015 | .max_register = SX150X_MAX_REGISTER, |
1016 | .volatile_reg = sx150x_reg_volatile, | |
1017 | }; | |
1018 | ||
9e80f906 NA |
1019 | static int sx150x_probe(struct i2c_client *client, |
1020 | const struct i2c_device_id *id) | |
1021 | { | |
1022 | static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | | |
1023 | I2C_FUNC_SMBUS_WRITE_WORD_DATA; | |
1024 | struct device *dev = &client->dev; | |
1025 | struct sx150x_pinctrl *pctl; | |
1026 | int ret; | |
1027 | ||
9e80f906 NA |
1028 | if (!i2c_check_functionality(client->adapter, i2c_funcs)) |
1029 | return -ENOSYS; | |
1030 | ||
1031 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
1032 | if (!pctl) | |
1033 | return -ENOMEM; | |
1034 | ||
0db0f26c AS |
1035 | i2c_set_clientdata(client, pctl); |
1036 | ||
9e80f906 NA |
1037 | pctl->dev = dev; |
1038 | pctl->client = client; | |
e3ba8120 AS |
1039 | |
1040 | if (dev->of_node) | |
1041 | pctl->data = of_device_get_match_data(dev); | |
1042 | else | |
1043 | pctl->data = (struct sx150x_device_data *)id->driver_data; | |
1044 | ||
1045 | if (!pctl->data) | |
1046 | return -EINVAL; | |
9e80f906 | 1047 | |
6489677f AS |
1048 | pctl->regmap = devm_regmap_init(dev, NULL, pctl, |
1049 | &sx150x_regmap_config); | |
0db0f26c AS |
1050 | if (IS_ERR(pctl->regmap)) { |
1051 | ret = PTR_ERR(pctl->regmap); | |
1052 | dev_err(dev, "Failed to allocate register map: %d\n", | |
1053 | ret); | |
1054 | return ret; | |
1055 | } | |
1056 | ||
9e80f906 NA |
1057 | mutex_init(&pctl->lock); |
1058 | ||
1059 | ret = sx150x_init_hw(pctl); | |
1060 | if (ret) | |
1061 | return ret; | |
1062 | ||
1063 | /* Register GPIO controller */ | |
1064 | pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); | |
1065 | pctl->gpio.base = -1; | |
1066 | pctl->gpio.ngpio = pctl->data->npins; | |
1067 | pctl->gpio.get_direction = sx150x_gpio_get_direction; | |
1068 | pctl->gpio.direction_input = sx150x_gpio_direction_input; | |
1069 | pctl->gpio.direction_output = sx150x_gpio_direction_output; | |
1070 | pctl->gpio.get = sx150x_gpio_get; | |
1071 | pctl->gpio.set = sx150x_gpio_set; | |
1072 | pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended; | |
1073 | pctl->gpio.parent = dev; | |
1074 | #ifdef CONFIG_OF_GPIO | |
1075 | pctl->gpio.of_node = dev->of_node; | |
1076 | #endif | |
1077 | pctl->gpio.can_sleep = true; | |
1078 | ||
1079 | ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); | |
1080 | if (ret) | |
1081 | return ret; | |
1082 | ||
1083 | /* Add Interrupt support if an irq is specified */ | |
1084 | if (client->irq > 0) { | |
1085 | pctl->irq_chip.name = devm_kstrdup(dev, client->name, | |
1086 | GFP_KERNEL); | |
1087 | pctl->irq_chip.irq_mask = sx150x_irq_mask; | |
1088 | pctl->irq_chip.irq_unmask = sx150x_irq_unmask; | |
1089 | pctl->irq_chip.irq_set_type = sx150x_irq_set_type; | |
1090 | pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; | |
1091 | pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; | |
1092 | ||
1093 | pctl->irq.masked = ~0; | |
1094 | pctl->irq.sense = 0; | |
9e80f906 | 1095 | |
080c489d AS |
1096 | /* |
1097 | * Because sx150x_irq_threaded_fn invokes all of the | |
1098 | * nested interrrupt handlers via handle_nested_irq, | |
1099 | * any "handler" passed to gpiochip_irqchip_add() | |
1100 | * below is going to be ignored, so the choice of the | |
1101 | * function does not matter that much. | |
1102 | * | |
1103 | * We set it to handle_bad_irq to avoid confusion, | |
1104 | * plus it will be instantly noticeable if it is ever | |
1105 | * called (should not happen) | |
1106 | */ | |
9e80f906 NA |
1107 | ret = gpiochip_irqchip_add(&pctl->gpio, |
1108 | &pctl->irq_chip, 0, | |
080c489d | 1109 | handle_bad_irq, IRQ_TYPE_NONE); |
9e80f906 NA |
1110 | if (ret) { |
1111 | dev_err(dev, "could not connect irqchip to gpiochip\n"); | |
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | ret = devm_request_threaded_irq(dev, client->irq, NULL, | |
1116 | sx150x_irq_thread_fn, | |
1117 | IRQF_ONESHOT | IRQF_SHARED | | |
1118 | IRQF_TRIGGER_FALLING, | |
1119 | pctl->irq_chip.name, pctl); | |
1120 | if (ret < 0) | |
1121 | return ret; | |
1122 | } | |
1123 | ||
1124 | /* Pinctrl_desc */ | |
1125 | pctl->pinctrl_desc.name = "sx150x-pinctrl"; | |
1126 | pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; | |
1127 | pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; | |
1128 | pctl->pinctrl_desc.pins = pctl->data->pins; | |
1129 | pctl->pinctrl_desc.npins = pctl->data->npins; | |
1130 | pctl->pinctrl_desc.owner = THIS_MODULE; | |
1131 | ||
1132 | pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl); | |
1133 | if (IS_ERR(pctl->pctldev)) { | |
1134 | dev_err(dev, "Failed to register pinctrl device\n"); | |
1135 | return PTR_ERR(pctl->pctldev); | |
1136 | } | |
1137 | ||
1138 | return 0; | |
1139 | } | |
1140 | ||
1141 | static struct i2c_driver sx150x_driver = { | |
1142 | .driver = { | |
1143 | .name = "sx150x-pinctrl", | |
1144 | .of_match_table = of_match_ptr(sx150x_of_match), | |
1145 | }, | |
1146 | .probe = sx150x_probe, | |
1147 | .id_table = sx150x_id, | |
1148 | }; | |
1149 | ||
1150 | static int __init sx150x_init(void) | |
1151 | { | |
1152 | return i2c_add_driver(&sx150x_driver); | |
1153 | } | |
1154 | subsys_initcall(sx150x_init); |