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bindings: pinctrl-sx150x: Document SX1503 compatibility string
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / pinctrl-sx150x.c
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9e80f906
NA		 1/*
2 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
3 * Author: Neil Armstrong <narmstrong@baylibre.com>
4 *
5 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
6 *
7 * Driver for Semtech SX150X I2C GPIO Expanders
8 *
9 * Author: Gregory Bean <gbean@codeaurora.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 and
13 * only version 2 as published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21#include <linux/i2c.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/mutex.h>
26#include <linux/slab.h>
27#include <linux/of.h>
e3ba8120 28#include <linux/of_device.h>
9e80f906
NA		 29#include <linux/gpio.h>
30#include <linux/pinctrl/machine.h>
31#include <linux/pinctrl/pinconf.h>
32#include <linux/pinctrl/pinctrl.h>
33#include <linux/pinctrl/pinmux.h>
34#include <linux/pinctrl/pinconf-generic.h>
35
36#include "core.h"
37#include "pinconf.h"
38#include "pinctrl-utils.h"
39
40/* The chip models of sx150x */
41enum {
42 SX150X_123 = 0,
43 SX150X_456,
44 SX150X_789,
45};
46
47struct sx150x_123_pri {
48 u8 reg_pld_mode;
49 u8 reg_pld_table0;
50 u8 reg_pld_table1;
51 u8 reg_pld_table2;
52 u8 reg_pld_table3;
53 u8 reg_pld_table4;
54 u8 reg_advance;
55};
56
57struct sx150x_456_pri {
58 u8 reg_pld_mode;
59 u8 reg_pld_table0;
60 u8 reg_pld_table1;
61 u8 reg_pld_table2;
62 u8 reg_pld_table3;
63 u8 reg_pld_table4;
64 u8 reg_advance;
65};
66
67struct sx150x_789_pri {
68 u8 reg_drain;
69 u8 reg_polarity;
70 u8 reg_clock;
71 u8 reg_misc;
72 u8 reg_reset;
73 u8 ngpios;
74};
75
76struct sx150x_device_data {
77 u8 model;
78 u8 reg_pullup;
79 u8 reg_pulldn;
80 u8 reg_dir;
81 u8 reg_data;
82 u8 reg_irq_mask;
83 u8 reg_irq_src;
84 u8 reg_sense;
85 u8 ngpios;
86 union {
87 struct sx150x_123_pri x123;
88 struct sx150x_456_pri x456;
89 struct sx150x_789_pri x789;
90 } pri;
91 const struct pinctrl_pin_desc *pins;
92 unsigned int npins;
93};
94
95struct sx150x_pinctrl {
96 struct device *dev;
97 struct i2c_client *client;
98 struct pinctrl_dev *pctldev;
99 struct pinctrl_desc pinctrl_desc;
100 struct gpio_chip gpio;
101 struct irq_chip irq_chip;
102 struct {
103 int update;
104 u32 sense;
105 u32 masked;
106 u32 dev_sense;
107 u32 dev_masked;
108 } irq;
109 struct mutex lock;
110 const struct sx150x_device_data *data;
111};
112
113static const struct pinctrl_pin_desc sx150x_8_pins[] = {
114 PINCTRL_PIN(0, "gpio0"),
115 PINCTRL_PIN(1, "gpio1"),
116 PINCTRL_PIN(2, "gpio2"),
117 PINCTRL_PIN(3, "gpio3"),
118 PINCTRL_PIN(4, "gpio4"),
119 PINCTRL_PIN(5, "gpio5"),
120 PINCTRL_PIN(6, "gpio6"),
121 PINCTRL_PIN(7, "gpio7"),
122 PINCTRL_PIN(8, "oscio"),
123};
124
125static const struct pinctrl_pin_desc sx150x_16_pins[] = {
126 PINCTRL_PIN(0, "gpio0"),
127 PINCTRL_PIN(1, "gpio1"),
128 PINCTRL_PIN(2, "gpio2"),
129 PINCTRL_PIN(3, "gpio3"),
130 PINCTRL_PIN(4, "gpio4"),
131 PINCTRL_PIN(5, "gpio5"),
132 PINCTRL_PIN(6, "gpio6"),
133 PINCTRL_PIN(7, "gpio7"),
134 PINCTRL_PIN(8, "gpio8"),
135 PINCTRL_PIN(9, "gpio9"),
136 PINCTRL_PIN(10, "gpio10"),
137 PINCTRL_PIN(11, "gpio11"),
138 PINCTRL_PIN(12, "gpio12"),
139 PINCTRL_PIN(13, "gpio13"),
140 PINCTRL_PIN(14, "gpio14"),
141 PINCTRL_PIN(15, "gpio15"),
142 PINCTRL_PIN(16, "oscio"),
143};
144
145static const struct sx150x_device_data sx1508q_device_data = {
146 .model = SX150X_789,
147 .reg_pullup = 0x03,
148 .reg_pulldn = 0x04,
149 .reg_dir = 0x07,
150 .reg_data = 0x08,
151 .reg_irq_mask = 0x09,
152 .reg_irq_src = 0x0c,
153 .reg_sense = 0x0b,
154 .pri.x789 = {
155 .reg_drain = 0x05,
156 .reg_polarity = 0x06,
157 .reg_clock = 0x0f,
158 .reg_misc = 0x10,
159 .reg_reset = 0x7d,
160 },
161 .ngpios = 8,
162 .pins = sx150x_8_pins,
163 .npins = ARRAY_SIZE(sx150x_8_pins),
164};
165
166static const struct sx150x_device_data sx1509q_device_data = {
167 .model = SX150X_789,
168 .reg_pullup = 0x07,
169 .reg_pulldn = 0x09,
170 .reg_dir = 0x0f,
171 .reg_data = 0x11,
172 .reg_irq_mask = 0x13,
173 .reg_irq_src = 0x19,
174 .reg_sense = 0x17,
175 .pri.x789 = {
176 .reg_drain = 0x0b,
177 .reg_polarity = 0x0d,
178 .reg_clock = 0x1e,
179 .reg_misc = 0x1f,
180 .reg_reset = 0x7d,
181 },
182 .ngpios = 16,
183 .pins = sx150x_16_pins,
184 .npins = ARRAY_SIZE(sx150x_16_pins),
185};
186
187static const struct sx150x_device_data sx1506q_device_data = {
188 .model = SX150X_456,
189 .reg_pullup = 0x05,
190 .reg_pulldn = 0x07,
191 .reg_dir = 0x03,
192 .reg_data = 0x01,
193 .reg_irq_mask = 0x09,
194 .reg_irq_src = 0x0f,
195 .reg_sense = 0x0d,
196 .pri.x456 = {
197 .reg_pld_mode = 0x21,
198 .reg_pld_table0 = 0x23,
199 .reg_pld_table1 = 0x25,
200 .reg_pld_table2 = 0x27,
201 .reg_pld_table3 = 0x29,
202 .reg_pld_table4 = 0x2b,
203 .reg_advance = 0xad,
204 },
205 .ngpios = 16,
206 .pins = sx150x_16_pins,
207 .npins = 16, /* oscio not available */
208};
209
210static const struct sx150x_device_data sx1502q_device_data = {
211 .model = SX150X_123,
212 .reg_pullup = 0x02,
213 .reg_pulldn = 0x03,
214 .reg_dir = 0x01,
215 .reg_data = 0x00,
216 .reg_irq_mask = 0x05,
217 .reg_irq_src = 0x08,
218 .reg_sense = 0x07,
219 .pri.x123 = {
220 .reg_pld_mode = 0x10,
221 .reg_pld_table0 = 0x11,
222 .reg_pld_table1 = 0x12,
223 .reg_pld_table2 = 0x13,
224 .reg_pld_table3 = 0x14,
225 .reg_pld_table4 = 0x15,
226 .reg_advance = 0xad,
227 },
228 .ngpios = 8,
229 .pins = sx150x_8_pins,
230 .npins = 8, /* oscio not available */
231};
232
6697546d
AS		 233static const struct sx150x_device_data sx1503q_device_data = {
234 .model = SX150X_123,
235 .reg_pullup = 0x05,
236 .reg_pulldn = 0x07,
237 .reg_dir = 0x03,
238 .reg_data = 0x01,
239 .reg_irq_mask = 0x09,
240 .reg_irq_src = 0x0f,
241 .reg_sense = 0x07,
242 .pri.x123 = {
243 .reg_pld_mode = 0x10,
244 .reg_pld_table0 = 0x11,
245 .reg_pld_table1 = 0x12,
246 .reg_pld_table2 = 0x13,
247 .reg_pld_table3 = 0x14,
248 .reg_pld_table4 = 0x15,
249 .reg_advance = 0xad,
250 },
251 .ngpios = 16,
252 .pins = sx150x_16_pins,
253 .npins = 16, /* oscio not available */
254};
255
9e80f906
NA		 256static s32 sx150x_i2c_write(struct i2c_client *client, u8 reg, u8 val)
257{
258 s32 err = i2c_smbus_write_byte_data(client, reg, val);
259
260 if (err < 0)
261 dev_warn(&client->dev,
262 "i2c write fail: can't write %02x to %02x: %d\n",
263 val, reg, err);
264 return err;
265}
266
267static s32 sx150x_i2c_read(struct i2c_client *client, u8 reg, u8 *val)
268{
269 s32 err = i2c_smbus_read_byte_data(client, reg);
270
271 if (err >= 0)
272 *val = err;
273 else
274 dev_warn(&client->dev,
275 "i2c read fail: can't read from %02x: %d\n",
276 reg, err);
277 return err;
278}
279
280/*
281 * These utility functions solve the common problem of locating and setting
282 * configuration bits. Configuration bits are grouped into registers
283 * whose indexes increase downwards. For example, with eight-bit registers,
284 * sixteen gpios would have their config bits grouped in the following order:
285 * REGISTER N-1 [ f e d c b a 9 8 ]
286 * N [ 7 6 5 4 3 2 1 0 ]
287 *
288 * For multi-bit configurations, the pattern gets wider:
289 * REGISTER N-3 [ f f e e d d c c ]
290 * N-2 [ b b a a 9 9 8 8 ]
291 * N-1 [ 7 7 6 6 5 5 4 4 ]
292 * N [ 3 3 2 2 1 1 0 0 ]
293 *
294 * Given the address of the starting register 'N', the index of the gpio
295 * whose configuration we seek to change, and the width in bits of that
296 * configuration, these functions allow us to locate the correct
297 * register and mask the correct bits.
298 */
299static inline void sx150x_find_cfg(u8 offset, u8 width,
300 u8 *reg, u8 *mask, u8 *shift)
301{
302 *reg -= offset * width / 8;
303 *mask = (1 << width) - 1;
304 *shift = (offset * width) % 8;
305 *mask <<= *shift;
306}
307
308static int sx150x_write_cfg(struct i2c_client *client,
309 u8 offset, u8 width, u8 reg, u8 val)
310{
311 u8 mask;
312 u8 data;
313 u8 shift;
314 int err;
315
316 sx150x_find_cfg(offset, width, &reg, &mask, &shift);
317 err = sx150x_i2c_read(client, reg, &data);
318 if (err < 0)
319 return err;
320
321 data &= ~mask;
322 data |= (val << shift) & mask;
323 return sx150x_i2c_write(client, reg, data);
324}
325
326static int sx150x_read_cfg(struct i2c_client *client,
327 u8 offset, u8 width, u8 reg)
328{
329 u8 mask;
330 u8 data;
331 u8 shift;
332 int err;
333
334 sx150x_find_cfg(offset, width, &reg, &mask, &shift);
335 err = sx150x_i2c_read(client, reg, &data);
336 if (err < 0)
337 return err;
338
339 return (data & mask);
340}
341
342static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
343{
344 return 0;
345}
346
347static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
348 unsigned int group)
349{
350 return NULL;
351}
352
353static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
354 unsigned int group,
355 const unsigned int **pins,
356 unsigned int *num_pins)
357{
358 return -ENOTSUPP;
359}
360
361static const struct pinctrl_ops sx150x_pinctrl_ops = {
362 .get_groups_count = sx150x_pinctrl_get_groups_count,
363 .get_group_name = sx150x_pinctrl_get_group_name,
364 .get_group_pins = sx150x_pinctrl_get_group_pins,
365#ifdef CONFIG_OF
366 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
367 .dt_free_map = pinctrl_utils_free_map,
368#endif
369};
370
371static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
372{
373 if (pin >= pctl->data->npins)
374 return false;
375
376 /* OSCIO pin is only present in 789 devices */
377 if (pctl->data->model != SX150X_789)
378 return false;
379
380 return !strcmp(pctl->data->pins[pin].name, "oscio");
381}
382
383static int sx150x_gpio_get_direction(struct gpio_chip *chip,
384 unsigned int offset)
385{
386 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
387 int status;
388
389 if (sx150x_pin_is_oscio(pctl, offset))
390 return false;
391
392 status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_dir);
393 if (status >= 0)
394 status = !!status;
395
396 return status;
397}
398
399static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
400{
401 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
402 int status;
403
404 if (sx150x_pin_is_oscio(pctl, offset))
405 return -EINVAL;
406
407 status = sx150x_read_cfg(pctl->client, offset, 1, pctl->data->reg_data);
408 if (status >= 0)
409 status = !!status;
410
411 return status;
412}
413
414static int sx150x_gpio_set_single_ended(struct gpio_chip *chip,
415 unsigned int offset,
416 enum single_ended_mode mode)
417{
418 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
419 int ret;
420
421 switch (mode) {
422 case LINE_MODE_PUSH_PULL:
423 if (pctl->data->model != SX150X_789 ||
424 sx150x_pin_is_oscio(pctl, offset))
425 return 0;
426
427 mutex_lock(&pctl->lock);
428 ret = sx150x_write_cfg(pctl->client, offset, 1,
429 pctl->data->pri.x789.reg_drain,
430 0);
431 mutex_unlock(&pctl->lock);
432 if (ret < 0)
433 return ret;
434 break;
435
436 case LINE_MODE_OPEN_DRAIN:
437 if (pctl->data->model != SX150X_789 ||
438 sx150x_pin_is_oscio(pctl, offset))
439 return -ENOTSUPP;
440
441 mutex_lock(&pctl->lock);
442 ret = sx150x_write_cfg(pctl->client, offset, 1,
443 pctl->data->pri.x789.reg_drain,
444 1);
445 mutex_unlock(&pctl->lock);
446 if (ret < 0)
447 return ret;
448 break;
449
450 default:
451 return -ENOTSUPP;
452 }
453
454 return 0;
455}
456
457static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
458 int value)
459{
460 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
461
462 if (sx150x_pin_is_oscio(pctl, offset)) {
463
464 mutex_lock(&pctl->lock);
465 sx150x_i2c_write(pctl->client,
466 pctl->data->pri.x789.reg_clock,
467 (value ? 0x1f : 0x10));
468 mutex_unlock(&pctl->lock);
469 } else {
470 mutex_lock(&pctl->lock);
471 sx150x_write_cfg(pctl->client, offset, 1,
472 pctl->data->reg_data,
473 (value ? 1 : 0));
474 mutex_unlock(&pctl->lock);
475 }
476}
477
478static int sx150x_gpio_direction_input(struct gpio_chip *chip,
479 unsigned int offset)
480{
481 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
482 int ret;
483
484 if (sx150x_pin_is_oscio(pctl, offset))
485 return -EINVAL;
486
487 mutex_lock(&pctl->lock);
488 ret = sx150x_write_cfg(pctl->client, offset, 1,
489 pctl->data->reg_dir, 1);
490 mutex_unlock(&pctl->lock);
491
492 return ret;
493}
494
495static int sx150x_gpio_direction_output(struct gpio_chip *chip,
496 unsigned int offset, int value)
497{
498 struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
499 int status;
500
501 if (sx150x_pin_is_oscio(pctl, offset)) {
502 sx150x_gpio_set(chip, offset, value);
503 return 0;
504 }
505
506 mutex_lock(&pctl->lock);
507 status = sx150x_write_cfg(pctl->client, offset, 1,
508 pctl->data->reg_data,
509 (value ? 1 : 0));
510 if (status >= 0)
511 status = sx150x_write_cfg(pctl->client, offset, 1,
512 pctl->data->reg_dir, 0);
513 mutex_unlock(&pctl->lock);
514
515 return status;
516}
517
518static void sx150x_irq_mask(struct irq_data *d)
519{
520 struct sx150x_pinctrl *pctl =
521 gpiochip_get_data(irq_data_get_irq_chip_data(d));
522 unsigned int n = d->hwirq;
523
524 pctl->irq.masked |= (1 << n);
525 pctl->irq.update = n;
526}
527
528static void sx150x_irq_unmask(struct irq_data *d)
529{
530 struct sx150x_pinctrl *pctl =
531 gpiochip_get_data(irq_data_get_irq_chip_data(d));
532 unsigned int n = d->hwirq;
533
534 pctl->irq.masked &= ~(1 << n);
535 pctl->irq.update = n;
536}
537
538static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
539{
540 struct sx150x_pinctrl *pctl =
541 gpiochip_get_data(irq_data_get_irq_chip_data(d));
542 unsigned int n, val = 0;
543
544 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
545 return -EINVAL;
546
547 n = d->hwirq;
548
549 if (flow_type & IRQ_TYPE_EDGE_RISING)
550 val |= 0x1;
551 if (flow_type & IRQ_TYPE_EDGE_FALLING)
552 val |= 0x2;
553
554 pctl->irq.sense &= ~(3UL << (n * 2));
555 pctl->irq.sense |= val << (n * 2);
556 pctl->irq.update = n;
557 return 0;
558}
559
560static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
561{
562 struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
563 unsigned int nhandled = 0;
564 unsigned int sub_irq;
565 unsigned int n;
566 s32 err;
567 u8 val;
568 int i;
569
570 for (i = (pctl->data->ngpios / 8) - 1; i >= 0; --i) {
571 err = sx150x_i2c_read(pctl->client,
572 pctl->data->reg_irq_src - i,
573 &val);
574 if (err < 0)
575 continue;
576
577 err = sx150x_i2c_write(pctl->client,
578 pctl->data->reg_irq_src - i,
579 val);
580 if (err < 0)
581 continue;
582
583 for (n = 0; n < 8; ++n) {
584 if (val & (1 << n)) {
585 sub_irq = irq_find_mapping(
586 pctl->gpio.irqdomain,
587 (i * 8) + n);
588 handle_nested_irq(sub_irq);
589 ++nhandled;
590 }
591 }
592 }
593
594 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
595}
596
597static void sx150x_irq_bus_lock(struct irq_data *d)
598{
599 struct sx150x_pinctrl *pctl =
600 gpiochip_get_data(irq_data_get_irq_chip_data(d));
601
602 mutex_lock(&pctl->lock);
603}
604
605static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
606{
607 struct sx150x_pinctrl *pctl =
608 gpiochip_get_data(irq_data_get_irq_chip_data(d));
609 unsigned int n;
610
611 if (pctl->irq.update < 0)
612 goto out;
613
614 n = pctl->irq.update;
615 pctl->irq.update = -1;
616
617 /* Avoid updates if nothing changed */
618 if (pctl->irq.dev_sense == pctl->irq.sense &&
619 pctl->irq.dev_masked == pctl->irq.masked)
620 goto out;
621
622 pctl->irq.dev_sense = pctl->irq.sense;
623 pctl->irq.dev_masked = pctl->irq.masked;
624
625 if (pctl->irq.masked & (1 << n)) {
626 sx150x_write_cfg(pctl->client, n, 1,
627 pctl->data->reg_irq_mask, 1);
628 sx150x_write_cfg(pctl->client, n, 2,
629 pctl->data->reg_sense, 0);
630 } else {
631 sx150x_write_cfg(pctl->client, n, 1,
632 pctl->data->reg_irq_mask, 0);
633 sx150x_write_cfg(pctl->client, n, 2,
634 pctl->data->reg_sense,
635 pctl->irq.sense >> (n * 2));
636 }
637out:
638 mutex_unlock(&pctl->lock);
639}
640
641static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
642 unsigned long *config)
643{
644 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
645 unsigned int param = pinconf_to_config_param(*config);
646 int ret;
647 u32 arg;
648
649 if (sx150x_pin_is_oscio(pctl, pin)) {
650 u8 data;
651
652 switch (param) {
653 case PIN_CONFIG_DRIVE_PUSH_PULL:
654 case PIN_CONFIG_OUTPUT:
655 mutex_lock(&pctl->lock);
656 ret = sx150x_i2c_read(pctl->client,
657 pctl->data->pri.x789.reg_clock,
658 &data);
659 mutex_unlock(&pctl->lock);
660
661 if (ret < 0)
662 return ret;
663
664 if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
665 arg = (data & 0x1f) ? 1 : 0;
666 else {
667 if ((data & 0x1f) == 0x1f)
668 arg = 1;
669 else if ((data & 0x1f) == 0x10)
670 arg = 0;
671 else
672 return -EINVAL;
673 }
674
675 break;
676 default:
677 return -ENOTSUPP;
678 }
679
680 goto out;
681 }
682
683 switch (param) {
684 case PIN_CONFIG_BIAS_PULL_DOWN:
685 mutex_lock(&pctl->lock);
686 ret = sx150x_read_cfg(pctl->client, pin, 1,
687 pctl->data->reg_pulldn);
688 mutex_unlock(&pctl->lock);
689
690 if (ret < 0)
691 return ret;
692
693 if (!ret)
694 return -EINVAL;
695
696 arg = 1;
697 break;
698
699 case PIN_CONFIG_BIAS_PULL_UP:
700 mutex_lock(&pctl->lock);
701 ret = sx150x_read_cfg(pctl->client, pin, 1,
702 pctl->data->reg_pullup);
703 mutex_unlock(&pctl->lock);
704
705 if (ret < 0)
706 return ret;
707
708 if (!ret)
709 return -EINVAL;
710
711 arg = 1;
712 break;
713
714 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
715 if (pctl->data->model != SX150X_789)
716 return -ENOTSUPP;
717
718 mutex_lock(&pctl->lock);
719 ret = sx150x_read_cfg(pctl->client, pin, 1,
720 pctl->data->pri.x789.reg_drain);
721 mutex_unlock(&pctl->lock);
722
723 if (ret < 0)
724 return ret;
725
726 if (!ret)
727 return -EINVAL;
728
729 arg = 1;
730 break;
731
732 case PIN_CONFIG_DRIVE_PUSH_PULL:
733 if (pctl->data->model != SX150X_789)
734 arg = true;
735 else {
736 mutex_lock(&pctl->lock);
737 ret = sx150x_read_cfg(pctl->client, pin, 1,
738 pctl->data->pri.x789.reg_drain);
739 mutex_unlock(&pctl->lock);
740
741 if (ret < 0)
742 return ret;
743
744 if (ret)
745 return -EINVAL;
746
747 arg = 1;
748 }
749 break;
750
751 case PIN_CONFIG_OUTPUT:
752 ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
753 if (ret < 0)
754 return ret;
755
756 if (ret)
757 return -EINVAL;
758
759 ret = sx150x_gpio_get(&pctl->gpio, pin);
760 if (ret < 0)
761 return ret;
762
763 arg = ret;
764 break;
765
766 default:
767 return -ENOTSUPP;
768 }
769
770out:
771 *config = pinconf_to_config_packed(param, arg);
772
773 return 0;
774}
775
776static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
777 unsigned long *configs, unsigned int num_configs)
778{
779 struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
780 enum pin_config_param param;
781 u32 arg;
782 int i;
783 int ret;
784
785 for (i = 0; i < num_configs; i++) {
786 param = pinconf_to_config_param(configs[i]);
787 arg = pinconf_to_config_argument(configs[i]);
788
789 if (sx150x_pin_is_oscio(pctl, pin)) {
790 if (param == PIN_CONFIG_OUTPUT) {
791 ret = sx150x_gpio_direction_output(&pctl->gpio,
792 pin, arg);
793 if (ret < 0)
794 return ret;
795
796 continue;
797 } else
798 return -ENOTSUPP;
799 }
800
801 switch (param) {
802 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
803 case PIN_CONFIG_BIAS_DISABLE:
804 mutex_lock(&pctl->lock);
805 ret = sx150x_write_cfg(pctl->client, pin, 1,
806 pctl->data->reg_pulldn, 0);
807 mutex_unlock(&pctl->lock);
808 if (ret < 0)
809 return ret;
810
811 mutex_lock(&pctl->lock);
812 ret = sx150x_write_cfg(pctl->client, pin, 1,
813 pctl->data->reg_pullup, 0);
814 mutex_unlock(&pctl->lock);
815 if (ret < 0)
816 return ret;
817
818 break;
819
820 case PIN_CONFIG_BIAS_PULL_UP:
821 mutex_lock(&pctl->lock);
822 ret = sx150x_write_cfg(pctl->client, pin, 1,
823 pctl->data->reg_pullup,
824 1);
825 mutex_unlock(&pctl->lock);
826 if (ret < 0)
827 return ret;
828
829 break;
830
831 case PIN_CONFIG_BIAS_PULL_DOWN:
832 mutex_lock(&pctl->lock);
833 ret = sx150x_write_cfg(pctl->client, pin, 1,
834 pctl->data->reg_pulldn,
835 1);
836 mutex_unlock(&pctl->lock);
837 if (ret < 0)
838 return ret;
839
840 break;
841
842 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
843 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
844 pin, LINE_MODE_OPEN_DRAIN);
845 if (ret < 0)
846 return ret;
847
848 break;
849
850 case PIN_CONFIG_DRIVE_PUSH_PULL:
851 ret = sx150x_gpio_set_single_ended(&pctl->gpio,
852 pin, LINE_MODE_PUSH_PULL);
853 if (ret < 0)
854 return ret;
855
856 break;
857
858 case PIN_CONFIG_OUTPUT:
859 ret = sx150x_gpio_direction_output(&pctl->gpio,
860 pin, arg);
861 if (ret < 0)
862 return ret;
863
864 break;
865
866 default:
867 return -ENOTSUPP;
868 }
869 } /* for each config */
870
871 return 0;
872}
873
874static const struct pinconf_ops sx150x_pinconf_ops = {
875 .pin_config_get = sx150x_pinconf_get,
876 .pin_config_set = sx150x_pinconf_set,
877 .is_generic = true,
878};
879
880static const struct i2c_device_id sx150x_id[] = {
881 {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
882 {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
883 {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
884 {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
6697546d 885 {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
9e80f906
NA		 886 {}
887};
888
889static const struct of_device_id sx150x_of_match[] = {
e3ba8120
AS		 890 { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
891 { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
892 { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
893 { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
6697546d 894 { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
9e80f906
NA		 895 {},
896};
897
898static int sx150x_init_io(struct sx150x_pinctrl *pctl, u8 base, u16 cfg)
899{
900 int err = 0;
901 unsigned int n;
902
903 for (n = 0; err >= 0 && n < (pctl->data->ngpios / 8); ++n)
904 err = sx150x_i2c_write(pctl->client, base - n, cfg >> (n * 8));
905 return err;
906}
907
908static int sx150x_reset(struct sx150x_pinctrl *pctl)
909{
910 int err;
911
912 err = i2c_smbus_write_byte_data(pctl->client,
913 pctl->data->pri.x789.reg_reset,
914 0x12);
915 if (err < 0)
916 return err;
917
918 err = i2c_smbus_write_byte_data(pctl->client,
919 pctl->data->pri.x789.reg_reset,
920 0x34);
921 return err;
922}
923
924static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
925{
926 int err;
927
928 if (pctl->data->model == SX150X_789 &&
929 of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
930 err = sx150x_reset(pctl);
931 if (err < 0)
932 return err;
933 }
934
935 if (pctl->data->model == SX150X_789)
936 err = sx150x_i2c_write(pctl->client,
937 pctl->data->pri.x789.reg_misc,
938 0x01);
939 else if (pctl->data->model == SX150X_456)
940 err = sx150x_i2c_write(pctl->client,
941 pctl->data->pri.x456.reg_advance,
942 0x04);
943 else
944 err = sx150x_i2c_write(pctl->client,
945 pctl->data->pri.x123.reg_advance,
946 0x00);
947 if (err < 0)
948 return err;
949
950 /* Set all pins to work in normal mode */
951 if (pctl->data->model == SX150X_789) {
952 err = sx150x_init_io(pctl,
953 pctl->data->pri.x789.reg_polarity,
954 0);
955 if (err < 0)
956 return err;
957 } else if (pctl->data->model == SX150X_456) {
958 /* Set all pins to work in normal mode */
959 err = sx150x_init_io(pctl,
960 pctl->data->pri.x456.reg_pld_mode,
961 0);
962 if (err < 0)
963 return err;
964 } else {
965 /* Set all pins to work in normal mode */
966 err = sx150x_init_io(pctl,
967 pctl->data->pri.x123.reg_pld_mode,
968 0);
969 if (err < 0)
970 return err;
971 }
972
973 return 0;
974}
975
976static int sx150x_probe(struct i2c_client *client,
977 const struct i2c_device_id *id)
978{
979 static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
980 I2C_FUNC_SMBUS_WRITE_WORD_DATA;
981 struct device *dev = &client->dev;
982 struct sx150x_pinctrl *pctl;
983 int ret;
984
9e80f906
NA		 985 if (!i2c_check_functionality(client->adapter, i2c_funcs))
986 return -ENOSYS;
987
988 pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
989 if (!pctl)
990 return -ENOMEM;
991
992 pctl->dev = dev;
993 pctl->client = client;
e3ba8120
AS		 994
995 if (dev->of_node)
996 pctl->data = of_device_get_match_data(dev);
997 else
998 pctl->data = (struct sx150x_device_data *)id->driver_data;
999
1000 if (!pctl->data)
1001 return -EINVAL;
9e80f906
NA		 1002
1003 mutex_init(&pctl->lock);
1004
1005 ret = sx150x_init_hw(pctl);
1006 if (ret)
1007 return ret;
1008
1009 /* Register GPIO controller */
1010 pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1011 pctl->gpio.base = -1;
1012 pctl->gpio.ngpio = pctl->data->npins;
1013 pctl->gpio.get_direction = sx150x_gpio_get_direction;
1014 pctl->gpio.direction_input = sx150x_gpio_direction_input;
1015 pctl->gpio.direction_output = sx150x_gpio_direction_output;
1016 pctl->gpio.get = sx150x_gpio_get;
1017 pctl->gpio.set = sx150x_gpio_set;
1018 pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended;
1019 pctl->gpio.parent = dev;
1020#ifdef CONFIG_OF_GPIO
1021 pctl->gpio.of_node = dev->of_node;
1022#endif
1023 pctl->gpio.can_sleep = true;
1024
1025 ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1026 if (ret)
1027 return ret;
1028
1029 /* Add Interrupt support if an irq is specified */
1030 if (client->irq > 0) {
1031 pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1032 GFP_KERNEL);
1033 pctl->irq_chip.irq_mask = sx150x_irq_mask;
1034 pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1035 pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1036 pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1037 pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1038
1039 pctl->irq.masked = ~0;
1040 pctl->irq.sense = 0;
1041 pctl->irq.dev_masked = ~0;
1042 pctl->irq.dev_sense = 0;
1043 pctl->irq.update = -1;
1044
1045 ret = gpiochip_irqchip_add(&pctl->gpio,
1046 &pctl->irq_chip, 0,
1047 handle_edge_irq, IRQ_TYPE_NONE);
1048 if (ret) {
1049 dev_err(dev, "could not connect irqchip to gpiochip\n");
1050 return ret;
1051 }
1052
1053 ret = devm_request_threaded_irq(dev, client->irq, NULL,
1054 sx150x_irq_thread_fn,
1055 IRQF_ONESHOT | IRQF_SHARED |
1056 IRQF_TRIGGER_FALLING,
1057 pctl->irq_chip.name, pctl);
1058 if (ret < 0)
1059 return ret;
1060 }
1061
1062 /* Pinctrl_desc */
1063 pctl->pinctrl_desc.name = "sx150x-pinctrl";
1064 pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1065 pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1066 pctl->pinctrl_desc.pins = pctl->data->pins;
1067 pctl->pinctrl_desc.npins = pctl->data->npins;
1068 pctl->pinctrl_desc.owner = THIS_MODULE;
1069
1070 pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl);
1071 if (IS_ERR(pctl->pctldev)) {
1072 dev_err(dev, "Failed to register pinctrl device\n");
1073 return PTR_ERR(pctl->pctldev);
1074 }
1075
1076 return 0;
1077}
1078
1079static struct i2c_driver sx150x_driver = {
1080 .driver = {
1081 .name = "sx150x-pinctrl",
1082 .of_match_table = of_match_ptr(sx150x_of_match),
1083 },
1084 .probe = sx150x_probe,
1085 .id_table = sx150x_id,
1086};
1087
1088static int __init sx150x_init(void)
1089{
1090 return i2c_add_driver(&sx150x_driver);
1091}
1092subsys_initcall(sx150x_init);
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