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9e80f906 NA |
1 | /* |
2 | * Copyright (c) 2016, BayLibre, SAS. All rights reserved. | |
3 | * Author: Neil Armstrong <narmstrong@baylibre.com> | |
4 | * | |
5 | * Copyright (c) 2010, Code Aurora Forum. All rights reserved. | |
6 | * | |
7 | * Driver for Semtech SX150X I2C GPIO Expanders | |
8 | * | |
9 | * Author: Gregory Bean <gbean@codeaurora.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 and | |
13 | * only version 2 as published by the Free Software Foundation. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | */ | |
20 | ||
0db0f26c | 21 | #include <linux/regmap.h> |
9e80f906 NA |
22 | #include <linux/i2c.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/mutex.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/of.h> | |
e3ba8120 | 29 | #include <linux/of_device.h> |
9e80f906 NA |
30 | #include <linux/gpio.h> |
31 | #include <linux/pinctrl/machine.h> | |
32 | #include <linux/pinctrl/pinconf.h> | |
33 | #include <linux/pinctrl/pinctrl.h> | |
34 | #include <linux/pinctrl/pinmux.h> | |
35 | #include <linux/pinctrl/pinconf-generic.h> | |
36 | ||
37 | #include "core.h" | |
38 | #include "pinconf.h" | |
39 | #include "pinctrl-utils.h" | |
40 | ||
41 | /* The chip models of sx150x */ | |
42 | enum { | |
43 | SX150X_123 = 0, | |
44 | SX150X_456, | |
45 | SX150X_789, | |
46 | }; | |
7d68a79a AS |
47 | enum { |
48 | SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0, | |
0db0f26c | 49 | SX150X_MAX_REGISTER = 0xad, |
fd931f23 AS |
50 | SX150X_IRQ_TYPE_EDGE_RISING = 0x1, |
51 | SX150X_IRQ_TYPE_EDGE_FALLING = 0x2, | |
f9038d60 AS |
52 | SX150X_789_RESET_KEY1 = 0x12, |
53 | SX150X_789_RESET_KEY2 = 0x34, | |
7d68a79a | 54 | }; |
9e80f906 NA |
55 | |
56 | struct sx150x_123_pri { | |
57 | u8 reg_pld_mode; | |
58 | u8 reg_pld_table0; | |
59 | u8 reg_pld_table1; | |
60 | u8 reg_pld_table2; | |
61 | u8 reg_pld_table3; | |
62 | u8 reg_pld_table4; | |
63 | u8 reg_advance; | |
64 | }; | |
65 | ||
66 | struct sx150x_456_pri { | |
67 | u8 reg_pld_mode; | |
68 | u8 reg_pld_table0; | |
69 | u8 reg_pld_table1; | |
70 | u8 reg_pld_table2; | |
71 | u8 reg_pld_table3; | |
72 | u8 reg_pld_table4; | |
73 | u8 reg_advance; | |
74 | }; | |
75 | ||
76 | struct sx150x_789_pri { | |
77 | u8 reg_drain; | |
78 | u8 reg_polarity; | |
79 | u8 reg_clock; | |
80 | u8 reg_misc; | |
81 | u8 reg_reset; | |
82 | u8 ngpios; | |
83 | }; | |
84 | ||
85 | struct sx150x_device_data { | |
86 | u8 model; | |
87 | u8 reg_pullup; | |
88 | u8 reg_pulldn; | |
89 | u8 reg_dir; | |
90 | u8 reg_data; | |
91 | u8 reg_irq_mask; | |
92 | u8 reg_irq_src; | |
93 | u8 reg_sense; | |
94 | u8 ngpios; | |
95 | union { | |
96 | struct sx150x_123_pri x123; | |
97 | struct sx150x_456_pri x456; | |
98 | struct sx150x_789_pri x789; | |
99 | } pri; | |
100 | const struct pinctrl_pin_desc *pins; | |
101 | unsigned int npins; | |
102 | }; | |
103 | ||
104 | struct sx150x_pinctrl { | |
105 | struct device *dev; | |
106 | struct i2c_client *client; | |
107 | struct pinctrl_dev *pctldev; | |
108 | struct pinctrl_desc pinctrl_desc; | |
109 | struct gpio_chip gpio; | |
110 | struct irq_chip irq_chip; | |
0db0f26c | 111 | struct regmap *regmap; |
9e80f906 | 112 | struct { |
9e80f906 NA |
113 | u32 sense; |
114 | u32 masked; | |
9e80f906 NA |
115 | } irq; |
116 | struct mutex lock; | |
117 | const struct sx150x_device_data *data; | |
118 | }; | |
119 | ||
120 | static const struct pinctrl_pin_desc sx150x_8_pins[] = { | |
121 | PINCTRL_PIN(0, "gpio0"), | |
122 | PINCTRL_PIN(1, "gpio1"), | |
123 | PINCTRL_PIN(2, "gpio2"), | |
124 | PINCTRL_PIN(3, "gpio3"), | |
125 | PINCTRL_PIN(4, "gpio4"), | |
126 | PINCTRL_PIN(5, "gpio5"), | |
127 | PINCTRL_PIN(6, "gpio6"), | |
128 | PINCTRL_PIN(7, "gpio7"), | |
129 | PINCTRL_PIN(8, "oscio"), | |
130 | }; | |
131 | ||
132 | static const struct pinctrl_pin_desc sx150x_16_pins[] = { | |
133 | PINCTRL_PIN(0, "gpio0"), | |
134 | PINCTRL_PIN(1, "gpio1"), | |
135 | PINCTRL_PIN(2, "gpio2"), | |
136 | PINCTRL_PIN(3, "gpio3"), | |
137 | PINCTRL_PIN(4, "gpio4"), | |
138 | PINCTRL_PIN(5, "gpio5"), | |
139 | PINCTRL_PIN(6, "gpio6"), | |
140 | PINCTRL_PIN(7, "gpio7"), | |
141 | PINCTRL_PIN(8, "gpio8"), | |
142 | PINCTRL_PIN(9, "gpio9"), | |
143 | PINCTRL_PIN(10, "gpio10"), | |
144 | PINCTRL_PIN(11, "gpio11"), | |
145 | PINCTRL_PIN(12, "gpio12"), | |
146 | PINCTRL_PIN(13, "gpio13"), | |
147 | PINCTRL_PIN(14, "gpio14"), | |
148 | PINCTRL_PIN(15, "gpio15"), | |
149 | PINCTRL_PIN(16, "oscio"), | |
150 | }; | |
151 | ||
152 | static const struct sx150x_device_data sx1508q_device_data = { | |
153 | .model = SX150X_789, | |
154 | .reg_pullup = 0x03, | |
155 | .reg_pulldn = 0x04, | |
156 | .reg_dir = 0x07, | |
157 | .reg_data = 0x08, | |
158 | .reg_irq_mask = 0x09, | |
159 | .reg_irq_src = 0x0c, | |
160 | .reg_sense = 0x0b, | |
161 | .pri.x789 = { | |
162 | .reg_drain = 0x05, | |
163 | .reg_polarity = 0x06, | |
164 | .reg_clock = 0x0f, | |
165 | .reg_misc = 0x10, | |
166 | .reg_reset = 0x7d, | |
167 | }, | |
168 | .ngpios = 8, | |
169 | .pins = sx150x_8_pins, | |
170 | .npins = ARRAY_SIZE(sx150x_8_pins), | |
171 | }; | |
172 | ||
173 | static const struct sx150x_device_data sx1509q_device_data = { | |
174 | .model = SX150X_789, | |
6489677f AS |
175 | .reg_pullup = 0x06, |
176 | .reg_pulldn = 0x08, | |
177 | .reg_dir = 0x0e, | |
178 | .reg_data = 0x10, | |
179 | .reg_irq_mask = 0x12, | |
180 | .reg_irq_src = 0x18, | |
181 | .reg_sense = 0x14, | |
9e80f906 | 182 | .pri.x789 = { |
6489677f AS |
183 | .reg_drain = 0x0a, |
184 | .reg_polarity = 0x0c, | |
9e80f906 NA |
185 | .reg_clock = 0x1e, |
186 | .reg_misc = 0x1f, | |
187 | .reg_reset = 0x7d, | |
188 | }, | |
189 | .ngpios = 16, | |
190 | .pins = sx150x_16_pins, | |
191 | .npins = ARRAY_SIZE(sx150x_16_pins), | |
192 | }; | |
193 | ||
194 | static const struct sx150x_device_data sx1506q_device_data = { | |
195 | .model = SX150X_456, | |
6489677f AS |
196 | .reg_pullup = 0x04, |
197 | .reg_pulldn = 0x06, | |
198 | .reg_dir = 0x02, | |
199 | .reg_data = 0x00, | |
200 | .reg_irq_mask = 0x08, | |
201 | .reg_irq_src = 0x0e, | |
202 | .reg_sense = 0x0a, | |
9e80f906 | 203 | .pri.x456 = { |
6489677f AS |
204 | .reg_pld_mode = 0x20, |
205 | .reg_pld_table0 = 0x22, | |
206 | .reg_pld_table1 = 0x24, | |
207 | .reg_pld_table2 = 0x26, | |
208 | .reg_pld_table3 = 0x28, | |
209 | .reg_pld_table4 = 0x2a, | |
9e80f906 NA |
210 | .reg_advance = 0xad, |
211 | }, | |
212 | .ngpios = 16, | |
213 | .pins = sx150x_16_pins, | |
214 | .npins = 16, /* oscio not available */ | |
215 | }; | |
216 | ||
217 | static const struct sx150x_device_data sx1502q_device_data = { | |
218 | .model = SX150X_123, | |
219 | .reg_pullup = 0x02, | |
220 | .reg_pulldn = 0x03, | |
221 | .reg_dir = 0x01, | |
222 | .reg_data = 0x00, | |
223 | .reg_irq_mask = 0x05, | |
224 | .reg_irq_src = 0x08, | |
225 | .reg_sense = 0x07, | |
226 | .pri.x123 = { | |
227 | .reg_pld_mode = 0x10, | |
228 | .reg_pld_table0 = 0x11, | |
229 | .reg_pld_table1 = 0x12, | |
230 | .reg_pld_table2 = 0x13, | |
231 | .reg_pld_table3 = 0x14, | |
232 | .reg_pld_table4 = 0x15, | |
233 | .reg_advance = 0xad, | |
234 | }, | |
235 | .ngpios = 8, | |
236 | .pins = sx150x_8_pins, | |
237 | .npins = 8, /* oscio not available */ | |
238 | }; | |
239 | ||
6697546d AS |
240 | static const struct sx150x_device_data sx1503q_device_data = { |
241 | .model = SX150X_123, | |
6489677f AS |
242 | .reg_pullup = 0x04, |
243 | .reg_pulldn = 0x06, | |
244 | .reg_dir = 0x02, | |
245 | .reg_data = 0x00, | |
246 | .reg_irq_mask = 0x08, | |
247 | .reg_irq_src = 0x0e, | |
248 | .reg_sense = 0x0a, | |
6697546d | 249 | .pri.x123 = { |
6489677f AS |
250 | .reg_pld_mode = 0x20, |
251 | .reg_pld_table0 = 0x22, | |
252 | .reg_pld_table1 = 0x24, | |
253 | .reg_pld_table2 = 0x26, | |
254 | .reg_pld_table3 = 0x28, | |
255 | .reg_pld_table4 = 0x2a, | |
6697546d AS |
256 | .reg_advance = 0xad, |
257 | }, | |
258 | .ngpios = 16, | |
259 | .pins = sx150x_16_pins, | |
260 | .npins = 16, /* oscio not available */ | |
261 | }; | |
262 | ||
9e80f906 NA |
263 | static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) |
264 | { | |
265 | return 0; | |
266 | } | |
267 | ||
268 | static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | |
269 | unsigned int group) | |
270 | { | |
271 | return NULL; | |
272 | } | |
273 | ||
274 | static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
275 | unsigned int group, | |
276 | const unsigned int **pins, | |
277 | unsigned int *num_pins) | |
278 | { | |
279 | return -ENOTSUPP; | |
280 | } | |
281 | ||
282 | static const struct pinctrl_ops sx150x_pinctrl_ops = { | |
283 | .get_groups_count = sx150x_pinctrl_get_groups_count, | |
284 | .get_group_name = sx150x_pinctrl_get_group_name, | |
285 | .get_group_pins = sx150x_pinctrl_get_group_pins, | |
286 | #ifdef CONFIG_OF | |
287 | .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, | |
288 | .dt_free_map = pinctrl_utils_free_map, | |
289 | #endif | |
290 | }; | |
291 | ||
292 | static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin) | |
293 | { | |
294 | if (pin >= pctl->data->npins) | |
295 | return false; | |
296 | ||
297 | /* OSCIO pin is only present in 789 devices */ | |
298 | if (pctl->data->model != SX150X_789) | |
299 | return false; | |
300 | ||
301 | return !strcmp(pctl->data->pins[pin].name, "oscio"); | |
302 | } | |
303 | ||
304 | static int sx150x_gpio_get_direction(struct gpio_chip *chip, | |
305 | unsigned int offset) | |
306 | { | |
307 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
6489677f AS |
308 | unsigned int value; |
309 | int ret; | |
9e80f906 NA |
310 | |
311 | if (sx150x_pin_is_oscio(pctl, offset)) | |
312 | return false; | |
313 | ||
6489677f AS |
314 | ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value); |
315 | if (ret < 0) | |
316 | return ret; | |
9e80f906 | 317 | |
6489677f | 318 | return !!(value & BIT(offset)); |
9e80f906 NA |
319 | } |
320 | ||
321 | static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset) | |
322 | { | |
323 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
6489677f AS |
324 | unsigned int value; |
325 | int ret; | |
9e80f906 NA |
326 | |
327 | if (sx150x_pin_is_oscio(pctl, offset)) | |
328 | return -EINVAL; | |
329 | ||
6489677f AS |
330 | ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value); |
331 | if (ret < 0) | |
332 | return ret; | |
9e80f906 | 333 | |
6489677f | 334 | return !!(value & BIT(offset)); |
9e80f906 NA |
335 | } |
336 | ||
337 | static int sx150x_gpio_set_single_ended(struct gpio_chip *chip, | |
338 | unsigned int offset, | |
339 | enum single_ended_mode mode) | |
340 | { | |
341 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
342 | int ret; | |
343 | ||
344 | switch (mode) { | |
345 | case LINE_MODE_PUSH_PULL: | |
346 | if (pctl->data->model != SX150X_789 || | |
347 | sx150x_pin_is_oscio(pctl, offset)) | |
348 | return 0; | |
349 | ||
6489677f AS |
350 | ret = regmap_write_bits(pctl->regmap, |
351 | pctl->data->pri.x789.reg_drain, | |
352 | BIT(offset), 0); | |
9e80f906 NA |
353 | break; |
354 | ||
355 | case LINE_MODE_OPEN_DRAIN: | |
356 | if (pctl->data->model != SX150X_789 || | |
357 | sx150x_pin_is_oscio(pctl, offset)) | |
358 | return -ENOTSUPP; | |
359 | ||
6489677f AS |
360 | ret = regmap_write_bits(pctl->regmap, |
361 | pctl->data->pri.x789.reg_drain, | |
362 | BIT(offset), BIT(offset)); | |
9e80f906 | 363 | break; |
9e80f906 | 364 | default: |
d977a876 AS |
365 | ret = -ENOTSUPP; |
366 | break; | |
9e80f906 NA |
367 | } |
368 | ||
d977a876 | 369 | return ret; |
9e80f906 NA |
370 | } |
371 | ||
6489677f AS |
372 | static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset, |
373 | int value) | |
374 | { | |
375 | return regmap_write_bits(pctl->regmap, pctl->data->reg_data, | |
376 | BIT(offset), value ? BIT(offset) : 0); | |
377 | } | |
378 | ||
ab5bd035 AS |
379 | static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl, |
380 | int value) | |
381 | { | |
382 | return regmap_write(pctl->regmap, | |
383 | pctl->data->pri.x789.reg_clock, | |
384 | (value ? 0x1f : 0x10)); | |
385 | } | |
386 | ||
9e80f906 NA |
387 | static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset, |
388 | int value) | |
389 | { | |
390 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
391 | ||
d977a876 | 392 | if (sx150x_pin_is_oscio(pctl, offset)) |
ab5bd035 | 393 | sx150x_gpio_oscio_set(pctl, value); |
d977a876 | 394 | else |
6489677f | 395 | __sx150x_gpio_set(pctl, offset, value); |
d977a876 | 396 | |
9e80f906 NA |
397 | } |
398 | ||
399 | static int sx150x_gpio_direction_input(struct gpio_chip *chip, | |
400 | unsigned int offset) | |
401 | { | |
402 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
9e80f906 NA |
403 | |
404 | if (sx150x_pin_is_oscio(pctl, offset)) | |
405 | return -EINVAL; | |
406 | ||
d977a876 AS |
407 | return regmap_write_bits(pctl->regmap, |
408 | pctl->data->reg_dir, | |
409 | BIT(offset), BIT(offset)); | |
9e80f906 NA |
410 | } |
411 | ||
412 | static int sx150x_gpio_direction_output(struct gpio_chip *chip, | |
413 | unsigned int offset, int value) | |
414 | { | |
415 | struct sx150x_pinctrl *pctl = gpiochip_get_data(chip); | |
d977a876 | 416 | int ret; |
9e80f906 | 417 | |
ab5bd035 AS |
418 | if (sx150x_pin_is_oscio(pctl, offset)) |
419 | return sx150x_gpio_oscio_set(pctl, value); | |
9e80f906 | 420 | |
d977a876 AS |
421 | ret = __sx150x_gpio_set(pctl, offset, value); |
422 | if (ret < 0) | |
423 | return ret; | |
9e80f906 | 424 | |
d977a876 AS |
425 | return regmap_write_bits(pctl->regmap, |
426 | pctl->data->reg_dir, | |
427 | BIT(offset), 0); | |
9e80f906 NA |
428 | } |
429 | ||
430 | static void sx150x_irq_mask(struct irq_data *d) | |
431 | { | |
432 | struct sx150x_pinctrl *pctl = | |
433 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
434 | unsigned int n = d->hwirq; | |
435 | ||
6489677f | 436 | pctl->irq.masked |= BIT(n); |
9e80f906 NA |
437 | } |
438 | ||
439 | static void sx150x_irq_unmask(struct irq_data *d) | |
440 | { | |
441 | struct sx150x_pinctrl *pctl = | |
442 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
443 | unsigned int n = d->hwirq; | |
444 | ||
6489677f | 445 | pctl->irq.masked &= ~BIT(n); |
9e80f906 NA |
446 | } |
447 | ||
fd931f23 AS |
448 | static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl, |
449 | unsigned int line, unsigned int sense) | |
450 | { | |
451 | /* | |
452 | * Every interrupt line is represented by two bits shifted | |
453 | * proportionally to the line number | |
454 | */ | |
455 | const unsigned int n = line * 2; | |
456 | const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING | | |
457 | SX150X_IRQ_TYPE_EDGE_FALLING) << n); | |
458 | ||
459 | pctl->irq.sense &= mask; | |
460 | pctl->irq.sense |= sense << n; | |
461 | } | |
462 | ||
9e80f906 NA |
463 | static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type) |
464 | { | |
465 | struct sx150x_pinctrl *pctl = | |
466 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
467 | unsigned int n, val = 0; | |
468 | ||
469 | if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) | |
470 | return -EINVAL; | |
471 | ||
472 | n = d->hwirq; | |
473 | ||
474 | if (flow_type & IRQ_TYPE_EDGE_RISING) | |
fd931f23 | 475 | val |= SX150X_IRQ_TYPE_EDGE_RISING; |
9e80f906 | 476 | if (flow_type & IRQ_TYPE_EDGE_FALLING) |
fd931f23 | 477 | val |= SX150X_IRQ_TYPE_EDGE_FALLING; |
9e80f906 | 478 | |
fd931f23 | 479 | sx150x_irq_set_sense(pctl, n, val); |
9e80f906 NA |
480 | return 0; |
481 | } | |
482 | ||
483 | static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id) | |
484 | { | |
485 | struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id; | |
05a90cc7 | 486 | unsigned long n, status; |
0db0f26c | 487 | unsigned int val; |
05a90cc7 | 488 | int err; |
9e80f906 | 489 | |
6489677f AS |
490 | err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val); |
491 | if (err < 0) | |
492 | return IRQ_NONE; | |
9e80f906 | 493 | |
6489677f AS |
494 | err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val); |
495 | if (err < 0) | |
496 | return IRQ_NONE; | |
497 | ||
05a90cc7 AS |
498 | status = val; |
499 | for_each_set_bit(n, &status, pctl->data->ngpios) | |
500 | handle_nested_irq(irq_find_mapping(pctl->gpio.irqdomain, n)); | |
9e80f906 | 501 | |
05a90cc7 | 502 | return IRQ_HANDLED; |
9e80f906 NA |
503 | } |
504 | ||
505 | static void sx150x_irq_bus_lock(struct irq_data *d) | |
506 | { | |
507 | struct sx150x_pinctrl *pctl = | |
508 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
509 | ||
510 | mutex_lock(&pctl->lock); | |
511 | } | |
512 | ||
513 | static void sx150x_irq_bus_sync_unlock(struct irq_data *d) | |
514 | { | |
515 | struct sx150x_pinctrl *pctl = | |
516 | gpiochip_get_data(irq_data_get_irq_chip_data(d)); | |
9e80f906 | 517 | |
6489677f AS |
518 | regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked); |
519 | regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense); | |
9e80f906 NA |
520 | mutex_unlock(&pctl->lock); |
521 | } | |
522 | ||
523 | static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, | |
524 | unsigned long *config) | |
525 | { | |
526 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
527 | unsigned int param = pinconf_to_config_param(*config); | |
528 | int ret; | |
529 | u32 arg; | |
6489677f | 530 | unsigned int data; |
9e80f906 NA |
531 | |
532 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
9e80f906 NA |
533 | switch (param) { |
534 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
535 | case PIN_CONFIG_OUTPUT: | |
0db0f26c AS |
536 | ret = regmap_read(pctl->regmap, |
537 | pctl->data->pri.x789.reg_clock, | |
538 | &data); | |
9e80f906 NA |
539 | if (ret < 0) |
540 | return ret; | |
541 | ||
542 | if (param == PIN_CONFIG_DRIVE_PUSH_PULL) | |
543 | arg = (data & 0x1f) ? 1 : 0; | |
544 | else { | |
545 | if ((data & 0x1f) == 0x1f) | |
546 | arg = 1; | |
547 | else if ((data & 0x1f) == 0x10) | |
548 | arg = 0; | |
549 | else | |
550 | return -EINVAL; | |
551 | } | |
552 | ||
553 | break; | |
554 | default: | |
555 | return -ENOTSUPP; | |
556 | } | |
557 | ||
558 | goto out; | |
559 | } | |
560 | ||
561 | switch (param) { | |
562 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
6489677f AS |
563 | ret = regmap_read(pctl->regmap, |
564 | pctl->data->reg_pulldn, | |
565 | &data); | |
566 | data &= BIT(pin); | |
9e80f906 NA |
567 | |
568 | if (ret < 0) | |
569 | return ret; | |
570 | ||
571 | if (!ret) | |
572 | return -EINVAL; | |
573 | ||
574 | arg = 1; | |
575 | break; | |
576 | ||
577 | case PIN_CONFIG_BIAS_PULL_UP: | |
6489677f AS |
578 | ret = regmap_read(pctl->regmap, |
579 | pctl->data->reg_pullup, | |
580 | &data); | |
581 | data &= BIT(pin); | |
9e80f906 NA |
582 | |
583 | if (ret < 0) | |
584 | return ret; | |
585 | ||
586 | if (!ret) | |
587 | return -EINVAL; | |
588 | ||
589 | arg = 1; | |
590 | break; | |
591 | ||
592 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
593 | if (pctl->data->model != SX150X_789) | |
594 | return -ENOTSUPP; | |
595 | ||
6489677f AS |
596 | ret = regmap_read(pctl->regmap, |
597 | pctl->data->pri.x789.reg_drain, | |
598 | &data); | |
599 | data &= BIT(pin); | |
9e80f906 NA |
600 | |
601 | if (ret < 0) | |
602 | return ret; | |
603 | ||
6489677f | 604 | if (!data) |
9e80f906 NA |
605 | return -EINVAL; |
606 | ||
607 | arg = 1; | |
608 | break; | |
609 | ||
610 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
611 | if (pctl->data->model != SX150X_789) | |
612 | arg = true; | |
613 | else { | |
6489677f AS |
614 | ret = regmap_read(pctl->regmap, |
615 | pctl->data->pri.x789.reg_drain, | |
616 | &data); | |
617 | data &= BIT(pin); | |
9e80f906 NA |
618 | |
619 | if (ret < 0) | |
620 | return ret; | |
621 | ||
6489677f | 622 | if (data) |
9e80f906 NA |
623 | return -EINVAL; |
624 | ||
625 | arg = 1; | |
626 | } | |
627 | break; | |
628 | ||
629 | case PIN_CONFIG_OUTPUT: | |
630 | ret = sx150x_gpio_get_direction(&pctl->gpio, pin); | |
631 | if (ret < 0) | |
632 | return ret; | |
633 | ||
634 | if (ret) | |
635 | return -EINVAL; | |
636 | ||
637 | ret = sx150x_gpio_get(&pctl->gpio, pin); | |
638 | if (ret < 0) | |
639 | return ret; | |
640 | ||
641 | arg = ret; | |
642 | break; | |
643 | ||
644 | default: | |
645 | return -ENOTSUPP; | |
646 | } | |
647 | ||
648 | out: | |
649 | *config = pinconf_to_config_packed(param, arg); | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
654 | static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
655 | unsigned long *configs, unsigned int num_configs) | |
656 | { | |
657 | struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
658 | enum pin_config_param param; | |
659 | u32 arg; | |
660 | int i; | |
661 | int ret; | |
662 | ||
663 | for (i = 0; i < num_configs; i++) { | |
664 | param = pinconf_to_config_param(configs[i]); | |
665 | arg = pinconf_to_config_argument(configs[i]); | |
666 | ||
667 | if (sx150x_pin_is_oscio(pctl, pin)) { | |
668 | if (param == PIN_CONFIG_OUTPUT) { | |
669 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
670 | pin, arg); | |
671 | if (ret < 0) | |
672 | return ret; | |
673 | ||
674 | continue; | |
675 | } else | |
676 | return -ENOTSUPP; | |
677 | } | |
678 | ||
679 | switch (param) { | |
680 | case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: | |
681 | case PIN_CONFIG_BIAS_DISABLE: | |
6489677f AS |
682 | ret = regmap_write_bits(pctl->regmap, |
683 | pctl->data->reg_pulldn, | |
684 | BIT(pin), 0); | |
9e80f906 NA |
685 | if (ret < 0) |
686 | return ret; | |
687 | ||
6489677f AS |
688 | ret = regmap_write_bits(pctl->regmap, |
689 | pctl->data->reg_pullup, | |
690 | BIT(pin), 0); | |
9e80f906 NA |
691 | if (ret < 0) |
692 | return ret; | |
693 | ||
694 | break; | |
695 | ||
696 | case PIN_CONFIG_BIAS_PULL_UP: | |
6489677f AS |
697 | ret = regmap_write_bits(pctl->regmap, |
698 | pctl->data->reg_pullup, | |
699 | BIT(pin), BIT(pin)); | |
9e80f906 NA |
700 | if (ret < 0) |
701 | return ret; | |
702 | ||
703 | break; | |
704 | ||
705 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
6489677f AS |
706 | ret = regmap_write_bits(pctl->regmap, |
707 | pctl->data->reg_pulldn, | |
708 | BIT(pin), BIT(pin)); | |
9e80f906 NA |
709 | if (ret < 0) |
710 | return ret; | |
711 | ||
712 | break; | |
713 | ||
714 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
715 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
716 | pin, LINE_MODE_OPEN_DRAIN); | |
717 | if (ret < 0) | |
718 | return ret; | |
719 | ||
720 | break; | |
721 | ||
722 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
723 | ret = sx150x_gpio_set_single_ended(&pctl->gpio, | |
724 | pin, LINE_MODE_PUSH_PULL); | |
725 | if (ret < 0) | |
726 | return ret; | |
727 | ||
728 | break; | |
729 | ||
730 | case PIN_CONFIG_OUTPUT: | |
731 | ret = sx150x_gpio_direction_output(&pctl->gpio, | |
732 | pin, arg); | |
733 | if (ret < 0) | |
734 | return ret; | |
735 | ||
736 | break; | |
737 | ||
738 | default: | |
739 | return -ENOTSUPP; | |
740 | } | |
741 | } /* for each config */ | |
742 | ||
743 | return 0; | |
744 | } | |
745 | ||
746 | static const struct pinconf_ops sx150x_pinconf_ops = { | |
747 | .pin_config_get = sx150x_pinconf_get, | |
748 | .pin_config_set = sx150x_pinconf_set, | |
749 | .is_generic = true, | |
750 | }; | |
751 | ||
752 | static const struct i2c_device_id sx150x_id[] = { | |
753 | {"sx1508q", (kernel_ulong_t) &sx1508q_device_data }, | |
754 | {"sx1509q", (kernel_ulong_t) &sx1509q_device_data }, | |
755 | {"sx1506q", (kernel_ulong_t) &sx1506q_device_data }, | |
756 | {"sx1502q", (kernel_ulong_t) &sx1502q_device_data }, | |
6697546d | 757 | {"sx1503q", (kernel_ulong_t) &sx1503q_device_data }, |
9e80f906 NA |
758 | {} |
759 | }; | |
760 | ||
761 | static const struct of_device_id sx150x_of_match[] = { | |
e3ba8120 AS |
762 | { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data }, |
763 | { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data }, | |
764 | { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data }, | |
765 | { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data }, | |
6697546d | 766 | { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data }, |
9e80f906 NA |
767 | {}, |
768 | }; | |
769 | ||
9e80f906 NA |
770 | static int sx150x_reset(struct sx150x_pinctrl *pctl) |
771 | { | |
772 | int err; | |
773 | ||
774 | err = i2c_smbus_write_byte_data(pctl->client, | |
775 | pctl->data->pri.x789.reg_reset, | |
f9038d60 | 776 | SX150X_789_RESET_KEY1); |
9e80f906 NA |
777 | if (err < 0) |
778 | return err; | |
779 | ||
780 | err = i2c_smbus_write_byte_data(pctl->client, | |
781 | pctl->data->pri.x789.reg_reset, | |
f9038d60 | 782 | SX150X_789_RESET_KEY2); |
9e80f906 NA |
783 | return err; |
784 | } | |
785 | ||
310cdfa0 AS |
786 | static int sx150x_init_misc(struct sx150x_pinctrl *pctl) |
787 | { | |
788 | u8 reg, value; | |
789 | ||
790 | switch (pctl->data->model) { | |
791 | case SX150X_789: | |
792 | reg = pctl->data->pri.x789.reg_misc; | |
793 | value = SX150X_789_REG_MISC_AUTOCLEAR_OFF; | |
794 | break; | |
795 | case SX150X_456: | |
796 | reg = pctl->data->pri.x456.reg_advance; | |
797 | value = 0x00; | |
b30d31e4 AS |
798 | |
799 | /* | |
800 | * Only SX1506 has RegAdvanced, SX1504/5 are expected | |
801 | * to initialize this offset to zero | |
802 | */ | |
803 | if (!reg) | |
804 | return 0; | |
310cdfa0 AS |
805 | break; |
806 | case SX150X_123: | |
807 | reg = pctl->data->pri.x123.reg_advance; | |
808 | value = 0x00; | |
809 | break; | |
810 | default: | |
811 | WARN(1, "Unknown chip model %d\n", pctl->data->model); | |
812 | return -EINVAL; | |
813 | } | |
814 | ||
6489677f | 815 | return regmap_write(pctl->regmap, reg, value); |
310cdfa0 AS |
816 | } |
817 | ||
9e80f906 NA |
818 | static int sx150x_init_hw(struct sx150x_pinctrl *pctl) |
819 | { | |
6489677f AS |
820 | const u8 reg[] = { |
821 | [SX150X_789] = pctl->data->pri.x789.reg_polarity, | |
822 | [SX150X_456] = pctl->data->pri.x456.reg_pld_mode, | |
823 | [SX150X_123] = pctl->data->pri.x123.reg_pld_mode, | |
824 | }; | |
9e80f906 NA |
825 | int err; |
826 | ||
827 | if (pctl->data->model == SX150X_789 && | |
828 | of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) { | |
829 | err = sx150x_reset(pctl); | |
830 | if (err < 0) | |
831 | return err; | |
832 | } | |
833 | ||
310cdfa0 | 834 | err = sx150x_init_misc(pctl); |
9e80f906 NA |
835 | if (err < 0) |
836 | return err; | |
837 | ||
838 | /* Set all pins to work in normal mode */ | |
6489677f AS |
839 | return regmap_write(pctl->regmap, reg[pctl->data->model], 0); |
840 | } | |
841 | ||
842 | static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl, | |
843 | unsigned int reg) | |
844 | { | |
845 | const struct sx150x_device_data *data = pctl->data; | |
846 | ||
847 | if (reg == data->reg_sense) { | |
848 | /* | |
849 | * RegSense packs two bits of configuration per GPIO, | |
850 | * so we'd need to read twice as many bits as there | |
851 | * are GPIO in our chip | |
852 | */ | |
853 | return 2 * data->ngpios; | |
854 | } else if ((data->model == SX150X_789 && | |
855 | (reg == data->pri.x789.reg_misc || | |
856 | reg == data->pri.x789.reg_clock || | |
857 | reg == data->pri.x789.reg_reset)) | |
858 | || | |
859 | (data->model == SX150X_123 && | |
860 | reg == data->pri.x123.reg_advance) | |
861 | || | |
862 | (data->model == SX150X_456 && | |
863 | reg == data->pri.x456.reg_advance)) { | |
864 | return 8; | |
9e80f906 | 865 | } else { |
6489677f AS |
866 | return data->ngpios; |
867 | } | |
868 | } | |
869 | ||
870 | static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl, | |
871 | unsigned int reg, unsigned int val) | |
872 | { | |
873 | unsigned int a, b; | |
874 | const struct sx150x_device_data *data = pctl->data; | |
875 | ||
876 | /* | |
877 | * Whereas SX1509 presents RegSense in a simple layout as such: | |
878 | * reg [ f f e e d d c c ] | |
879 | * reg + 1 [ b b a a 9 9 8 8 ] | |
880 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] | |
881 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
882 | * | |
883 | * SX1503 and SX1506 deviate from that data layout, instead storing | |
884 | * thier contents as follows: | |
885 | * | |
886 | * reg [ f f e e d d c c ] | |
887 | * reg + 1 [ 7 7 6 6 5 5 4 4 ] | |
888 | * reg + 2 [ b b a a 9 9 8 8 ] | |
889 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
890 | * | |
891 | * so, taking that into account, we swap two | |
892 | * inner bytes of a 4-byte result | |
893 | */ | |
894 | ||
895 | if (reg == data->reg_sense && | |
896 | data->ngpios == 16 && | |
897 | (data->model == SX150X_123 || | |
898 | data->model == SX150X_456)) { | |
899 | a = val & 0x00ff0000; | |
900 | b = val & 0x0000ff00; | |
901 | ||
902 | val &= 0xff0000ff; | |
903 | val |= b << 8; | |
904 | val |= a >> 8; | |
9e80f906 NA |
905 | } |
906 | ||
6489677f AS |
907 | return val; |
908 | } | |
909 | ||
910 | /* | |
911 | * In order to mask the differences between 16 and 8 bit expander | |
912 | * devices we set up a sligthly ficticious regmap that pretends to be | |
913 | * a set of 32-bit (to accomodate RegSenseLow/RegSenseHigh | |
914 | * pair/quartet) registers and transparently reconstructs those | |
915 | * registers via multiple I2C/SMBus reads | |
916 | * | |
917 | * This way the rest of the driver code, interfacing with the chip via | |
918 | * regmap API, can work assuming that each GPIO pin is represented by | |
919 | * a group of bits at an offset proportioan to GPIO number within a | |
920 | * given register. | |
921 | * | |
922 | */ | |
923 | static int sx150x_regmap_reg_read(void *context, unsigned int reg, | |
924 | unsigned int *result) | |
925 | { | |
926 | int ret, n; | |
927 | struct sx150x_pinctrl *pctl = context; | |
928 | struct i2c_client *i2c = pctl->client; | |
929 | const int width = sx150x_regmap_reg_width(pctl, reg); | |
930 | unsigned int idx, val; | |
931 | ||
932 | /* | |
933 | * There are four potential cases coverd by this function: | |
934 | * | |
935 | * 1) 8-pin chip, single configuration bit register | |
936 | * | |
937 | * This is trivial the code below just needs to read: | |
938 | * reg [ 7 6 5 4 3 2 1 0 ] | |
939 | * | |
940 | * 2) 8-pin chip, double configuration bit register (RegSense) | |
941 | * | |
942 | * The read will be done as follows: | |
943 | * reg [ 7 7 6 6 5 5 4 4 ] | |
944 | * reg + 1 [ 3 3 2 2 1 1 0 0 ] | |
945 | * | |
946 | * 3) 16-pin chip, single configuration bit register | |
947 | * | |
948 | * The read will be done as follows: | |
949 | * reg [ f e d c b a 9 8 ] | |
950 | * reg + 1 [ 7 6 5 4 3 2 1 0 ] | |
951 | * | |
952 | * 4) 16-pin chip, double configuration bit register (RegSense) | |
953 | * | |
954 | * The read will be done as follows: | |
955 | * reg [ f f e e d d c c ] | |
956 | * reg + 1 [ b b a a 9 9 8 8 ] | |
957 | * reg + 2 [ 7 7 6 6 5 5 4 4 ] | |
958 | * reg + 3 [ 3 3 2 2 1 1 0 0 ] | |
959 | */ | |
960 | ||
961 | for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) { | |
962 | val <<= 8; | |
963 | ||
964 | ret = i2c_smbus_read_byte_data(i2c, idx); | |
965 | if (ret < 0) | |
966 | return ret; | |
967 | ||
968 | val |= ret; | |
969 | } | |
970 | ||
971 | *result = sx150x_maybe_swizzle(pctl, reg, val); | |
972 | ||
973 | return 0; | |
974 | } | |
975 | ||
976 | static int sx150x_regmap_reg_write(void *context, unsigned int reg, | |
977 | unsigned int val) | |
978 | { | |
979 | int ret, n; | |
980 | struct sx150x_pinctrl *pctl = context; | |
981 | struct i2c_client *i2c = pctl->client; | |
982 | const int width = sx150x_regmap_reg_width(pctl, reg); | |
983 | ||
984 | val = sx150x_maybe_swizzle(pctl, reg, val); | |
985 | ||
986 | n = width - 8; | |
987 | do { | |
988 | const u8 byte = (val >> n) & 0xff; | |
989 | ||
990 | ret = i2c_smbus_write_byte_data(i2c, reg, byte); | |
991 | if (ret < 0) | |
992 | return ret; | |
993 | ||
994 | reg++; | |
995 | n -= 8; | |
996 | } while (n >= 0); | |
997 | ||
9e80f906 NA |
998 | return 0; |
999 | } | |
1000 | ||
0db0f26c AS |
1001 | static bool sx150x_reg_volatile(struct device *dev, unsigned int reg) |
1002 | { | |
1003 | struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev)); | |
1004 | ||
6489677f | 1005 | return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data; |
0db0f26c AS |
1006 | } |
1007 | ||
1008 | const struct regmap_config sx150x_regmap_config = { | |
1009 | .reg_bits = 8, | |
6489677f | 1010 | .val_bits = 32, |
0db0f26c AS |
1011 | |
1012 | .cache_type = REGCACHE_RBTREE, | |
1013 | ||
6489677f AS |
1014 | .reg_read = sx150x_regmap_reg_read, |
1015 | .reg_write = sx150x_regmap_reg_write, | |
1016 | ||
0db0f26c AS |
1017 | .max_register = SX150X_MAX_REGISTER, |
1018 | .volatile_reg = sx150x_reg_volatile, | |
1019 | }; | |
1020 | ||
9e80f906 NA |
1021 | static int sx150x_probe(struct i2c_client *client, |
1022 | const struct i2c_device_id *id) | |
1023 | { | |
1024 | static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA | | |
1025 | I2C_FUNC_SMBUS_WRITE_WORD_DATA; | |
1026 | struct device *dev = &client->dev; | |
1027 | struct sx150x_pinctrl *pctl; | |
1028 | int ret; | |
1029 | ||
9e80f906 NA |
1030 | if (!i2c_check_functionality(client->adapter, i2c_funcs)) |
1031 | return -ENOSYS; | |
1032 | ||
1033 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
1034 | if (!pctl) | |
1035 | return -ENOMEM; | |
1036 | ||
0db0f26c AS |
1037 | i2c_set_clientdata(client, pctl); |
1038 | ||
9e80f906 NA |
1039 | pctl->dev = dev; |
1040 | pctl->client = client; | |
e3ba8120 AS |
1041 | |
1042 | if (dev->of_node) | |
1043 | pctl->data = of_device_get_match_data(dev); | |
1044 | else | |
1045 | pctl->data = (struct sx150x_device_data *)id->driver_data; | |
1046 | ||
1047 | if (!pctl->data) | |
1048 | return -EINVAL; | |
9e80f906 | 1049 | |
6489677f AS |
1050 | pctl->regmap = devm_regmap_init(dev, NULL, pctl, |
1051 | &sx150x_regmap_config); | |
0db0f26c AS |
1052 | if (IS_ERR(pctl->regmap)) { |
1053 | ret = PTR_ERR(pctl->regmap); | |
1054 | dev_err(dev, "Failed to allocate register map: %d\n", | |
1055 | ret); | |
1056 | return ret; | |
1057 | } | |
1058 | ||
9e80f906 NA |
1059 | mutex_init(&pctl->lock); |
1060 | ||
1061 | ret = sx150x_init_hw(pctl); | |
1062 | if (ret) | |
1063 | return ret; | |
1064 | ||
1065 | /* Register GPIO controller */ | |
1066 | pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL); | |
1067 | pctl->gpio.base = -1; | |
1068 | pctl->gpio.ngpio = pctl->data->npins; | |
1069 | pctl->gpio.get_direction = sx150x_gpio_get_direction; | |
1070 | pctl->gpio.direction_input = sx150x_gpio_direction_input; | |
1071 | pctl->gpio.direction_output = sx150x_gpio_direction_output; | |
1072 | pctl->gpio.get = sx150x_gpio_get; | |
1073 | pctl->gpio.set = sx150x_gpio_set; | |
1074 | pctl->gpio.set_single_ended = sx150x_gpio_set_single_ended; | |
1075 | pctl->gpio.parent = dev; | |
1076 | #ifdef CONFIG_OF_GPIO | |
1077 | pctl->gpio.of_node = dev->of_node; | |
1078 | #endif | |
1079 | pctl->gpio.can_sleep = true; | |
1080 | ||
1081 | ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
1085 | /* Add Interrupt support if an irq is specified */ | |
1086 | if (client->irq > 0) { | |
1087 | pctl->irq_chip.name = devm_kstrdup(dev, client->name, | |
1088 | GFP_KERNEL); | |
1089 | pctl->irq_chip.irq_mask = sx150x_irq_mask; | |
1090 | pctl->irq_chip.irq_unmask = sx150x_irq_unmask; | |
1091 | pctl->irq_chip.irq_set_type = sx150x_irq_set_type; | |
1092 | pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock; | |
1093 | pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock; | |
1094 | ||
1095 | pctl->irq.masked = ~0; | |
1096 | pctl->irq.sense = 0; | |
9e80f906 | 1097 | |
080c489d AS |
1098 | /* |
1099 | * Because sx150x_irq_threaded_fn invokes all of the | |
1100 | * nested interrrupt handlers via handle_nested_irq, | |
1101 | * any "handler" passed to gpiochip_irqchip_add() | |
1102 | * below is going to be ignored, so the choice of the | |
1103 | * function does not matter that much. | |
1104 | * | |
1105 | * We set it to handle_bad_irq to avoid confusion, | |
1106 | * plus it will be instantly noticeable if it is ever | |
1107 | * called (should not happen) | |
1108 | */ | |
9e80f906 NA |
1109 | ret = gpiochip_irqchip_add(&pctl->gpio, |
1110 | &pctl->irq_chip, 0, | |
080c489d | 1111 | handle_bad_irq, IRQ_TYPE_NONE); |
9e80f906 NA |
1112 | if (ret) { |
1113 | dev_err(dev, "could not connect irqchip to gpiochip\n"); | |
1114 | return ret; | |
1115 | } | |
1116 | ||
1117 | ret = devm_request_threaded_irq(dev, client->irq, NULL, | |
1118 | sx150x_irq_thread_fn, | |
1119 | IRQF_ONESHOT | IRQF_SHARED | | |
1120 | IRQF_TRIGGER_FALLING, | |
1121 | pctl->irq_chip.name, pctl); | |
1122 | if (ret < 0) | |
1123 | return ret; | |
1124 | } | |
1125 | ||
1126 | /* Pinctrl_desc */ | |
1127 | pctl->pinctrl_desc.name = "sx150x-pinctrl"; | |
1128 | pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops; | |
1129 | pctl->pinctrl_desc.confops = &sx150x_pinconf_ops; | |
1130 | pctl->pinctrl_desc.pins = pctl->data->pins; | |
1131 | pctl->pinctrl_desc.npins = pctl->data->npins; | |
1132 | pctl->pinctrl_desc.owner = THIS_MODULE; | |
1133 | ||
1134 | pctl->pctldev = pinctrl_register(&pctl->pinctrl_desc, dev, pctl); | |
1135 | if (IS_ERR(pctl->pctldev)) { | |
1136 | dev_err(dev, "Failed to register pinctrl device\n"); | |
1137 | return PTR_ERR(pctl->pctldev); | |
1138 | } | |
1139 | ||
1140 | return 0; | |
1141 | } | |
1142 | ||
1143 | static struct i2c_driver sx150x_driver = { | |
1144 | .driver = { | |
1145 | .name = "sx150x-pinctrl", | |
1146 | .of_match_table = of_match_ptr(sx150x_of_match), | |
1147 | }, | |
1148 | .probe = sx150x_probe, | |
1149 | .id_table = sx150x_id, | |
1150 | }; | |
1151 | ||
1152 | static int __init sx150x_init(void) | |
1153 | { | |
1154 | return i2c_add_driver(&sx150x_driver); | |
1155 | } | |
1156 | subsys_initcall(sx150x_init); |