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Commit | Line | Data |
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2744e8af LW |
1 | /* |
2 | * Core driver for the pin muxing portions of the pin control subsystem | |
3 | * | |
e93bcee0 | 4 | * Copyright (C) 2011-2012 ST-Ericsson SA |
2744e8af LW |
5 | * Written on behalf of Linaro for ST-Ericsson |
6 | * Based on bits of regulator core, gpio core and clk core | |
7 | * | |
8 | * Author: Linus Walleij <linus.walleij@linaro.org> | |
9 | * | |
7ecdb16f SW |
10 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. |
11 | * | |
2744e8af LW |
12 | * License terms: GNU General Public License (GPL) version 2 |
13 | */ | |
14 | #define pr_fmt(fmt) "pinmux core: " fmt | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/slab.h> | |
21 | #include <linux/radix-tree.h> | |
22 | #include <linux/err.h> | |
23 | #include <linux/list.h> | |
97607d15 | 24 | #include <linux/string.h> |
2744e8af LW |
25 | #include <linux/sysfs.h> |
26 | #include <linux/debugfs.h> | |
27 | #include <linux/seq_file.h> | |
28 | #include <linux/pinctrl/machine.h> | |
29 | #include <linux/pinctrl/pinmux.h> | |
30 | #include "core.h" | |
befe5bdf | 31 | #include "pinmux.h" |
2744e8af | 32 | |
03665e0f SW |
33 | int pinmux_check_ops(struct pinctrl_dev *pctldev) |
34 | { | |
35 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
a1d31f71 | 36 | unsigned nfuncs; |
03665e0f SW |
37 | unsigned selector = 0; |
38 | ||
39 | /* Check that we implement required operations */ | |
a1d31f71 DA |
40 | if (!ops || |
41 | !ops->get_functions_count || | |
03665e0f SW |
42 | !ops->get_function_name || |
43 | !ops->get_function_groups || | |
03e9f0ca | 44 | !ops->set_mux) { |
ad6e1107 | 45 | dev_err(pctldev->dev, "pinmux ops lacks necessary functions\n"); |
03665e0f | 46 | return -EINVAL; |
ad6e1107 | 47 | } |
03665e0f | 48 | /* Check that all functions registered have names */ |
a1d31f71 | 49 | nfuncs = ops->get_functions_count(pctldev); |
d1e90e9e | 50 | while (selector < nfuncs) { |
03665e0f SW |
51 | const char *fname = ops->get_function_name(pctldev, |
52 | selector); | |
53 | if (!fname) { | |
a1d31f71 | 54 | dev_err(pctldev->dev, "pinmux ops has no name for function%u\n", |
03665e0f SW |
55 | selector); |
56 | return -EINVAL; | |
57 | } | |
58 | selector++; | |
59 | } | |
60 | ||
61 | return 0; | |
62 | } | |
63 | ||
1e2082b5 SW |
64 | int pinmux_validate_map(struct pinctrl_map const *map, int i) |
65 | { | |
66 | if (!map->data.mux.function) { | |
67 | pr_err("failed to register map %s (%d): no function given\n", | |
68 | map->name, i); | |
69 | return -EINVAL; | |
70 | } | |
71 | ||
72 | return 0; | |
73 | } | |
74 | ||
2744e8af LW |
75 | /** |
76 | * pin_request() - request a single pin to be muxed in, typically for GPIO | |
77 | * @pin: the pin number in the global pin space | |
3cc70ed3 SW |
78 | * @owner: a representation of the owner of this pin; typically the device |
79 | * name that controls its mux function, or the requested GPIO name | |
2744e8af LW |
80 | * @gpio_range: the range matching the GPIO pin if this is a request for a |
81 | * single GPIO pin | |
82 | */ | |
83 | static int pin_request(struct pinctrl_dev *pctldev, | |
3cc70ed3 | 84 | int pin, const char *owner, |
2744e8af LW |
85 | struct pinctrl_gpio_range *gpio_range) |
86 | { | |
87 | struct pin_desc *desc; | |
88 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
89 | int status = -EINVAL; | |
90 | ||
2744e8af LW |
91 | desc = pin_desc_get(pctldev, pin); |
92 | if (desc == NULL) { | |
51cd24ee | 93 | dev_err(pctldev->dev, |
d4705316 SW |
94 | "pin %d is not registered so it cannot be requested\n", |
95 | pin); | |
2744e8af LW |
96 | goto out; |
97 | } | |
98 | ||
d0bd8df5 DA |
99 | dev_dbg(pctldev->dev, "request pin %d (%s) for %s\n", |
100 | pin, desc->name, owner); | |
101 | ||
652162d4 SW |
102 | if (gpio_range) { |
103 | /* There's no need to support multiple GPIO requests */ | |
104 | if (desc->gpio_owner) { | |
105 | dev_err(pctldev->dev, | |
d4705316 SW |
106 | "pin %s already requested by %s; cannot claim for %s\n", |
107 | desc->name, desc->gpio_owner, owner); | |
652162d4 SW |
108 | goto out; |
109 | } | |
8c4c2016 | 110 | if (ops->strict && desc->mux_usecount && |
fa76a3db SZ |
111 | strcmp(desc->mux_owner, owner)) { |
112 | dev_err(pctldev->dev, | |
113 | "pin %s already requested by %s; cannot claim for %s\n", | |
114 | desc->name, desc->mux_owner, owner); | |
115 | goto out; | |
116 | } | |
0e3db173 | 117 | |
652162d4 SW |
118 | desc->gpio_owner = owner; |
119 | } else { | |
120 | if (desc->mux_usecount && strcmp(desc->mux_owner, owner)) { | |
121 | dev_err(pctldev->dev, | |
d4705316 SW |
122 | "pin %s already requested by %s; cannot claim for %s\n", |
123 | desc->name, desc->mux_owner, owner); | |
652162d4 SW |
124 | goto out; |
125 | } | |
8c4c2016 | 126 | if (ops->strict && desc->gpio_owner) { |
fa76a3db SZ |
127 | dev_err(pctldev->dev, |
128 | "pin %s already requested by %s; cannot claim for %s\n", | |
129 | desc->name, desc->gpio_owner, owner); | |
130 | goto out; | |
131 | } | |
0e3db173 | 132 | |
652162d4 SW |
133 | desc->mux_usecount++; |
134 | if (desc->mux_usecount > 1) | |
135 | return 0; | |
136 | ||
137 | desc->mux_owner = owner; | |
138 | } | |
2744e8af LW |
139 | |
140 | /* Let each pin increase references to this module */ | |
141 | if (!try_module_get(pctldev->owner)) { | |
51cd24ee | 142 | dev_err(pctldev->dev, |
2744e8af LW |
143 | "could not increase module refcount for pin %d\n", |
144 | pin); | |
145 | status = -EINVAL; | |
146 | goto out_free_pin; | |
147 | } | |
148 | ||
149 | /* | |
150 | * If there is no kind of request function for the pin we just assume | |
151 | * we got it by default and proceed. | |
152 | */ | |
3712a3c4 | 153 | if (gpio_range && ops->gpio_request_enable) |
2744e8af LW |
154 | /* This requests and enables a single GPIO pin */ |
155 | status = ops->gpio_request_enable(pctldev, gpio_range, pin); | |
156 | else if (ops->request) | |
157 | status = ops->request(pctldev, pin); | |
158 | else | |
159 | status = 0; | |
160 | ||
0e3db173 | 161 | if (status) { |
d4705316 | 162 | dev_err(pctldev->dev, "request() failed for pin %d\n", pin); |
0e3db173 SW |
163 | module_put(pctldev->owner); |
164 | } | |
165 | ||
2744e8af | 166 | out_free_pin: |
0e3db173 | 167 | if (status) { |
652162d4 SW |
168 | if (gpio_range) { |
169 | desc->gpio_owner = NULL; | |
170 | } else { | |
171 | desc->mux_usecount--; | |
172 | if (!desc->mux_usecount) | |
173 | desc->mux_owner = NULL; | |
174 | } | |
0e3db173 | 175 | } |
2744e8af LW |
176 | out: |
177 | if (status) | |
51cd24ee | 178 | dev_err(pctldev->dev, "pin-%d (%s) status %d\n", |
d4705316 | 179 | pin, owner, status); |
2744e8af LW |
180 | |
181 | return status; | |
182 | } | |
183 | ||
184 | /** | |
185 | * pin_free() - release a single muxed in pin so something else can be muxed | |
186 | * @pctldev: pin controller device handling this pin | |
187 | * @pin: the pin to free | |
3712a3c4 SW |
188 | * @gpio_range: the range matching the GPIO pin if this is a request for a |
189 | * single GPIO pin | |
336cdba0 | 190 | * |
3cc70ed3 SW |
191 | * This function returns a pointer to the previous owner. This is used |
192 | * for callers that dynamically allocate an owner name so it can be freed | |
336cdba0 | 193 | * once the pin is free. This is done for GPIO request functions. |
2744e8af | 194 | */ |
3712a3c4 SW |
195 | static const char *pin_free(struct pinctrl_dev *pctldev, int pin, |
196 | struct pinctrl_gpio_range *gpio_range) | |
2744e8af LW |
197 | { |
198 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
199 | struct pin_desc *desc; | |
3cc70ed3 | 200 | const char *owner; |
2744e8af LW |
201 | |
202 | desc = pin_desc_get(pctldev, pin); | |
203 | if (desc == NULL) { | |
51cd24ee | 204 | dev_err(pctldev->dev, |
2744e8af | 205 | "pin is not registered so it cannot be freed\n"); |
3712a3c4 | 206 | return NULL; |
2744e8af LW |
207 | } |
208 | ||
652162d4 | 209 | if (!gpio_range) { |
740924a2 RG |
210 | /* |
211 | * A pin should not be freed more times than allocated. | |
212 | */ | |
213 | if (WARN_ON(!desc->mux_usecount)) | |
214 | return NULL; | |
652162d4 SW |
215 | desc->mux_usecount--; |
216 | if (desc->mux_usecount) | |
217 | return NULL; | |
218 | } | |
0e3db173 | 219 | |
3712a3c4 SW |
220 | /* |
221 | * If there is no kind of request function for the pin we just assume | |
222 | * we got it by default and proceed. | |
223 | */ | |
224 | if (gpio_range && ops->gpio_disable_free) | |
225 | ops->gpio_disable_free(pctldev, gpio_range, pin); | |
226 | else if (ops->free) | |
2744e8af LW |
227 | ops->free(pctldev, pin); |
228 | ||
652162d4 SW |
229 | if (gpio_range) { |
230 | owner = desc->gpio_owner; | |
231 | desc->gpio_owner = NULL; | |
232 | } else { | |
233 | owner = desc->mux_owner; | |
234 | desc->mux_owner = NULL; | |
235 | desc->mux_setting = NULL; | |
236 | } | |
237 | ||
2744e8af | 238 | module_put(pctldev->owner); |
3712a3c4 | 239 | |
3cc70ed3 | 240 | return owner; |
2744e8af LW |
241 | } |
242 | ||
243 | /** | |
befe5bdf LW |
244 | * pinmux_request_gpio() - request pinmuxing for a GPIO pin |
245 | * @pctldev: pin controller device affected | |
246 | * @pin: the pin to mux in for GPIO | |
247 | * @range: the applicable GPIO range | |
2744e8af | 248 | */ |
befe5bdf LW |
249 | int pinmux_request_gpio(struct pinctrl_dev *pctldev, |
250 | struct pinctrl_gpio_range *range, | |
251 | unsigned pin, unsigned gpio) | |
2744e8af | 252 | { |
3cc70ed3 | 253 | const char *owner; |
2744e8af | 254 | int ret; |
2744e8af LW |
255 | |
256 | /* Conjure some name stating what chip and pin this is taken by */ | |
23a895ae | 257 | owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio); |
3cc70ed3 | 258 | if (!owner) |
5d2eaf80 SW |
259 | return -EINVAL; |
260 | ||
3cc70ed3 | 261 | ret = pin_request(pctldev, pin, owner, range); |
5d2eaf80 | 262 | if (ret < 0) |
3cc70ed3 | 263 | kfree(owner); |
5d2eaf80 SW |
264 | |
265 | return ret; | |
2744e8af | 266 | } |
2744e8af LW |
267 | |
268 | /** | |
befe5bdf LW |
269 | * pinmux_free_gpio() - release a pin from GPIO muxing |
270 | * @pctldev: the pin controller device for the pin | |
271 | * @pin: the affected currently GPIO-muxed in pin | |
272 | * @range: applicable GPIO range | |
2744e8af | 273 | */ |
befe5bdf LW |
274 | void pinmux_free_gpio(struct pinctrl_dev *pctldev, unsigned pin, |
275 | struct pinctrl_gpio_range *range) | |
2744e8af | 276 | { |
3cc70ed3 | 277 | const char *owner; |
2744e8af | 278 | |
3cc70ed3 SW |
279 | owner = pin_free(pctldev, pin, range); |
280 | kfree(owner); | |
2744e8af | 281 | } |
2744e8af | 282 | |
befe5bdf LW |
283 | /** |
284 | * pinmux_gpio_direction() - set the direction of a single muxed-in GPIO pin | |
285 | * @pctldev: the pin controller handling this pin | |
286 | * @range: applicable GPIO range | |
287 | * @pin: the affected GPIO pin in this controller | |
288 | * @input: true if we set the pin as input, false for output | |
289 | */ | |
290 | int pinmux_gpio_direction(struct pinctrl_dev *pctldev, | |
291 | struct pinctrl_gpio_range *range, | |
292 | unsigned pin, bool input) | |
542e704f | 293 | { |
542e704f LW |
294 | const struct pinmux_ops *ops; |
295 | int ret; | |
542e704f LW |
296 | |
297 | ops = pctldev->desc->pmxops; | |
298 | ||
542e704f LW |
299 | if (ops->gpio_set_direction) |
300 | ret = ops->gpio_set_direction(pctldev, range, pin, input); | |
301 | else | |
302 | ret = 0; | |
303 | ||
304 | return ret; | |
305 | } | |
306 | ||
7ecdb16f SW |
307 | static int pinmux_func_name_to_selector(struct pinctrl_dev *pctldev, |
308 | const char *function) | |
2744e8af LW |
309 | { |
310 | const struct pinmux_ops *ops = pctldev->desc->pmxops; | |
d1e90e9e | 311 | unsigned nfuncs = ops->get_functions_count(pctldev); |
2744e8af LW |
312 | unsigned selector = 0; |
313 | ||
314 | /* See if this pctldev has this function */ | |
d1e90e9e | 315 | while (selector < nfuncs) { |
163dc9f3 | 316 | const char *fname = ops->get_function_name(pctldev, selector); |
2744e8af | 317 | |
7ecdb16f SW |
318 | if (!strcmp(function, fname)) |
319 | return selector; | |
2744e8af | 320 | |
2744e8af LW |
321 | selector++; |
322 | } | |
323 | ||
e3249570 | 324 | dev_err(pctldev->dev, "function '%s' not supported\n", function); |
2744e8af LW |
325 | return -EINVAL; |
326 | } | |
327 | ||
7ecdb16f SW |
328 | int pinmux_map_to_setting(struct pinctrl_map const *map, |
329 | struct pinctrl_setting *setting) | |
2744e8af | 330 | { |
7ecdb16f SW |
331 | struct pinctrl_dev *pctldev = setting->pctldev; |
332 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
7ecdb16f SW |
333 | char const * const *groups; |
334 | unsigned num_groups; | |
2744e8af | 335 | int ret; |
7ecdb16f SW |
336 | const char *group; |
337 | int i; | |
2744e8af | 338 | |
ad8bb720 DA |
339 | if (!pmxops) { |
340 | dev_err(pctldev->dev, "does not support mux function\n"); | |
341 | return -EINVAL; | |
342 | } | |
343 | ||
15f70e1b | 344 | ret = pinmux_func_name_to_selector(pctldev, map->data.mux.function); |
ad6e1107 JC |
345 | if (ret < 0) { |
346 | dev_err(pctldev->dev, "invalid function %s in map table\n", | |
347 | map->data.mux.function); | |
15f70e1b | 348 | return ret; |
ad6e1107 | 349 | } |
15f70e1b | 350 | setting->data.mux.func = ret; |
2744e8af | 351 | |
1e2082b5 | 352 | ret = pmxops->get_function_groups(pctldev, setting->data.mux.func, |
7ecdb16f | 353 | &groups, &num_groups); |
ad6e1107 JC |
354 | if (ret < 0) { |
355 | dev_err(pctldev->dev, "can't query groups for function %s\n", | |
356 | map->data.mux.function); | |
7ecdb16f | 357 | return ret; |
ad6e1107 JC |
358 | } |
359 | if (!num_groups) { | |
360 | dev_err(pctldev->dev, | |
361 | "function %s can't be selected on any group\n", | |
362 | map->data.mux.function); | |
2744e8af | 363 | return -EINVAL; |
ad6e1107 | 364 | } |
1e2082b5 | 365 | if (map->data.mux.group) { |
7ecdb16f | 366 | bool found = false; |
1e2082b5 | 367 | group = map->data.mux.group; |
7ecdb16f SW |
368 | for (i = 0; i < num_groups; i++) { |
369 | if (!strcmp(group, groups[i])) { | |
370 | found = true; | |
371 | break; | |
372 | } | |
373 | } | |
ad6e1107 JC |
374 | if (!found) { |
375 | dev_err(pctldev->dev, | |
376 | "invalid group \"%s\" for function \"%s\"\n", | |
377 | group, map->data.mux.function); | |
7ecdb16f | 378 | return -EINVAL; |
ad6e1107 | 379 | } |
7ecdb16f SW |
380 | } else { |
381 | group = groups[0]; | |
2744e8af | 382 | } |
2744e8af | 383 | |
15f70e1b | 384 | ret = pinctrl_get_group_selector(pctldev, group); |
ad6e1107 JC |
385 | if (ret < 0) { |
386 | dev_err(pctldev->dev, "invalid group %s in map table\n", | |
387 | map->data.mux.group); | |
15f70e1b | 388 | return ret; |
ad6e1107 | 389 | } |
15f70e1b | 390 | setting->data.mux.group = ret; |
2744e8af | 391 | |
2744e8af LW |
392 | return 0; |
393 | } | |
394 | ||
7ecdb16f | 395 | void pinmux_free_setting(struct pinctrl_setting const *setting) |
2744e8af | 396 | { |
1a78958d | 397 | /* This function is currently unused */ |
2744e8af | 398 | } |
2744e8af | 399 | |
7ecdb16f | 400 | int pinmux_enable_setting(struct pinctrl_setting const *setting) |
2744e8af | 401 | { |
7ecdb16f | 402 | struct pinctrl_dev *pctldev = setting->pctldev; |
ba110d90 | 403 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
befe5bdf | 404 | const struct pinmux_ops *ops = pctldev->desc->pmxops; |
e5b3b2d9 AT |
405 | int ret = 0; |
406 | const unsigned *pins = NULL; | |
407 | unsigned num_pins = 0; | |
ba110d90 SW |
408 | int i; |
409 | struct pin_desc *desc; | |
410 | ||
e5b3b2d9 AT |
411 | if (pctlops->get_group_pins) |
412 | ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, | |
413 | &pins, &num_pins); | |
414 | ||
ba110d90 | 415 | if (ret) { |
1c8e7944 LW |
416 | const char *gname; |
417 | ||
ba110d90 | 418 | /* errors only affect debug data, so just warn */ |
1c8e7944 LW |
419 | gname = pctlops->get_group_name(pctldev, |
420 | setting->data.mux.group); | |
ba110d90 | 421 | dev_warn(pctldev->dev, |
1c8e7944 LW |
422 | "could not get pins for group %s\n", |
423 | gname); | |
ba110d90 SW |
424 | num_pins = 0; |
425 | } | |
426 | ||
1a78958d LW |
427 | /* Try to allocate all pins in this group, one by one */ |
428 | for (i = 0; i < num_pins; i++) { | |
429 | ret = pin_request(pctldev, pins[i], setting->dev_name, NULL); | |
430 | if (ret) { | |
1c8e7944 LW |
431 | const char *gname; |
432 | const char *pname; | |
433 | ||
434 | desc = pin_desc_get(pctldev, pins[i]); | |
435 | pname = desc ? desc->name : "non-existing"; | |
436 | gname = pctlops->get_group_name(pctldev, | |
437 | setting->data.mux.group); | |
1a78958d | 438 | dev_err(pctldev->dev, |
1c8e7944 LW |
439 | "could not request pin %d (%s) from group %s " |
440 | " on device %s\n", | |
441 | pins[i], pname, gname, | |
442 | pinctrl_dev_get_name(pctldev)); | |
e38d457d | 443 | goto err_pin_request; |
1a78958d LW |
444 | } |
445 | } | |
446 | ||
447 | /* Now that we have acquired the pins, encode the mux setting */ | |
ba110d90 SW |
448 | for (i = 0; i < num_pins; i++) { |
449 | desc = pin_desc_get(pctldev, pins[i]); | |
450 | if (desc == NULL) { | |
451 | dev_warn(pctldev->dev, | |
452 | "could not get pin desc for pin %d\n", | |
453 | pins[i]); | |
454 | continue; | |
455 | } | |
456 | desc->mux_setting = &(setting->data.mux); | |
457 | } | |
2744e8af | 458 | |
03e9f0ca LW |
459 | ret = ops->set_mux(pctldev, setting->data.mux.func, |
460 | setting->data.mux.group); | |
e38d457d AL |
461 | |
462 | if (ret) | |
03e9f0ca | 463 | goto err_set_mux; |
e38d457d AL |
464 | |
465 | return 0; | |
466 | ||
03e9f0ca | 467 | err_set_mux: |
e38d457d AL |
468 | for (i = 0; i < num_pins; i++) { |
469 | desc = pin_desc_get(pctldev, pins[i]); | |
470 | if (desc) | |
471 | desc->mux_setting = NULL; | |
472 | } | |
473 | err_pin_request: | |
474 | /* On error release all taken pins */ | |
475 | while (--i >= 0) | |
476 | pin_free(pctldev, pins[i], NULL); | |
477 | ||
478 | return ret; | |
2744e8af | 479 | } |
2744e8af | 480 | |
7ecdb16f | 481 | void pinmux_disable_setting(struct pinctrl_setting const *setting) |
2744e8af | 482 | { |
7ecdb16f | 483 | struct pinctrl_dev *pctldev = setting->pctldev; |
ba110d90 | 484 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
e5b3b2d9 AT |
485 | int ret = 0; |
486 | const unsigned *pins = NULL; | |
487 | unsigned num_pins = 0; | |
ba110d90 SW |
488 | int i; |
489 | struct pin_desc *desc; | |
490 | ||
e5b3b2d9 AT |
491 | if (pctlops->get_group_pins) |
492 | ret = pctlops->get_group_pins(pctldev, setting->data.mux.group, | |
493 | &pins, &num_pins); | |
ba110d90 | 494 | if (ret) { |
1c8e7944 LW |
495 | const char *gname; |
496 | ||
ba110d90 | 497 | /* errors only affect debug data, so just warn */ |
1c8e7944 LW |
498 | gname = pctlops->get_group_name(pctldev, |
499 | setting->data.mux.group); | |
ba110d90 | 500 | dev_warn(pctldev->dev, |
1c8e7944 LW |
501 | "could not get pins for group %s\n", |
502 | gname); | |
ba110d90 SW |
503 | num_pins = 0; |
504 | } | |
505 | ||
1a78958d | 506 | /* Flag the descs that no setting is active */ |
ba110d90 SW |
507 | for (i = 0; i < num_pins; i++) { |
508 | desc = pin_desc_get(pctldev, pins[i]); | |
509 | if (desc == NULL) { | |
510 | dev_warn(pctldev->dev, | |
511 | "could not get pin desc for pin %d\n", | |
512 | pins[i]); | |
513 | continue; | |
514 | } | |
744f0a9a SZ |
515 | if (desc->mux_setting == &(setting->data.mux)) { |
516 | desc->mux_setting = NULL; | |
517 | /* And release the pin */ | |
518 | pin_free(pctldev, pins[i], NULL); | |
1c8e7944 LW |
519 | } else { |
520 | const char *gname; | |
1c8e7944 | 521 | |
1c8e7944 LW |
522 | gname = pctlops->get_group_name(pctldev, |
523 | setting->data.mux.group); | |
524 | dev_warn(pctldev->dev, | |
525 | "not freeing pin %d (%s) as part of " | |
526 | "deactivating group %s - it is already " | |
527 | "used for some other setting", | |
808e657c | 528 | pins[i], desc->name, gname); |
744f0a9a | 529 | } |
ba110d90 | 530 | } |
2744e8af | 531 | } |
2744e8af | 532 | |
2744e8af LW |
533 | #ifdef CONFIG_DEBUG_FS |
534 | ||
535 | /* Called from pincontrol core */ | |
536 | static int pinmux_functions_show(struct seq_file *s, void *what) | |
537 | { | |
538 | struct pinctrl_dev *pctldev = s->private; | |
539 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
ad8bb720 | 540 | unsigned nfuncs; |
2744e8af LW |
541 | unsigned func_selector = 0; |
542 | ||
ad8bb720 DA |
543 | if (!pmxops) |
544 | return 0; | |
57b676f9 | 545 | |
42fed7ba | 546 | mutex_lock(&pctldev->mutex); |
ad8bb720 | 547 | nfuncs = pmxops->get_functions_count(pctldev); |
d1e90e9e | 548 | while (func_selector < nfuncs) { |
2744e8af LW |
549 | const char *func = pmxops->get_function_name(pctldev, |
550 | func_selector); | |
551 | const char * const *groups; | |
552 | unsigned num_groups; | |
553 | int ret; | |
554 | int i; | |
555 | ||
556 | ret = pmxops->get_function_groups(pctldev, func_selector, | |
557 | &groups, &num_groups); | |
9d7ebbbf | 558 | if (ret) { |
2744e8af LW |
559 | seq_printf(s, "function %s: COULD NOT GET GROUPS\n", |
560 | func); | |
9d7ebbbf LD |
561 | func_selector++; |
562 | continue; | |
563 | } | |
2744e8af LW |
564 | |
565 | seq_printf(s, "function: %s, groups = [ ", func); | |
566 | for (i = 0; i < num_groups; i++) | |
567 | seq_printf(s, "%s ", groups[i]); | |
568 | seq_puts(s, "]\n"); | |
569 | ||
570 | func_selector++; | |
2744e8af LW |
571 | } |
572 | ||
42fed7ba | 573 | mutex_unlock(&pctldev->mutex); |
57b676f9 | 574 | |
2744e8af LW |
575 | return 0; |
576 | } | |
577 | ||
578 | static int pinmux_pins_show(struct seq_file *s, void *what) | |
579 | { | |
580 | struct pinctrl_dev *pctldev = s->private; | |
ba110d90 SW |
581 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; |
582 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
706e8520 | 583 | unsigned i, pin; |
2744e8af | 584 | |
ad8bb720 DA |
585 | if (!pmxops) |
586 | return 0; | |
587 | ||
2744e8af | 588 | seq_puts(s, "Pinmux settings per pin\n"); |
81508855 LW |
589 | if (pmxops->strict) |
590 | seq_puts(s, | |
591 | "Format: pin (name): mux_owner|gpio_owner (strict) hog?\n"); | |
592 | else | |
593 | seq_puts(s, | |
594 | "Format: pin (name): mux_owner gpio_owner hog?\n"); | |
2744e8af | 595 | |
42fed7ba | 596 | mutex_lock(&pctldev->mutex); |
57b676f9 | 597 | |
706e8520 CP |
598 | /* The pin number can be retrived from the pin controller descriptor */ |
599 | for (i = 0; i < pctldev->desc->npins; i++) { | |
2744e8af | 600 | struct pin_desc *desc; |
1cf94c45 | 601 | bool is_hog = false; |
2744e8af | 602 | |
706e8520 | 603 | pin = pctldev->desc->pins[i].number; |
2744e8af | 604 | desc = pin_desc_get(pctldev, pin); |
706e8520 | 605 | /* Skip if we cannot search the pin */ |
2744e8af LW |
606 | if (desc == NULL) |
607 | continue; | |
608 | ||
652162d4 SW |
609 | if (desc->mux_owner && |
610 | !strcmp(desc->mux_owner, pinctrl_dev_get_name(pctldev))) | |
1cf94c45 LW |
611 | is_hog = true; |
612 | ||
81508855 LW |
613 | if (pmxops->strict) { |
614 | if (desc->mux_owner) | |
615 | seq_printf(s, "pin %d (%s): device %s%s", | |
616 | pin, | |
617 | desc->name ? desc->name : "unnamed", | |
618 | desc->mux_owner, | |
619 | is_hog ? " (HOG)" : ""); | |
620 | else if (desc->gpio_owner) | |
621 | seq_printf(s, "pin %d (%s): GPIO %s", | |
622 | pin, | |
623 | desc->name ? desc->name : "unnamed", | |
624 | desc->gpio_owner); | |
625 | else | |
626 | seq_printf(s, "pin %d (%s): UNCLAIMED", | |
627 | pin, | |
628 | desc->name ? desc->name : "unnamed"); | |
629 | } else { | |
630 | /* For non-strict controllers */ | |
631 | seq_printf(s, "pin %d (%s): %s %s%s", pin, | |
632 | desc->name ? desc->name : "unnamed", | |
633 | desc->mux_owner ? desc->mux_owner | |
634 | : "(MUX UNCLAIMED)", | |
635 | desc->gpio_owner ? desc->gpio_owner | |
636 | : "(GPIO UNCLAIMED)", | |
637 | is_hog ? " (HOG)" : ""); | |
638 | } | |
ba110d90 | 639 | |
81508855 | 640 | /* If mux: print function+group claiming the pin */ |
ba110d90 SW |
641 | if (desc->mux_setting) |
642 | seq_printf(s, " function %s group %s\n", | |
643 | pmxops->get_function_name(pctldev, | |
644 | desc->mux_setting->func), | |
645 | pctlops->get_group_name(pctldev, | |
646 | desc->mux_setting->group)); | |
647 | else | |
648 | seq_printf(s, "\n"); | |
2744e8af LW |
649 | } |
650 | ||
42fed7ba | 651 | mutex_unlock(&pctldev->mutex); |
57b676f9 | 652 | |
2744e8af LW |
653 | return 0; |
654 | } | |
655 | ||
1e2082b5 SW |
656 | void pinmux_show_map(struct seq_file *s, struct pinctrl_map const *map) |
657 | { | |
658 | seq_printf(s, "group %s\nfunction %s\n", | |
659 | map->data.mux.group ? map->data.mux.group : "(default)", | |
660 | map->data.mux.function); | |
661 | } | |
662 | ||
663 | void pinmux_show_setting(struct seq_file *s, | |
664 | struct pinctrl_setting const *setting) | |
2744e8af | 665 | { |
7ecdb16f SW |
666 | struct pinctrl_dev *pctldev = setting->pctldev; |
667 | const struct pinmux_ops *pmxops = pctldev->desc->pmxops; | |
668 | const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; | |
669 | ||
1e2082b5 SW |
670 | seq_printf(s, "group: %s (%u) function: %s (%u)\n", |
671 | pctlops->get_group_name(pctldev, setting->data.mux.group), | |
672 | setting->data.mux.group, | |
673 | pmxops->get_function_name(pctldev, setting->data.mux.func), | |
674 | setting->data.mux.func); | |
2744e8af LW |
675 | } |
676 | ||
677 | static int pinmux_functions_open(struct inode *inode, struct file *file) | |
678 | { | |
679 | return single_open(file, pinmux_functions_show, inode->i_private); | |
680 | } | |
681 | ||
682 | static int pinmux_pins_open(struct inode *inode, struct file *file) | |
683 | { | |
684 | return single_open(file, pinmux_pins_show, inode->i_private); | |
685 | } | |
686 | ||
2744e8af LW |
687 | static const struct file_operations pinmux_functions_ops = { |
688 | .open = pinmux_functions_open, | |
689 | .read = seq_read, | |
690 | .llseek = seq_lseek, | |
691 | .release = single_release, | |
692 | }; | |
693 | ||
694 | static const struct file_operations pinmux_pins_ops = { | |
695 | .open = pinmux_pins_open, | |
696 | .read = seq_read, | |
697 | .llseek = seq_lseek, | |
698 | .release = single_release, | |
699 | }; | |
700 | ||
2744e8af LW |
701 | void pinmux_init_device_debugfs(struct dentry *devroot, |
702 | struct pinctrl_dev *pctldev) | |
703 | { | |
704 | debugfs_create_file("pinmux-functions", S_IFREG | S_IRUGO, | |
705 | devroot, pctldev, &pinmux_functions_ops); | |
706 | debugfs_create_file("pinmux-pins", S_IFREG | S_IRUGO, | |
707 | devroot, pctldev, &pinmux_pins_ops); | |
2744e8af LW |
708 | } |
709 | ||
710 | #endif /* CONFIG_DEBUG_FS */ |