[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / qcom / pinctrl-ipq8064.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 */

#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/pinctrl.h>

#include "pinctrl-msm.h"

static const struct pinctrl_pin_desc ipq8064_pins[] = {
	PINCTRL_PIN(0, "GPIO_0"),
	PINCTRL_PIN(1, "GPIO_1"),
	PINCTRL_PIN(2, "GPIO_2"),
	PINCTRL_PIN(3, "GPIO_3"),
	PINCTRL_PIN(4, "GPIO_4"),
	PINCTRL_PIN(5, "GPIO_5"),
	PINCTRL_PIN(6, "GPIO_6"),
	PINCTRL_PIN(7, "GPIO_7"),
	PINCTRL_PIN(8, "GPIO_8"),
	PINCTRL_PIN(9, "GPIO_9"),
	PINCTRL_PIN(10, "GPIO_10"),
	PINCTRL_PIN(11, "GPIO_11"),
	PINCTRL_PIN(12, "GPIO_12"),
	PINCTRL_PIN(13, "GPIO_13"),
	PINCTRL_PIN(14, "GPIO_14"),
	PINCTRL_PIN(15, "GPIO_15"),
	PINCTRL_PIN(16, "GPIO_16"),
	PINCTRL_PIN(17, "GPIO_17"),
	PINCTRL_PIN(18, "GPIO_18"),
	PINCTRL_PIN(19, "GPIO_19"),
	PINCTRL_PIN(20, "GPIO_20"),
	PINCTRL_PIN(21, "GPIO_21"),
	PINCTRL_PIN(22, "GPIO_22"),
	PINCTRL_PIN(23, "GPIO_23"),
	PINCTRL_PIN(24, "GPIO_24"),
	PINCTRL_PIN(25, "GPIO_25"),
	PINCTRL_PIN(26, "GPIO_26"),
	PINCTRL_PIN(27, "GPIO_27"),
	PINCTRL_PIN(28, "GPIO_28"),
	PINCTRL_PIN(29, "GPIO_29"),
	PINCTRL_PIN(30, "GPIO_30"),
	PINCTRL_PIN(31, "GPIO_31"),
	PINCTRL_PIN(32, "GPIO_32"),
	PINCTRL_PIN(33, "GPIO_33"),
	PINCTRL_PIN(34, "GPIO_34"),
	PINCTRL_PIN(35, "GPIO_35"),
	PINCTRL_PIN(36, "GPIO_36"),
	PINCTRL_PIN(37, "GPIO_37"),
	PINCTRL_PIN(38, "GPIO_38"),
	PINCTRL_PIN(39, "GPIO_39"),
	PINCTRL_PIN(40, "GPIO_40"),
	PINCTRL_PIN(41, "GPIO_41"),
	PINCTRL_PIN(42, "GPIO_42"),
	PINCTRL_PIN(43, "GPIO_43"),
	PINCTRL_PIN(44, "GPIO_44"),
	PINCTRL_PIN(45, "GPIO_45"),
	PINCTRL_PIN(46, "GPIO_46"),
	PINCTRL_PIN(47, "GPIO_47"),
	PINCTRL_PIN(48, "GPIO_48"),
	PINCTRL_PIN(49, "GPIO_49"),
	PINCTRL_PIN(50, "GPIO_50"),
	PINCTRL_PIN(51, "GPIO_51"),
	PINCTRL_PIN(52, "GPIO_52"),
	PINCTRL_PIN(53, "GPIO_53"),
	PINCTRL_PIN(54, "GPIO_54"),
	PINCTRL_PIN(55, "GPIO_55"),
	PINCTRL_PIN(56, "GPIO_56"),
	PINCTRL_PIN(57, "GPIO_57"),
	PINCTRL_PIN(58, "GPIO_58"),
	PINCTRL_PIN(59, "GPIO_59"),
	PINCTRL_PIN(60, "GPIO_60"),
	PINCTRL_PIN(61, "GPIO_61"),
	PINCTRL_PIN(62, "GPIO_62"),
	PINCTRL_PIN(63, "GPIO_63"),
	PINCTRL_PIN(64, "GPIO_64"),
	PINCTRL_PIN(65, "GPIO_65"),
	PINCTRL_PIN(66, "GPIO_66"),
	PINCTRL_PIN(67, "GPIO_67"),
	PINCTRL_PIN(68, "GPIO_68"),

	PINCTRL_PIN(69, "SDC3_CLK"),
	PINCTRL_PIN(70, "SDC3_CMD"),
	PINCTRL_PIN(71, "SDC3_DATA"),
};

#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
DECLARE_IPQ_GPIO_PINS(0);
DECLARE_IPQ_GPIO_PINS(1);
DECLARE_IPQ_GPIO_PINS(2);
DECLARE_IPQ_GPIO_PINS(3);
DECLARE_IPQ_GPIO_PINS(4);
DECLARE_IPQ_GPIO_PINS(5);
DECLARE_IPQ_GPIO_PINS(6);
DECLARE_IPQ_GPIO_PINS(7);
DECLARE_IPQ_GPIO_PINS(8);
DECLARE_IPQ_GPIO_PINS(9);
DECLARE_IPQ_GPIO_PINS(10);
DECLARE_IPQ_GPIO_PINS(11);
DECLARE_IPQ_GPIO_PINS(12);
DECLARE_IPQ_GPIO_PINS(13);
DECLARE_IPQ_GPIO_PINS(14);
DECLARE_IPQ_GPIO_PINS(15);
DECLARE_IPQ_GPIO_PINS(16);
DECLARE_IPQ_GPIO_PINS(17);
DECLARE_IPQ_GPIO_PINS(18);
DECLARE_IPQ_GPIO_PINS(19);
DECLARE_IPQ_GPIO_PINS(20);
DECLARE_IPQ_GPIO_PINS(21);
DECLARE_IPQ_GPIO_PINS(22);
DECLARE_IPQ_GPIO_PINS(23);
DECLARE_IPQ_GPIO_PINS(24);
DECLARE_IPQ_GPIO_PINS(25);
DECLARE_IPQ_GPIO_PINS(26);
DECLARE_IPQ_GPIO_PINS(27);
DECLARE_IPQ_GPIO_PINS(28);
DECLARE_IPQ_GPIO_PINS(29);
DECLARE_IPQ_GPIO_PINS(30);
DECLARE_IPQ_GPIO_PINS(31);
DECLARE_IPQ_GPIO_PINS(32);
DECLARE_IPQ_GPIO_PINS(33);
DECLARE_IPQ_GPIO_PINS(34);
DECLARE_IPQ_GPIO_PINS(35);
DECLARE_IPQ_GPIO_PINS(36);
DECLARE_IPQ_GPIO_PINS(37);
DECLARE_IPQ_GPIO_PINS(38);
DECLARE_IPQ_GPIO_PINS(39);
DECLARE_IPQ_GPIO_PINS(40);
DECLARE_IPQ_GPIO_PINS(41);
DECLARE_IPQ_GPIO_PINS(42);
DECLARE_IPQ_GPIO_PINS(43);
DECLARE_IPQ_GPIO_PINS(44);
DECLARE_IPQ_GPIO_PINS(45);
DECLARE_IPQ_GPIO_PINS(46);
DECLARE_IPQ_GPIO_PINS(47);
DECLARE_IPQ_GPIO_PINS(48);
DECLARE_IPQ_GPIO_PINS(49);
DECLARE_IPQ_GPIO_PINS(50);
DECLARE_IPQ_GPIO_PINS(51);
DECLARE_IPQ_GPIO_PINS(52);
DECLARE_IPQ_GPIO_PINS(53);
DECLARE_IPQ_GPIO_PINS(54);
DECLARE_IPQ_GPIO_PINS(55);
DECLARE_IPQ_GPIO_PINS(56);
DECLARE_IPQ_GPIO_PINS(57);
DECLARE_IPQ_GPIO_PINS(58);
DECLARE_IPQ_GPIO_PINS(59);
DECLARE_IPQ_GPIO_PINS(60);
DECLARE_IPQ_GPIO_PINS(61);
DECLARE_IPQ_GPIO_PINS(62);
DECLARE_IPQ_GPIO_PINS(63);
DECLARE_IPQ_GPIO_PINS(64);
DECLARE_IPQ_GPIO_PINS(65);
DECLARE_IPQ_GPIO_PINS(66);
DECLARE_IPQ_GPIO_PINS(67);
DECLARE_IPQ_GPIO_PINS(68);

static const unsigned int sdc3_clk_pins[] = { 69 };
static const unsigned int sdc3_cmd_pins[] = { 70 };
static const unsigned int sdc3_data_pins[] = { 71 };

#define FUNCTION(fname)					\
	[IPQ_MUX_##fname] = {				\
		.name = #fname,				\
		.groups = fname##_groups,		\
		.ngroups = ARRAY_SIZE(fname##_groups),	\
	}

#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
	{						\
		.name = "gpio" #id,			\
		.pins = gpio##id##_pins,		\
		.npins = ARRAY_SIZE(gpio##id##_pins),	\
		.funcs = (int[]){			\
			IPQ_MUX_gpio,			\
			IPQ_MUX_##f1,			\
			IPQ_MUX_##f2,			\
			IPQ_MUX_##f3,			\
			IPQ_MUX_##f4,			\
			IPQ_MUX_##f5,			\
			IPQ_MUX_##f6,			\
			IPQ_MUX_##f7,			\
			IPQ_MUX_##f8,			\
			IPQ_MUX_##f9,			\
			IPQ_MUX_##f10,			\
		},					\
		.nfuncs = 11,				\
		.ctl_reg = 0x1000 + 0x10 * id,		\
		.io_reg = 0x1004 + 0x10 * id,		\
		.intr_cfg_reg = 0x1008 + 0x10 * id,	\
		.intr_status_reg = 0x100c + 0x10 * id,	\
		.intr_target_reg = 0x400 + 0x4 * id,	\
		.mux_bit = 2,				\
		.pull_bit = 0,				\
		.drv_bit = 6,				\
		.oe_bit = 9,				\
		.in_bit = 0,				\
		.out_bit = 1,				\
		.intr_enable_bit = 0,			\
		.intr_status_bit = 0,			\
		.intr_ack_high = 1,			\
		.intr_target_bit = 0,			\
		.intr_target_kpss_val = 4,		\
		.intr_raw_status_bit = 3,		\
		.intr_polarity_bit = 1,			\
		.intr_detection_bit = 2,		\
		.intr_detection_width = 1,		\
	}

#define SDC_PINGROUP(pg_name, ctl, pull, drv)		\
	{						\
		.name = #pg_name,	                \
		.pins = pg_name##_pins,                 \
		.npins = ARRAY_SIZE(pg_name##_pins),    \
		.ctl_reg = ctl,                         \
		.io_reg = 0,                            \
		.intr_cfg_reg = 0,                      \
		.intr_status_reg = 0,                   \
		.intr_target_reg = 0,                   \
		.mux_bit = -1,                          \
		.pull_bit = pull,                       \
		.drv_bit = drv,                         \
		.oe_bit = -1,                           \
		.in_bit = -1,                           \
		.out_bit = -1,                          \
		.intr_enable_bit = -1,                  \
		.intr_status_bit = -1,                  \
		.intr_target_bit = -1,                  \
		.intr_target_kpss_val = -1,		\
		.intr_raw_status_bit = -1,              \
		.intr_polarity_bit = -1,                \
		.intr_detection_bit = -1,               \
		.intr_detection_width = -1,             \
	}

enum ipq8064_functions {
	IPQ_MUX_gpio,
	IPQ_MUX_mdio,
	IPQ_MUX_mi2s,
	IPQ_MUX_pdm,
	IPQ_MUX_ssbi,
	IPQ_MUX_spmi,
	IPQ_MUX_audio_pcm,
	IPQ_MUX_gsbi1,
	IPQ_MUX_gsbi2,
	IPQ_MUX_gsbi4,
	IPQ_MUX_gsbi5,
	IPQ_MUX_gsbi5_spi_cs1,
	IPQ_MUX_gsbi5_spi_cs2,
	IPQ_MUX_gsbi5_spi_cs3,
	IPQ_MUX_gsbi6,
	IPQ_MUX_gsbi7,
	IPQ_MUX_nss_spi,
	IPQ_MUX_sdc1,
	IPQ_MUX_spdif,
	IPQ_MUX_nand,
	IPQ_MUX_tsif1,
	IPQ_MUX_tsif2,
	IPQ_MUX_usb_fs_n,
	IPQ_MUX_usb_fs,
	IPQ_MUX_usb2_hsic,
	IPQ_MUX_rgmii2,
	IPQ_MUX_sata,
	IPQ_MUX_pcie1_rst,
	IPQ_MUX_pcie1_prsnt,
	IPQ_MUX_pcie1_pwrflt,
	IPQ_MUX_pcie1_pwren_n,
	IPQ_MUX_pcie1_pwren,
	IPQ_MUX_pcie1_clk_req,
	IPQ_MUX_pcie2_rst,
	IPQ_MUX_pcie2_prsnt,
	IPQ_MUX_pcie2_pwrflt,
	IPQ_MUX_pcie2_pwren_n,
	IPQ_MUX_pcie2_pwren,
	IPQ_MUX_pcie2_clk_req,
	IPQ_MUX_pcie3_rst,
	IPQ_MUX_pcie3_prsnt,
	IPQ_MUX_pcie3_pwrflt,
	IPQ_MUX_pcie3_pwren_n,
	IPQ_MUX_pcie3_pwren,
	IPQ_MUX_pcie3_clk_req,
	IPQ_MUX_ps_hold,
	IPQ_MUX_NA,
};

static const char * const gpio_groups[] = {
	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
};

static const char * const mdio_groups[] = {
	"gpio0", "gpio1", "gpio10", "gpio11",
};

static const char * const mi2s_groups[] = {
	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
	"gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
};

static const char * const pdm_groups[] = {
	"gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
	"gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
	"gpio59",
};

static const char * const ssbi_groups[] = {
	"gpio10", "gpio11",
};

static const char * const spmi_groups[] = {
	"gpio10", "gpio11",
};

static const char * const audio_pcm_groups[] = {
	"gpio14", "gpio15", "gpio16", "gpio17",
};

static const char * const gsbi1_groups[] = {
	"gpio51", "gpio52", "gpio53", "gpio54",
};

static const char * const gsbi2_groups[] = {
	"gpio22", "gpio23", "gpio24", "gpio25",
};

static const char * const gsbi4_groups[] = {
	"gpio10", "gpio11", "gpio12", "gpio13",
};

static const char * const gsbi5_groups[] = {
	"gpio18", "gpio19", "gpio20", "gpio21",
};

static const char * const gsbi5_spi_cs1_groups[] = {
	"gpio6", "gpio61",
};

static const char * const gsbi5_spi_cs2_groups[] = {
	"gpio7", "gpio62",
};

static const char * const gsbi5_spi_cs3_groups[] = {
	"gpio2",
};

static const char * const gsbi6_groups[] = {
	"gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
	"gpio57", "gpio58",
};

static const char * const gsbi7_groups[] = {
	"gpio6", "gpio7", "gpio8", "gpio9",
};

static const char * const nss_spi_groups[] = {
	"gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
	"gpio57", "gpio58",
};

static const char * const sdc1_groups[] = {
	"gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
	"gpio44", "gpio45", "gpio46", "gpio47",
};

static const char * const spdif_groups[] = {
	"gpio10", "gpio48",
};

static const char * const nand_groups[] = {
	"gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
	"gpio46", "gpio47",
};

static const char * const tsif1_groups[] = {
	"gpio55", "gpio56", "gpio57", "gpio58",
};

static const char * const tsif2_groups[] = {
	"gpio59", "gpio60", "gpio61", "gpio62",
};

static const char * const usb_fs_n_groups[] = {
	"gpio6",
};

static const char * const usb_fs_groups[] = {
	"gpio6", "gpio7", "gpio8",
};

static const char * const usb2_hsic_groups[] = {
	"gpio67", "gpio68",
};

static const char * const rgmii2_groups[] = {
	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
};

static const char * const sata_groups[] = {
	"gpio10",
};

static const char * const pcie1_rst_groups[] = {
	"gpio3",
};

static const char * const pcie1_prsnt_groups[] = {
	"gpio3", "gpio11",
};

static const char * const pcie1_pwren_n_groups[] = {
	"gpio4", "gpio12",
};

static const char * const pcie1_pwren_groups[] = {
	"gpio4", "gpio12",
};

static const char * const pcie1_pwrflt_groups[] = {
	"gpio5", "gpio13",
};

static const char * const pcie1_clk_req_groups[] = {
	"gpio5",
};

static const char * const pcie2_rst_groups[] = {
	"gpio48",
};

static const char * const pcie2_prsnt_groups[] = {
	"gpio11", "gpio48",
};

static const char * const pcie2_pwren_n_groups[] = {
	"gpio12", "gpio49",
};

static const char * const pcie2_pwren_groups[] = {
	"gpio12", "gpio49",
};

static const char * const pcie2_pwrflt_groups[] = {
	"gpio13", "gpio50",
};

static const char * const pcie2_clk_req_groups[] = {
	"gpio50",
};

static const char * const pcie3_rst_groups[] = {
	"gpio63",
};

static const char * const pcie3_prsnt_groups[] = {
	"gpio11",
};

static const char * const pcie3_pwren_n_groups[] = {
	"gpio12",
};

static const char * const pcie3_pwren_groups[] = {
	"gpio12",
};

static const char * const pcie3_pwrflt_groups[] = {
	"gpio13",
};

static const char * const pcie3_clk_req_groups[] = {
	"gpio65",
};

static const char * const ps_hold_groups[] = {
	"gpio26",
};

static const struct msm_function ipq8064_functions[] = {
	FUNCTION(gpio),
	FUNCTION(mdio),
	FUNCTION(ssbi),
	FUNCTION(spmi),
	FUNCTION(mi2s),
	FUNCTION(pdm),
	FUNCTION(audio_pcm),
	FUNCTION(gsbi1),
	FUNCTION(gsbi2),
	FUNCTION(gsbi4),
	FUNCTION(gsbi5),
	FUNCTION(gsbi5_spi_cs1),
	FUNCTION(gsbi5_spi_cs2),
	FUNCTION(gsbi5_spi_cs3),
	FUNCTION(gsbi6),
	FUNCTION(gsbi7),
	FUNCTION(nss_spi),
	FUNCTION(sdc1),
	FUNCTION(spdif),
	FUNCTION(nand),
	FUNCTION(tsif1),
	FUNCTION(tsif2),
	FUNCTION(usb_fs_n),
	FUNCTION(usb_fs),
	FUNCTION(usb2_hsic),
	FUNCTION(rgmii2),
	FUNCTION(sata),
	FUNCTION(pcie1_rst),
	FUNCTION(pcie1_prsnt),
	FUNCTION(pcie1_pwren_n),
	FUNCTION(pcie1_pwren),
	FUNCTION(pcie1_pwrflt),
	FUNCTION(pcie1_clk_req),
	FUNCTION(pcie2_rst),
	FUNCTION(pcie2_prsnt),
	FUNCTION(pcie2_pwren_n),
	FUNCTION(pcie2_pwren),
	FUNCTION(pcie2_pwrflt),
	FUNCTION(pcie2_clk_req),
	FUNCTION(pcie3_rst),
	FUNCTION(pcie3_prsnt),
	FUNCTION(pcie3_pwren_n),
	FUNCTION(pcie3_pwren),
	FUNCTION(pcie3_pwrflt),
	FUNCTION(pcie3_clk_req),
	FUNCTION(ps_hold),
};

static const struct msm_pingroup ipq8064_groups[] = {
	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
	PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
	PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
	PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
	PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
	PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
	PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
	PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
	PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
	PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
	PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
	SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
	SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
};

#define NUM_GPIO_PINGROUPS 69

static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
	.pins = ipq8064_pins,
	.npins = ARRAY_SIZE(ipq8064_pins),
	.functions = ipq8064_functions,
	.nfunctions = ARRAY_SIZE(ipq8064_functions),
	.groups = ipq8064_groups,
	.ngroups = ARRAY_SIZE(ipq8064_groups),
	.ngpios = NUM_GPIO_PINGROUPS,
};

static int ipq8064_pinctrl_probe(struct platform_device *pdev)
{
	return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
}

static const struct of_device_id ipq8064_pinctrl_of_match[] = {
	{ .compatible = "qcom,ipq8064-pinctrl", },
	{ },
};

static struct platform_driver ipq8064_pinctrl_driver = {
	.driver = {
		.name = "ipq8064-pinctrl",
		.of_match_table = ipq8064_pinctrl_of_match,
	},
	.probe = ipq8064_pinctrl_probe,
	.remove = msm_pinctrl_remove,
};

static int __init ipq8064_pinctrl_init(void)
{
	return platform_driver_register(&ipq8064_pinctrl_driver);
}
arch_initcall(ipq8064_pinctrl_init);

static void __exit ipq8064_pinctrl_exit(void)
{
	platform_driver_unregister(&ipq8064_pinctrl_driver);
}
module_exit(ipq8064_pinctrl_exit);

MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
MODULE_LICENSE("GPL v2");
MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
b4da6573 AG	2	/*
b4da6573 AG	3	* Copyright (c) 2014, The Linux Foundation. All rights reserved.
b4da6573 AG	4	*/
	5
	6	#include <linux/module.h>
	7	#include <linux/of.h>
	8	#include <linux/platform_device.h>
	9	#include <linux/pinctrl/pinctrl.h>
	10
	11	#include "pinctrl-msm.h"
	12
	13	static const struct pinctrl_pin_desc ipq8064_pins[] = {
2aa02733	14	PINCTRL_PIN(0, "GPIO_0"),
b4da6573 AG	15	PINCTRL_PIN(1, "GPIO_1"),
	16	PINCTRL_PIN(2, "GPIO_2"),
	17	PINCTRL_PIN(3, "GPIO_3"),
	18	PINCTRL_PIN(4, "GPIO_4"),
	19	PINCTRL_PIN(5, "GPIO_5"),
	20	PINCTRL_PIN(6, "GPIO_6"),
	21	PINCTRL_PIN(7, "GPIO_7"),
	22	PINCTRL_PIN(8, "GPIO_8"),
	23	PINCTRL_PIN(9, "GPIO_9"),
	24	PINCTRL_PIN(10, "GPIO_10"),
	25	PINCTRL_PIN(11, "GPIO_11"),
	26	PINCTRL_PIN(12, "GPIO_12"),
	27	PINCTRL_PIN(13, "GPIO_13"),
	28	PINCTRL_PIN(14, "GPIO_14"),
	29	PINCTRL_PIN(15, "GPIO_15"),
	30	PINCTRL_PIN(16, "GPIO_16"),
	31	PINCTRL_PIN(17, "GPIO_17"),
	32	PINCTRL_PIN(18, "GPIO_18"),
	33	PINCTRL_PIN(19, "GPIO_19"),
	34	PINCTRL_PIN(20, "GPIO_20"),
	35	PINCTRL_PIN(21, "GPIO_21"),
	36	PINCTRL_PIN(22, "GPIO_22"),
	37	PINCTRL_PIN(23, "GPIO_23"),
	38	PINCTRL_PIN(24, "GPIO_24"),
	39	PINCTRL_PIN(25, "GPIO_25"),
	40	PINCTRL_PIN(26, "GPIO_26"),
	41	PINCTRL_PIN(27, "GPIO_27"),
	42	PINCTRL_PIN(28, "GPIO_28"),
	43	PINCTRL_PIN(29, "GPIO_29"),
	44	PINCTRL_PIN(30, "GPIO_30"),
	45	PINCTRL_PIN(31, "GPIO_31"),
	46	PINCTRL_PIN(32, "GPIO_32"),
	47	PINCTRL_PIN(33, "GPIO_33"),
	48	PINCTRL_PIN(34, "GPIO_34"),
	49	PINCTRL_PIN(35, "GPIO_35"),
	50	PINCTRL_PIN(36, "GPIO_36"),
	51	PINCTRL_PIN(37, "GPIO_37"),
	52	PINCTRL_PIN(38, "GPIO_38"),
	53	PINCTRL_PIN(39, "GPIO_39"),
	54	PINCTRL_PIN(40, "GPIO_40"),
	55	PINCTRL_PIN(41, "GPIO_41"),
	56	PINCTRL_PIN(42, "GPIO_42"),
	57	PINCTRL_PIN(43, "GPIO_43"),
	58	PINCTRL_PIN(44, "GPIO_44"),
	59	PINCTRL_PIN(45, "GPIO_45"),
	60	PINCTRL_PIN(46, "GPIO_46"),
	61	PINCTRL_PIN(47, "GPIO_47"),
	62	PINCTRL_PIN(48, "GPIO_48"),
	63	PINCTRL_PIN(49, "GPIO_49"),
	64	PINCTRL_PIN(50, "GPIO_50"),
	65	PINCTRL_PIN(51, "GPIO_51"),
	66	PINCTRL_PIN(52, "GPIO_52"),
	67	PINCTRL_PIN(53, "GPIO_53"),
	68	PINCTRL_PIN(54, "GPIO_54"),
	69	PINCTRL_PIN(55, "GPIO_55"),
	70	PINCTRL_PIN(56, "GPIO_56"),
	71	PINCTRL_PIN(57, "GPIO_57"),
	72	PINCTRL_PIN(58, "GPIO_58"),
	73	PINCTRL_PIN(59, "GPIO_59"),
	74	PINCTRL_PIN(60, "GPIO_60"),
	75	PINCTRL_PIN(61, "GPIO_61"),
	76	PINCTRL_PIN(62, "GPIO_62"),
	77	PINCTRL_PIN(63, "GPIO_63"),
	78	PINCTRL_PIN(64, "GPIO_64"),
79	PINCTRL_PIN(65, "GPIO_65"),
80	PINCTRL_PIN(66, "GPIO_66"),
81	PINCTRL_PIN(67, "GPIO_67"),
82	PINCTRL_PIN(68, "GPIO_68"),
83
84	PINCTRL_PIN(69, "SDC3_CLK"),
85	PINCTRL_PIN(70, "SDC3_CMD"),
86	PINCTRL_PIN(71, "SDC3_DATA"),
87	};
88
89	#define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
90	DECLARE_IPQ_GPIO_PINS(0);
91	DECLARE_IPQ_GPIO_PINS(1);
92	DECLARE_IPQ_GPIO_PINS(2);
93	DECLARE_IPQ_GPIO_PINS(3);
94	DECLARE_IPQ_GPIO_PINS(4);
95	DECLARE_IPQ_GPIO_PINS(5);
96	DECLARE_IPQ_GPIO_PINS(6);
97	DECLARE_IPQ_GPIO_PINS(7);
98	DECLARE_IPQ_GPIO_PINS(8);
99	DECLARE_IPQ_GPIO_PINS(9);
100	DECLARE_IPQ_GPIO_PINS(10);
101	DECLARE_IPQ_GPIO_PINS(11);
102	DECLARE_IPQ_GPIO_PINS(12);
103	DECLARE_IPQ_GPIO_PINS(13);
104	DECLARE_IPQ_GPIO_PINS(14);
105	DECLARE_IPQ_GPIO_PINS(15);
106	DECLARE_IPQ_GPIO_PINS(16);
107	DECLARE_IPQ_GPIO_PINS(17);
108	DECLARE_IPQ_GPIO_PINS(18);
109	DECLARE_IPQ_GPIO_PINS(19);
110	DECLARE_IPQ_GPIO_PINS(20);
111	DECLARE_IPQ_GPIO_PINS(21);
112	DECLARE_IPQ_GPIO_PINS(22);
113	DECLARE_IPQ_GPIO_PINS(23);
114	DECLARE_IPQ_GPIO_PINS(24);
115	DECLARE_IPQ_GPIO_PINS(25);
116	DECLARE_IPQ_GPIO_PINS(26);
117	DECLARE_IPQ_GPIO_PINS(27);
118	DECLARE_IPQ_GPIO_PINS(28);
119	DECLARE_IPQ_GPIO_PINS(29);
120	DECLARE_IPQ_GPIO_PINS(30);
121	DECLARE_IPQ_GPIO_PINS(31);
122	DECLARE_IPQ_GPIO_PINS(32);
123	DECLARE_IPQ_GPIO_PINS(33);
124	DECLARE_IPQ_GPIO_PINS(34);
125	DECLARE_IPQ_GPIO_PINS(35);
126	DECLARE_IPQ_GPIO_PINS(36);
127	DECLARE_IPQ_GPIO_PINS(37);
128	DECLARE_IPQ_GPIO_PINS(38);
129	DECLARE_IPQ_GPIO_PINS(39);
130	DECLARE_IPQ_GPIO_PINS(40);
131	DECLARE_IPQ_GPIO_PINS(41);
132	DECLARE_IPQ_GPIO_PINS(42);
133	DECLARE_IPQ_GPIO_PINS(43);
134	DECLARE_IPQ_GPIO_PINS(44);
135	DECLARE_IPQ_GPIO_PINS(45);
136	DECLARE_IPQ_GPIO_PINS(46);
137	DECLARE_IPQ_GPIO_PINS(47);
138	DECLARE_IPQ_GPIO_PINS(48);
139	DECLARE_IPQ_GPIO_PINS(49);
140	DECLARE_IPQ_GPIO_PINS(50);
141	DECLARE_IPQ_GPIO_PINS(51);
142	DECLARE_IPQ_GPIO_PINS(52);
143	DECLARE_IPQ_GPIO_PINS(53);
144	DECLARE_IPQ_GPIO_PINS(54);
145	DECLARE_IPQ_GPIO_PINS(55);
146	DECLARE_IPQ_GPIO_PINS(56);
147	DECLARE_IPQ_GPIO_PINS(57);
148	DECLARE_IPQ_GPIO_PINS(58);
149	DECLARE_IPQ_GPIO_PINS(59);
150	DECLARE_IPQ_GPIO_PINS(60);
151	DECLARE_IPQ_GPIO_PINS(61);
152	DECLARE_IPQ_GPIO_PINS(62);
153	DECLARE_IPQ_GPIO_PINS(63);
154	DECLARE_IPQ_GPIO_PINS(64);
155	DECLARE_IPQ_GPIO_PINS(65);
156	DECLARE_IPQ_GPIO_PINS(66);
157	DECLARE_IPQ_GPIO_PINS(67);
158	DECLARE_IPQ_GPIO_PINS(68);
159
160	static const unsigned int sdc3_clk_pins[] = { 69 };
161	static const unsigned int sdc3_cmd_pins[] = { 70 };
162	static const unsigned int sdc3_data_pins[] = { 71 };
163
164	#define FUNCTION(fname) \
165	[IPQ_MUX_##fname] = { \
166	.name = #fname, \
167	.groups = fname##_groups, \
168	.ngroups = ARRAY_SIZE(fname##_groups), \
169	}
170
171	#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
172	{ \
173	.name = "gpio" #id, \
174	.pins = gpio##id##_pins, \
175	.npins = ARRAY_SIZE(gpio##id##_pins), \
176	.funcs = (int[]){ \
144ef626	177	IPQ_MUX_gpio, \
b4da6573 AG	178	IPQ_MUX_##f1, \
	179	IPQ_MUX_##f2, \
	180	IPQ_MUX_##f3, \
	181	IPQ_MUX_##f4, \
	182	IPQ_MUX_##f5, \
	183	IPQ_MUX_##f6, \
	184	IPQ_MUX_##f7, \
	185	IPQ_MUX_##f8, \
	186	IPQ_MUX_##f9, \
	187	IPQ_MUX_##f10, \
	188	}, \
	189	.nfuncs = 11, \
	190	.ctl_reg = 0x1000 + 0x10 * id, \
	191	.io_reg = 0x1004 + 0x10 * id, \
	192	.intr_cfg_reg = 0x1008 + 0x10 * id, \
	193	.intr_status_reg = 0x100c + 0x10 * id, \
	194	.intr_target_reg = 0x400 + 0x4 * id, \
	195	.mux_bit = 2, \
	196	.pull_bit = 0, \
	197	.drv_bit = 6, \
	198	.oe_bit = 9, \
	199	.in_bit = 0, \
	200	.out_bit = 1, \
	201	.intr_enable_bit = 0, \
	202	.intr_status_bit = 0, \
	203	.intr_ack_high = 1, \
	204	.intr_target_bit = 0, \
f712c554	205	.intr_target_kpss_val = 4, \
b4da6573 AG	206	.intr_raw_status_bit = 3, \
	207	.intr_polarity_bit = 1, \
	208	.intr_detection_bit = 2, \
	209	.intr_detection_width = 1, \
	210	}
	211
	212	#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
	213	{ \
	214	.name = #pg_name, \
	215	.pins = pg_name##_pins, \
	216	.npins = ARRAY_SIZE(pg_name##_pins), \
	217	.ctl_reg = ctl, \
	218	.io_reg = 0, \
	219	.intr_cfg_reg = 0, \
	220	.intr_status_reg = 0, \
	221	.intr_target_reg = 0, \
	222	.mux_bit = -1, \
	223	.pull_bit = pull, \
	224	.drv_bit = drv, \
	225	.oe_bit = -1, \
	226	.in_bit = -1, \
	227	.out_bit = -1, \
	228	.intr_enable_bit = -1, \
	229	.intr_status_bit = -1, \
	230	.intr_target_bit = -1, \
f712c554	231	.intr_target_kpss_val = -1, \
b4da6573 AG	232	.intr_raw_status_bit = -1, \
	233	.intr_polarity_bit = -1, \
	234	.intr_detection_bit = -1, \
	235	.intr_detection_width = -1, \
	236	}
	237
	238	enum ipq8064_functions {
144ef626	239	IPQ_MUX_gpio,
b4da6573 AG	240	IPQ_MUX_mdio,
	241	IPQ_MUX_mi2s,
	242	IPQ_MUX_pdm,
	243	IPQ_MUX_ssbi,
	244	IPQ_MUX_spmi,
	245	IPQ_MUX_audio_pcm,
	246	IPQ_MUX_gsbi1,
	247	IPQ_MUX_gsbi2,
	248	IPQ_MUX_gsbi4,
	249	IPQ_MUX_gsbi5,
	250	IPQ_MUX_gsbi5_spi_cs1,
	251	IPQ_MUX_gsbi5_spi_cs2,
	252	IPQ_MUX_gsbi5_spi_cs3,
	253	IPQ_MUX_gsbi6,
	254	IPQ_MUX_gsbi7,
	255	IPQ_MUX_nss_spi,
	256	IPQ_MUX_sdc1,
	257	IPQ_MUX_spdif,
	258	IPQ_MUX_nand,
	259	IPQ_MUX_tsif1,
	260	IPQ_MUX_tsif2,
	261	IPQ_MUX_usb_fs_n,
	262	IPQ_MUX_usb_fs,
	263	IPQ_MUX_usb2_hsic,
	264	IPQ_MUX_rgmii2,
	265	IPQ_MUX_sata,
	266	IPQ_MUX_pcie1_rst,
	267	IPQ_MUX_pcie1_prsnt,
	268	IPQ_MUX_pcie1_pwrflt,
	269	IPQ_MUX_pcie1_pwren_n,
	270	IPQ_MUX_pcie1_pwren,
	271	IPQ_MUX_pcie1_clk_req,
	272	IPQ_MUX_pcie2_rst,
	273	IPQ_MUX_pcie2_prsnt,
	274	IPQ_MUX_pcie2_pwrflt,
	275	IPQ_MUX_pcie2_pwren_n,
	276	IPQ_MUX_pcie2_pwren,
	277	IPQ_MUX_pcie2_clk_req,
	278	IPQ_MUX_pcie3_rst,
	279	IPQ_MUX_pcie3_prsnt,
	280	IPQ_MUX_pcie3_pwrflt,
	281	IPQ_MUX_pcie3_pwren_n,
	282	IPQ_MUX_pcie3_pwren,
	283	IPQ_MUX_pcie3_clk_req,
	284	IPQ_MUX_ps_hold,
	285	IPQ_MUX_NA,
	286	};
	287
144ef626 BA	288	static const char * const gpio_groups[] = {
	289	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
	290	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
	291	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
	292	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
	293	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
	294	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
	295	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
	296	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
	297	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
	298	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
	299	};
	300
b4da6573 AG	301	static const char * const mdio_groups[] = {
	302	"gpio0", "gpio1", "gpio10", "gpio11",
	303	};
	304
	305	static const char * const mi2s_groups[] = {
	306	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
	307	"gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
	308	};
	309
	310	static const char * const pdm_groups[] = {
	311	"gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
	312	"gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
	313	"gpio59",
	314	};
	315
	316	static const char * const ssbi_groups[] = {
	317	"gpio10", "gpio11",
	318	};
	319
	320	static const char * const spmi_groups[] = {
	321	"gpio10", "gpio11",
	322	};
	323
	324	static const char * const audio_pcm_groups[] = {
	325	"gpio14", "gpio15", "gpio16", "gpio17",
	326	};
	327
	328	static const char * const gsbi1_groups[] = {
	329	"gpio51", "gpio52", "gpio53", "gpio54",
	330	};
	331
	332	static const char * const gsbi2_groups[] = {
	333	"gpio22", "gpio23", "gpio24", "gpio25",
	334	};
	335
	336	static const char * const gsbi4_groups[] = {
	337	"gpio10", "gpio11", "gpio12", "gpio13",
	338	};
	339
	340	static const char * const gsbi5_groups[] = {
	341	"gpio18", "gpio19", "gpio20", "gpio21",
	342	};
	343
	344	static const char * const gsbi5_spi_cs1_groups[] = {
	345	"gpio6", "gpio61",
	346	};
	347
	348	static const char * const gsbi5_spi_cs2_groups[] = {
	349	"gpio7", "gpio62",
	350	};
	351
	352	static const char * const gsbi5_spi_cs3_groups[] = {
	353	"gpio2",
	354	};
	355
	356	static const char * const gsbi6_groups[] = {
	357	"gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
	358	"gpio57", "gpio58",
	359	};
	360
	361	static const char * const gsbi7_groups[] = {
	362	"gpio6", "gpio7", "gpio8", "gpio9",
	363	};
	364
365	static const char * const nss_spi_groups[] = {
366	"gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
367	"gpio57", "gpio58",
368	};
369
370	static const char * const sdc1_groups[] = {
371	"gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
372	"gpio44", "gpio45", "gpio46", "gpio47",
373	};
374
375	static const char * const spdif_groups[] = {
888bb3f9	376	"gpio10", "gpio48",
b4da6573 AG	377	};
	378
	379	static const char * const nand_groups[] = {
	380	"gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
	381	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
	382	"gpio46", "gpio47",
	383	};
	384
	385	static const char * const tsif1_groups[] = {
	386	"gpio55", "gpio56", "gpio57", "gpio58",
	387	};
	388
	389	static const char * const tsif2_groups[] = {
	390	"gpio59", "gpio60", "gpio61", "gpio62",
	391	};
	392
	393	static const char * const usb_fs_n_groups[] = {
	394	"gpio6",
	395	};
	396
	397	static const char * const usb_fs_groups[] = {
	398	"gpio6", "gpio7", "gpio8",
	399	};
	400
	401	static const char * const usb2_hsic_groups[] = {
	402	"gpio67", "gpio68",
	403	};
	404
	405	static const char * const rgmii2_groups[] = {
	406	"gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
	407	"gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62",
	408	};
	409
	410	static const char * const sata_groups[] = {
	411	"gpio10",
	412	};
	413
	414	static const char * const pcie1_rst_groups[] = {
	415	"gpio3",
	416	};
	417
	418	static const char * const pcie1_prsnt_groups[] = {
	419	"gpio3", "gpio11",
	420	};
	421
	422	static const char * const pcie1_pwren_n_groups[] = {
	423	"gpio4", "gpio12",
	424	};
	425
	426	static const char * const pcie1_pwren_groups[] = {
	427	"gpio4", "gpio12",
	428	};
	429
	430	static const char * const pcie1_pwrflt_groups[] = {
	431	"gpio5", "gpio13",
	432	};
	433
	434	static const char * const pcie1_clk_req_groups[] = {
	435	"gpio5",
	436	};
	437
	438	static const char * const pcie2_rst_groups[] = {
	439	"gpio48",
	440	};
441
442	static const char * const pcie2_prsnt_groups[] = {
443	"gpio11", "gpio48",
444	};
445
446	static const char * const pcie2_pwren_n_groups[] = {
447	"gpio12", "gpio49",
448	};
449
450	static const char * const pcie2_pwren_groups[] = {
451	"gpio12", "gpio49",
452	};
453
454	static const char * const pcie2_pwrflt_groups[] = {
455	"gpio13", "gpio50",
456	};
457
458	static const char * const pcie2_clk_req_groups[] = {
459	"gpio50",
460	};
461
462	static const char * const pcie3_rst_groups[] = {
463	"gpio63",
464	};
465
466	static const char * const pcie3_prsnt_groups[] = {
467	"gpio11",
468	};
469
470	static const char * const pcie3_pwren_n_groups[] = {
471	"gpio12",
472	};
473
474	static const char * const pcie3_pwren_groups[] = {
475	"gpio12",
476	};
477
478	static const char * const pcie3_pwrflt_groups[] = {
479	"gpio13",
480	};
481
482	static const char * const pcie3_clk_req_groups[] = {
483	"gpio65",
484	};
485
486	static const char * const ps_hold_groups[] = {
487	"gpio26",
488	};
489
490	static const struct msm_function ipq8064_functions[] = {
144ef626	491	FUNCTION(gpio),
b4da6573 AG	492	FUNCTION(mdio),
	493	FUNCTION(ssbi),
	494	FUNCTION(spmi),
	495	FUNCTION(mi2s),
	496	FUNCTION(pdm),
	497	FUNCTION(audio_pcm),
	498	FUNCTION(gsbi1),
	499	FUNCTION(gsbi2),
	500	FUNCTION(gsbi4),
	501	FUNCTION(gsbi5),
	502	FUNCTION(gsbi5_spi_cs1),
	503	FUNCTION(gsbi5_spi_cs2),
	504	FUNCTION(gsbi5_spi_cs3),
	505	FUNCTION(gsbi6),
	506	FUNCTION(gsbi7),
	507	FUNCTION(nss_spi),
	508	FUNCTION(sdc1),
	509	FUNCTION(spdif),
	510	FUNCTION(nand),
	511	FUNCTION(tsif1),
	512	FUNCTION(tsif2),
	513	FUNCTION(usb_fs_n),
	514	FUNCTION(usb_fs),
	515	FUNCTION(usb2_hsic),
	516	FUNCTION(rgmii2),
	517	FUNCTION(sata),
	518	FUNCTION(pcie1_rst),
	519	FUNCTION(pcie1_prsnt),
	520	FUNCTION(pcie1_pwren_n),
	521	FUNCTION(pcie1_pwren),
	522	FUNCTION(pcie1_pwrflt),
	523	FUNCTION(pcie1_clk_req),
	524	FUNCTION(pcie2_rst),
	525	FUNCTION(pcie2_prsnt),
	526	FUNCTION(pcie2_pwren_n),
	527	FUNCTION(pcie2_pwren),
	528	FUNCTION(pcie2_pwrflt),
	529	FUNCTION(pcie2_clk_req),
	530	FUNCTION(pcie3_rst),
	531	FUNCTION(pcie3_prsnt),
	532	FUNCTION(pcie3_pwren_n),
	533	FUNCTION(pcie3_pwren),
	534	FUNCTION(pcie3_pwrflt),
	535	FUNCTION(pcie3_clk_req),
	536	FUNCTION(ps_hold),
	537	};
	538
	539	static const struct msm_pingroup ipq8064_groups[] = {
	540	PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	541	PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	542	PINGROUP(2, gsbi5_spi_cs3, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	543	PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
	544	PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
	545	PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
	546	PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
	547	PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
	548	PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
	549	PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
	550	PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
	551	PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
	552	PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
	553	PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
	554	PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
	555	PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
556	PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
557	PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
558	PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
559	PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
560	PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
561	PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
562	PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
563	PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
564	PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
565	PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
566	PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
567	PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
568	PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
569	PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
570	PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
571	PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
572	PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
573	PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
574	PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
575	PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
576	PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
577	PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
578	PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
579	PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
580	PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
581	PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
582	PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
583	PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
584	PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
585	PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
586	PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
587	PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
588	PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
589	PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
590	PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
591	PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
592	PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
593	PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
594	PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
595	PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
596	PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
597	PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
598	PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
599	PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
600	PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
601	PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
602	PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
603	PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
604	PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
605	PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
606	PINGROUP(66, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
607	PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
608	PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
609	SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
610	SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
611	SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
612	};
613
614	#define NUM_GPIO_PINGROUPS 69
615
616	static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
617	.pins = ipq8064_pins,
618	.npins = ARRAY_SIZE(ipq8064_pins),
619	.functions = ipq8064_functions,
620	.nfunctions = ARRAY_SIZE(ipq8064_functions),
621	.groups = ipq8064_groups,
622	.ngroups = ARRAY_SIZE(ipq8064_groups),
623	.ngpios = NUM_GPIO_PINGROUPS,
624	};
625
626	static int ipq8064_pinctrl_probe(struct platform_device *pdev)
627	{
628	return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
629	}
630
631	static const struct of_device_id ipq8064_pinctrl_of_match[] = {
632	{ .compatible = "qcom,ipq8064-pinctrl", },
633	{ },
634	};
635
636	static struct platform_driver ipq8064_pinctrl_driver = {
637	.driver = {
638	.name = "ipq8064-pinctrl",
b4da6573 AG	639	.of_match_table = ipq8064_pinctrl_of_match,
	640	},
	641	.probe = ipq8064_pinctrl_probe,
	642	.remove = msm_pinctrl_remove,
	643	};
	644
	645	static int __init ipq8064_pinctrl_init(void)
	646	{
	647	return platform_driver_register(&ipq8064_pinctrl_driver);
	648	}
	649	arch_initcall(ipq8064_pinctrl_init);
	650
	651	static void __exit ipq8064_pinctrl_exit(void)
	652	{
	653	platform_driver_unregister(&ipq8064_pinctrl_driver);
	654	}
	655	module_exit(ipq8064_pinctrl_exit);
	656
	657	MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
	658	MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
	659	MODULE_LICENSE("GPL v2");
	660	MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);