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f365be09 BA |
1 | /* |
2 | * Copyright (c) 2013, Sony Mobile Communications AB. | |
3 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 and | |
7 | * only version 2 as published by the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | */ | |
14 | ||
32745581 | 15 | #include <linux/delay.h> |
f365be09 | 16 | #include <linux/err.h> |
f365be09 BA |
17 | #include <linux/io.h> |
18 | #include <linux/module.h> | |
19 | #include <linux/of.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/pinctrl/machine.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/pinctrl/pinconf.h> | |
25 | #include <linux/pinctrl/pinconf-generic.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/gpio.h> | |
28 | #include <linux/interrupt.h> | |
f365be09 BA |
29 | #include <linux/spinlock.h> |
30 | ||
32745581 PG |
31 | #include <asm/system_misc.h> |
32 | ||
69b78b8d LW |
33 | #include "../core.h" |
34 | #include "../pinconf.h" | |
f365be09 | 35 | #include "pinctrl-msm.h" |
69b78b8d | 36 | #include "../pinctrl-utils.h" |
f365be09 | 37 | |
408e3c66 | 38 | #define MAX_NR_GPIO 300 |
32745581 | 39 | #define PS_HOLD_OFFSET 0x820 |
408e3c66 | 40 | |
f365be09 BA |
41 | /** |
42 | * struct msm_pinctrl - state for a pinctrl-msm device | |
43 | * @dev: device handle. | |
44 | * @pctrl: pinctrl handle. | |
f365be09 BA |
45 | * @chip: gpiochip handle. |
46 | * @irq: parent irq for the TLMM irq_chip. | |
47 | * @lock: Spinlock to protect register resources as well | |
48 | * as msm_pinctrl data structures. | |
49 | * @enabled_irqs: Bitmap of currently enabled irqs. | |
50 | * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge | |
51 | * detection. | |
f365be09 BA |
52 | * @soc; Reference to soc_data of platform specific data. |
53 | * @regs: Base address for the TLMM register map. | |
54 | */ | |
55 | struct msm_pinctrl { | |
56 | struct device *dev; | |
57 | struct pinctrl_dev *pctrl; | |
f365be09 | 58 | struct gpio_chip chip; |
f393e489 | 59 | int irq; |
f365be09 BA |
60 | |
61 | spinlock_t lock; | |
62 | ||
408e3c66 BA |
63 | DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO); |
64 | DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO); | |
f365be09 BA |
65 | |
66 | const struct msm_pinctrl_soc_data *soc; | |
67 | void __iomem *regs; | |
68 | }; | |
69 | ||
cdcb0ab6 LW |
70 | static inline struct msm_pinctrl *to_msm_pinctrl(struct gpio_chip *gc) |
71 | { | |
72 | return container_of(gc, struct msm_pinctrl, chip); | |
73 | } | |
74 | ||
f365be09 BA |
75 | static int msm_get_groups_count(struct pinctrl_dev *pctldev) |
76 | { | |
77 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
78 | ||
79 | return pctrl->soc->ngroups; | |
80 | } | |
81 | ||
82 | static const char *msm_get_group_name(struct pinctrl_dev *pctldev, | |
83 | unsigned group) | |
84 | { | |
85 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
86 | ||
87 | return pctrl->soc->groups[group].name; | |
88 | } | |
89 | ||
90 | static int msm_get_group_pins(struct pinctrl_dev *pctldev, | |
91 | unsigned group, | |
92 | const unsigned **pins, | |
93 | unsigned *num_pins) | |
94 | { | |
95 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
96 | ||
97 | *pins = pctrl->soc->groups[group].pins; | |
98 | *num_pins = pctrl->soc->groups[group].npins; | |
99 | return 0; | |
100 | } | |
101 | ||
1f2b2398 | 102 | static const struct pinctrl_ops msm_pinctrl_ops = { |
f365be09 BA |
103 | .get_groups_count = msm_get_groups_count, |
104 | .get_group_name = msm_get_group_name, | |
105 | .get_group_pins = msm_get_group_pins, | |
106 | .dt_node_to_map = pinconf_generic_dt_node_to_map_group, | |
107 | .dt_free_map = pinctrl_utils_dt_free_map, | |
108 | }; | |
109 | ||
110 | static int msm_get_functions_count(struct pinctrl_dev *pctldev) | |
111 | { | |
112 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
113 | ||
114 | return pctrl->soc->nfunctions; | |
115 | } | |
116 | ||
117 | static const char *msm_get_function_name(struct pinctrl_dev *pctldev, | |
118 | unsigned function) | |
119 | { | |
120 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
121 | ||
122 | return pctrl->soc->functions[function].name; | |
123 | } | |
124 | ||
125 | static int msm_get_function_groups(struct pinctrl_dev *pctldev, | |
126 | unsigned function, | |
127 | const char * const **groups, | |
128 | unsigned * const num_groups) | |
129 | { | |
130 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
131 | ||
132 | *groups = pctrl->soc->functions[function].groups; | |
133 | *num_groups = pctrl->soc->functions[function].ngroups; | |
134 | return 0; | |
135 | } | |
136 | ||
137 | static int msm_pinmux_enable(struct pinctrl_dev *pctldev, | |
138 | unsigned function, | |
139 | unsigned group) | |
140 | { | |
141 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
142 | const struct msm_pingroup *g; | |
143 | unsigned long flags; | |
144 | u32 val; | |
145 | int i; | |
146 | ||
147 | g = &pctrl->soc->groups[group]; | |
148 | ||
3c25381f | 149 | for (i = 0; i < g->nfuncs; i++) { |
f365be09 BA |
150 | if (g->funcs[i] == function) |
151 | break; | |
152 | } | |
153 | ||
3c25381f | 154 | if (WARN_ON(i == g->nfuncs)) |
f365be09 BA |
155 | return -EINVAL; |
156 | ||
157 | spin_lock_irqsave(&pctrl->lock, flags); | |
158 | ||
159 | val = readl(pctrl->regs + g->ctl_reg); | |
160 | val &= ~(0x7 << g->mux_bit); | |
161 | val |= i << g->mux_bit; | |
162 | writel(val, pctrl->regs + g->ctl_reg); | |
163 | ||
164 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
165 | ||
166 | return 0; | |
167 | } | |
168 | ||
1f2b2398 | 169 | static const struct pinmux_ops msm_pinmux_ops = { |
f365be09 BA |
170 | .get_functions_count = msm_get_functions_count, |
171 | .get_function_name = msm_get_function_name, | |
172 | .get_function_groups = msm_get_function_groups, | |
173 | .enable = msm_pinmux_enable, | |
f365be09 BA |
174 | }; |
175 | ||
176 | static int msm_config_reg(struct msm_pinctrl *pctrl, | |
177 | const struct msm_pingroup *g, | |
178 | unsigned param, | |
f365be09 BA |
179 | unsigned *mask, |
180 | unsigned *bit) | |
181 | { | |
182 | switch (param) { | |
183 | case PIN_CONFIG_BIAS_DISABLE: | |
f365be09 | 184 | case PIN_CONFIG_BIAS_PULL_DOWN: |
b831a15e | 185 | case PIN_CONFIG_BIAS_BUS_HOLD: |
f365be09 | 186 | case PIN_CONFIG_BIAS_PULL_UP: |
f365be09 BA |
187 | *bit = g->pull_bit; |
188 | *mask = 3; | |
189 | break; | |
190 | case PIN_CONFIG_DRIVE_STRENGTH: | |
f365be09 BA |
191 | *bit = g->drv_bit; |
192 | *mask = 7; | |
193 | break; | |
ed118a5f | 194 | case PIN_CONFIG_OUTPUT: |
ed118a5f BA |
195 | *bit = g->oe_bit; |
196 | *mask = 1; | |
197 | break; | |
f365be09 BA |
198 | default: |
199 | dev_err(pctrl->dev, "Invalid config param %04x\n", param); | |
200 | return -ENOTSUPP; | |
201 | } | |
202 | ||
f365be09 BA |
203 | return 0; |
204 | } | |
205 | ||
206 | static int msm_config_get(struct pinctrl_dev *pctldev, | |
207 | unsigned int pin, | |
208 | unsigned long *config) | |
209 | { | |
210 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
211 | return -ENOTSUPP; | |
212 | } | |
213 | ||
214 | static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin, | |
215 | unsigned long *configs, unsigned num_configs) | |
216 | { | |
217 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | |
218 | return -ENOTSUPP; | |
219 | } | |
220 | ||
221 | #define MSM_NO_PULL 0 | |
222 | #define MSM_PULL_DOWN 1 | |
b831a15e | 223 | #define MSM_KEEPER 2 |
f365be09 BA |
224 | #define MSM_PULL_UP 3 |
225 | ||
7cc34e2e SB |
226 | static unsigned msm_regval_to_drive(u32 val) |
227 | { | |
228 | return (val + 1) * 2; | |
229 | } | |
f365be09 BA |
230 | |
231 | static int msm_config_group_get(struct pinctrl_dev *pctldev, | |
232 | unsigned int group, | |
233 | unsigned long *config) | |
234 | { | |
235 | const struct msm_pingroup *g; | |
236 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
237 | unsigned param = pinconf_to_config_param(*config); | |
238 | unsigned mask; | |
239 | unsigned arg; | |
240 | unsigned bit; | |
f365be09 BA |
241 | int ret; |
242 | u32 val; | |
243 | ||
244 | g = &pctrl->soc->groups[group]; | |
245 | ||
051a58b4 | 246 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
247 | if (ret < 0) |
248 | return ret; | |
249 | ||
051a58b4 | 250 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
251 | arg = (val >> bit) & mask; |
252 | ||
253 | /* Convert register value to pinconf value */ | |
254 | switch (param) { | |
255 | case PIN_CONFIG_BIAS_DISABLE: | |
256 | arg = arg == MSM_NO_PULL; | |
257 | break; | |
258 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
259 | arg = arg == MSM_PULL_DOWN; | |
260 | break; | |
b831a15e AG |
261 | case PIN_CONFIG_BIAS_BUS_HOLD: |
262 | arg = arg == MSM_KEEPER; | |
263 | break; | |
f365be09 BA |
264 | case PIN_CONFIG_BIAS_PULL_UP: |
265 | arg = arg == MSM_PULL_UP; | |
266 | break; | |
267 | case PIN_CONFIG_DRIVE_STRENGTH: | |
7cc34e2e | 268 | arg = msm_regval_to_drive(arg); |
f365be09 | 269 | break; |
ed118a5f BA |
270 | case PIN_CONFIG_OUTPUT: |
271 | /* Pin is not output */ | |
272 | if (!arg) | |
273 | return -EINVAL; | |
274 | ||
275 | val = readl(pctrl->regs + g->io_reg); | |
276 | arg = !!(val & BIT(g->in_bit)); | |
277 | break; | |
f365be09 BA |
278 | default: |
279 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
280 | param); | |
281 | return -EINVAL; | |
282 | } | |
283 | ||
284 | *config = pinconf_to_config_packed(param, arg); | |
285 | ||
286 | return 0; | |
287 | } | |
288 | ||
289 | static int msm_config_group_set(struct pinctrl_dev *pctldev, | |
290 | unsigned group, | |
291 | unsigned long *configs, | |
292 | unsigned num_configs) | |
293 | { | |
294 | const struct msm_pingroup *g; | |
295 | struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); | |
296 | unsigned long flags; | |
297 | unsigned param; | |
298 | unsigned mask; | |
299 | unsigned arg; | |
300 | unsigned bit; | |
f365be09 BA |
301 | int ret; |
302 | u32 val; | |
303 | int i; | |
304 | ||
305 | g = &pctrl->soc->groups[group]; | |
306 | ||
307 | for (i = 0; i < num_configs; i++) { | |
308 | param = pinconf_to_config_param(configs[i]); | |
309 | arg = pinconf_to_config_argument(configs[i]); | |
310 | ||
051a58b4 | 311 | ret = msm_config_reg(pctrl, g, param, &mask, &bit); |
f365be09 BA |
312 | if (ret < 0) |
313 | return ret; | |
314 | ||
315 | /* Convert pinconf values to register values */ | |
316 | switch (param) { | |
317 | case PIN_CONFIG_BIAS_DISABLE: | |
318 | arg = MSM_NO_PULL; | |
319 | break; | |
320 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
321 | arg = MSM_PULL_DOWN; | |
322 | break; | |
b831a15e AG |
323 | case PIN_CONFIG_BIAS_BUS_HOLD: |
324 | arg = MSM_KEEPER; | |
325 | break; | |
f365be09 BA |
326 | case PIN_CONFIG_BIAS_PULL_UP: |
327 | arg = MSM_PULL_UP; | |
328 | break; | |
329 | case PIN_CONFIG_DRIVE_STRENGTH: | |
330 | /* Check for invalid values */ | |
7cc34e2e | 331 | if (arg > 16 || arg < 2 || (arg % 2) != 0) |
f365be09 BA |
332 | arg = -1; |
333 | else | |
7cc34e2e | 334 | arg = (arg / 2) - 1; |
f365be09 | 335 | break; |
ed118a5f BA |
336 | case PIN_CONFIG_OUTPUT: |
337 | /* set output value */ | |
338 | spin_lock_irqsave(&pctrl->lock, flags); | |
339 | val = readl(pctrl->regs + g->io_reg); | |
340 | if (arg) | |
341 | val |= BIT(g->out_bit); | |
342 | else | |
343 | val &= ~BIT(g->out_bit); | |
344 | writel(val, pctrl->regs + g->io_reg); | |
345 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
346 | ||
347 | /* enable output */ | |
348 | arg = 1; | |
349 | break; | |
f365be09 BA |
350 | default: |
351 | dev_err(pctrl->dev, "Unsupported config parameter: %x\n", | |
352 | param); | |
353 | return -EINVAL; | |
354 | } | |
355 | ||
356 | /* Range-check user-supplied value */ | |
357 | if (arg & ~mask) { | |
358 | dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg); | |
359 | return -EINVAL; | |
360 | } | |
361 | ||
362 | spin_lock_irqsave(&pctrl->lock, flags); | |
051a58b4 | 363 | val = readl(pctrl->regs + g->ctl_reg); |
f365be09 BA |
364 | val &= ~(mask << bit); |
365 | val |= arg << bit; | |
051a58b4 | 366 | writel(val, pctrl->regs + g->ctl_reg); |
f365be09 BA |
367 | spin_unlock_irqrestore(&pctrl->lock, flags); |
368 | } | |
369 | ||
370 | return 0; | |
371 | } | |
372 | ||
1f2b2398 | 373 | static const struct pinconf_ops msm_pinconf_ops = { |
f365be09 BA |
374 | .pin_config_get = msm_config_get, |
375 | .pin_config_set = msm_config_set, | |
376 | .pin_config_group_get = msm_config_group_get, | |
377 | .pin_config_group_set = msm_config_group_set, | |
378 | }; | |
379 | ||
380 | static struct pinctrl_desc msm_pinctrl_desc = { | |
381 | .pctlops = &msm_pinctrl_ops, | |
382 | .pmxops = &msm_pinmux_ops, | |
383 | .confops = &msm_pinconf_ops, | |
384 | .owner = THIS_MODULE, | |
385 | }; | |
386 | ||
387 | static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
388 | { | |
389 | const struct msm_pingroup *g; | |
390 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
391 | unsigned long flags; | |
392 | u32 val; | |
393 | ||
f365be09 | 394 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
395 | |
396 | spin_lock_irqsave(&pctrl->lock, flags); | |
397 | ||
398 | val = readl(pctrl->regs + g->ctl_reg); | |
399 | val &= ~BIT(g->oe_bit); | |
400 | writel(val, pctrl->regs + g->ctl_reg); | |
401 | ||
402 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value) | |
408 | { | |
409 | const struct msm_pingroup *g; | |
410 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
411 | unsigned long flags; | |
412 | u32 val; | |
413 | ||
f365be09 | 414 | g = &pctrl->soc->groups[offset]; |
f365be09 BA |
415 | |
416 | spin_lock_irqsave(&pctrl->lock, flags); | |
417 | ||
e476e77f AL |
418 | val = readl(pctrl->regs + g->io_reg); |
419 | if (value) | |
420 | val |= BIT(g->out_bit); | |
421 | else | |
422 | val &= ~BIT(g->out_bit); | |
423 | writel(val, pctrl->regs + g->io_reg); | |
f365be09 BA |
424 | |
425 | val = readl(pctrl->regs + g->ctl_reg); | |
426 | val |= BIT(g->oe_bit); | |
427 | writel(val, pctrl->regs + g->ctl_reg); | |
428 | ||
429 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
430 | ||
431 | return 0; | |
432 | } | |
433 | ||
434 | static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) | |
435 | { | |
436 | const struct msm_pingroup *g; | |
437 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
438 | u32 val; | |
439 | ||
f365be09 BA |
440 | g = &pctrl->soc->groups[offset]; |
441 | ||
442 | val = readl(pctrl->regs + g->io_reg); | |
443 | return !!(val & BIT(g->in_bit)); | |
444 | } | |
445 | ||
446 | static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
447 | { | |
448 | const struct msm_pingroup *g; | |
449 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
450 | unsigned long flags; | |
451 | u32 val; | |
452 | ||
f365be09 BA |
453 | g = &pctrl->soc->groups[offset]; |
454 | ||
455 | spin_lock_irqsave(&pctrl->lock, flags); | |
456 | ||
457 | val = readl(pctrl->regs + g->io_reg); | |
e476e77f AL |
458 | if (value) |
459 | val |= BIT(g->out_bit); | |
460 | else | |
461 | val &= ~BIT(g->out_bit); | |
f365be09 BA |
462 | writel(val, pctrl->regs + g->io_reg); |
463 | ||
464 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
465 | } | |
466 | ||
f365be09 BA |
467 | static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
468 | { | |
469 | int gpio = chip->base + offset; | |
470 | return pinctrl_request_gpio(gpio); | |
471 | } | |
472 | ||
473 | static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) | |
474 | { | |
475 | int gpio = chip->base + offset; | |
476 | return pinctrl_free_gpio(gpio); | |
477 | } | |
478 | ||
479 | #ifdef CONFIG_DEBUG_FS | |
480 | #include <linux/seq_file.h> | |
481 | ||
482 | static void msm_gpio_dbg_show_one(struct seq_file *s, | |
483 | struct pinctrl_dev *pctldev, | |
484 | struct gpio_chip *chip, | |
485 | unsigned offset, | |
486 | unsigned gpio) | |
487 | { | |
488 | const struct msm_pingroup *g; | |
489 | struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip); | |
490 | unsigned func; | |
491 | int is_out; | |
492 | int drive; | |
493 | int pull; | |
494 | u32 ctl_reg; | |
495 | ||
1f2b2398 | 496 | static const char * const pulls[] = { |
f365be09 BA |
497 | "no pull", |
498 | "pull down", | |
499 | "keeper", | |
500 | "pull up" | |
501 | }; | |
502 | ||
503 | g = &pctrl->soc->groups[offset]; | |
504 | ctl_reg = readl(pctrl->regs + g->ctl_reg); | |
505 | ||
506 | is_out = !!(ctl_reg & BIT(g->oe_bit)); | |
507 | func = (ctl_reg >> g->mux_bit) & 7; | |
508 | drive = (ctl_reg >> g->drv_bit) & 7; | |
509 | pull = (ctl_reg >> g->pull_bit) & 3; | |
510 | ||
511 | seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func); | |
7cc34e2e | 512 | seq_printf(s, " %dmA", msm_regval_to_drive(drive)); |
f365be09 BA |
513 | seq_printf(s, " %s", pulls[pull]); |
514 | } | |
515 | ||
516 | static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
517 | { | |
518 | unsigned gpio = chip->base; | |
519 | unsigned i; | |
520 | ||
521 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
522 | msm_gpio_dbg_show_one(s, NULL, chip, i, gpio); | |
1f2b2398 | 523 | seq_puts(s, "\n"); |
f365be09 BA |
524 | } |
525 | } | |
526 | ||
527 | #else | |
528 | #define msm_gpio_dbg_show NULL | |
529 | #endif | |
530 | ||
531 | static struct gpio_chip msm_gpio_template = { | |
532 | .direction_input = msm_gpio_direction_input, | |
533 | .direction_output = msm_gpio_direction_output, | |
534 | .get = msm_gpio_get, | |
535 | .set = msm_gpio_set, | |
f365be09 BA |
536 | .request = msm_gpio_request, |
537 | .free = msm_gpio_free, | |
538 | .dbg_show = msm_gpio_dbg_show, | |
539 | }; | |
540 | ||
541 | /* For dual-edge interrupts in software, since some hardware has no | |
542 | * such support: | |
543 | * | |
544 | * At appropriate moments, this function may be called to flip the polarity | |
545 | * settings of both-edge irq lines to try and catch the next edge. | |
546 | * | |
547 | * The attempt is considered successful if: | |
548 | * - the status bit goes high, indicating that an edge was caught, or | |
549 | * - the input value of the gpio doesn't change during the attempt. | |
550 | * If the value changes twice during the process, that would cause the first | |
551 | * test to fail but would force the second, as two opposite | |
552 | * transitions would cause a detection no matter the polarity setting. | |
553 | * | |
554 | * The do-loop tries to sledge-hammer closed the timing hole between | |
555 | * the initial value-read and the polarity-write - if the line value changes | |
556 | * during that window, an interrupt is lost, the new polarity setting is | |
557 | * incorrect, and the first success test will fail, causing a retry. | |
558 | * | |
559 | * Algorithm comes from Google's msmgpio driver. | |
560 | */ | |
561 | static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl, | |
562 | const struct msm_pingroup *g, | |
563 | struct irq_data *d) | |
564 | { | |
565 | int loop_limit = 100; | |
566 | unsigned val, val2, intstat; | |
567 | unsigned pol; | |
568 | ||
569 | do { | |
570 | val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
571 | ||
572 | pol = readl(pctrl->regs + g->intr_cfg_reg); | |
573 | pol ^= BIT(g->intr_polarity_bit); | |
574 | writel(pol, pctrl->regs + g->intr_cfg_reg); | |
575 | ||
576 | val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit); | |
577 | intstat = readl(pctrl->regs + g->intr_status_reg); | |
578 | if (intstat || (val == val2)) | |
579 | return; | |
580 | } while (loop_limit-- > 0); | |
581 | dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n", | |
582 | val, val2); | |
583 | } | |
584 | ||
585 | static void msm_gpio_irq_mask(struct irq_data *d) | |
586 | { | |
cdcb0ab6 LW |
587 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
588 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 589 | const struct msm_pingroup *g; |
f365be09 BA |
590 | unsigned long flags; |
591 | u32 val; | |
592 | ||
f365be09 BA |
593 | g = &pctrl->soc->groups[d->hwirq]; |
594 | ||
595 | spin_lock_irqsave(&pctrl->lock, flags); | |
596 | ||
597 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
598 | val &= ~BIT(g->intr_enable_bit); | |
599 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
600 | ||
601 | clear_bit(d->hwirq, pctrl->enabled_irqs); | |
602 | ||
603 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
604 | } | |
605 | ||
606 | static void msm_gpio_irq_unmask(struct irq_data *d) | |
607 | { | |
cdcb0ab6 LW |
608 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
609 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 610 | const struct msm_pingroup *g; |
f365be09 BA |
611 | unsigned long flags; |
612 | u32 val; | |
613 | ||
f365be09 BA |
614 | g = &pctrl->soc->groups[d->hwirq]; |
615 | ||
616 | spin_lock_irqsave(&pctrl->lock, flags); | |
617 | ||
618 | val = readl(pctrl->regs + g->intr_status_reg); | |
619 | val &= ~BIT(g->intr_status_bit); | |
620 | writel(val, pctrl->regs + g->intr_status_reg); | |
621 | ||
622 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
623 | val |= BIT(g->intr_enable_bit); | |
624 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
625 | ||
626 | set_bit(d->hwirq, pctrl->enabled_irqs); | |
627 | ||
628 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
629 | } | |
630 | ||
631 | static void msm_gpio_irq_ack(struct irq_data *d) | |
632 | { | |
cdcb0ab6 LW |
633 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
634 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 635 | const struct msm_pingroup *g; |
f365be09 BA |
636 | unsigned long flags; |
637 | u32 val; | |
638 | ||
f365be09 BA |
639 | g = &pctrl->soc->groups[d->hwirq]; |
640 | ||
641 | spin_lock_irqsave(&pctrl->lock, flags); | |
642 | ||
643 | val = readl(pctrl->regs + g->intr_status_reg); | |
48f15e94 BA |
644 | if (g->intr_ack_high) |
645 | val |= BIT(g->intr_status_bit); | |
646 | else | |
647 | val &= ~BIT(g->intr_status_bit); | |
f365be09 BA |
648 | writel(val, pctrl->regs + g->intr_status_reg); |
649 | ||
650 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
651 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
652 | ||
653 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
654 | } | |
655 | ||
656 | #define INTR_TARGET_PROC_APPS 4 | |
657 | ||
658 | static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |
659 | { | |
cdcb0ab6 LW |
660 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
661 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 662 | const struct msm_pingroup *g; |
f365be09 BA |
663 | unsigned long flags; |
664 | u32 val; | |
665 | ||
f365be09 BA |
666 | g = &pctrl->soc->groups[d->hwirq]; |
667 | ||
668 | spin_lock_irqsave(&pctrl->lock, flags); | |
669 | ||
670 | /* | |
671 | * For hw without possibility of detecting both edges | |
672 | */ | |
673 | if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH) | |
674 | set_bit(d->hwirq, pctrl->dual_edge_irqs); | |
675 | else | |
676 | clear_bit(d->hwirq, pctrl->dual_edge_irqs); | |
677 | ||
678 | /* Route interrupts to application cpu */ | |
679 | val = readl(pctrl->regs + g->intr_target_reg); | |
680 | val &= ~(7 << g->intr_target_bit); | |
681 | val |= INTR_TARGET_PROC_APPS << g->intr_target_bit; | |
682 | writel(val, pctrl->regs + g->intr_target_reg); | |
683 | ||
684 | /* Update configuration for gpio. | |
685 | * RAW_STATUS_EN is left on for all gpio irqs. Due to the | |
686 | * internal circuitry of TLMM, toggling the RAW_STATUS | |
687 | * could cause the INTR_STATUS to be set for EDGE interrupts. | |
688 | */ | |
689 | val = readl(pctrl->regs + g->intr_cfg_reg); | |
690 | val |= BIT(g->intr_raw_status_bit); | |
691 | if (g->intr_detection_width == 2) { | |
692 | val &= ~(3 << g->intr_detection_bit); | |
693 | val &= ~(1 << g->intr_polarity_bit); | |
694 | switch (type) { | |
695 | case IRQ_TYPE_EDGE_RISING: | |
696 | val |= 1 << g->intr_detection_bit; | |
697 | val |= BIT(g->intr_polarity_bit); | |
698 | break; | |
699 | case IRQ_TYPE_EDGE_FALLING: | |
700 | val |= 2 << g->intr_detection_bit; | |
701 | val |= BIT(g->intr_polarity_bit); | |
702 | break; | |
703 | case IRQ_TYPE_EDGE_BOTH: | |
704 | val |= 3 << g->intr_detection_bit; | |
705 | val |= BIT(g->intr_polarity_bit); | |
706 | break; | |
707 | case IRQ_TYPE_LEVEL_LOW: | |
708 | break; | |
709 | case IRQ_TYPE_LEVEL_HIGH: | |
710 | val |= BIT(g->intr_polarity_bit); | |
711 | break; | |
712 | } | |
713 | } else if (g->intr_detection_width == 1) { | |
714 | val &= ~(1 << g->intr_detection_bit); | |
715 | val &= ~(1 << g->intr_polarity_bit); | |
716 | switch (type) { | |
717 | case IRQ_TYPE_EDGE_RISING: | |
718 | val |= BIT(g->intr_detection_bit); | |
719 | val |= BIT(g->intr_polarity_bit); | |
720 | break; | |
721 | case IRQ_TYPE_EDGE_FALLING: | |
722 | val |= BIT(g->intr_detection_bit); | |
723 | break; | |
724 | case IRQ_TYPE_EDGE_BOTH: | |
725 | val |= BIT(g->intr_detection_bit); | |
48f15e94 | 726 | val |= BIT(g->intr_polarity_bit); |
f365be09 BA |
727 | break; |
728 | case IRQ_TYPE_LEVEL_LOW: | |
729 | break; | |
730 | case IRQ_TYPE_LEVEL_HIGH: | |
731 | val |= BIT(g->intr_polarity_bit); | |
732 | break; | |
733 | } | |
734 | } else { | |
735 | BUG(); | |
736 | } | |
737 | writel(val, pctrl->regs + g->intr_cfg_reg); | |
738 | ||
739 | if (test_bit(d->hwirq, pctrl->dual_edge_irqs)) | |
740 | msm_gpio_update_dual_edge_pos(pctrl, g, d); | |
741 | ||
742 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
743 | ||
744 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
745 | __irq_set_handler_locked(d->irq, handle_level_irq); | |
746 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
747 | __irq_set_handler_locked(d->irq, handle_edge_irq); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |
753 | { | |
cdcb0ab6 LW |
754 | struct gpio_chip *gc = irq_data_get_irq_chip_data(d); |
755 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); | |
f365be09 | 756 | unsigned long flags; |
f365be09 | 757 | |
f365be09 BA |
758 | spin_lock_irqsave(&pctrl->lock, flags); |
759 | ||
6aced33f | 760 | irq_set_irq_wake(pctrl->irq, on); |
f365be09 BA |
761 | |
762 | spin_unlock_irqrestore(&pctrl->lock, flags); | |
763 | ||
764 | return 0; | |
765 | } | |
766 | ||
f365be09 BA |
767 | static struct irq_chip msm_gpio_irq_chip = { |
768 | .name = "msmgpio", | |
769 | .irq_mask = msm_gpio_irq_mask, | |
770 | .irq_unmask = msm_gpio_irq_unmask, | |
771 | .irq_ack = msm_gpio_irq_ack, | |
772 | .irq_set_type = msm_gpio_irq_set_type, | |
773 | .irq_set_wake = msm_gpio_irq_set_wake, | |
f365be09 BA |
774 | }; |
775 | ||
776 | static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
777 | { | |
cdcb0ab6 | 778 | struct gpio_chip *gc = irq_desc_get_handler_data(desc); |
f365be09 | 779 | const struct msm_pingroup *g; |
cdcb0ab6 | 780 | struct msm_pinctrl *pctrl = to_msm_pinctrl(gc); |
f365be09 BA |
781 | struct irq_chip *chip = irq_get_chip(irq); |
782 | int irq_pin; | |
783 | int handled = 0; | |
784 | u32 val; | |
785 | int i; | |
786 | ||
787 | chained_irq_enter(chip, desc); | |
788 | ||
789 | /* | |
1f2b2398 | 790 | * Each pin has it's own IRQ status register, so use |
f365be09 BA |
791 | * enabled_irq bitmap to limit the number of reads. |
792 | */ | |
793 | for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) { | |
794 | g = &pctrl->soc->groups[i]; | |
795 | val = readl(pctrl->regs + g->intr_status_reg); | |
796 | if (val & BIT(g->intr_status_bit)) { | |
cdcb0ab6 | 797 | irq_pin = irq_find_mapping(gc->irqdomain, i); |
f365be09 BA |
798 | generic_handle_irq(irq_pin); |
799 | handled++; | |
800 | } | |
801 | } | |
802 | ||
1f2b2398 | 803 | /* No interrupts were flagged */ |
f365be09 BA |
804 | if (handled == 0) |
805 | handle_bad_irq(irq, desc); | |
806 | ||
807 | chained_irq_exit(chip, desc); | |
808 | } | |
809 | ||
810 | static int msm_gpio_init(struct msm_pinctrl *pctrl) | |
811 | { | |
812 | struct gpio_chip *chip; | |
f365be09 | 813 | int ret; |
dcd278b8 SB |
814 | unsigned ngpio = pctrl->soc->ngpios; |
815 | ||
816 | if (WARN_ON(ngpio > MAX_NR_GPIO)) | |
817 | return -EINVAL; | |
f365be09 BA |
818 | |
819 | chip = &pctrl->chip; | |
820 | chip->base = 0; | |
dcd278b8 | 821 | chip->ngpio = ngpio; |
f365be09 BA |
822 | chip->label = dev_name(pctrl->dev); |
823 | chip->dev = pctrl->dev; | |
824 | chip->owner = THIS_MODULE; | |
825 | chip->of_node = pctrl->dev->of_node; | |
826 | ||
f365be09 BA |
827 | ret = gpiochip_add(&pctrl->chip); |
828 | if (ret) { | |
829 | dev_err(pctrl->dev, "Failed register gpiochip\n"); | |
830 | return ret; | |
831 | } | |
832 | ||
833 | ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio); | |
834 | if (ret) { | |
835 | dev_err(pctrl->dev, "Failed to add pin range\n"); | |
c6e927a2 | 836 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
837 | return ret; |
838 | } | |
839 | ||
cdcb0ab6 LW |
840 | ret = gpiochip_irqchip_add(chip, |
841 | &msm_gpio_irq_chip, | |
842 | 0, | |
843 | handle_edge_irq, | |
844 | IRQ_TYPE_NONE); | |
845 | if (ret) { | |
846 | dev_err(pctrl->dev, "Failed to add irqchip to gpiochip\n"); | |
c6e927a2 | 847 | gpiochip_remove(&pctrl->chip); |
f365be09 BA |
848 | return -ENOSYS; |
849 | } | |
850 | ||
cdcb0ab6 LW |
851 | gpiochip_set_chained_irqchip(chip, &msm_gpio_irq_chip, pctrl->irq, |
852 | msm_gpio_irq_handler); | |
f365be09 BA |
853 | |
854 | return 0; | |
855 | } | |
856 | ||
32745581 PG |
857 | #ifdef CONFIG_ARM |
858 | static void __iomem *msm_ps_hold; | |
859 | ||
860 | static void msm_reset(enum reboot_mode reboot_mode, const char *cmd) | |
861 | { | |
862 | writel(0, msm_ps_hold); | |
863 | mdelay(10000); | |
864 | } | |
865 | ||
866 | static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl) | |
867 | { | |
868 | int i = 0; | |
869 | const struct msm_function *func = pctrl->soc->functions; | |
870 | ||
871 | for (; i <= pctrl->soc->nfunctions; i++) | |
872 | if (!strcmp(func[i].name, "ps_hold")) { | |
873 | msm_ps_hold = pctrl->regs + PS_HOLD_OFFSET; | |
874 | arm_pm_restart = msm_reset; | |
875 | } | |
876 | } | |
877 | #else | |
878 | static void msm_pinctrl_setup_pm_reset(const struct msm_pinctrl *pctrl) {} | |
879 | #endif | |
880 | ||
f365be09 BA |
881 | int msm_pinctrl_probe(struct platform_device *pdev, |
882 | const struct msm_pinctrl_soc_data *soc_data) | |
883 | { | |
884 | struct msm_pinctrl *pctrl; | |
885 | struct resource *res; | |
886 | int ret; | |
887 | ||
888 | pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); | |
889 | if (!pctrl) { | |
890 | dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n"); | |
891 | return -ENOMEM; | |
892 | } | |
893 | pctrl->dev = &pdev->dev; | |
894 | pctrl->soc = soc_data; | |
895 | pctrl->chip = msm_gpio_template; | |
896 | ||
897 | spin_lock_init(&pctrl->lock); | |
898 | ||
899 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
900 | pctrl->regs = devm_ioremap_resource(&pdev->dev, res); | |
901 | if (IS_ERR(pctrl->regs)) | |
902 | return PTR_ERR(pctrl->regs); | |
903 | ||
32745581 PG |
904 | msm_pinctrl_setup_pm_reset(pctrl); |
905 | ||
f393e489 | 906 | pctrl->irq = platform_get_irq(pdev, 0); |
f365be09 BA |
907 | if (pctrl->irq < 0) { |
908 | dev_err(&pdev->dev, "No interrupt defined for msmgpio\n"); | |
909 | return pctrl->irq; | |
910 | } | |
911 | ||
912 | msm_pinctrl_desc.name = dev_name(&pdev->dev); | |
913 | msm_pinctrl_desc.pins = pctrl->soc->pins; | |
914 | msm_pinctrl_desc.npins = pctrl->soc->npins; | |
915 | pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl); | |
916 | if (!pctrl->pctrl) { | |
917 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | |
918 | return -ENODEV; | |
919 | } | |
920 | ||
921 | ret = msm_gpio_init(pctrl); | |
922 | if (ret) { | |
923 | pinctrl_unregister(pctrl->pctrl); | |
924 | return ret; | |
925 | } | |
926 | ||
927 | platform_set_drvdata(pdev, pctrl); | |
928 | ||
929 | dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n"); | |
930 | ||
931 | return 0; | |
932 | } | |
933 | EXPORT_SYMBOL(msm_pinctrl_probe); | |
934 | ||
935 | int msm_pinctrl_remove(struct platform_device *pdev) | |
936 | { | |
937 | struct msm_pinctrl *pctrl = platform_get_drvdata(pdev); | |
938 | int ret; | |
939 | ||
f393e489 BA |
940 | ret = gpiochip_remove(&pctrl->chip); |
941 | if (ret) { | |
942 | dev_err(&pdev->dev, "Failed to remove gpiochip\n"); | |
943 | return ret; | |
944 | } | |
945 | ||
f365be09 BA |
946 | pinctrl_unregister(pctrl->pctrl); |
947 | ||
948 | return 0; | |
949 | } | |
950 | EXPORT_SYMBOL(msm_pinctrl_remove); | |
951 |