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Commit | Line | Data |
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43b169db TA |
1 | /* |
2 | * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support. | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * http://www.samsung.com | |
6 | * Copyright (c) 2012 Linaro Ltd | |
7 | * http://www.linaro.org | |
8 | * | |
9 | * Author: Thomas Abraham <thomas.ab@samsung.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This file contains the Samsung Exynos specific information required by the | |
17 | * the Samsung pinctrl/gpiolib driver. It also includes the implementation of | |
18 | * external gpio and wakeup interrupt support. | |
19 | */ | |
20 | ||
43b169db TA |
21 | #include <linux/device.h> |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irqdomain.h> | |
24 | #include <linux/irq.h> | |
de88cbb7 | 25 | #include <linux/irqchip/chained_irq.h> |
cfa76ddf | 26 | #include <linux/of.h> |
43b169db | 27 | #include <linux/of_irq.h> |
43b169db | 28 | #include <linux/slab.h> |
19846950 | 29 | #include <linux/spinlock.h> |
07731019 | 30 | #include <linux/regmap.h> |
43b169db | 31 | #include <linux/err.h> |
07731019 | 32 | #include <linux/soc/samsung/exynos-pmu.h> |
43b169db | 33 | |
4460dc21 KK |
34 | #include <dt-bindings/pinctrl/samsung.h> |
35 | ||
43b169db TA |
36 | #include "pinctrl-samsung.h" |
37 | #include "pinctrl-exynos.h" | |
38 | ||
2e4a4fda TF |
39 | struct exynos_irq_chip { |
40 | struct irq_chip chip; | |
41 | ||
42 | u32 eint_con; | |
43 | u32 eint_mask; | |
44 | u32 eint_pend; | |
45 | }; | |
46 | ||
47 | static inline struct exynos_irq_chip *to_exynos_irq_chip(struct irq_chip *chip) | |
48 | { | |
49 | return container_of(chip, struct exynos_irq_chip, chip); | |
50 | } | |
499147c9 | 51 | |
2e4a4fda | 52 | static void exynos_irq_mask(struct irq_data *irqd) |
43b169db | 53 | { |
2e4a4fda TF |
54 | struct irq_chip *chip = irq_data_get_irq_chip(irqd); |
55 | struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); | |
595be726 | 56 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
2e4a4fda | 57 | unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; |
43b169db | 58 | unsigned long mask; |
5ae8cf79 DA |
59 | unsigned long flags; |
60 | ||
61 | spin_lock_irqsave(&bank->slock, flags); | |
43b169db | 62 | |
8b1bd11c | 63 | mask = readl(bank->eint_base + reg_mask); |
5ace03fb | 64 | mask |= 1 << irqd->hwirq; |
8b1bd11c | 65 | writel(mask, bank->eint_base + reg_mask); |
5ae8cf79 DA |
66 | |
67 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
68 | } |
69 | ||
2e4a4fda | 70 | static void exynos_irq_ack(struct irq_data *irqd) |
43b169db | 71 | { |
2e4a4fda TF |
72 | struct irq_chip *chip = irq_data_get_irq_chip(irqd); |
73 | struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); | |
595be726 | 74 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
2e4a4fda | 75 | unsigned long reg_pend = our_chip->eint_pend + bank->eint_offset; |
43b169db | 76 | |
8b1bd11c | 77 | writel(1 << irqd->hwirq, bank->eint_base + reg_pend); |
43b169db TA |
78 | } |
79 | ||
2e4a4fda | 80 | static void exynos_irq_unmask(struct irq_data *irqd) |
43b169db | 81 | { |
2e4a4fda TF |
82 | struct irq_chip *chip = irq_data_get_irq_chip(irqd); |
83 | struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); | |
595be726 | 84 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
2e4a4fda | 85 | unsigned long reg_mask = our_chip->eint_mask + bank->eint_offset; |
43b169db | 86 | unsigned long mask; |
5ae8cf79 | 87 | unsigned long flags; |
43b169db | 88 | |
5a68e7a7 DA |
89 | /* |
90 | * Ack level interrupts right before unmask | |
91 | * | |
92 | * If we don't do this we'll get a double-interrupt. Level triggered | |
93 | * interrupts must not fire an interrupt if the level is not | |
94 | * _currently_ active, even if it was active while the interrupt was | |
95 | * masked. | |
96 | */ | |
97 | if (irqd_get_trigger_type(irqd) & IRQ_TYPE_LEVEL_MASK) | |
2e4a4fda | 98 | exynos_irq_ack(irqd); |
5a68e7a7 | 99 | |
5ae8cf79 | 100 | spin_lock_irqsave(&bank->slock, flags); |
43b169db | 101 | |
8b1bd11c | 102 | mask = readl(bank->eint_base + reg_mask); |
5ace03fb | 103 | mask &= ~(1 << irqd->hwirq); |
8b1bd11c | 104 | writel(mask, bank->eint_base + reg_mask); |
5ae8cf79 DA |
105 | |
106 | spin_unlock_irqrestore(&bank->slock, flags); | |
43b169db TA |
107 | } |
108 | ||
2e4a4fda | 109 | static int exynos_irq_set_type(struct irq_data *irqd, unsigned int type) |
43b169db | 110 | { |
2e4a4fda TF |
111 | struct irq_chip *chip = irq_data_get_irq_chip(irqd); |
112 | struct exynos_irq_chip *our_chip = to_exynos_irq_chip(chip); | |
595be726 | 113 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
f6a8249f | 114 | unsigned int shift = EXYNOS_EINT_CON_LEN * irqd->hwirq; |
43b169db | 115 | unsigned int con, trig_type; |
2e4a4fda | 116 | unsigned long reg_con = our_chip->eint_con + bank->eint_offset; |
43b169db TA |
117 | |
118 | switch (type) { | |
119 | case IRQ_TYPE_EDGE_RISING: | |
120 | trig_type = EXYNOS_EINT_EDGE_RISING; | |
121 | break; | |
122 | case IRQ_TYPE_EDGE_FALLING: | |
123 | trig_type = EXYNOS_EINT_EDGE_FALLING; | |
124 | break; | |
125 | case IRQ_TYPE_EDGE_BOTH: | |
126 | trig_type = EXYNOS_EINT_EDGE_BOTH; | |
127 | break; | |
128 | case IRQ_TYPE_LEVEL_HIGH: | |
129 | trig_type = EXYNOS_EINT_LEVEL_HIGH; | |
130 | break; | |
131 | case IRQ_TYPE_LEVEL_LOW: | |
132 | trig_type = EXYNOS_EINT_LEVEL_LOW; | |
133 | break; | |
134 | default: | |
135 | pr_err("unsupported external interrupt type\n"); | |
136 | return -EINVAL; | |
137 | } | |
138 | ||
139 | if (type & IRQ_TYPE_EDGE_BOTH) | |
40ec168a | 140 | irq_set_handler_locked(irqd, handle_edge_irq); |
43b169db | 141 | else |
40ec168a | 142 | irq_set_handler_locked(irqd, handle_level_irq); |
43b169db | 143 | |
8b1bd11c | 144 | con = readl(bank->eint_base + reg_con); |
43b169db TA |
145 | con &= ~(EXYNOS_EINT_CON_MASK << shift); |
146 | con |= trig_type << shift; | |
8b1bd11c | 147 | writel(con, bank->eint_base + reg_con); |
ee2f573c | 148 | |
f6a8249f TF |
149 | return 0; |
150 | } | |
151 | ||
152 | static int exynos_irq_request_resources(struct irq_data *irqd) | |
153 | { | |
f6a8249f | 154 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
94ce944b | 155 | const struct samsung_pin_bank_type *bank_type = bank->type; |
bbed85f4 KK |
156 | unsigned long reg_con, flags; |
157 | unsigned int shift, mask, con; | |
f6a8249f TF |
158 | int ret; |
159 | ||
e3a2e878 | 160 | ret = gpiochip_lock_as_irq(&bank->gpio_chip, irqd->hwirq); |
f6a8249f | 161 | if (ret) { |
58383c78 LW |
162 | dev_err(bank->gpio_chip.parent, |
163 | "unable to lock pin %s-%lu IRQ\n", | |
f6a8249f TF |
164 | bank->name, irqd->hwirq); |
165 | return ret; | |
166 | } | |
167 | ||
43fc9e7f | 168 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; |
f6a8249f | 169 | shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; |
499147c9 | 170 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; |
ee2f573c | 171 | |
19846950 TF |
172 | spin_lock_irqsave(&bank->slock, flags); |
173 | ||
af0b0baa | 174 | con = readl(bank->pctl_base + reg_con); |
ee2f573c | 175 | con &= ~(mask << shift); |
4460dc21 | 176 | con |= EXYNOS_PIN_FUNC_EINT << shift; |
af0b0baa | 177 | writel(con, bank->pctl_base + reg_con); |
ee2f573c | 178 | |
19846950 TF |
179 | spin_unlock_irqrestore(&bank->slock, flags); |
180 | ||
43b169db TA |
181 | return 0; |
182 | } | |
183 | ||
f6a8249f TF |
184 | static void exynos_irq_release_resources(struct irq_data *irqd) |
185 | { | |
f6a8249f | 186 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); |
94ce944b | 187 | const struct samsung_pin_bank_type *bank_type = bank->type; |
bbed85f4 KK |
188 | unsigned long reg_con, flags; |
189 | unsigned int shift, mask, con; | |
f6a8249f TF |
190 | |
191 | reg_con = bank->pctl_offset + bank_type->reg_offset[PINCFG_TYPE_FUNC]; | |
192 | shift = irqd->hwirq * bank_type->fld_width[PINCFG_TYPE_FUNC]; | |
193 | mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1; | |
194 | ||
f6a8249f TF |
195 | spin_lock_irqsave(&bank->slock, flags); |
196 | ||
af0b0baa | 197 | con = readl(bank->pctl_base + reg_con); |
f6a8249f | 198 | con &= ~(mask << shift); |
4460dc21 | 199 | con |= EXYNOS_PIN_FUNC_INPUT << shift; |
af0b0baa | 200 | writel(con, bank->pctl_base + reg_con); |
f6a8249f TF |
201 | |
202 | spin_unlock_irqrestore(&bank->slock, flags); | |
203 | ||
e3a2e878 | 204 | gpiochip_unlock_as_irq(&bank->gpio_chip, irqd->hwirq); |
f6a8249f TF |
205 | } |
206 | ||
43b169db TA |
207 | /* |
208 | * irq_chip for gpio interrupts. | |
209 | */ | |
2e4a4fda TF |
210 | static struct exynos_irq_chip exynos_gpio_irq_chip = { |
211 | .chip = { | |
212 | .name = "exynos_gpio_irq_chip", | |
213 | .irq_unmask = exynos_irq_unmask, | |
214 | .irq_mask = exynos_irq_mask, | |
215 | .irq_ack = exynos_irq_ack, | |
216 | .irq_set_type = exynos_irq_set_type, | |
f6a8249f TF |
217 | .irq_request_resources = exynos_irq_request_resources, |
218 | .irq_release_resources = exynos_irq_release_resources, | |
2e4a4fda TF |
219 | }, |
220 | .eint_con = EXYNOS_GPIO_ECON_OFFSET, | |
221 | .eint_mask = EXYNOS_GPIO_EMASK_OFFSET, | |
222 | .eint_pend = EXYNOS_GPIO_EPEND_OFFSET, | |
43b169db TA |
223 | }; |
224 | ||
6f5e41bd | 225 | static int exynos_eint_irq_map(struct irq_domain *h, unsigned int virq, |
43b169db TA |
226 | irq_hw_number_t hw) |
227 | { | |
595be726 | 228 | struct samsung_pin_bank *b = h->host_data; |
43b169db | 229 | |
595be726 | 230 | irq_set_chip_data(virq, b); |
0d3d30db | 231 | irq_set_chip_and_handler(virq, &b->irq_chip->chip, |
43b169db | 232 | handle_level_irq); |
43b169db TA |
233 | return 0; |
234 | } | |
235 | ||
43b169db | 236 | /* |
6f5e41bd | 237 | * irq domain callbacks for external gpio and wakeup interrupt controllers. |
43b169db | 238 | */ |
6f5e41bd AK |
239 | static const struct irq_domain_ops exynos_eint_irqd_ops = { |
240 | .map = exynos_eint_irq_map, | |
43b169db TA |
241 | .xlate = irq_domain_xlate_twocell, |
242 | }; | |
243 | ||
244 | static irqreturn_t exynos_eint_gpio_irq(int irq, void *data) | |
245 | { | |
246 | struct samsung_pinctrl_drv_data *d = data; | |
1bf00d7a | 247 | struct samsung_pin_bank *bank = d->pin_banks; |
43b169db TA |
248 | unsigned int svc, group, pin, virq; |
249 | ||
8b1bd11c | 250 | svc = readl(bank->eint_base + EXYNOS_SVC_OFFSET); |
43b169db TA |
251 | group = EXYNOS_SVC_GROUP(svc); |
252 | pin = svc & EXYNOS_SVC_NUM_MASK; | |
253 | ||
254 | if (!group) | |
255 | return IRQ_HANDLED; | |
256 | bank += (group - 1); | |
257 | ||
595be726 | 258 | virq = irq_linear_revmap(bank->irq_domain, pin); |
43b169db TA |
259 | if (!virq) |
260 | return IRQ_NONE; | |
261 | generic_handle_irq(virq); | |
262 | return IRQ_HANDLED; | |
263 | } | |
264 | ||
7ccbc60c TF |
265 | struct exynos_eint_gpio_save { |
266 | u32 eint_con; | |
267 | u32 eint_fltcon0; | |
268 | u32 eint_fltcon1; | |
269 | }; | |
270 | ||
43b169db TA |
271 | /* |
272 | * exynos_eint_gpio_init() - setup handling of external gpio interrupts. | |
273 | * @d: driver data of samsung pinctrl driver. | |
274 | */ | |
cfa76ddf | 275 | int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d) |
43b169db | 276 | { |
595be726 | 277 | struct samsung_pin_bank *bank; |
43b169db | 278 | struct device *dev = d->dev; |
7ccbc60c TF |
279 | int ret; |
280 | int i; | |
43b169db TA |
281 | |
282 | if (!d->irq) { | |
283 | dev_err(dev, "irq number not available\n"); | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | ret = devm_request_irq(dev, d->irq, exynos_eint_gpio_irq, | |
288 | 0, dev_name(dev), d); | |
289 | if (ret) { | |
290 | dev_err(dev, "irq request failed\n"); | |
291 | return -ENXIO; | |
292 | } | |
293 | ||
1bf00d7a TF |
294 | bank = d->pin_banks; |
295 | for (i = 0; i < d->nr_banks; ++i, ++bank) { | |
595be726 TF |
296 | if (bank->eint_type != EINT_TYPE_GPIO) |
297 | continue; | |
298 | bank->irq_domain = irq_domain_add_linear(bank->of_node, | |
6f5e41bd | 299 | bank->nr_pins, &exynos_eint_irqd_ops, bank); |
595be726 TF |
300 | if (!bank->irq_domain) { |
301 | dev_err(dev, "gpio irq domain add failed\n"); | |
7ccbc60c TF |
302 | ret = -ENXIO; |
303 | goto err_domains; | |
304 | } | |
305 | ||
306 | bank->soc_priv = devm_kzalloc(d->dev, | |
307 | sizeof(struct exynos_eint_gpio_save), GFP_KERNEL); | |
308 | if (!bank->soc_priv) { | |
309 | irq_domain_remove(bank->irq_domain); | |
310 | ret = -ENOMEM; | |
311 | goto err_domains; | |
595be726 | 312 | } |
0d3d30db AK |
313 | |
314 | bank->irq_chip = &exynos_gpio_irq_chip; | |
43b169db TA |
315 | } |
316 | ||
317 | return 0; | |
7ccbc60c TF |
318 | |
319 | err_domains: | |
320 | for (--i, --bank; i >= 0; --i, --bank) { | |
321 | if (bank->eint_type != EINT_TYPE_GPIO) | |
322 | continue; | |
323 | irq_domain_remove(bank->irq_domain); | |
324 | } | |
325 | ||
326 | return ret; | |
43b169db TA |
327 | } |
328 | ||
ad350cd9 TF |
329 | static u32 exynos_eint_wake_mask = 0xffffffff; |
330 | ||
331 | u32 exynos_get_eint_wake_mask(void) | |
332 | { | |
333 | return exynos_eint_wake_mask; | |
334 | } | |
335 | ||
336 | static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on) | |
337 | { | |
338 | struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd); | |
339 | unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); | |
340 | ||
341 | pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq); | |
342 | ||
343 | if (!on) | |
344 | exynos_eint_wake_mask |= bit; | |
345 | else | |
346 | exynos_eint_wake_mask &= ~bit; | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
43b169db TA |
351 | /* |
352 | * irq_chip for wakeup interrupts | |
353 | */ | |
71b96c3a | 354 | static const struct exynos_irq_chip exynos4210_wkup_irq_chip __initconst = { |
2e4a4fda | 355 | .chip = { |
14c255d3 | 356 | .name = "exynos4210_wkup_irq_chip", |
2e4a4fda TF |
357 | .irq_unmask = exynos_irq_unmask, |
358 | .irq_mask = exynos_irq_mask, | |
359 | .irq_ack = exynos_irq_ack, | |
360 | .irq_set_type = exynos_irq_set_type, | |
361 | .irq_set_wake = exynos_wkup_irq_set_wake, | |
f6a8249f TF |
362 | .irq_request_resources = exynos_irq_request_resources, |
363 | .irq_release_resources = exynos_irq_release_resources, | |
2e4a4fda TF |
364 | }, |
365 | .eint_con = EXYNOS_WKUP_ECON_OFFSET, | |
366 | .eint_mask = EXYNOS_WKUP_EMASK_OFFSET, | |
367 | .eint_pend = EXYNOS_WKUP_EPEND_OFFSET, | |
43b169db TA |
368 | }; |
369 | ||
71b96c3a | 370 | static const struct exynos_irq_chip exynos7_wkup_irq_chip __initconst = { |
14c255d3 AK |
371 | .chip = { |
372 | .name = "exynos7_wkup_irq_chip", | |
373 | .irq_unmask = exynos_irq_unmask, | |
374 | .irq_mask = exynos_irq_mask, | |
375 | .irq_ack = exynos_irq_ack, | |
376 | .irq_set_type = exynos_irq_set_type, | |
377 | .irq_set_wake = exynos_wkup_irq_set_wake, | |
378 | .irq_request_resources = exynos_irq_request_resources, | |
379 | .irq_release_resources = exynos_irq_release_resources, | |
380 | }, | |
381 | .eint_con = EXYNOS7_WKUP_ECON_OFFSET, | |
382 | .eint_mask = EXYNOS7_WKUP_EMASK_OFFSET, | |
383 | .eint_pend = EXYNOS7_WKUP_EPEND_OFFSET, | |
384 | }; | |
385 | ||
386 | /* list of external wakeup controllers supported */ | |
387 | static const struct of_device_id exynos_wkup_irq_ids[] = { | |
388 | { .compatible = "samsung,exynos4210-wakeup-eint", | |
389 | .data = &exynos4210_wkup_irq_chip }, | |
390 | { .compatible = "samsung,exynos7-wakeup-eint", | |
391 | .data = &exynos7_wkup_irq_chip }, | |
392 | { } | |
393 | }; | |
394 | ||
43b169db | 395 | /* interrupt handler for wakeup interrupts 0..15 */ |
bd0b9ac4 | 396 | static void exynos_irq_eint0_15(struct irq_desc *desc) |
43b169db | 397 | { |
5663bb27 | 398 | struct exynos_weint_data *eintd = irq_desc_get_handler_data(desc); |
a04b07c0 | 399 | struct samsung_pin_bank *bank = eintd->bank; |
5663bb27 | 400 | struct irq_chip *chip = irq_desc_get_chip(desc); |
43b169db TA |
401 | int eint_irq; |
402 | ||
403 | chained_irq_enter(chip, desc); | |
43b169db | 404 | |
a04b07c0 | 405 | eint_irq = irq_linear_revmap(bank->irq_domain, eintd->irq); |
43b169db | 406 | generic_handle_irq(eint_irq); |
26fecf0b | 407 | |
43b169db TA |
408 | chained_irq_exit(chip, desc); |
409 | } | |
410 | ||
a04b07c0 TF |
411 | static inline void exynos_irq_demux_eint(unsigned long pend, |
412 | struct irq_domain *domain) | |
43b169db TA |
413 | { |
414 | unsigned int irq; | |
415 | ||
416 | while (pend) { | |
417 | irq = fls(pend) - 1; | |
a04b07c0 | 418 | generic_handle_irq(irq_find_mapping(domain, irq)); |
43b169db TA |
419 | pend &= ~(1 << irq); |
420 | } | |
421 | } | |
422 | ||
423 | /* interrupt handler for wakeup interrupt 16 */ | |
bd0b9ac4 | 424 | static void exynos_irq_demux_eint16_31(struct irq_desc *desc) |
43b169db | 425 | { |
5663bb27 JL |
426 | struct irq_chip *chip = irq_desc_get_chip(desc); |
427 | struct exynos_muxed_weint_data *eintd = irq_desc_get_handler_data(desc); | |
43b169db | 428 | unsigned long pend; |
de59049b | 429 | unsigned long mask; |
a04b07c0 | 430 | int i; |
43b169db TA |
431 | |
432 | chained_irq_enter(chip, desc); | |
a04b07c0 TF |
433 | |
434 | for (i = 0; i < eintd->nr_banks; ++i) { | |
435 | struct samsung_pin_bank *b = eintd->banks[i]; | |
8b1bd11c | 436 | pend = readl(b->eint_base + b->irq_chip->eint_pend |
2e4a4fda | 437 | + b->eint_offset); |
8b1bd11c | 438 | mask = readl(b->eint_base + b->irq_chip->eint_mask |
2e4a4fda | 439 | + b->eint_offset); |
a04b07c0 TF |
440 | exynos_irq_demux_eint(pend & ~mask, b->irq_domain); |
441 | } | |
442 | ||
43b169db TA |
443 | chained_irq_exit(chip, desc); |
444 | } | |
445 | ||
43b169db TA |
446 | /* |
447 | * exynos_eint_wkup_init() - setup handling of external wakeup interrupts. | |
448 | * @d: driver data of samsung pinctrl driver. | |
449 | */ | |
cfa76ddf | 450 | int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d) |
43b169db TA |
451 | { |
452 | struct device *dev = d->dev; | |
c3ad056b TF |
453 | struct device_node *wkup_np = NULL; |
454 | struct device_node *np; | |
a04b07c0 | 455 | struct samsung_pin_bank *bank; |
43b169db | 456 | struct exynos_weint_data *weint_data; |
a04b07c0 | 457 | struct exynos_muxed_weint_data *muxed_data; |
14c255d3 | 458 | struct exynos_irq_chip *irq_chip; |
a04b07c0 TF |
459 | unsigned int muxed_banks = 0; |
460 | unsigned int i; | |
43b169db TA |
461 | int idx, irq; |
462 | ||
c3ad056b | 463 | for_each_child_of_node(dev->of_node, np) { |
14c255d3 AK |
464 | const struct of_device_id *match; |
465 | ||
466 | match = of_match_node(exynos_wkup_irq_ids, np); | |
467 | if (match) { | |
468 | irq_chip = kmemdup(match->data, | |
469 | sizeof(*irq_chip), GFP_KERNEL); | |
40e58ca5 ND |
470 | if (!irq_chip) { |
471 | of_node_put(np); | |
a1ea9a40 | 472 | return -ENOMEM; |
40e58ca5 | 473 | } |
c3ad056b TF |
474 | wkup_np = np; |
475 | break; | |
476 | } | |
43b169db | 477 | } |
c3ad056b TF |
478 | if (!wkup_np) |
479 | return -ENODEV; | |
43b169db | 480 | |
1bf00d7a TF |
481 | bank = d->pin_banks; |
482 | for (i = 0; i < d->nr_banks; ++i, ++bank) { | |
a04b07c0 TF |
483 | if (bank->eint_type != EINT_TYPE_WKUP) |
484 | continue; | |
43b169db | 485 | |
a04b07c0 | 486 | bank->irq_domain = irq_domain_add_linear(bank->of_node, |
6f5e41bd | 487 | bank->nr_pins, &exynos_eint_irqd_ops, bank); |
a04b07c0 TF |
488 | if (!bank->irq_domain) { |
489 | dev_err(dev, "wkup irq domain add failed\n"); | |
3f307757 | 490 | of_node_put(wkup_np); |
a04b07c0 TF |
491 | return -ENXIO; |
492 | } | |
43b169db | 493 | |
14c255d3 | 494 | bank->irq_chip = irq_chip; |
0d3d30db | 495 | |
a04b07c0 TF |
496 | if (!of_find_property(bank->of_node, "interrupts", NULL)) { |
497 | bank->eint_type = EINT_TYPE_WKUP_MUX; | |
498 | ++muxed_banks; | |
499 | continue; | |
500 | } | |
43b169db | 501 | |
a04b07c0 TF |
502 | weint_data = devm_kzalloc(dev, bank->nr_pins |
503 | * sizeof(*weint_data), GFP_KERNEL); | |
3f307757 KK |
504 | if (!weint_data) { |
505 | of_node_put(wkup_np); | |
a04b07c0 | 506 | return -ENOMEM; |
3f307757 | 507 | } |
43b169db | 508 | |
a04b07c0 TF |
509 | for (idx = 0; idx < bank->nr_pins; ++idx) { |
510 | irq = irq_of_parse_and_map(bank->of_node, idx); | |
511 | if (!irq) { | |
512 | dev_err(dev, "irq number for eint-%s-%d not found\n", | |
513 | bank->name, idx); | |
514 | continue; | |
515 | } | |
516 | weint_data[idx].irq = idx; | |
517 | weint_data[idx].bank = bank; | |
c21f7849 TG |
518 | irq_set_chained_handler_and_data(irq, |
519 | exynos_irq_eint0_15, | |
520 | &weint_data[idx]); | |
43b169db TA |
521 | } |
522 | } | |
a04b07c0 | 523 | |
3f307757 KK |
524 | if (!muxed_banks) { |
525 | of_node_put(wkup_np); | |
a04b07c0 | 526 | return 0; |
3f307757 | 527 | } |
a04b07c0 TF |
528 | |
529 | irq = irq_of_parse_and_map(wkup_np, 0); | |
3f307757 | 530 | of_node_put(wkup_np); |
a04b07c0 TF |
531 | if (!irq) { |
532 | dev_err(dev, "irq number for muxed EINTs not found\n"); | |
533 | return 0; | |
534 | } | |
535 | ||
536 | muxed_data = devm_kzalloc(dev, sizeof(*muxed_data) | |
537 | + muxed_banks*sizeof(struct samsung_pin_bank *), GFP_KERNEL); | |
fa5c0f46 | 538 | if (!muxed_data) |
a04b07c0 | 539 | return -ENOMEM; |
a04b07c0 | 540 | |
bb56fc35 TG |
541 | irq_set_chained_handler_and_data(irq, exynos_irq_demux_eint16_31, |
542 | muxed_data); | |
a04b07c0 | 543 | |
1bf00d7a | 544 | bank = d->pin_banks; |
a04b07c0 | 545 | idx = 0; |
1bf00d7a | 546 | for (i = 0; i < d->nr_banks; ++i, ++bank) { |
a04b07c0 TF |
547 | if (bank->eint_type != EINT_TYPE_WKUP_MUX) |
548 | continue; | |
549 | ||
550 | muxed_data->banks[idx++] = bank; | |
551 | } | |
552 | muxed_data->nr_banks = muxed_banks; | |
553 | ||
43b169db TA |
554 | return 0; |
555 | } | |
556 | ||
7ccbc60c TF |
557 | static void exynos_pinctrl_suspend_bank( |
558 | struct samsung_pinctrl_drv_data *drvdata, | |
559 | struct samsung_pin_bank *bank) | |
560 | { | |
561 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
8b1bd11c | 562 | void __iomem *regs = bank->eint_base; |
7ccbc60c TF |
563 | |
564 | save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
565 | + bank->eint_offset); | |
566 | save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
567 | + 2 * bank->eint_offset); | |
568 | save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
569 | + 2 * bank->eint_offset + 4); | |
570 | ||
571 | pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); | |
572 | pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); | |
573 | pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); | |
574 | } | |
575 | ||
cfa76ddf | 576 | void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) |
7ccbc60c | 577 | { |
1bf00d7a | 578 | struct samsung_pin_bank *bank = drvdata->pin_banks; |
7ccbc60c TF |
579 | int i; |
580 | ||
1bf00d7a | 581 | for (i = 0; i < drvdata->nr_banks; ++i, ++bank) |
7ccbc60c TF |
582 | if (bank->eint_type == EINT_TYPE_GPIO) |
583 | exynos_pinctrl_suspend_bank(drvdata, bank); | |
584 | } | |
585 | ||
586 | static void exynos_pinctrl_resume_bank( | |
587 | struct samsung_pinctrl_drv_data *drvdata, | |
588 | struct samsung_pin_bank *bank) | |
589 | { | |
590 | struct exynos_eint_gpio_save *save = bank->soc_priv; | |
8b1bd11c | 591 | void __iomem *regs = bank->eint_base; |
7ccbc60c TF |
592 | |
593 | pr_debug("%s: con %#010x => %#010x\n", bank->name, | |
594 | readl(regs + EXYNOS_GPIO_ECON_OFFSET | |
595 | + bank->eint_offset), save->eint_con); | |
596 | pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name, | |
597 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
598 | + 2 * bank->eint_offset), save->eint_fltcon0); | |
599 | pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name, | |
600 | readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
601 | + 2 * bank->eint_offset + 4), save->eint_fltcon1); | |
602 | ||
603 | writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET | |
604 | + bank->eint_offset); | |
605 | writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
606 | + 2 * bank->eint_offset); | |
607 | writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET | |
608 | + 2 * bank->eint_offset + 4); | |
609 | } | |
610 | ||
cfa76ddf | 611 | void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) |
7ccbc60c | 612 | { |
1bf00d7a | 613 | struct samsung_pin_bank *bank = drvdata->pin_banks; |
7ccbc60c TF |
614 | int i; |
615 | ||
1bf00d7a | 616 | for (i = 0; i < drvdata->nr_banks; ++i, ++bank) |
7ccbc60c TF |
617 | if (bank->eint_type == EINT_TYPE_GPIO) |
618 | exynos_pinctrl_resume_bank(drvdata, bank); | |
619 | } | |
620 | ||
07731019 MS |
621 | static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvdata) |
622 | { | |
623 | if (drvdata->retention_ctrl->refcnt) | |
624 | atomic_inc(drvdata->retention_ctrl->refcnt); | |
625 | } | |
626 | ||
627 | static void exynos_retention_disable(struct samsung_pinctrl_drv_data *drvdata) | |
628 | { | |
629 | struct samsung_retention_ctrl *ctrl = drvdata->retention_ctrl; | |
630 | struct regmap *pmu_regs = ctrl->priv; | |
631 | int i; | |
632 | ||
633 | if (ctrl->refcnt && !atomic_dec_and_test(ctrl->refcnt)) | |
634 | return; | |
635 | ||
636 | for (i = 0; i < ctrl->nr_regs; i++) | |
637 | regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); | |
638 | } | |
639 | ||
cfa76ddf | 640 | struct samsung_retention_ctrl * |
07731019 MS |
641 | exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, |
642 | const struct samsung_retention_data *data) | |
643 | { | |
644 | struct samsung_retention_ctrl *ctrl; | |
645 | struct regmap *pmu_regs; | |
8fe9bf07 | 646 | int i; |
07731019 MS |
647 | |
648 | ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL); | |
649 | if (!ctrl) | |
650 | return ERR_PTR(-ENOMEM); | |
651 | ||
652 | pmu_regs = exynos_get_pmu_regmap(); | |
653 | if (IS_ERR(pmu_regs)) | |
654 | return ERR_CAST(pmu_regs); | |
655 | ||
656 | ctrl->priv = pmu_regs; | |
657 | ctrl->regs = data->regs; | |
658 | ctrl->nr_regs = data->nr_regs; | |
659 | ctrl->value = data->value; | |
660 | ctrl->refcnt = data->refcnt; | |
661 | ctrl->enable = exynos_retention_enable; | |
662 | ctrl->disable = exynos_retention_disable; | |
663 | ||
8fe9bf07 MS |
664 | /* Ensure that retention is disabled on driver init */ |
665 | for (i = 0; i < ctrl->nr_regs; i++) | |
666 | regmap_write(pmu_regs, ctrl->regs[i], ctrl->value); | |
667 | ||
07731019 MS |
668 | return ctrl; |
669 | } |