[mirror_ubuntu-zesty-kernel.git] / drivers / pinctrl / samsung / pinctrl-s3c24xx.c

/*
 * S3C24XX specific support for Samsung pinctrl/gpiolib driver.
 *
 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This file contains the SamsungS3C24XX specific information required by the
 * Samsung pinctrl/gpiolib driver. It also includes the implementation of
 * external gpio and wakeup interrupt support.
 */

#include <linux/module.h>
#include <linux/device.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/irq.h>
#include <linux/of_irq.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/err.h>

#include "pinctrl-samsung.h"

#define NUM_EINT	24
#define NUM_EINT_IRQ	6
#define EINT_MAX_PER_GROUP	8

#define EINTPEND_REG	0xa8
#define EINTMASK_REG	0xa4

#define EINT_GROUP(i)		((int)((i) / EINT_MAX_PER_GROUP))
#define EINT_REG(i)		((EINT_GROUP(i) * 4) + 0x88)
#define EINT_OFFS(i)		((i) % EINT_MAX_PER_GROUP * 4)

#define EINT_LEVEL_LOW		0
#define EINT_LEVEL_HIGH		1
#define EINT_EDGE_FALLING	2
#define EINT_EDGE_RISING	4
#define EINT_EDGE_BOTH		6
#define EINT_MASK		0xf

static const struct samsung_pin_bank_type bank_type_1bit = {
	.fld_width = { 1, 1, },
	.reg_offset = { 0x00, 0x04, },
};

static const struct samsung_pin_bank_type bank_type_2bit = {
	.fld_width = { 2, 1, 2, },
	.reg_offset = { 0x00, 0x04, 0x08, },
};

#define PIN_BANK_A(pins, reg, id)		\
	{						\
		.type		= &bank_type_1bit,	\
		.pctl_offset	= reg,			\
		.nr_pins	= pins,			\
		.eint_type	= EINT_TYPE_NONE,	\
		.name		= id			\
	}

#define PIN_BANK_2BIT(pins, reg, id)		\
	{						\
		.type		= &bank_type_2bit,	\
		.pctl_offset	= reg,			\
		.nr_pins	= pins,			\
		.eint_type	= EINT_TYPE_NONE,	\
		.name		= id			\
	}

#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
	{						\
		.type		= &bank_type_2bit,	\
		.pctl_offset	= reg,			\
		.nr_pins	= pins,			\
		.eint_type	= EINT_TYPE_WKUP,	\
		.eint_func	= 2,			\
		.eint_mask	= emask,		\
		.eint_offset	= eoffs,		\
		.name		= id			\
	}

/**
 * struct s3c24xx_eint_data: EINT common data
 * @drvdata: pin controller driver data
 * @domains: IRQ domains of particular EINT interrupts
 * @parents: mapped parent irqs in the main interrupt controller
 */
struct s3c24xx_eint_data {
	struct samsung_pinctrl_drv_data *drvdata;
	struct irq_domain *domains[NUM_EINT];
	int parents[NUM_EINT_IRQ];
};

/**
 * struct s3c24xx_eint_domain_data: per irq-domain data
 * @bank: pin bank related to the domain
 * @eint_data: common data
 * eint0_3_parent_only: live eints 0-3 only in the main intc
 */
struct s3c24xx_eint_domain_data {
	struct samsung_pin_bank *bank;
	struct s3c24xx_eint_data *eint_data;
	bool eint0_3_parent_only;
};

static int s3c24xx_eint_get_trigger(unsigned int type)
{
	switch (type) {
	case IRQ_TYPE_EDGE_RISING:
		return EINT_EDGE_RISING;
		break;
	case IRQ_TYPE_EDGE_FALLING:
		return EINT_EDGE_FALLING;
		break;
	case IRQ_TYPE_EDGE_BOTH:
		return EINT_EDGE_BOTH;
		break;
	case IRQ_TYPE_LEVEL_HIGH:
		return EINT_LEVEL_HIGH;
		break;
	case IRQ_TYPE_LEVEL_LOW:
		return EINT_LEVEL_LOW;
		break;
	default:
		return -EINVAL;
	}
}

static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
{
	/* Edge- and level-triggered interrupts need different handlers */
	if (type & IRQ_TYPE_EDGE_BOTH)
		irq_set_handler_locked(d, handle_edge_irq);
	else
		irq_set_handler_locked(d, handle_level_irq);
}

static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
					struct samsung_pin_bank *bank, int pin)
{
	const struct samsung_pin_bank_type *bank_type = bank->type;
	unsigned long flags;
	void __iomem *reg;
	u8 shift;
	u32 mask;
	u32 val;

	/* Make sure that pin is configured as interrupt */
	reg = bank->pctl_base + bank->pctl_offset;
	shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;

	spin_lock_irqsave(&bank->slock, flags);

	val = readl(reg);
	val &= ~(mask << shift);
	val |= bank->eint_func << shift;
	writel(val, reg);

	spin_unlock_irqrestore(&bank->slock, flags);
}

static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	struct samsung_pinctrl_drv_data *d = bank->drvdata;
	int index = bank->eint_offset + data->hwirq;
	void __iomem *reg;
	int trigger;
	u8 shift;
	u32 val;

	trigger = s3c24xx_eint_get_trigger(type);
	if (trigger < 0) {
		dev_err(d->dev, "unsupported external interrupt type\n");
		return -EINVAL;
	}

	s3c24xx_eint_set_handler(data, type);

	/* Set up interrupt trigger */
	reg = bank->eint_base + EINT_REG(index);
	shift = EINT_OFFS(index);

	val = readl(reg);
	val &= ~(EINT_MASK << shift);
	val |= trigger << shift;
	writel(val, reg);

	s3c24xx_eint_set_function(d, bank, data->hwirq);

	return 0;
}

/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */

static void s3c2410_eint0_3_ack(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	int parent_irq = eint_data->parents[data->hwirq];
	struct irq_chip *parent_chip = irq_get_chip(parent_irq);

	parent_chip->irq_ack(irq_get_irq_data(parent_irq));
}

static void s3c2410_eint0_3_mask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	int parent_irq = eint_data->parents[data->hwirq];
	struct irq_chip *parent_chip = irq_get_chip(parent_irq);

	parent_chip->irq_mask(irq_get_irq_data(parent_irq));
}

static void s3c2410_eint0_3_unmask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	int parent_irq = eint_data->parents[data->hwirq];
	struct irq_chip *parent_chip = irq_get_chip(parent_irq);

	parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
}

static struct irq_chip s3c2410_eint0_3_chip = {
	.name		= "s3c2410-eint0_3",
	.irq_ack	= s3c2410_eint0_3_ack,
	.irq_mask	= s3c2410_eint0_3_mask,
	.irq_unmask	= s3c2410_eint0_3_unmask,
	.irq_set_type	= s3c24xx_eint_type,
};

static void s3c2410_demux_eint0_3(struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
	unsigned int virq;

	/* the first 4 eints have a simple 1 to 1 mapping */
	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
	/* Something must be really wrong if an unmapped EINT is unmasked */
	BUG_ON(!virq);

	generic_handle_irq(virq);
}

/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */

static void s3c2412_eint0_3_ack(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);

	unsigned long bitval = 1UL << data->hwirq;
	writel(bitval, bank->eint_base + EINTPEND_REG);
}

static void s3c2412_eint0_3_mask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	unsigned long mask;

	mask = readl(bank->eint_base + EINTMASK_REG);
	mask |= (1UL << data->hwirq);
	writel(mask, bank->eint_base + EINTMASK_REG);
}

static void s3c2412_eint0_3_unmask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	unsigned long mask;

	mask = readl(bank->eint_base + EINTMASK_REG);
	mask &= ~(1UL << data->hwirq);
	writel(mask, bank->eint_base + EINTMASK_REG);
}

static struct irq_chip s3c2412_eint0_3_chip = {
	.name		= "s3c2412-eint0_3",
	.irq_ack	= s3c2412_eint0_3_ack,
	.irq_mask	= s3c2412_eint0_3_mask,
	.irq_unmask	= s3c2412_eint0_3_unmask,
	.irq_set_type	= s3c24xx_eint_type,
};

static void s3c2412_demux_eint0_3(struct irq_desc *desc)
{
	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	unsigned int virq;

	chained_irq_enter(chip, desc);

	/* the first 4 eints have a simple 1 to 1 mapping */
	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
	/* Something must be really wrong if an unmapped EINT is unmasked */
	BUG_ON(!virq);

	generic_handle_irq(virq);

	chained_irq_exit(chip, desc);
}

/* Handling of all other eints */

static void s3c24xx_eint_ack(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	unsigned char index = bank->eint_offset + data->hwirq;

	writel(1UL << index, bank->eint_base + EINTPEND_REG);
}

static void s3c24xx_eint_mask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	unsigned char index = bank->eint_offset + data->hwirq;
	unsigned long mask;

	mask = readl(bank->eint_base + EINTMASK_REG);
	mask |= (1UL << index);
	writel(mask, bank->eint_base + EINTMASK_REG);
}

static void s3c24xx_eint_unmask(struct irq_data *data)
{
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	unsigned char index = bank->eint_offset + data->hwirq;
	unsigned long mask;

	mask = readl(bank->eint_base + EINTMASK_REG);
	mask &= ~(1UL << index);
	writel(mask, bank->eint_base + EINTMASK_REG);
}

static struct irq_chip s3c24xx_eint_chip = {
	.name		= "s3c-eint",
	.irq_ack	= s3c24xx_eint_ack,
	.irq_mask	= s3c24xx_eint_mask,
	.irq_unmask	= s3c24xx_eint_unmask,
	.irq_set_type	= s3c24xx_eint_type,
};

static inline void s3c24xx_demux_eint(struct irq_desc *desc,
				      u32 offset, u32 range)
{
	struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
	struct irq_chip *chip = irq_desc_get_chip(desc);
	struct irq_data *irqd = irq_desc_get_irq_data(desc);
	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
	unsigned int pend, mask;

	chained_irq_enter(chip, desc);

	pend = readl(bank->eint_base + EINTPEND_REG);
	mask = readl(bank->eint_base + EINTMASK_REG);

	pend &= ~mask;
	pend &= range;

	while (pend) {
		unsigned int virq, irq;

		irq = __ffs(pend);
		pend &= ~(1 << irq);
		virq = irq_linear_revmap(data->domains[irq], irq - offset);
		/* Something is really wrong if an unmapped EINT is unmasked */
		BUG_ON(!virq);

		generic_handle_irq(virq);
	}

	chained_irq_exit(chip, desc);
}

static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
{
	s3c24xx_demux_eint(desc, 0, 0xf0);
}

static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
{
	s3c24xx_demux_eint(desc, 8, 0xffff00);
}

static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
	s3c2410_demux_eint0_3,
	s3c2410_demux_eint0_3,
	s3c2410_demux_eint0_3,
	s3c2410_demux_eint0_3,
	s3c24xx_demux_eint4_7,
	s3c24xx_demux_eint8_23,
};

static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
	s3c2412_demux_eint0_3,
	s3c2412_demux_eint0_3,
	s3c2412_demux_eint0_3,
	s3c2412_demux_eint0_3,
	s3c24xx_demux_eint4_7,
	s3c24xx_demux_eint8_23,
};

static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
					irq_hw_number_t hw)
{
	struct s3c24xx_eint_domain_data *ddata = h->host_data;
	struct samsung_pin_bank *bank = ddata->bank;

	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
		return -EINVAL;

	if (hw <= 3) {
		if (ddata->eint0_3_parent_only)
			irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
						 handle_edge_irq);
		else
			irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
						 handle_edge_irq);
	} else {
		irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
					 handle_edge_irq);
	}
	irq_set_chip_data(virq, bank);
	return 0;
}

static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
	.map	= s3c24xx_gpf_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
					irq_hw_number_t hw)
{
	struct s3c24xx_eint_domain_data *ddata = h->host_data;
	struct samsung_pin_bank *bank = ddata->bank;

	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
		return -EINVAL;

	irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
	irq_set_chip_data(virq, bank);
	return 0;
}

static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
	.map	= s3c24xx_gpg_irq_map,
	.xlate	= irq_domain_xlate_twocell,
};

static const struct of_device_id s3c24xx_eint_irq_ids[] = {
	{ .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
	{ .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
	{ }
};

static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
{
	struct device *dev = d->dev;
	const struct of_device_id *match;
	struct device_node *eint_np = NULL;
	struct device_node *np;
	struct samsung_pin_bank *bank;
	struct s3c24xx_eint_data *eint_data;
	const struct irq_domain_ops *ops;
	unsigned int i;
	bool eint0_3_parent_only;
	irq_flow_handler_t *handlers;

	for_each_child_of_node(dev->of_node, np) {
		match = of_match_node(s3c24xx_eint_irq_ids, np);
		if (match) {
			eint_np = np;
			eint0_3_parent_only = (bool)match->data;
			break;
		}
	}
	if (!eint_np)
		return -ENODEV;

	eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
	if (!eint_data)
		return -ENOMEM;

	eint_data->drvdata = d;

	handlers = eint0_3_parent_only ? s3c2410_eint_handlers
				       : s3c2412_eint_handlers;
	for (i = 0; i < NUM_EINT_IRQ; ++i) {
		unsigned int irq;

		irq = irq_of_parse_and_map(eint_np, i);
		if (!irq) {
			dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
			return -ENXIO;
		}

		eint_data->parents[i] = irq;
		irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
	}

	bank = d->pin_banks;
	for (i = 0; i < d->nr_banks; ++i, ++bank) {
		struct s3c24xx_eint_domain_data *ddata;
		unsigned int mask;
		unsigned int irq;
		unsigned int pin;

		if (bank->eint_type != EINT_TYPE_WKUP)
			continue;

		ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
		if (!ddata)
			return -ENOMEM;

		ddata->bank = bank;
		ddata->eint_data = eint_data;
		ddata->eint0_3_parent_only = eint0_3_parent_only;

		ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
					       : &s3c24xx_gpg_irq_ops;

		bank->irq_domain = irq_domain_add_linear(bank->of_node,
				bank->nr_pins, ops, ddata);
		if (!bank->irq_domain) {
			dev_err(dev, "wkup irq domain add failed\n");
			return -ENXIO;
		}

		irq = bank->eint_offset;
		mask = bank->eint_mask;
		for (pin = 0; mask; ++pin, mask >>= 1) {
			if (irq >= NUM_EINT)
				break;
			if (!(mask & 1))
				continue;
			eint_data->domains[irq] = bank->irq_domain;
			++irq;
		}
	}

	return 0;
}

static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
	PIN_BANK_A(23, 0x000, "gpa"),
	PIN_BANK_2BIT(11, 0x010, "gpb"),
	PIN_BANK_2BIT(16, 0x020, "gpc"),
	PIN_BANK_2BIT(16, 0x030, "gpd"),
	PIN_BANK_2BIT(16, 0x040, "gpe"),
	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	PIN_BANK_2BIT(11, 0x070, "gph"),
	PIN_BANK_2BIT(13, 0x080, "gpj"),
};

const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
	{
		.pin_banks	= s3c2412_pin_banks,
		.nr_banks	= ARRAY_SIZE(s3c2412_pin_banks),
		.eint_wkup_init = s3c24xx_eint_init,
	},
};

static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
	PIN_BANK_A(27, 0x000, "gpa"),
	PIN_BANK_2BIT(11, 0x010, "gpb"),
	PIN_BANK_2BIT(16, 0x020, "gpc"),
	PIN_BANK_2BIT(16, 0x030, "gpd"),
	PIN_BANK_2BIT(16, 0x040, "gpe"),
	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
	PIN_BANK_2BIT(15, 0x070, "gph"),
	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
	PIN_BANK_2BIT(14, 0x0f0, "gpl"),
	PIN_BANK_2BIT(2, 0x100, "gpm"),
};

const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
	{
		.pin_banks	= s3c2416_pin_banks,
		.nr_banks	= ARRAY_SIZE(s3c2416_pin_banks),
		.eint_wkup_init = s3c24xx_eint_init,
	},
};

static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
	PIN_BANK_A(25, 0x000, "gpa"),
	PIN_BANK_2BIT(11, 0x010, "gpb"),
	PIN_BANK_2BIT(16, 0x020, "gpc"),
	PIN_BANK_2BIT(16, 0x030, "gpd"),
	PIN_BANK_2BIT(16, 0x040, "gpe"),
	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	PIN_BANK_2BIT(11, 0x070, "gph"),
	PIN_BANK_2BIT(13, 0x0d0, "gpj"),
};

const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
	{
		.pin_banks	= s3c2440_pin_banks,
		.nr_banks	= ARRAY_SIZE(s3c2440_pin_banks),
		.eint_wkup_init = s3c24xx_eint_init,
	},
};

static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
	PIN_BANK_A(28, 0x000, "gpa"),
	PIN_BANK_2BIT(11, 0x010, "gpb"),
	PIN_BANK_2BIT(16, 0x020, "gpc"),
	PIN_BANK_2BIT(16, 0x030, "gpd"),
	PIN_BANK_2BIT(16, 0x040, "gpe"),
	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	PIN_BANK_2BIT(15, 0x070, "gph"),
	PIN_BANK_2BIT(16, 0x0d0, "gpj"),
	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
	PIN_BANK_2BIT(15, 0x0f0, "gpl"),
	PIN_BANK_2BIT(2, 0x100, "gpm"),
};

const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
	{
		.pin_banks	= s3c2450_pin_banks,
		.nr_banks	= ARRAY_SIZE(s3c2450_pin_banks),
		.eint_wkup_init = s3c24xx_eint_init,
	},
};
Commit	Line	Data
af99a750 HS	1	/*
	2	* S3C24XX specific support for Samsung pinctrl/gpiolib driver.
	3	*
	4	* Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This file contains the SamsungS3C24XX specific information required by the
	12	* Samsung pinctrl/gpiolib driver. It also includes the implementation of
	13	* external gpio and wakeup interrupt support.
	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/device.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/irqdomain.h>
	20	#include <linux/irq.h>
	21	#include <linux/of_irq.h>
c2c70a79	22	#include <linux/irqchip/chained_irq.h>
af99a750 HS	23	#include <linux/io.h>
	24	#include <linux/slab.h>
	25	#include <linux/err.h>
	26
af99a750 HS	27	#include "pinctrl-samsung.h"
	28
	29	#define NUM_EINT 24
	30	#define NUM_EINT_IRQ 6
	31	#define EINT_MAX_PER_GROUP 8
	32
	33	#define EINTPEND_REG 0xa8
	34	#define EINTMASK_REG 0xa4
	35
	36	#define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
	37	#define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
	38	#define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
	39
	40	#define EINT_LEVEL_LOW 0
	41	#define EINT_LEVEL_HIGH 1
	42	#define EINT_EDGE_FALLING 2
	43	#define EINT_EDGE_RISING 4
	44	#define EINT_EDGE_BOTH 6
	45	#define EINT_MASK 0xf
	46
94ce944b	47	static const struct samsung_pin_bank_type bank_type_1bit = {
af99a750 HS	48	.fld_width = { 1, 1, },
	49	.reg_offset = { 0x00, 0x04, },
	50	};
	51
94ce944b	52	static const struct samsung_pin_bank_type bank_type_2bit = {
af99a750 HS	53	.fld_width = { 2, 1, 2, },
	54	.reg_offset = { 0x00, 0x04, 0x08, },
	55	};
	56
	57	#define PIN_BANK_A(pins, reg, id) \
	58	{ \
	59	.type = &bank_type_1bit, \
	60	.pctl_offset = reg, \
	61	.nr_pins = pins, \
	62	.eint_type = EINT_TYPE_NONE, \
	63	.name = id \
	64	}
	65
	66	#define PIN_BANK_2BIT(pins, reg, id) \
	67	{ \
	68	.type = &bank_type_2bit, \
	69	.pctl_offset = reg, \
	70	.nr_pins = pins, \
	71	.eint_type = EINT_TYPE_NONE, \
	72	.name = id \
	73	}
	74
	75	#define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
	76	{ \
	77	.type = &bank_type_2bit, \
	78	.pctl_offset = reg, \
	79	.nr_pins = pins, \
	80	.eint_type = EINT_TYPE_WKUP, \
	81	.eint_func = 2, \
	82	.eint_mask = emask, \
	83	.eint_offset = eoffs, \
	84	.name = id \
	85	}
	86
	87	/**
	88	* struct s3c24xx_eint_data: EINT common data
	89	* @drvdata: pin controller driver data
	90	* @domains: IRQ domains of particular EINT interrupts
	91	* @parents: mapped parent irqs in the main interrupt controller
	92	*/
	93	struct s3c24xx_eint_data {
	94	struct samsung_pinctrl_drv_data *drvdata;
	95	struct irq_domain *domains[NUM_EINT];
	96	int parents[NUM_EINT_IRQ];
	97	};
	98
	99	/**
	100	* struct s3c24xx_eint_domain_data: per irq-domain data
	101	* @bank: pin bank related to the domain
	102	* @eint_data: common data
	103	* eint0_3_parent_only: live eints 0-3 only in the main intc
	104	*/
	105	struct s3c24xx_eint_domain_data {
	106	struct samsung_pin_bank *bank;
	107	struct s3c24xx_eint_data *eint_data;
	108	bool eint0_3_parent_only;
	109	};
	110
	111	static int s3c24xx_eint_get_trigger(unsigned int type)
	112	{
	113	switch (type) {
	114	case IRQ_TYPE_EDGE_RISING:
	115	return EINT_EDGE_RISING;
	116	break;
117	case IRQ_TYPE_EDGE_FALLING:
118	return EINT_EDGE_FALLING;
119	break;
120	case IRQ_TYPE_EDGE_BOTH:
121	return EINT_EDGE_BOTH;
122	break;
123	case IRQ_TYPE_LEVEL_HIGH:
124	return EINT_LEVEL_HIGH;
125	break;
126	case IRQ_TYPE_LEVEL_LOW:
127	return EINT_LEVEL_LOW;
128	break;
129	default:
130	return -EINVAL;
131	}
132	}
133
f66eb498	134	static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
af99a750 HS	135	{
	136	/* Edge- and level-triggered interrupts need different handlers */
	137	if (type & IRQ_TYPE_EDGE_BOTH)
f66eb498	138	irq_set_handler_locked(d, handle_edge_irq);
af99a750	139	else
f66eb498	140	irq_set_handler_locked(d, handle_level_irq);
af99a750 HS	141	}
	142
	143	static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
	144	struct samsung_pin_bank *bank, int pin)
	145	{
94ce944b	146	const struct samsung_pin_bank_type *bank_type = bank->type;
af99a750 HS	147	unsigned long flags;
	148	void __iomem *reg;
	149	u8 shift;
	150	u32 mask;
	151	u32 val;
	152
	153	/* Make sure that pin is configured as interrupt */
8b1bd11c	154	reg = bank->pctl_base + bank->pctl_offset;
af99a750 HS	155	shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
	156	mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
	157
	158	spin_lock_irqsave(&bank->slock, flags);
	159
	160	val = readl(reg);
	161	val &= ~(mask << shift);
	162	val \|= bank->eint_func << shift;
	163	writel(val, reg);
	164
	165	spin_unlock_irqrestore(&bank->slock, flags);
	166	}
	167
	168	static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
	169	{
	170	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	171	struct samsung_pinctrl_drv_data *d = bank->drvdata;
	172	int index = bank->eint_offset + data->hwirq;
	173	void __iomem *reg;
	174	int trigger;
	175	u8 shift;
	176	u32 val;
	177
	178	trigger = s3c24xx_eint_get_trigger(type);
	179	if (trigger < 0) {
	180	dev_err(d->dev, "unsupported external interrupt type\n");
	181	return -EINVAL;
	182	}
	183
f66eb498	184	s3c24xx_eint_set_handler(data, type);
af99a750 HS	185
af99a750 HS	186	/* Set up interrupt trigger */
8b1bd11c	187	reg = bank->eint_base + EINT_REG(index);
af99a750 HS	188	shift = EINT_OFFS(index);
	189
	190	val = readl(reg);
	191	val &= ~(EINT_MASK << shift);
	192	val \|= trigger << shift;
	193	writel(val, reg);
	194
	195	s3c24xx_eint_set_function(d, bank, data->hwirq);
	196
	197	return 0;
	198	}
	199
	200	/* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
	201
	202	static void s3c2410_eint0_3_ack(struct irq_data *data)
	203	{
	204	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	205	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	206	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	207	int parent_irq = eint_data->parents[data->hwirq];
	208	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
	209
	210	parent_chip->irq_ack(irq_get_irq_data(parent_irq));
	211	}
	212
	213	static void s3c2410_eint0_3_mask(struct irq_data *data)
	214	{
	215	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	216	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	217	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	218	int parent_irq = eint_data->parents[data->hwirq];
	219	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
	220
	221	parent_chip->irq_mask(irq_get_irq_data(parent_irq));
	222	}
	223
	224	static void s3c2410_eint0_3_unmask(struct irq_data *data)
	225	{
	226	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
	227	struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
	228	struct s3c24xx_eint_data *eint_data = ddata->eint_data;
	229	int parent_irq = eint_data->parents[data->hwirq];
	230	struct irq_chip *parent_chip = irq_get_chip(parent_irq);
	231
	232	parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
	233	}
	234
	235	static struct irq_chip s3c2410_eint0_3_chip = {
	236	.name = "s3c2410-eint0_3",
	237	.irq_ack = s3c2410_eint0_3_ack,
	238	.irq_mask = s3c2410_eint0_3_mask,
	239	.irq_unmask = s3c2410_eint0_3_unmask,
	240	.irq_set_type = s3c24xx_eint_type,
	241	};
	242
bd0b9ac4	243	static void s3c2410_demux_eint0_3(struct irq_desc *desc)
af99a750 HS	244	{
af99a750 HS	245	struct irq_data *data = irq_desc_get_irq_data(desc);
5663bb27	246	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
af99a750 HS	247	unsigned int virq;
	248
	249	/* the first 4 eints have a simple 1 to 1 mapping */
	250	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
	251	/* Something must be really wrong if an unmapped EINT is unmasked */
	252	BUG_ON(!virq);
	253
	254	generic_handle_irq(virq);
	255	}
	256
	257	/* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
	258
	259	static void s3c2412_eint0_3_ack(struct irq_data *data)
	260	{
	261	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	262
af99a750 HS	263	unsigned long bitval = 1UL << data->hwirq;
8b1bd11c	264	writel(bitval, bank->eint_base + EINTPEND_REG);
af99a750 HS	265	}
	266
	267	static void s3c2412_eint0_3_mask(struct irq_data *data)
	268	{
	269	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	270	unsigned long mask;
af99a750 HS	271
8b1bd11c	272	mask = readl(bank->eint_base + EINTMASK_REG);
af99a750	273	mask \|= (1UL << data->hwirq);
8b1bd11c	274	writel(mask, bank->eint_base + EINTMASK_REG);
af99a750 HS	275	}
	276
	277	static void s3c2412_eint0_3_unmask(struct irq_data *data)
	278	{
	279	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	280	unsigned long mask;
af99a750 HS	281
8b1bd11c	282	mask = readl(bank->eint_base + EINTMASK_REG);
af99a750	283	mask &= ~(1UL << data->hwirq);
8b1bd11c	284	writel(mask, bank->eint_base + EINTMASK_REG);
af99a750 HS	285	}
	286
	287	static struct irq_chip s3c2412_eint0_3_chip = {
	288	.name = "s3c2412-eint0_3",
	289	.irq_ack = s3c2412_eint0_3_ack,
	290	.irq_mask = s3c2412_eint0_3_mask,
	291	.irq_unmask = s3c2412_eint0_3_unmask,
	292	.irq_set_type = s3c24xx_eint_type,
	293	};
	294
bd0b9ac4	295	static void s3c2412_demux_eint0_3(struct irq_desc *desc)
af99a750	296	{
5663bb27	297	struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
af99a750	298	struct irq_data *data = irq_desc_get_irq_data(desc);
5663bb27	299	struct irq_chip *chip = irq_data_get_irq_chip(data);
af99a750 HS	300	unsigned int virq;
	301
	302	chained_irq_enter(chip, desc);
	303
	304	/* the first 4 eints have a simple 1 to 1 mapping */
	305	virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
	306	/* Something must be really wrong if an unmapped EINT is unmasked */
	307	BUG_ON(!virq);
	308
	309	generic_handle_irq(virq);
	310
	311	chained_irq_exit(chip, desc);
	312	}
	313
	314	/* Handling of all other eints */
	315
	316	static void s3c24xx_eint_ack(struct irq_data *data)
	317	{
	318	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	319	unsigned char index = bank->eint_offset + data->hwirq;
af99a750 HS	320
8b1bd11c	321	writel(1UL << index, bank->eint_base + EINTPEND_REG);
af99a750 HS	322	}
	323
	324	static void s3c24xx_eint_mask(struct irq_data *data)
	325	{
	326	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	327	unsigned char index = bank->eint_offset + data->hwirq;
	328	unsigned long mask;
	329
8b1bd11c	330	mask = readl(bank->eint_base + EINTMASK_REG);
af99a750	331	mask \|= (1UL << index);
8b1bd11c	332	writel(mask, bank->eint_base + EINTMASK_REG);
af99a750 HS	333	}
	334
	335	static void s3c24xx_eint_unmask(struct irq_data *data)
	336	{
	337	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
af99a750 HS	338	unsigned char index = bank->eint_offset + data->hwirq;
	339	unsigned long mask;
	340
8b1bd11c	341	mask = readl(bank->eint_base + EINTMASK_REG);
af99a750	342	mask &= ~(1UL << index);
8b1bd11c	343	writel(mask, bank->eint_base + EINTMASK_REG);
af99a750 HS	344	}
	345
	346	static struct irq_chip s3c24xx_eint_chip = {
	347	.name = "s3c-eint",
	348	.irq_ack = s3c24xx_eint_ack,
	349	.irq_mask = s3c24xx_eint_mask,
	350	.irq_unmask = s3c24xx_eint_unmask,
	351	.irq_set_type = s3c24xx_eint_type,
	352	};
	353
5663bb27	354	static inline void s3c24xx_demux_eint(struct irq_desc *desc,
af99a750 HS	355	u32 offset, u32 range)
af99a750 HS	356	{
5663bb27	357	struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
fa84b52c	358	struct irq_chip *chip = irq_desc_get_chip(desc);
8b1bd11c CC	359	struct irq_data *irqd = irq_desc_get_irq_data(desc);
8b1bd11c CC	360	struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
af99a750 HS	361	unsigned int pend, mask;
	362
	363	chained_irq_enter(chip, desc);
	364
8b1bd11c CC	365	pend = readl(bank->eint_base + EINTPEND_REG);
8b1bd11c CC	366	mask = readl(bank->eint_base + EINTMASK_REG);
af99a750 HS	367
	368	pend &= ~mask;
	369	pend &= range;
	370
	371	while (pend) {
5663bb27	372	unsigned int virq, irq;
af99a750 HS	373
	374	irq = __ffs(pend);
	375	pend &= ~(1 << irq);
	376	virq = irq_linear_revmap(data->domains[irq], irq - offset);
	377	/* Something is really wrong if an unmapped EINT is unmasked */
	378	BUG_ON(!virq);
	379
	380	generic_handle_irq(virq);
	381	}
	382
	383	chained_irq_exit(chip, desc);
	384	}
	385
bd0b9ac4	386	static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
af99a750	387	{
5663bb27	388	s3c24xx_demux_eint(desc, 0, 0xf0);
af99a750 HS	389	}
af99a750 HS	390
bd0b9ac4	391	static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
af99a750	392	{
5663bb27	393	s3c24xx_demux_eint(desc, 8, 0xffff00);
af99a750 HS	394	}
	395
	396	static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
	397	s3c2410_demux_eint0_3,
	398	s3c2410_demux_eint0_3,
	399	s3c2410_demux_eint0_3,
	400	s3c2410_demux_eint0_3,
	401	s3c24xx_demux_eint4_7,
	402	s3c24xx_demux_eint8_23,
	403	};
	404
	405	static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
	406	s3c2412_demux_eint0_3,
	407	s3c2412_demux_eint0_3,
	408	s3c2412_demux_eint0_3,
	409	s3c2412_demux_eint0_3,
	410	s3c24xx_demux_eint4_7,
	411	s3c24xx_demux_eint8_23,
	412	};
	413
	414	static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
	415	irq_hw_number_t hw)
	416	{
	417	struct s3c24xx_eint_domain_data *ddata = h->host_data;
	418	struct samsung_pin_bank *bank = ddata->bank;
	419
	420	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
	421	return -EINVAL;
	422
	423	if (hw <= 3) {
	424	if (ddata->eint0_3_parent_only)
	425	irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
	426	handle_edge_irq);
	427	else
	428	irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
	429	handle_edge_irq);
	430	} else {
	431	irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
	432	handle_edge_irq);
	433	}
	434	irq_set_chip_data(virq, bank);
af99a750 HS	435	return 0;
	436	}
	437
	438	static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
	439	.map = s3c24xx_gpf_irq_map,
	440	.xlate = irq_domain_xlate_twocell,
	441	};
	442
	443	static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
	444	irq_hw_number_t hw)
	445	{
	446	struct s3c24xx_eint_domain_data *ddata = h->host_data;
	447	struct samsung_pin_bank *bank = ddata->bank;
	448
	449	if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
	450	return -EINVAL;
	451
	452	irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
	453	irq_set_chip_data(virq, bank);
af99a750 HS	454	return 0;
	455	}
	456
	457	static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
	458	.map = s3c24xx_gpg_irq_map,
	459	.xlate = irq_domain_xlate_twocell,
	460	};
	461
	462	static const struct of_device_id s3c24xx_eint_irq_ids[] = {
	463	{ .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
	464	{ .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
	465	{ }
	466	};
	467
	468	static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
	469	{
	470	struct device *dev = d->dev;
	471	const struct of_device_id *match;
	472	struct device_node *eint_np = NULL;
	473	struct device_node *np;
	474	struct samsung_pin_bank *bank;
	475	struct s3c24xx_eint_data *eint_data;
	476	const struct irq_domain_ops *ops;
	477	unsigned int i;
	478	bool eint0_3_parent_only;
	479	irq_flow_handler_t *handlers;
	480
	481	for_each_child_of_node(dev->of_node, np) {
	482	match = of_match_node(s3c24xx_eint_irq_ids, np);
	483	if (match) {
	484	eint_np = np;
	485	eint0_3_parent_only = (bool)match->data;
	486	break;
	487	}
	488	}
	489	if (!eint_np)
	490	return -ENODEV;
	491
	492	eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
	493	if (!eint_data)
	494	return -ENOMEM;
	495
	496	eint_data->drvdata = d;
	497
	498	handlers = eint0_3_parent_only ? s3c2410_eint_handlers
	499	: s3c2412_eint_handlers;
	500	for (i = 0; i < NUM_EINT_IRQ; ++i) {
	501	unsigned int irq;
	502
	503	irq = irq_of_parse_and_map(eint_np, i);
	504	if (!irq) {
	505	dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
	506	return -ENXIO;
	507	}
	508
	509	eint_data->parents[i] = irq;
0cfc45cf	510	irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
af99a750 HS	511	}
af99a750 HS	512
1bf00d7a TF	513	bank = d->pin_banks;
1bf00d7a TF	514	for (i = 0; i < d->nr_banks; ++i, ++bank) {
af99a750 HS	515	struct s3c24xx_eint_domain_data *ddata;
	516	unsigned int mask;
	517	unsigned int irq;
	518	unsigned int pin;
	519
	520	if (bank->eint_type != EINT_TYPE_WKUP)
	521	continue;
	522
	523	ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
	524	if (!ddata)
	525	return -ENOMEM;
	526
	527	ddata->bank = bank;
	528	ddata->eint_data = eint_data;
	529	ddata->eint0_3_parent_only = eint0_3_parent_only;
	530
	531	ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
	532	: &s3c24xx_gpg_irq_ops;
	533
	534	bank->irq_domain = irq_domain_add_linear(bank->of_node,
	535	bank->nr_pins, ops, ddata);
	536	if (!bank->irq_domain) {
	537	dev_err(dev, "wkup irq domain add failed\n");
	538	return -ENXIO;
	539	}
	540
	541	irq = bank->eint_offset;
	542	mask = bank->eint_mask;
	543	for (pin = 0; mask; ++pin, mask >>= 1) {
774e2d98	544	if (irq >= NUM_EINT)
af99a750 HS	545	break;
	546	if (!(mask & 1))
	547	continue;
	548	eint_data->domains[irq] = bank->irq_domain;
	549	++irq;
	550	}
	551	}
	552
	553	return 0;
	554	}
	555
8100cf47	556	static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
af99a750 HS	557	PIN_BANK_A(23, 0x000, "gpa"),
	558	PIN_BANK_2BIT(11, 0x010, "gpb"),
	559	PIN_BANK_2BIT(16, 0x020, "gpc"),
	560	PIN_BANK_2BIT(16, 0x030, "gpd"),
	561	PIN_BANK_2BIT(16, 0x040, "gpe"),
	562	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	563	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	564	PIN_BANK_2BIT(11, 0x070, "gph"),
	565	PIN_BANK_2BIT(13, 0x080, "gpj"),
	566	};
	567
1bf00d7a	568	const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
af99a750 HS	569	{
	570	.pin_banks = s3c2412_pin_banks,
	571	.nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
	572	.eint_wkup_init = s3c24xx_eint_init,
af99a750 HS	573	},
	574	};
	575
8100cf47	576	static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
af99a750 HS	577	PIN_BANK_A(27, 0x000, "gpa"),
	578	PIN_BANK_2BIT(11, 0x010, "gpb"),
	579	PIN_BANK_2BIT(16, 0x020, "gpc"),
	580	PIN_BANK_2BIT(16, 0x030, "gpd"),
	581	PIN_BANK_2BIT(16, 0x040, "gpe"),
	582	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	583	PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
	584	PIN_BANK_2BIT(15, 0x070, "gph"),
	585	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
	586	PIN_BANK_2BIT(14, 0x0f0, "gpl"),
	587	PIN_BANK_2BIT(2, 0x100, "gpm"),
	588	};
	589
1bf00d7a	590	const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
af99a750 HS	591	{
	592	.pin_banks = s3c2416_pin_banks,
	593	.nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
	594	.eint_wkup_init = s3c24xx_eint_init,
af99a750 HS	595	},
	596	};
	597
8100cf47	598	static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
af99a750 HS	599	PIN_BANK_A(25, 0x000, "gpa"),
	600	PIN_BANK_2BIT(11, 0x010, "gpb"),
	601	PIN_BANK_2BIT(16, 0x020, "gpc"),
	602	PIN_BANK_2BIT(16, 0x030, "gpd"),
	603	PIN_BANK_2BIT(16, 0x040, "gpe"),
	604	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	605	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	606	PIN_BANK_2BIT(11, 0x070, "gph"),
	607	PIN_BANK_2BIT(13, 0x0d0, "gpj"),
	608	};
	609
1bf00d7a	610	const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
af99a750 HS	611	{
	612	.pin_banks = s3c2440_pin_banks,
	613	.nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
	614	.eint_wkup_init = s3c24xx_eint_init,
af99a750 HS	615	},
	616	};
	617
8100cf47	618	static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
af99a750 HS	619	PIN_BANK_A(28, 0x000, "gpa"),
	620	PIN_BANK_2BIT(11, 0x010, "gpb"),
	621	PIN_BANK_2BIT(16, 0x020, "gpc"),
	622	PIN_BANK_2BIT(16, 0x030, "gpd"),
	623	PIN_BANK_2BIT(16, 0x040, "gpe"),
	624	PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
	625	PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
	626	PIN_BANK_2BIT(15, 0x070, "gph"),
	627	PIN_BANK_2BIT(16, 0x0d0, "gpj"),
	628	PIN_BANK_2BIT(16, 0x0e0, "gpk"),
	629	PIN_BANK_2BIT(15, 0x0f0, "gpl"),
	630	PIN_BANK_2BIT(2, 0x100, "gpm"),
	631	};
	632
1bf00d7a	633	const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
af99a750 HS	634	{
	635	.pin_banks = s3c2450_pin_banks,
	636	.nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
	637	.eint_wkup_init = s3c24xx_eint_init,
af99a750 HS	638	},
af99a750 HS	639	};