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Commit | Line | Data |
---|---|---|
2967dab1 | 1 | /* |
a43647b6 PG |
2 | * Pin Control and GPIO driver for SuperH Pin Function Controller. |
3 | * | |
4 | * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart | |
2967dab1 MD |
5 | * |
6 | * Copyright (C) 2008 Magnus Damm | |
b3c185a7 | 7 | * Copyright (C) 2009 - 2012 Paul Mundt |
2967dab1 MD |
8 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
c6193eac LP |
13 | |
14 | #define DRV_NAME "sh-pfc" | |
b72421d8 | 15 | |
90efde22 | 16 | #include <linux/bitops.h> |
2967dab1 | 17 | #include <linux/err.h> |
90efde22 | 18 | #include <linux/errno.h> |
2967dab1 | 19 | #include <linux/io.h> |
b0e10211 | 20 | #include <linux/ioport.h> |
90efde22 | 21 | #include <linux/kernel.h> |
a43647b6 | 22 | #include <linux/init.h> |
fe1c9a82 LP |
23 | #include <linux/of.h> |
24 | #include <linux/of_device.h> | |
ca5481c6 | 25 | #include <linux/pinctrl/machine.h> |
c6193eac | 26 | #include <linux/platform_device.h> |
90efde22 | 27 | #include <linux/slab.h> |
b0e10211 | 28 | |
f9165132 LP |
29 | #include "core.h" |
30 | ||
70c8f01a LP |
31 | static int sh_pfc_map_resources(struct sh_pfc *pfc, |
32 | struct platform_device *pdev) | |
b0e10211 | 33 | { |
c7977ec4 | 34 | unsigned int num_windows, num_irqs; |
70c8f01a LP |
35 | struct sh_pfc_window *windows; |
36 | unsigned int *irqs = NULL; | |
b0e10211 | 37 | struct resource *res; |
70c8f01a | 38 | unsigned int i; |
c7977ec4 | 39 | int irq; |
70c8f01a LP |
40 | |
41 | /* Count the MEM and IRQ resources. */ | |
c7977ec4 GU |
42 | for (num_windows = 0;; num_windows++) { |
43 | res = platform_get_resource(pdev, IORESOURCE_MEM, num_windows); | |
44 | if (!res) | |
70c8f01a | 45 | break; |
c7977ec4 GU |
46 | } |
47 | for (num_irqs = 0;; num_irqs++) { | |
48 | irq = platform_get_irq(pdev, num_irqs); | |
49 | if (irq == -EPROBE_DEFER) | |
50 | return irq; | |
51 | if (irq < 0) | |
70c8f01a | 52 | break; |
70c8f01a | 53 | } |
b0e10211 | 54 | |
70c8f01a | 55 | if (num_windows == 0) |
bee9f22b | 56 | return -EINVAL; |
b0e10211 | 57 | |
70c8f01a LP |
58 | /* Allocate memory windows and IRQs arrays. */ |
59 | windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows), | |
60 | GFP_KERNEL); | |
61 | if (windows == NULL) | |
1724acfd | 62 | return -ENOMEM; |
b0e10211 | 63 | |
70c8f01a LP |
64 | pfc->num_windows = num_windows; |
65 | pfc->windows = windows; | |
973931ae | 66 | |
70c8f01a LP |
67 | if (num_irqs) { |
68 | irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs), | |
69 | GFP_KERNEL); | |
70 | if (irqs == NULL) | |
1724acfd | 71 | return -ENOMEM; |
70c8f01a LP |
72 | |
73 | pfc->num_irqs = num_irqs; | |
74 | pfc->irqs = irqs; | |
75 | } | |
76 | ||
77 | /* Fill them. */ | |
c7977ec4 GU |
78 | for (i = 0; i < num_windows; i++) { |
79 | res = platform_get_resource(pdev, IORESOURCE_MEM, i); | |
80 | windows->phys = res->start; | |
81 | windows->size = resource_size(res); | |
82 | windows->virt = devm_ioremap_resource(pfc->dev, res); | |
83 | if (IS_ERR(windows->virt)) | |
84 | return -ENOMEM; | |
85 | windows++; | |
b0e10211 | 86 | } |
c7977ec4 GU |
87 | for (i = 0; i < num_irqs; i++) |
88 | *irqs++ = platform_get_irq(pdev, i); | |
b0e10211 MD |
89 | |
90 | return 0; | |
b0e10211 MD |
91 | } |
92 | ||
1f34de05 | 93 | static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg) |
b0e10211 | 94 | { |
4aeacd5b | 95 | struct sh_pfc_window *window; |
1f34de05 | 96 | phys_addr_t address = reg; |
bee9f22b | 97 | unsigned int i; |
b0e10211 MD |
98 | |
99 | /* scan through physical windows and convert address */ | |
bee9f22b | 100 | for (i = 0; i < pfc->num_windows; i++) { |
5b46ac3a | 101 | window = pfc->windows + i; |
b0e10211 MD |
102 | |
103 | if (address < window->phys) | |
104 | continue; | |
105 | ||
106 | if (address >= (window->phys + window->size)) | |
107 | continue; | |
108 | ||
109 | return window->virt + (address - window->phys); | |
110 | } | |
111 | ||
bee9f22b | 112 | BUG(); |
1960d580 | 113 | return NULL; |
b0e10211 | 114 | } |
2967dab1 | 115 | |
1a0039dc | 116 | int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin) |
934cb02b | 117 | { |
63d57383 LP |
118 | unsigned int offset; |
119 | unsigned int i; | |
120 | ||
acac8ed5 LP |
121 | for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) { |
122 | const struct sh_pfc_pin_range *range = &pfc->ranges[i]; | |
63d57383 LP |
123 | |
124 | if (pin <= range->end) | |
acac8ed5 LP |
125 | return pin >= range->start |
126 | ? offset + pin - range->start : -1; | |
63d57383 | 127 | |
acac8ed5 | 128 | offset += range->end - range->start + 1; |
63d57383 LP |
129 | } |
130 | ||
b705c054 | 131 | return -EINVAL; |
934cb02b LP |
132 | } |
133 | ||
533743dc | 134 | static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r) |
2967dab1 MD |
135 | { |
136 | if (enum_id < r->begin) | |
137 | return 0; | |
138 | ||
139 | if (enum_id > r->end) | |
140 | return 0; | |
141 | ||
142 | return 1; | |
143 | } | |
144 | ||
cef28a28 | 145 | u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) |
3292094e MD |
146 | { |
147 | switch (reg_width) { | |
148 | case 8: | |
b0e10211 | 149 | return ioread8(mapped_reg); |
3292094e | 150 | case 16: |
b0e10211 | 151 | return ioread16(mapped_reg); |
3292094e | 152 | case 32: |
b0e10211 | 153 | return ioread32(mapped_reg); |
3292094e MD |
154 | } |
155 | ||
156 | BUG(); | |
157 | return 0; | |
158 | } | |
159 | ||
cef28a28 | 160 | void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, |
fc88936a | 161 | u32 data) |
3292094e MD |
162 | { |
163 | switch (reg_width) { | |
164 | case 8: | |
b0e10211 | 165 | iowrite8(data, mapped_reg); |
3292094e MD |
166 | return; |
167 | case 16: | |
b0e10211 | 168 | iowrite16(data, mapped_reg); |
3292094e MD |
169 | return; |
170 | case 32: | |
b0e10211 | 171 | iowrite32(data, mapped_reg); |
3292094e MD |
172 | return; |
173 | } | |
174 | ||
175 | BUG(); | |
176 | } | |
177 | ||
4aeacd5b | 178 | static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, |
cd3c1bee | 179 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 180 | unsigned int in_pos, |
fc88936a | 181 | void __iomem **mapped_regp, u32 *maskp, |
cef28a28 | 182 | unsigned int *posp) |
2967dab1 | 183 | { |
8d72a7fc | 184 | unsigned int k; |
f78a26f5 | 185 | |
4aeacd5b | 186 | *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); |
2967dab1 | 187 | |
f78a26f5 MD |
188 | if (crp->field_width) { |
189 | *maskp = (1 << crp->field_width) - 1; | |
190 | *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); | |
191 | } else { | |
192 | *maskp = (1 << crp->var_field_width[in_pos]) - 1; | |
193 | *posp = crp->reg_width; | |
194 | for (k = 0; k <= in_pos; k++) | |
195 | *posp -= crp->var_field_width[k]; | |
196 | } | |
18925e11 MD |
197 | } |
198 | ||
4aeacd5b | 199 | static void sh_pfc_write_config_reg(struct sh_pfc *pfc, |
cd3c1bee | 200 | const struct pinmux_cfg_reg *crp, |
cef28a28 | 201 | unsigned int field, u32 value) |
0fc64cc0 | 202 | { |
18925e11 | 203 | void __iomem *mapped_reg; |
cef28a28 | 204 | unsigned int pos; |
fc88936a | 205 | u32 mask, data; |
0fc64cc0 | 206 | |
4aeacd5b | 207 | sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); |
2967dab1 | 208 | |
1f34de05 | 209 | dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, " |
dc700715 | 210 | "r_width = %u, f_width = %u\n", |
9a643c9a | 211 | crp->reg, value, field, crp->reg_width, crp->field_width); |
0fc64cc0 MD |
212 | |
213 | mask = ~(mask << pos); | |
214 | value = value << pos; | |
2967dab1 | 215 | |
4aeacd5b | 216 | data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); |
e499ada8 MD |
217 | data &= mask; |
218 | data |= value; | |
219 | ||
19bb7fe3 | 220 | if (pfc->info->unlock_reg) |
4aeacd5b | 221 | sh_pfc_write_raw_reg( |
19bb7fe3 | 222 | sh_pfc_phys_to_virt(pfc, pfc->info->unlock_reg), 32, |
4aeacd5b | 223 | ~data); |
e499ada8 | 224 | |
4aeacd5b | 225 | sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); |
2967dab1 MD |
226 | } |
227 | ||
533743dc | 228 | static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id, |
cef28a28 GU |
229 | const struct pinmux_cfg_reg **crp, |
230 | unsigned int *fieldp, u32 *valuep) | |
2967dab1 | 231 | { |
cef28a28 | 232 | unsigned int k = 0; |
2967dab1 | 233 | |
2967dab1 | 234 | while (1) { |
cef28a28 GU |
235 | const struct pinmux_cfg_reg *config_reg = |
236 | pfc->info->cfg_regs + k; | |
237 | unsigned int r_width = config_reg->reg_width; | |
238 | unsigned int f_width = config_reg->field_width; | |
239 | unsigned int curr_width; | |
240 | unsigned int bit_pos; | |
241 | unsigned int pos = 0; | |
242 | unsigned int m = 0; | |
2967dab1 MD |
243 | |
244 | if (!r_width) | |
245 | break; | |
f78a26f5 | 246 | |
f78a26f5 | 247 | for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) { |
cef28a28 GU |
248 | u32 ncomb; |
249 | u32 n; | |
250 | ||
f78a26f5 MD |
251 | if (f_width) |
252 | curr_width = f_width; | |
253 | else | |
254 | curr_width = config_reg->var_field_width[m]; | |
255 | ||
256 | ncomb = 1 << curr_width; | |
257 | for (n = 0; n < ncomb; n++) { | |
258 | if (config_reg->enum_ids[pos + n] == enum_id) { | |
259 | *crp = config_reg; | |
260 | *fieldp = m; | |
261 | *valuep = n; | |
f78a26f5 MD |
262 | return 0; |
263 | } | |
2967dab1 | 264 | } |
f78a26f5 MD |
265 | pos += ncomb; |
266 | m++; | |
2967dab1 MD |
267 | } |
268 | k++; | |
269 | } | |
270 | ||
b705c054 | 271 | return -EINVAL; |
2967dab1 MD |
272 | } |
273 | ||
533743dc LP |
274 | static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos, |
275 | u16 *enum_idp) | |
2967dab1 | 276 | { |
b8b47d67 | 277 | const u16 *data = pfc->info->pinmux_data; |
8d72a7fc | 278 | unsigned int k; |
2967dab1 | 279 | |
2967dab1 MD |
280 | if (pos) { |
281 | *enum_idp = data[pos + 1]; | |
282 | return pos + 1; | |
283 | } | |
284 | ||
b8b47d67 | 285 | for (k = 0; k < pfc->info->pinmux_data_size; k++) { |
a68fdca9 | 286 | if (data[k] == mark) { |
2967dab1 MD |
287 | *enum_idp = data[k + 1]; |
288 | return k + 1; | |
289 | } | |
290 | } | |
291 | ||
9a643c9a LP |
292 | dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n", |
293 | mark); | |
b705c054 | 294 | return -EINVAL; |
2967dab1 MD |
295 | } |
296 | ||
861601de | 297 | int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type) |
2967dab1 | 298 | { |
cd3c1bee | 299 | const struct pinmux_range *range; |
cef28a28 | 300 | int pos = 0; |
2967dab1 MD |
301 | |
302 | switch (pinmux_type) { | |
e3c47051 | 303 | case PINMUX_TYPE_GPIO: |
2967dab1 MD |
304 | case PINMUX_TYPE_FUNCTION: |
305 | range = NULL; | |
306 | break; | |
307 | ||
308 | case PINMUX_TYPE_OUTPUT: | |
19bb7fe3 | 309 | range = &pfc->info->output; |
2967dab1 MD |
310 | break; |
311 | ||
312 | case PINMUX_TYPE_INPUT: | |
19bb7fe3 | 313 | range = &pfc->info->input; |
2967dab1 MD |
314 | break; |
315 | ||
2967dab1 | 316 | default: |
b705c054 | 317 | return -EINVAL; |
2967dab1 MD |
318 | } |
319 | ||
e3c47051 | 320 | /* Iterate over all the configuration fields we need to update. */ |
2967dab1 | 321 | while (1) { |
cef28a28 GU |
322 | const struct pinmux_cfg_reg *cr; |
323 | unsigned int field; | |
324 | u16 enum_id; | |
325 | u32 value; | |
326 | int in_range; | |
327 | int ret; | |
328 | ||
a68fdca9 | 329 | pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id); |
b705c054 LP |
330 | if (pos < 0) |
331 | return pos; | |
2967dab1 MD |
332 | |
333 | if (!enum_id) | |
334 | break; | |
335 | ||
e3c47051 LP |
336 | /* Check if the configuration field selects a function. If it |
337 | * doesn't, skip the field if it's not applicable to the | |
338 | * requested pinmux type. | |
339 | */ | |
19bb7fe3 | 340 | in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); |
50dd3145 | 341 | if (!in_range) { |
e3c47051 LP |
342 | if (pinmux_type == PINMUX_TYPE_FUNCTION) { |
343 | /* Functions are allowed to modify all | |
344 | * fields. | |
345 | */ | |
346 | in_range = 1; | |
347 | } else if (pinmux_type != PINMUX_TYPE_GPIO) { | |
348 | /* Input/output types can only modify fields | |
349 | * that correspond to their respective ranges. | |
50dd3145 | 350 | */ |
4aeacd5b | 351 | in_range = sh_pfc_enum_in_range(enum_id, range); |
50dd3145 MD |
352 | |
353 | /* | |
354 | * special case pass through for fixed | |
355 | * input-only or output-only pins without | |
356 | * function enum register association. | |
357 | */ | |
358 | if (in_range && enum_id == range->force) | |
359 | continue; | |
50dd3145 | 360 | } |
e3c47051 | 361 | /* GPIOs are only allowed to modify function fields. */ |
42eed42b MD |
362 | } |
363 | ||
2967dab1 MD |
364 | if (!in_range) |
365 | continue; | |
366 | ||
b705c054 LP |
367 | ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value); |
368 | if (ret < 0) | |
369 | return ret; | |
2967dab1 | 370 | |
861601de | 371 | sh_pfc_write_config_reg(pfc, cr, field, value); |
2967dab1 MD |
372 | } |
373 | ||
374 | return 0; | |
2967dab1 MD |
375 | } |
376 | ||
acac8ed5 LP |
377 | static int sh_pfc_init_ranges(struct sh_pfc *pfc) |
378 | { | |
379 | struct sh_pfc_pin_range *range; | |
380 | unsigned int nr_ranges; | |
381 | unsigned int i; | |
382 | ||
383 | if (pfc->info->pins[0].pin == (u16)-1) { | |
384 | /* Pin number -1 denotes that the SoC doesn't report pin numbers | |
385 | * in its pin arrays yet. Consider the pin numbers range as | |
386 | * continuous and allocate a single range. | |
387 | */ | |
388 | pfc->nr_ranges = 1; | |
389 | pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges), | |
390 | GFP_KERNEL); | |
391 | if (pfc->ranges == NULL) | |
392 | return -ENOMEM; | |
393 | ||
394 | pfc->ranges->start = 0; | |
395 | pfc->ranges->end = pfc->info->nr_pins - 1; | |
396 | pfc->nr_gpio_pins = pfc->info->nr_pins; | |
397 | ||
398 | return 0; | |
399 | } | |
400 | ||
4f82e3ee LP |
401 | /* Count, allocate and fill the ranges. The PFC SoC data pins array must |
402 | * be sorted by pin numbers, and pins without a GPIO port must come | |
403 | * last. | |
404 | */ | |
acac8ed5 LP |
405 | for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) { |
406 | if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1) | |
407 | nr_ranges++; | |
408 | } | |
409 | ||
410 | pfc->nr_ranges = nr_ranges; | |
411 | pfc->ranges = devm_kzalloc(pfc->dev, sizeof(*pfc->ranges) * nr_ranges, | |
412 | GFP_KERNEL); | |
413 | if (pfc->ranges == NULL) | |
414 | return -ENOMEM; | |
415 | ||
416 | range = pfc->ranges; | |
417 | range->start = pfc->info->pins[0].pin; | |
418 | ||
419 | for (i = 1; i < pfc->info->nr_pins; ++i) { | |
4f82e3ee LP |
420 | if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1) |
421 | continue; | |
422 | ||
423 | range->end = pfc->info->pins[i-1].pin; | |
424 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) | |
425 | pfc->nr_gpio_pins = range->end + 1; | |
426 | ||
427 | range++; | |
428 | range->start = pfc->info->pins[i].pin; | |
acac8ed5 LP |
429 | } |
430 | ||
431 | range->end = pfc->info->pins[i-1].pin; | |
4f82e3ee LP |
432 | if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO)) |
433 | pfc->nr_gpio_pins = range->end + 1; | |
acac8ed5 LP |
434 | |
435 | return 0; | |
436 | } | |
437 | ||
fe1c9a82 LP |
438 | #ifdef CONFIG_OF |
439 | static const struct of_device_id sh_pfc_of_table[] = { | |
1e7d5d84 NS |
440 | #ifdef CONFIG_PINCTRL_PFC_EMEV2 |
441 | { | |
442 | .compatible = "renesas,pfc-emev2", | |
443 | .data = &emev2_pinmux_info, | |
444 | }, | |
445 | #endif | |
fe1c9a82 LP |
446 | #ifdef CONFIG_PINCTRL_PFC_R8A73A4 |
447 | { | |
448 | .compatible = "renesas,pfc-r8a73a4", | |
449 | .data = &r8a73a4_pinmux_info, | |
450 | }, | |
451 | #endif | |
452 | #ifdef CONFIG_PINCTRL_PFC_R8A7740 | |
453 | { | |
454 | .compatible = "renesas,pfc-r8a7740", | |
455 | .data = &r8a7740_pinmux_info, | |
456 | }, | |
457 | #endif | |
458 | #ifdef CONFIG_PINCTRL_PFC_R8A7778 | |
459 | { | |
460 | .compatible = "renesas,pfc-r8a7778", | |
461 | .data = &r8a7778_pinmux_info, | |
462 | }, | |
463 | #endif | |
464 | #ifdef CONFIG_PINCTRL_PFC_R8A7779 | |
465 | { | |
466 | .compatible = "renesas,pfc-r8a7779", | |
467 | .data = &r8a7779_pinmux_info, | |
468 | }, | |
469 | #endif | |
470 | #ifdef CONFIG_PINCTRL_PFC_R8A7790 | |
471 | { | |
472 | .compatible = "renesas,pfc-r8a7790", | |
473 | .data = &r8a7790_pinmux_info, | |
474 | }, | |
475 | #endif | |
50884519 HN |
476 | #ifdef CONFIG_PINCTRL_PFC_R8A7791 |
477 | { | |
478 | .compatible = "renesas,pfc-r8a7791", | |
479 | .data = &r8a7791_pinmux_info, | |
480 | }, | |
481 | #endif | |
19e1e98f UH |
482 | #ifdef CONFIG_PINCTRL_PFC_R8A7793 |
483 | { | |
484 | .compatible = "renesas,pfc-r8a7793", | |
485 | .data = &r8a7793_pinmux_info, | |
486 | }, | |
487 | #endif | |
43c4436e HN |
488 | #ifdef CONFIG_PINCTRL_PFC_R8A7794 |
489 | { | |
490 | .compatible = "renesas,pfc-r8a7794", | |
491 | .data = &r8a7794_pinmux_info, | |
492 | }, | |
493 | #endif | |
0b0ffc96 TK |
494 | #ifdef CONFIG_PINCTRL_PFC_R8A7795 |
495 | { | |
496 | .compatible = "renesas,pfc-r8a7795", | |
497 | .data = &r8a7795_pinmux_info, | |
498 | }, | |
499 | #endif | |
fe1c9a82 LP |
500 | #ifdef CONFIG_PINCTRL_PFC_SH73A0 |
501 | { | |
502 | .compatible = "renesas,pfc-sh73a0", | |
503 | .data = &sh73a0_pinmux_info, | |
504 | }, | |
505 | #endif | |
506 | { }, | |
507 | }; | |
fe1c9a82 LP |
508 | #endif |
509 | ||
c6193eac | 510 | static int sh_pfc_probe(struct platform_device *pdev) |
2967dab1 | 511 | { |
fe1c9a82 LP |
512 | const struct platform_device_id *platid = platform_get_device_id(pdev); |
513 | #ifdef CONFIG_OF | |
514 | struct device_node *np = pdev->dev.of_node; | |
515 | #endif | |
cd3c1bee | 516 | const struct sh_pfc_soc_info *info; |
c6193eac | 517 | struct sh_pfc *pfc; |
0fc64cc0 | 518 | int ret; |
2967dab1 | 519 | |
fe1c9a82 LP |
520 | #ifdef CONFIG_OF |
521 | if (np) | |
331207af | 522 | info = of_device_get_match_data(&pdev->dev); |
fe1c9a82 LP |
523 | else |
524 | #endif | |
525 | info = platid ? (const void *)platid->driver_data : NULL; | |
526 | ||
19bb7fe3 | 527 | if (info == NULL) |
c6193eac | 528 | return -ENODEV; |
2967dab1 | 529 | |
8c43fcc7 | 530 | pfc = devm_kzalloc(&pdev->dev, sizeof(*pfc), GFP_KERNEL); |
c6193eac LP |
531 | if (pfc == NULL) |
532 | return -ENOMEM; | |
d4e62d00 | 533 | |
19bb7fe3 | 534 | pfc->info = info; |
c6193eac LP |
535 | pfc->dev = &pdev->dev; |
536 | ||
70c8f01a | 537 | ret = sh_pfc_map_resources(pfc, pdev); |
c6193eac | 538 | if (unlikely(ret < 0)) |
b0e10211 MD |
539 | return ret; |
540 | ||
c6193eac | 541 | spin_lock_init(&pfc->lock); |
69edbba0 | 542 | |
0c151062 LP |
543 | if (info->ops && info->ops->init) { |
544 | ret = info->ops->init(pfc); | |
545 | if (ret < 0) | |
546 | return ret; | |
547 | } | |
548 | ||
0129801b WS |
549 | /* Enable dummy states for those platforms without pinctrl support */ |
550 | if (!of_have_populated_dt()) | |
551 | pinctrl_provide_dummies(); | |
b0e10211 | 552 | |
acac8ed5 LP |
553 | ret = sh_pfc_init_ranges(pfc); |
554 | if (ret < 0) | |
555 | return ret; | |
556 | ||
ca5481c6 PM |
557 | /* |
558 | * Initialize pinctrl bindings first | |
559 | */ | |
c6193eac | 560 | ret = sh_pfc_register_pinctrl(pfc); |
f9492fda | 561 | if (unlikely(ret != 0)) |
0a332c96 | 562 | return ret; |
ca5481c6 | 563 | |
abc60d48 | 564 | #ifdef CONFIG_PINCTRL_SH_PFC_GPIO |
ca5481c6 PM |
565 | /* |
566 | * Then the GPIO chip | |
567 | */ | |
c6193eac | 568 | ret = sh_pfc_register_gpiochip(pfc); |
6f6a4a68 | 569 | if (unlikely(ret != 0)) { |
ca5481c6 PM |
570 | /* |
571 | * If the GPIO chip fails to come up we still leave the | |
572 | * PFC state as it is, given that there are already | |
573 | * extant users of it that have succeeded by this point. | |
574 | */ | |
9a643c9a | 575 | dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n"); |
b3c185a7 | 576 | } |
6f6a4a68 | 577 | #endif |
b72421d8 | 578 | |
c6193eac LP |
579 | platform_set_drvdata(pdev, pfc); |
580 | ||
9a643c9a | 581 | dev_info(pfc->dev, "%s support registered\n", info->name); |
ca5481c6 | 582 | |
b3c185a7 | 583 | return 0; |
b72421d8 | 584 | } |
6f6a4a68 | 585 | |
c6193eac LP |
586 | static int sh_pfc_remove(struct platform_device *pdev) |
587 | { | |
588 | struct sh_pfc *pfc = platform_get_drvdata(pdev); | |
589 | ||
abc60d48 | 590 | #ifdef CONFIG_PINCTRL_SH_PFC_GPIO |
c6193eac LP |
591 | sh_pfc_unregister_gpiochip(pfc); |
592 | #endif | |
593 | sh_pfc_unregister_pinctrl(pfc); | |
594 | ||
c6193eac LP |
595 | return 0; |
596 | } | |
597 | ||
598 | static const struct platform_device_id sh_pfc_id_table[] = { | |
ccda552e LP |
599 | #ifdef CONFIG_PINCTRL_PFC_SH7203 |
600 | { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, | |
601 | #endif | |
a8d42fc4 LP |
602 | #ifdef CONFIG_PINCTRL_PFC_SH7264 |
603 | { "pfc-sh7264", (kernel_ulong_t)&sh7264_pinmux_info }, | |
604 | #endif | |
f5e811f2 LP |
605 | #ifdef CONFIG_PINCTRL_PFC_SH7269 |
606 | { "pfc-sh7269", (kernel_ulong_t)&sh7269_pinmux_info }, | |
607 | #endif | |
74cad605 LP |
608 | #ifdef CONFIG_PINCTRL_PFC_SH7720 |
609 | { "pfc-sh7720", (kernel_ulong_t)&sh7720_pinmux_info }, | |
f5e25ae5 LP |
610 | #endif |
611 | #ifdef CONFIG_PINCTRL_PFC_SH7722 | |
612 | { "pfc-sh7722", (kernel_ulong_t)&sh7722_pinmux_info }, | |
d05afa0a LP |
613 | #endif |
614 | #ifdef CONFIG_PINCTRL_PFC_SH7723 | |
615 | { "pfc-sh7723", (kernel_ulong_t)&sh7723_pinmux_info }, | |
0ff25bab LP |
616 | #endif |
617 | #ifdef CONFIG_PINCTRL_PFC_SH7724 | |
618 | { "pfc-sh7724", (kernel_ulong_t)&sh7724_pinmux_info }, | |
ac1ebc21 LP |
619 | #endif |
620 | #ifdef CONFIG_PINCTRL_PFC_SH7734 | |
621 | { "pfc-sh7734", (kernel_ulong_t)&sh7734_pinmux_info }, | |
0bb92677 LP |
622 | #endif |
623 | #ifdef CONFIG_PINCTRL_PFC_SH7757 | |
624 | { "pfc-sh7757", (kernel_ulong_t)&sh7757_pinmux_info }, | |
a56398e9 LP |
625 | #endif |
626 | #ifdef CONFIG_PINCTRL_PFC_SH7785 | |
627 | { "pfc-sh7785", (kernel_ulong_t)&sh7785_pinmux_info }, | |
d2a31bdd LP |
628 | #endif |
629 | #ifdef CONFIG_PINCTRL_PFC_SH7786 | |
630 | { "pfc-sh7786", (kernel_ulong_t)&sh7786_pinmux_info }, | |
d5d9a818 LP |
631 | #endif |
632 | #ifdef CONFIG_PINCTRL_PFC_SHX3 | |
633 | { "pfc-shx3", (kernel_ulong_t)&shx3_pinmux_info }, | |
d5b1521a | 634 | #endif |
c6193eac LP |
635 | { "sh-pfc", 0 }, |
636 | { }, | |
637 | }; | |
c6193eac LP |
638 | |
639 | static struct platform_driver sh_pfc_driver = { | |
640 | .probe = sh_pfc_probe, | |
641 | .remove = sh_pfc_remove, | |
642 | .id_table = sh_pfc_id_table, | |
643 | .driver = { | |
644 | .name = DRV_NAME, | |
fe1c9a82 | 645 | .of_match_table = of_match_ptr(sh_pfc_of_table), |
c6193eac LP |
646 | }, |
647 | }; | |
648 | ||
40ee6fce LP |
649 | static int __init sh_pfc_init(void) |
650 | { | |
651 | return platform_driver_register(&sh_pfc_driver); | |
c6193eac | 652 | } |
40ee6fce | 653 | postcore_initcall(sh_pfc_init); |