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Commit | Line | Data |
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b3c185a7 PM |
1 | /* |
2 | * SuperH Pin Function Controller GPIO driver. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * Copyright (C) 2009 - 2012 Paul Mundt | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac LP |
11 | |
12 | #define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt | |
b3c185a7 | 13 | |
1724acfd | 14 | #include <linux/device.h> |
b3c185a7 | 15 | #include <linux/gpio.h> |
90efde22 | 16 | #include <linux/init.h> |
b3c185a7 | 17 | #include <linux/module.h> |
ca5481c6 | 18 | #include <linux/pinctrl/consumer.h> |
90efde22 LP |
19 | #include <linux/slab.h> |
20 | #include <linux/spinlock.h> | |
b3c185a7 | 21 | |
f9165132 LP |
22 | #include "core.h" |
23 | ||
51cb226b LP |
24 | struct sh_pfc_gpio_data_reg { |
25 | const struct pinmux_data_reg *info; | |
26 | unsigned long shadow; | |
27 | }; | |
28 | ||
b3c185a7 PM |
29 | struct sh_pfc_chip { |
30 | struct sh_pfc *pfc; | |
31 | struct gpio_chip gpio_chip; | |
e51d5343 LP |
32 | |
33 | struct sh_pfc_window *mem; | |
51cb226b | 34 | struct sh_pfc_gpio_data_reg *regs; |
b3c185a7 PM |
35 | }; |
36 | ||
37 | static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) | |
38 | { | |
39 | return container_of(gc, struct sh_pfc_chip, gpio_chip); | |
40 | } | |
41 | ||
42 | static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) | |
43 | { | |
44 | return gpio_to_pfc_chip(gc)->pfc; | |
45 | } | |
46 | ||
51cb226b LP |
47 | static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio, |
48 | struct sh_pfc_gpio_data_reg **reg, | |
49 | unsigned int *bit) | |
41f1219f | 50 | { |
51cb226b LP |
51 | struct sh_pfc_pin *gpiop = sh_pfc_get_pin(chip->pfc, gpio); |
52 | unsigned int reg_idx; | |
41f1219f | 53 | |
51cb226b LP |
54 | reg_idx = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT; |
55 | ||
56 | *reg = &chip->regs[reg_idx]; | |
41f1219f LP |
57 | *bit = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT; |
58 | } | |
59 | ||
e51d5343 LP |
60 | static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip, |
61 | const struct pinmux_data_reg *dreg) | |
41f1219f | 62 | { |
e51d5343 LP |
63 | void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; |
64 | ||
65 | return sh_pfc_read_raw_reg(mem, dreg->reg_width); | |
66 | } | |
41f1219f | 67 | |
e51d5343 LP |
68 | static void gpio_write_data_reg(struct sh_pfc_chip *chip, |
69 | const struct pinmux_data_reg *dreg, | |
70 | unsigned long value) | |
71 | { | |
72 | void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt; | |
41f1219f | 73 | |
e51d5343 LP |
74 | sh_pfc_write_raw_reg(mem, dreg->reg_width, value); |
75 | } | |
41f1219f | 76 | |
e51d5343 LP |
77 | static void gpio_setup_data_reg(struct sh_pfc *pfc, unsigned gpio) |
78 | { | |
79 | struct sh_pfc_pin *gpiop = &pfc->info->pins[gpio]; | |
80 | const struct pinmux_data_reg *dreg; | |
81 | unsigned int bit; | |
82 | unsigned int i; | |
41f1219f | 83 | |
e51d5343 LP |
84 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) { |
85 | for (bit = 0; bit < dreg->reg_width; bit++) { | |
86 | if (dreg->enum_ids[bit] == gpiop->enum_id) { | |
41f1219f | 87 | gpiop->flags &= ~PINMUX_FLAG_DREG; |
e51d5343 | 88 | gpiop->flags |= i << PINMUX_FLAG_DREG_SHIFT; |
41f1219f | 89 | gpiop->flags &= ~PINMUX_FLAG_DBIT; |
e51d5343 | 90 | gpiop->flags |= bit << PINMUX_FLAG_DBIT_SHIFT; |
41f1219f LP |
91 | return; |
92 | } | |
93 | } | |
41f1219f LP |
94 | } |
95 | ||
96 | BUG(); | |
97 | } | |
98 | ||
e51d5343 | 99 | static int gpio_setup_data_regs(struct sh_pfc_chip *chip) |
41f1219f | 100 | { |
e51d5343 LP |
101 | struct sh_pfc *pfc = chip->pfc; |
102 | unsigned long addr = pfc->info->data_regs[0].reg; | |
51cb226b | 103 | const struct pinmux_data_reg *dreg; |
e51d5343 | 104 | unsigned int i; |
41f1219f | 105 | |
e51d5343 LP |
106 | /* Find the window that contain the GPIO registers. */ |
107 | for (i = 0; i < pfc->num_windows; ++i) { | |
108 | struct sh_pfc_window *window = &pfc->window[i]; | |
41f1219f | 109 | |
e51d5343 LP |
110 | if (addr >= window->phys && addr < window->phys + window->size) |
111 | break; | |
41f1219f LP |
112 | } |
113 | ||
e51d5343 LP |
114 | if (i == pfc->num_windows) |
115 | return -EINVAL; | |
116 | ||
117 | /* GPIO data registers must be in the first memory resource. */ | |
118 | chip->mem = &pfc->window[i]; | |
41f1219f | 119 | |
51cb226b LP |
120 | /* Count the number of data registers, allocate memory and initialize |
121 | * them. | |
122 | */ | |
123 | for (i = 0; pfc->info->data_regs[i].reg_width; ++i) | |
124 | ; | |
125 | ||
126 | chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), | |
127 | GFP_KERNEL); | |
128 | if (chip->regs == NULL) | |
129 | return -ENOMEM; | |
130 | ||
131 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { | |
132 | chip->regs[i].info = dreg; | |
133 | chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); | |
134 | } | |
41f1219f | 135 | |
e51d5343 LP |
136 | for (i = 0; i < pfc->info->nr_pins; i++) { |
137 | if (pfc->info->pins[i].enum_id == 0) | |
138 | continue; | |
139 | ||
140 | gpio_setup_data_reg(pfc, i); | |
41f1219f | 141 | } |
e51d5343 LP |
142 | |
143 | return 0; | |
41f1219f LP |
144 | } |
145 | ||
16883814 LP |
146 | /* ----------------------------------------------------------------------------- |
147 | * Pin GPIOs | |
148 | */ | |
b3c185a7 | 149 | |
16883814 | 150 | static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 151 | { |
0b73ee5d | 152 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
934cb02b | 153 | struct sh_pfc_pin *pin = sh_pfc_get_pin(pfc, offset); |
0b73ee5d | 154 | |
63d57383 | 155 | if (pin == NULL || pin->enum_id == 0) |
0b73ee5d LP |
156 | return -EINVAL; |
157 | ||
16883814 | 158 | return pinctrl_request_gpio(offset); |
b3c185a7 PM |
159 | } |
160 | ||
16883814 | 161 | static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 162 | { |
16883814 | 163 | return pinctrl_free_gpio(offset); |
b3c185a7 PM |
164 | } |
165 | ||
e51d5343 LP |
166 | static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, |
167 | int value) | |
b3c185a7 | 168 | { |
51cb226b | 169 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f LP |
170 | unsigned long pos; |
171 | unsigned int bit; | |
b3c185a7 | 172 | |
51cb226b | 173 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 174 | |
51cb226b | 175 | pos = reg->info->reg_width - (bit + 1); |
41f1219f LP |
176 | |
177 | if (value) | |
51cb226b | 178 | set_bit(pos, ®->shadow); |
41f1219f | 179 | else |
51cb226b | 180 | clear_bit(pos, ®->shadow); |
41f1219f | 181 | |
51cb226b | 182 | gpio_write_data_reg(chip, reg->info, reg->shadow); |
b3c185a7 PM |
183 | } |
184 | ||
16883814 | 185 | static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) |
ca5481c6 PM |
186 | { |
187 | return pinctrl_gpio_direction_input(offset); | |
188 | } | |
189 | ||
16883814 | 190 | static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, |
ca5481c6 PM |
191 | int value) |
192 | { | |
e51d5343 | 193 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
ca5481c6 PM |
194 | |
195 | return pinctrl_gpio_direction_output(offset); | |
196 | } | |
197 | ||
16883814 | 198 | static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 199 | { |
e51d5343 | 200 | struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); |
51cb226b | 201 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f LP |
202 | unsigned long pos; |
203 | unsigned int bit; | |
16883814 | 204 | |
51cb226b | 205 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 206 | |
51cb226b | 207 | pos = reg->info->reg_width - (bit + 1); |
41f1219f | 208 | |
51cb226b | 209 | return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; |
b3c185a7 PM |
210 | } |
211 | ||
16883814 | 212 | static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) |
b3c185a7 | 213 | { |
e51d5343 | 214 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
b3c185a7 PM |
215 | } |
216 | ||
16883814 | 217 | static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) |
b3c185a7 PM |
218 | { |
219 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
c07f54f6 LP |
220 | int i, k; |
221 | ||
222 | for (i = 0; i < pfc->info->gpio_irq_size; i++) { | |
223 | unsigned short *gpios = pfc->info->gpio_irq[i].gpios; | |
224 | ||
225 | for (k = 0; gpios[k]; k++) { | |
226 | if (gpios[k] == offset) | |
227 | return pfc->info->gpio_irq[i].irq; | |
b3c185a7 PM |
228 | } |
229 | } | |
230 | ||
231 | return -ENOSYS; | |
232 | } | |
233 | ||
e51d5343 | 234 | static int gpio_pin_setup(struct sh_pfc_chip *chip) |
b3c185a7 PM |
235 | { |
236 | struct sh_pfc *pfc = chip->pfc; | |
237 | struct gpio_chip *gc = &chip->gpio_chip; | |
e51d5343 LP |
238 | int ret; |
239 | ||
240 | ret = gpio_setup_data_regs(chip); | |
241 | if (ret < 0) | |
242 | return ret; | |
b3c185a7 | 243 | |
16883814 LP |
244 | gc->request = gpio_pin_request; |
245 | gc->free = gpio_pin_free; | |
246 | gc->direction_input = gpio_pin_direction_input; | |
247 | gc->get = gpio_pin_get; | |
248 | gc->direction_output = gpio_pin_direction_output; | |
249 | gc->set = gpio_pin_set; | |
250 | gc->to_irq = gpio_pin_to_irq; | |
b3c185a7 | 251 | |
19bb7fe3 | 252 | gc->label = pfc->info->name; |
16883814 | 253 | gc->dev = pfc->dev; |
b3c185a7 | 254 | gc->owner = THIS_MODULE; |
d7a7ca57 | 255 | gc->base = 0; |
63d57383 | 256 | gc->ngpio = pfc->nr_pins; |
e51d5343 LP |
257 | |
258 | return 0; | |
b3c185a7 PM |
259 | } |
260 | ||
16883814 LP |
261 | /* ----------------------------------------------------------------------------- |
262 | * Function GPIOs | |
263 | */ | |
264 | ||
265 | static int gpio_function_request(struct gpio_chip *gc, unsigned offset) | |
266 | { | |
267 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
a68fdca9 | 268 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 LP |
269 | unsigned long flags; |
270 | int ret = -EINVAL; | |
271 | ||
272 | pr_notice_once("Use of GPIO API for function requests is deprecated, convert to pinctrl\n"); | |
273 | ||
a68fdca9 | 274 | if (mark == 0) |
16883814 LP |
275 | return ret; |
276 | ||
277 | spin_lock_irqsave(&pfc->lock, flags); | |
278 | ||
a68fdca9 | 279 | if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_DRYRUN)) |
16883814 LP |
280 | goto done; |
281 | ||
a68fdca9 | 282 | if (sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_REQ)) |
16883814 LP |
283 | goto done; |
284 | ||
285 | ret = 0; | |
286 | ||
287 | done: | |
288 | spin_unlock_irqrestore(&pfc->lock, flags); | |
289 | return ret; | |
290 | } | |
291 | ||
292 | static void gpio_function_free(struct gpio_chip *gc, unsigned offset) | |
293 | { | |
294 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
a68fdca9 | 295 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 LP |
296 | unsigned long flags; |
297 | ||
298 | spin_lock_irqsave(&pfc->lock, flags); | |
299 | ||
a68fdca9 | 300 | sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION, GPIO_CFG_FREE); |
16883814 LP |
301 | |
302 | spin_unlock_irqrestore(&pfc->lock, flags); | |
303 | } | |
304 | ||
e51d5343 | 305 | static int gpio_function_setup(struct sh_pfc_chip *chip) |
16883814 LP |
306 | { |
307 | struct sh_pfc *pfc = chip->pfc; | |
308 | struct gpio_chip *gc = &chip->gpio_chip; | |
309 | ||
310 | gc->request = gpio_function_request; | |
311 | gc->free = gpio_function_free; | |
312 | ||
313 | gc->label = pfc->info->name; | |
314 | gc->owner = THIS_MODULE; | |
63d57383 | 315 | gc->base = pfc->nr_pins; |
16883814 | 316 | gc->ngpio = pfc->info->nr_func_gpios; |
e51d5343 LP |
317 | |
318 | return 0; | |
16883814 LP |
319 | } |
320 | ||
321 | /* ----------------------------------------------------------------------------- | |
322 | * Register/unregister | |
323 | */ | |
324 | ||
325 | static struct sh_pfc_chip * | |
e51d5343 | 326 | sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *)) |
b3c185a7 PM |
327 | { |
328 | struct sh_pfc_chip *chip; | |
329 | int ret; | |
330 | ||
1724acfd | 331 | chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); |
b3c185a7 | 332 | if (unlikely(!chip)) |
16883814 | 333 | return ERR_PTR(-ENOMEM); |
b3c185a7 PM |
334 | |
335 | chip->pfc = pfc; | |
336 | ||
e51d5343 LP |
337 | ret = setup(chip); |
338 | if (ret < 0) | |
339 | return ERR_PTR(ret); | |
b3c185a7 PM |
340 | |
341 | ret = gpiochip_add(&chip->gpio_chip); | |
1724acfd | 342 | if (unlikely(ret < 0)) |
16883814 LP |
343 | return ERR_PTR(ret); |
344 | ||
345 | pr_info("%s handling gpio %u -> %u\n", | |
346 | chip->gpio_chip.label, chip->gpio_chip.base, | |
347 | chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); | |
348 | ||
349 | return chip; | |
350 | } | |
351 | ||
352 | int sh_pfc_register_gpiochip(struct sh_pfc *pfc) | |
353 | { | |
63d57383 LP |
354 | const struct pinmux_range *ranges; |
355 | struct pinmux_range def_range; | |
16883814 | 356 | struct sh_pfc_chip *chip; |
63d57383 LP |
357 | unsigned int nr_ranges; |
358 | unsigned int i; | |
247127f9 | 359 | int ret; |
16883814 | 360 | |
63d57383 | 361 | /* Register the real GPIOs chip. */ |
16883814 LP |
362 | chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup); |
363 | if (IS_ERR(chip)) | |
364 | return PTR_ERR(chip); | |
6f6a4a68 LP |
365 | |
366 | pfc->gpio = chip; | |
b3c185a7 | 367 | |
63d57383 LP |
368 | /* Register the GPIO to pin mappings. */ |
369 | if (pfc->info->ranges == NULL) { | |
370 | def_range.begin = 0; | |
371 | def_range.end = pfc->info->nr_pins - 1; | |
372 | ranges = &def_range; | |
373 | nr_ranges = 1; | |
374 | } else { | |
375 | ranges = pfc->info->ranges; | |
376 | nr_ranges = pfc->info->nr_ranges; | |
377 | } | |
378 | ||
379 | for (i = 0; i < nr_ranges; ++i) { | |
380 | const struct pinmux_range *range = &ranges[i]; | |
381 | ||
382 | ret = gpiochip_add_pin_range(&chip->gpio_chip, | |
383 | dev_name(pfc->dev), | |
384 | range->begin, range->begin, | |
385 | range->end - range->begin + 1); | |
386 | if (ret < 0) | |
387 | return ret; | |
388 | } | |
247127f9 | 389 | |
63d57383 | 390 | /* Register the function GPIOs chip. */ |
16883814 LP |
391 | chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup); |
392 | if (IS_ERR(chip)) | |
393 | return PTR_ERR(chip); | |
394 | ||
395 | pfc->func = chip; | |
b3c185a7 | 396 | |
b3c185a7 PM |
397 | return 0; |
398 | } | |
399 | ||
6f6a4a68 | 400 | int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) |
b3c185a7 | 401 | { |
16883814 | 402 | int err; |
b3c185a7 PM |
403 | int ret; |
404 | ||
16883814 LP |
405 | ret = gpiochip_remove(&pfc->gpio->gpio_chip); |
406 | err = gpiochip_remove(&pfc->func->gpio_chip); | |
b3c185a7 | 407 | |
16883814 | 408 | return ret < 0 ? ret : err; |
b3c185a7 | 409 | } |