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Commit | Line | Data |
---|---|---|
b3c185a7 PM |
1 | /* |
2 | * SuperH Pin Function Controller GPIO driver. | |
3 | * | |
4 | * Copyright (C) 2008 Magnus Damm | |
5 | * Copyright (C) 2009 - 2012 Paul Mundt | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
c6193eac | 11 | |
1724acfd | 12 | #include <linux/device.h> |
b3c185a7 | 13 | #include <linux/gpio.h> |
90efde22 | 14 | #include <linux/init.h> |
b3c185a7 | 15 | #include <linux/module.h> |
ca5481c6 | 16 | #include <linux/pinctrl/consumer.h> |
90efde22 LP |
17 | #include <linux/slab.h> |
18 | #include <linux/spinlock.h> | |
b3c185a7 | 19 | |
f9165132 LP |
20 | #include "core.h" |
21 | ||
51cb226b LP |
22 | struct sh_pfc_gpio_data_reg { |
23 | const struct pinmux_data_reg *info; | |
fc88936a | 24 | u32 shadow; |
51cb226b LP |
25 | }; |
26 | ||
1a0039dc LP |
27 | struct sh_pfc_gpio_pin { |
28 | u8 dbit; | |
29 | u8 dreg; | |
30 | }; | |
31 | ||
b3c185a7 | 32 | struct sh_pfc_chip { |
1a0039dc LP |
33 | struct sh_pfc *pfc; |
34 | struct gpio_chip gpio_chip; | |
e51d5343 | 35 | |
1a0039dc | 36 | struct sh_pfc_window *mem; |
51cb226b | 37 | struct sh_pfc_gpio_data_reg *regs; |
1a0039dc | 38 | struct sh_pfc_gpio_pin *pins; |
b3c185a7 PM |
39 | }; |
40 | ||
41 | static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) | |
42 | { | |
43 | return container_of(gc, struct sh_pfc_chip, gpio_chip); | |
44 | } | |
45 | ||
46 | static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc) | |
47 | { | |
48 | return gpio_to_pfc_chip(gc)->pfc; | |
49 | } | |
50 | ||
757b055a | 51 | static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset, |
51cb226b LP |
52 | struct sh_pfc_gpio_data_reg **reg, |
53 | unsigned int *bit) | |
41f1219f | 54 | { |
757b055a | 55 | int idx = sh_pfc_get_pin_index(chip->pfc, offset); |
1a0039dc | 56 | struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; |
41f1219f | 57 | |
1a0039dc LP |
58 | *reg = &chip->regs[gpio_pin->dreg]; |
59 | *bit = gpio_pin->dbit; | |
41f1219f LP |
60 | } |
61 | ||
fc88936a GU |
62 | static u32 gpio_read_data_reg(struct sh_pfc_chip *chip, |
63 | const struct pinmux_data_reg *dreg) | |
41f1219f | 64 | { |
1f34de05 GU |
65 | phys_addr_t address = dreg->reg; |
66 | void __iomem *mem = address - chip->mem->phys + chip->mem->virt; | |
e51d5343 LP |
67 | |
68 | return sh_pfc_read_raw_reg(mem, dreg->reg_width); | |
69 | } | |
41f1219f | 70 | |
e51d5343 | 71 | static void gpio_write_data_reg(struct sh_pfc_chip *chip, |
fc88936a | 72 | const struct pinmux_data_reg *dreg, u32 value) |
e51d5343 | 73 | { |
1f34de05 GU |
74 | phys_addr_t address = dreg->reg; |
75 | void __iomem *mem = address - chip->mem->phys + chip->mem->virt; | |
41f1219f | 76 | |
e51d5343 LP |
77 | sh_pfc_write_raw_reg(mem, dreg->reg_width, value); |
78 | } | |
41f1219f | 79 | |
757b055a | 80 | static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx) |
e51d5343 | 81 | { |
1a0039dc | 82 | struct sh_pfc *pfc = chip->pfc; |
757b055a LP |
83 | struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx]; |
84 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
e51d5343 LP |
85 | const struct pinmux_data_reg *dreg; |
86 | unsigned int bit; | |
87 | unsigned int i; | |
41f1219f | 88 | |
17c7cbb0 | 89 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { |
e51d5343 | 90 | for (bit = 0; bit < dreg->reg_width; bit++) { |
1a0039dc LP |
91 | if (dreg->enum_ids[bit] == pin->enum_id) { |
92 | gpio_pin->dreg = i; | |
93 | gpio_pin->dbit = bit; | |
41f1219f LP |
94 | return; |
95 | } | |
96 | } | |
41f1219f LP |
97 | } |
98 | ||
99 | BUG(); | |
100 | } | |
101 | ||
e51d5343 | 102 | static int gpio_setup_data_regs(struct sh_pfc_chip *chip) |
41f1219f | 103 | { |
e51d5343 | 104 | struct sh_pfc *pfc = chip->pfc; |
51cb226b | 105 | const struct pinmux_data_reg *dreg; |
e51d5343 | 106 | unsigned int i; |
41f1219f | 107 | |
51cb226b LP |
108 | /* Count the number of data registers, allocate memory and initialize |
109 | * them. | |
110 | */ | |
111 | for (i = 0; pfc->info->data_regs[i].reg_width; ++i) | |
112 | ; | |
113 | ||
114 | chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs), | |
115 | GFP_KERNEL); | |
116 | if (chip->regs == NULL) | |
117 | return -ENOMEM; | |
118 | ||
119 | for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) { | |
120 | chip->regs[i].info = dreg; | |
121 | chip->regs[i].shadow = gpio_read_data_reg(chip, dreg); | |
122 | } | |
41f1219f | 123 | |
e51d5343 LP |
124 | for (i = 0; i < pfc->info->nr_pins; i++) { |
125 | if (pfc->info->pins[i].enum_id == 0) | |
126 | continue; | |
127 | ||
1a0039dc | 128 | gpio_setup_data_reg(chip, i); |
41f1219f | 129 | } |
e51d5343 LP |
130 | |
131 | return 0; | |
41f1219f LP |
132 | } |
133 | ||
16883814 LP |
134 | /* ----------------------------------------------------------------------------- |
135 | * Pin GPIOs | |
136 | */ | |
b3c185a7 | 137 | |
16883814 | 138 | static int gpio_pin_request(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 139 | { |
0b73ee5d | 140 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
1a0039dc | 141 | int idx = sh_pfc_get_pin_index(pfc, offset); |
0b73ee5d | 142 | |
1a0039dc | 143 | if (idx < 0 || pfc->info->pins[idx].enum_id == 0) |
0b73ee5d LP |
144 | return -EINVAL; |
145 | ||
16883814 | 146 | return pinctrl_request_gpio(offset); |
b3c185a7 PM |
147 | } |
148 | ||
16883814 | 149 | static void gpio_pin_free(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 150 | { |
16883814 | 151 | return pinctrl_free_gpio(offset); |
b3c185a7 PM |
152 | } |
153 | ||
e51d5343 LP |
154 | static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset, |
155 | int value) | |
b3c185a7 | 156 | { |
51cb226b | 157 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f | 158 | unsigned int bit; |
cef28a28 | 159 | unsigned int pos; |
b3c185a7 | 160 | |
51cb226b | 161 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 162 | |
51cb226b | 163 | pos = reg->info->reg_width - (bit + 1); |
41f1219f LP |
164 | |
165 | if (value) | |
fc88936a | 166 | reg->shadow |= BIT(pos); |
41f1219f | 167 | else |
fc88936a | 168 | reg->shadow &= ~BIT(pos); |
41f1219f | 169 | |
51cb226b | 170 | gpio_write_data_reg(chip, reg->info, reg->shadow); |
b3c185a7 PM |
171 | } |
172 | ||
16883814 | 173 | static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset) |
ca5481c6 PM |
174 | { |
175 | return pinctrl_gpio_direction_input(offset); | |
176 | } | |
177 | ||
16883814 | 178 | static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset, |
ca5481c6 PM |
179 | int value) |
180 | { | |
e51d5343 | 181 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
ca5481c6 PM |
182 | |
183 | return pinctrl_gpio_direction_output(offset); | |
184 | } | |
185 | ||
16883814 | 186 | static int gpio_pin_get(struct gpio_chip *gc, unsigned offset) |
b3c185a7 | 187 | { |
e51d5343 | 188 | struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc); |
51cb226b | 189 | struct sh_pfc_gpio_data_reg *reg; |
41f1219f | 190 | unsigned int bit; |
cef28a28 | 191 | unsigned int pos; |
16883814 | 192 | |
51cb226b | 193 | gpio_get_data_reg(chip, offset, ®, &bit); |
41f1219f | 194 | |
51cb226b | 195 | pos = reg->info->reg_width - (bit + 1); |
41f1219f | 196 | |
51cb226b | 197 | return (gpio_read_data_reg(chip, reg->info) >> pos) & 1; |
b3c185a7 PM |
198 | } |
199 | ||
16883814 | 200 | static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value) |
b3c185a7 | 201 | { |
e51d5343 | 202 | gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value); |
b3c185a7 PM |
203 | } |
204 | ||
16883814 | 205 | static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) |
b3c185a7 PM |
206 | { |
207 | struct sh_pfc *pfc = gpio_to_pfc(gc); | |
8d72a7fc | 208 | unsigned int i, k; |
c07f54f6 LP |
209 | |
210 | for (i = 0; i < pfc->info->gpio_irq_size; i++) { | |
6d5bddd5 | 211 | const short *gpios = pfc->info->gpio_irq[i].gpios; |
c07f54f6 | 212 | |
316b2550 | 213 | for (k = 0; gpios[k] >= 0; k++) { |
c07f54f6 | 214 | if (gpios[k] == offset) |
70c8f01a | 215 | goto found; |
b3c185a7 PM |
216 | } |
217 | } | |
218 | ||
219 | return -ENOSYS; | |
70c8f01a LP |
220 | |
221 | found: | |
222 | if (pfc->num_irqs) | |
223 | return pfc->irqs[i]; | |
224 | else | |
225 | return pfc->info->gpio_irq[i].irq; | |
b3c185a7 PM |
226 | } |
227 | ||
e51d5343 | 228 | static int gpio_pin_setup(struct sh_pfc_chip *chip) |
b3c185a7 PM |
229 | { |
230 | struct sh_pfc *pfc = chip->pfc; | |
231 | struct gpio_chip *gc = &chip->gpio_chip; | |
e51d5343 LP |
232 | int ret; |
233 | ||
a1a3580c LP |
234 | chip->pins = devm_kzalloc(pfc->dev, pfc->info->nr_pins * |
235 | sizeof(*chip->pins), GFP_KERNEL); | |
1a0039dc LP |
236 | if (chip->pins == NULL) |
237 | return -ENOMEM; | |
238 | ||
e51d5343 LP |
239 | ret = gpio_setup_data_regs(chip); |
240 | if (ret < 0) | |
241 | return ret; | |
b3c185a7 | 242 | |
16883814 LP |
243 | gc->request = gpio_pin_request; |
244 | gc->free = gpio_pin_free; | |
245 | gc->direction_input = gpio_pin_direction_input; | |
246 | gc->get = gpio_pin_get; | |
247 | gc->direction_output = gpio_pin_direction_output; | |
248 | gc->set = gpio_pin_set; | |
249 | gc->to_irq = gpio_pin_to_irq; | |
b3c185a7 | 250 | |
19bb7fe3 | 251 | gc->label = pfc->info->name; |
16883814 | 252 | gc->dev = pfc->dev; |
b3c185a7 | 253 | gc->owner = THIS_MODULE; |
d7a7ca57 | 254 | gc->base = 0; |
28818fa5 | 255 | gc->ngpio = pfc->nr_gpio_pins; |
e51d5343 LP |
256 | |
257 | return 0; | |
b3c185a7 PM |
258 | } |
259 | ||
16883814 LP |
260 | /* ----------------------------------------------------------------------------- |
261 | * Function GPIOs | |
262 | */ | |
263 | ||
264 | static int gpio_function_request(struct gpio_chip *gc, unsigned offset) | |
265 | { | |
9a643c9a | 266 | static bool __print_once; |
16883814 | 267 | struct sh_pfc *pfc = gpio_to_pfc(gc); |
a68fdca9 | 268 | unsigned int mark = pfc->info->func_gpios[offset].enum_id; |
16883814 | 269 | unsigned long flags; |
b705c054 | 270 | int ret; |
16883814 | 271 | |
9a643c9a LP |
272 | if (!__print_once) { |
273 | dev_notice(pfc->dev, | |
274 | "Use of GPIO API for function requests is deprecated." | |
275 | " Convert to pinctrl\n"); | |
276 | __print_once = true; | |
277 | } | |
16883814 | 278 | |
a68fdca9 | 279 | if (mark == 0) |
b705c054 | 280 | return -EINVAL; |
16883814 LP |
281 | |
282 | spin_lock_irqsave(&pfc->lock, flags); | |
b705c054 | 283 | ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION); |
16883814 | 284 | spin_unlock_irqrestore(&pfc->lock, flags); |
b705c054 | 285 | |
16883814 LP |
286 | return ret; |
287 | } | |
288 | ||
289 | static void gpio_function_free(struct gpio_chip *gc, unsigned offset) | |
290 | { | |
16883814 LP |
291 | } |
292 | ||
e51d5343 | 293 | static int gpio_function_setup(struct sh_pfc_chip *chip) |
16883814 LP |
294 | { |
295 | struct sh_pfc *pfc = chip->pfc; | |
296 | struct gpio_chip *gc = &chip->gpio_chip; | |
297 | ||
298 | gc->request = gpio_function_request; | |
299 | gc->free = gpio_function_free; | |
300 | ||
301 | gc->label = pfc->info->name; | |
302 | gc->owner = THIS_MODULE; | |
28818fa5 | 303 | gc->base = pfc->nr_gpio_pins; |
16883814 | 304 | gc->ngpio = pfc->info->nr_func_gpios; |
e51d5343 LP |
305 | |
306 | return 0; | |
16883814 LP |
307 | } |
308 | ||
309 | /* ----------------------------------------------------------------------------- | |
310 | * Register/unregister | |
311 | */ | |
312 | ||
313 | static struct sh_pfc_chip * | |
ceef91dc LP |
314 | sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *), |
315 | struct sh_pfc_window *mem) | |
b3c185a7 PM |
316 | { |
317 | struct sh_pfc_chip *chip; | |
318 | int ret; | |
319 | ||
1724acfd | 320 | chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); |
b3c185a7 | 321 | if (unlikely(!chip)) |
16883814 | 322 | return ERR_PTR(-ENOMEM); |
b3c185a7 | 323 | |
ceef91dc | 324 | chip->mem = mem; |
b3c185a7 PM |
325 | chip->pfc = pfc; |
326 | ||
e51d5343 LP |
327 | ret = setup(chip); |
328 | if (ret < 0) | |
329 | return ERR_PTR(ret); | |
b3c185a7 PM |
330 | |
331 | ret = gpiochip_add(&chip->gpio_chip); | |
1724acfd | 332 | if (unlikely(ret < 0)) |
16883814 LP |
333 | return ERR_PTR(ret); |
334 | ||
9a643c9a LP |
335 | dev_info(pfc->dev, "%s handling gpio %u -> %u\n", |
336 | chip->gpio_chip.label, chip->gpio_chip.base, | |
337 | chip->gpio_chip.base + chip->gpio_chip.ngpio - 1); | |
16883814 LP |
338 | |
339 | return chip; | |
340 | } | |
341 | ||
342 | int sh_pfc_register_gpiochip(struct sh_pfc *pfc) | |
343 | { | |
344 | struct sh_pfc_chip *chip; | |
1f34de05 | 345 | phys_addr_t address; |
63d57383 | 346 | unsigned int i; |
247127f9 | 347 | int ret; |
16883814 | 348 | |
1a4fd58f LP |
349 | if (pfc->info->data_regs == NULL) |
350 | return 0; | |
351 | ||
ceef91dc LP |
352 | /* Find the memory window that contain the GPIO registers. Boards that |
353 | * register a separate GPIO device will not supply a memory resource | |
354 | * that covers the data registers. In that case don't try to handle | |
355 | * GPIOs. | |
356 | */ | |
1f34de05 | 357 | address = pfc->info->data_regs[0].reg; |
ceef91dc | 358 | for (i = 0; i < pfc->num_windows; ++i) { |
5b46ac3a | 359 | struct sh_pfc_window *window = &pfc->windows[i]; |
ceef91dc | 360 | |
1f34de05 GU |
361 | if (address >= window->phys && |
362 | address < window->phys + window->size) | |
ceef91dc LP |
363 | break; |
364 | } | |
365 | ||
366 | if (i == pfc->num_windows) | |
367 | return 0; | |
368 | ||
70c8f01a LP |
369 | /* If we have IRQ resources make sure their number is correct. */ |
370 | if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) { | |
371 | dev_err(pfc->dev, "invalid number of IRQ resources\n"); | |
372 | return -EINVAL; | |
373 | } | |
374 | ||
63d57383 | 375 | /* Register the real GPIOs chip. */ |
5b46ac3a | 376 | chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]); |
16883814 LP |
377 | if (IS_ERR(chip)) |
378 | return PTR_ERR(chip); | |
6f6a4a68 LP |
379 | |
380 | pfc->gpio = chip; | |
b3c185a7 | 381 | |
4f82e3ee LP |
382 | /* Register the GPIO to pin mappings. As pins with GPIO ports must come |
383 | * first in the ranges, skip the pins without GPIO ports by stopping at | |
384 | * the first range that contains such a pin. | |
385 | */ | |
acac8ed5 LP |
386 | for (i = 0; i < pfc->nr_ranges; ++i) { |
387 | const struct sh_pfc_pin_range *range = &pfc->ranges[i]; | |
63d57383 | 388 | |
4f82e3ee LP |
389 | if (range->start >= pfc->nr_gpio_pins) |
390 | break; | |
391 | ||
63d57383 LP |
392 | ret = gpiochip_add_pin_range(&chip->gpio_chip, |
393 | dev_name(pfc->dev), | |
acac8ed5 LP |
394 | range->start, range->start, |
395 | range->end - range->start + 1); | |
63d57383 LP |
396 | if (ret < 0) |
397 | return ret; | |
398 | } | |
247127f9 | 399 | |
63d57383 | 400 | /* Register the function GPIOs chip. */ |
542a564d LP |
401 | if (pfc->info->nr_func_gpios == 0) |
402 | return 0; | |
403 | ||
ceef91dc | 404 | chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL); |
16883814 LP |
405 | if (IS_ERR(chip)) |
406 | return PTR_ERR(chip); | |
407 | ||
408 | pfc->func = chip; | |
b3c185a7 | 409 | |
b3c185a7 PM |
410 | return 0; |
411 | } | |
412 | ||
6f6a4a68 | 413 | int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) |
b3c185a7 | 414 | { |
b4e7c55d | 415 | gpiochip_remove(&pfc->gpio->gpio_chip); |
416 | gpiochip_remove(&pfc->func->gpio_chip); | |
b3c185a7 | 417 | |
b4e7c55d | 418 | return 0; |
b3c185a7 | 419 | } |