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d5b1521a LP |
1 | /* |
2 | * R8A7740 processor support | |
3 | * | |
4 | * Copyright (C) 2011 Renesas Solutions Corp. | |
5 | * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; version 2 of the | |
10 | * License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
20 | */ | |
21 | #include <linux/kernel.h> | |
d5b1521a LP |
22 | #include <mach/r8a7740.h> |
23 | #include <mach/irqs.h> | |
24 | ||
c3323806 LP |
25 | #include "sh_pfc.h" |
26 | ||
d5b1521a LP |
27 | #define CPU_ALL_PORT(fn, pfx, sfx) \ |
28 | PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ | |
29 | PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ | |
30 | PORT_10(fn, pfx##20, sfx), \ | |
31 | PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) | |
32 | ||
09bbc1fd BH |
33 | #define IRQC_PIN_MUX(irq, pin) \ |
34 | static const unsigned int intc_irq##irq##_pins[] = { \ | |
35 | pin, \ | |
36 | }; \ | |
37 | static const unsigned int intc_irq##irq##_mux[] = { \ | |
38 | IRQ##irq##_MARK, \ | |
39 | } | |
40 | ||
41 | #define IRQC_PINS_MUX(irq, idx, pin) \ | |
42 | static const unsigned int intc_irq##irq##_##idx##_pins[] = { \ | |
43 | pin, \ | |
44 | }; \ | |
45 | static const unsigned int intc_irq##irq##_##idx##_mux[] = { \ | |
46 | IRQ##irq##_PORT##pin##_MARK, \ | |
47 | } | |
48 | ||
d5b1521a LP |
49 | enum { |
50 | PINMUX_RESERVED = 0, | |
51 | ||
52 | /* PORT0_DATA -> PORT211_DATA */ | |
53 | PINMUX_DATA_BEGIN, | |
54 | PORT_ALL(DATA), | |
55 | PINMUX_DATA_END, | |
56 | ||
57 | /* PORT0_IN -> PORT211_IN */ | |
58 | PINMUX_INPUT_BEGIN, | |
59 | PORT_ALL(IN), | |
60 | PINMUX_INPUT_END, | |
61 | ||
62 | /* PORT0_IN_PU -> PORT211_IN_PU */ | |
63 | PINMUX_INPUT_PULLUP_BEGIN, | |
64 | PORT_ALL(IN_PU), | |
65 | PINMUX_INPUT_PULLUP_END, | |
66 | ||
67 | /* PORT0_IN_PD -> PORT211_IN_PD */ | |
68 | PINMUX_INPUT_PULLDOWN_BEGIN, | |
69 | PORT_ALL(IN_PD), | |
70 | PINMUX_INPUT_PULLDOWN_END, | |
71 | ||
72 | /* PORT0_OUT -> PORT211_OUT */ | |
73 | PINMUX_OUTPUT_BEGIN, | |
74 | PORT_ALL(OUT), | |
75 | PINMUX_OUTPUT_END, | |
76 | ||
77 | PINMUX_FUNCTION_BEGIN, | |
78 | PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */ | |
79 | PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */ | |
80 | PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */ | |
81 | PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */ | |
82 | PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */ | |
83 | PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */ | |
84 | PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */ | |
85 | PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */ | |
86 | PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */ | |
87 | PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */ | |
88 | ||
89 | MSEL1CR_31_0, MSEL1CR_31_1, | |
90 | MSEL1CR_30_0, MSEL1CR_30_1, | |
91 | MSEL1CR_29_0, MSEL1CR_29_1, | |
92 | MSEL1CR_28_0, MSEL1CR_28_1, | |
93 | MSEL1CR_27_0, MSEL1CR_27_1, | |
94 | MSEL1CR_26_0, MSEL1CR_26_1, | |
95 | MSEL1CR_16_0, MSEL1CR_16_1, | |
96 | MSEL1CR_15_0, MSEL1CR_15_1, | |
97 | MSEL1CR_14_0, MSEL1CR_14_1, | |
98 | MSEL1CR_13_0, MSEL1CR_13_1, | |
99 | MSEL1CR_12_0, MSEL1CR_12_1, | |
100 | MSEL1CR_9_0, MSEL1CR_9_1, | |
101 | MSEL1CR_7_0, MSEL1CR_7_1, | |
102 | MSEL1CR_6_0, MSEL1CR_6_1, | |
103 | MSEL1CR_5_0, MSEL1CR_5_1, | |
104 | MSEL1CR_4_0, MSEL1CR_4_1, | |
105 | MSEL1CR_3_0, MSEL1CR_3_1, | |
106 | MSEL1CR_2_0, MSEL1CR_2_1, | |
107 | MSEL1CR_0_0, MSEL1CR_0_1, | |
108 | ||
109 | MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */ | |
110 | MSEL3CR_6_0, MSEL3CR_6_1, | |
111 | ||
112 | MSEL4CR_19_0, MSEL4CR_19_1, | |
113 | MSEL4CR_18_0, MSEL4CR_18_1, | |
114 | MSEL4CR_15_0, MSEL4CR_15_1, | |
115 | MSEL4CR_10_0, MSEL4CR_10_1, | |
116 | MSEL4CR_6_0, MSEL4CR_6_1, | |
117 | MSEL4CR_4_0, MSEL4CR_4_1, | |
118 | MSEL4CR_1_0, MSEL4CR_1_1, | |
119 | ||
120 | MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */ | |
121 | MSEL5CR_30_0, MSEL5CR_30_1, | |
122 | MSEL5CR_29_0, MSEL5CR_29_1, | |
123 | MSEL5CR_27_0, MSEL5CR_27_1, | |
124 | MSEL5CR_25_0, MSEL5CR_25_1, | |
125 | MSEL5CR_23_0, MSEL5CR_23_1, | |
126 | MSEL5CR_21_0, MSEL5CR_21_1, | |
127 | MSEL5CR_19_0, MSEL5CR_19_1, | |
128 | MSEL5CR_17_0, MSEL5CR_17_1, | |
129 | MSEL5CR_15_0, MSEL5CR_15_1, | |
130 | MSEL5CR_14_0, MSEL5CR_14_1, | |
131 | MSEL5CR_13_0, MSEL5CR_13_1, | |
132 | MSEL5CR_12_0, MSEL5CR_12_1, | |
133 | MSEL5CR_11_0, MSEL5CR_11_1, | |
134 | MSEL5CR_10_0, MSEL5CR_10_1, | |
135 | MSEL5CR_8_0, MSEL5CR_8_1, | |
136 | MSEL5CR_7_0, MSEL5CR_7_1, | |
137 | MSEL5CR_6_0, MSEL5CR_6_1, | |
138 | MSEL5CR_5_0, MSEL5CR_5_1, | |
139 | MSEL5CR_4_0, MSEL5CR_4_1, | |
140 | MSEL5CR_3_0, MSEL5CR_3_1, | |
141 | MSEL5CR_2_0, MSEL5CR_2_1, | |
142 | MSEL5CR_0_0, MSEL5CR_0_1, | |
143 | PINMUX_FUNCTION_END, | |
144 | ||
145 | PINMUX_MARK_BEGIN, | |
146 | ||
147 | /* IRQ */ | |
148 | IRQ0_PORT2_MARK, IRQ0_PORT13_MARK, | |
149 | IRQ1_MARK, | |
150 | IRQ2_PORT11_MARK, IRQ2_PORT12_MARK, | |
151 | IRQ3_PORT10_MARK, IRQ3_PORT14_MARK, | |
152 | IRQ4_PORT15_MARK, IRQ4_PORT172_MARK, | |
153 | IRQ5_PORT0_MARK, IRQ5_PORT1_MARK, | |
154 | IRQ6_PORT121_MARK, IRQ6_PORT173_MARK, | |
155 | IRQ7_PORT120_MARK, IRQ7_PORT209_MARK, | |
156 | IRQ8_MARK, | |
157 | IRQ9_PORT118_MARK, IRQ9_PORT210_MARK, | |
158 | IRQ10_MARK, | |
159 | IRQ11_MARK, | |
160 | IRQ12_PORT42_MARK, IRQ12_PORT97_MARK, | |
161 | IRQ13_PORT64_MARK, IRQ13_PORT98_MARK, | |
162 | IRQ14_PORT63_MARK, IRQ14_PORT99_MARK, | |
163 | IRQ15_PORT62_MARK, IRQ15_PORT100_MARK, | |
164 | IRQ16_PORT68_MARK, IRQ16_PORT211_MARK, | |
165 | IRQ17_MARK, | |
166 | IRQ18_MARK, | |
167 | IRQ19_MARK, | |
168 | IRQ20_MARK, | |
169 | IRQ21_MARK, | |
170 | IRQ22_MARK, | |
171 | IRQ23_MARK, | |
172 | IRQ24_MARK, | |
173 | IRQ25_MARK, | |
174 | IRQ26_PORT58_MARK, IRQ26_PORT81_MARK, | |
175 | IRQ27_PORT57_MARK, IRQ27_PORT168_MARK, | |
176 | IRQ28_PORT56_MARK, IRQ28_PORT169_MARK, | |
177 | IRQ29_PORT50_MARK, IRQ29_PORT170_MARK, | |
178 | IRQ30_PORT49_MARK, IRQ30_PORT171_MARK, | |
179 | IRQ31_PORT41_MARK, IRQ31_PORT167_MARK, | |
180 | ||
181 | /* Function */ | |
182 | ||
183 | /* DBGT */ | |
184 | DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK, | |
185 | DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK, | |
186 | DBGMD21_MARK, | |
187 | ||
188 | /* FSI-A */ | |
189 | FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */ | |
190 | FSIAISLD_PORT5_MARK, | |
191 | FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */ | |
192 | FSIASPDIF_PORT18_MARK, | |
193 | FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK, | |
194 | FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK, | |
195 | FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK, | |
196 | ||
197 | /* FSI-B */ | |
198 | FSIBCK_MARK, | |
199 | ||
200 | /* FMSI */ | |
201 | FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */ | |
202 | FMSISLD_PORT6_MARK, | |
203 | FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK, | |
204 | FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK, | |
205 | FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK, | |
206 | ||
207 | /* SCIFA0 */ | |
208 | SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK, | |
209 | SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, | |
210 | ||
211 | /* SCIFA1 */ | |
212 | SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK, | |
213 | SCIFA1_TXD_MARK, SCIFA1_RTS_MARK, | |
214 | ||
215 | /* SCIFA2 */ | |
216 | SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */ | |
217 | SCIFA2_SCK_PORT199_MARK, | |
218 | SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, | |
219 | SCIFA2_CTS_MARK, SCIFA2_RTS_MARK, | |
220 | ||
221 | /* SCIFA3 */ | |
222 | SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */ | |
223 | SCIFA3_SCK_PORT116_MARK, | |
224 | SCIFA3_CTS_PORT117_MARK, | |
225 | SCIFA3_RXD_PORT174_MARK, | |
226 | SCIFA3_TXD_PORT175_MARK, | |
227 | ||
228 | SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */ | |
229 | SCIFA3_SCK_PORT158_MARK, | |
230 | SCIFA3_CTS_PORT162_MARK, | |
231 | SCIFA3_RXD_PORT159_MARK, | |
232 | SCIFA3_TXD_PORT160_MARK, | |
233 | ||
234 | /* SCIFA4 */ | |
235 | SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */ | |
236 | SCIFA4_TXD_PORT13_MARK, | |
237 | ||
238 | SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */ | |
239 | SCIFA4_TXD_PORT203_MARK, | |
240 | ||
241 | SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */ | |
242 | SCIFA4_TXD_PORT93_MARK, | |
243 | ||
244 | SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */ | |
245 | SCIFA4_SCK_PORT205_MARK, | |
246 | ||
247 | /* SCIFA5 */ | |
248 | SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */ | |
249 | SCIFA5_RXD_PORT10_MARK, | |
250 | ||
251 | SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */ | |
252 | SCIFA5_TXD_PORT208_MARK, | |
253 | ||
254 | SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */ | |
255 | SCIFA5_RXD_PORT92_MARK, | |
256 | ||
257 | SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */ | |
258 | SCIFA5_SCK_PORT206_MARK, | |
259 | ||
260 | /* SCIFA6 */ | |
261 | SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, | |
262 | ||
263 | /* SCIFA7 */ | |
264 | SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, | |
265 | ||
266 | /* SCIFAB */ | |
267 | SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ | |
268 | SCIFB_RXD_PORT191_MARK, | |
269 | SCIFB_TXD_PORT192_MARK, | |
270 | SCIFB_RTS_PORT186_MARK, | |
271 | SCIFB_CTS_PORT187_MARK, | |
272 | ||
273 | SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */ | |
274 | SCIFB_RXD_PORT3_MARK, | |
275 | SCIFB_TXD_PORT4_MARK, | |
276 | SCIFB_RTS_PORT172_MARK, | |
277 | SCIFB_CTS_PORT173_MARK, | |
278 | ||
279 | /* LCD0 */ | |
280 | LCDC0_SELECT_MARK, | |
281 | ||
282 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
283 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
284 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
285 | LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, | |
286 | LCD0_D16_MARK, LCD0_D17_MARK, | |
287 | LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, | |
288 | LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */ | |
289 | LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */ | |
290 | LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */ | |
291 | LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */ | |
292 | ||
293 | LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */ | |
294 | LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK, | |
295 | LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK, | |
296 | LCD0_LCLK_PORT165_MARK, | |
297 | ||
298 | LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */ | |
299 | LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK, | |
300 | LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK, | |
301 | LCD0_LCLK_PORT102_MARK, | |
302 | ||
303 | /* LCD1 */ | |
304 | LCDC1_SELECT_MARK, | |
305 | ||
306 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
307 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
308 | LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, | |
309 | LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, | |
310 | LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, | |
311 | LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, | |
312 | LCD1_DON_MARK, LCD1_VCPWC_MARK, | |
313 | LCD1_LCLK_MARK, LCD1_VEPWC_MARK, | |
314 | ||
315 | LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */ | |
316 | LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */ | |
317 | LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */ | |
318 | LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */ | |
319 | ||
320 | /* RSPI */ | |
321 | RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK, | |
322 | RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK, | |
323 | RSPI_MISO_A_MARK, | |
324 | ||
325 | /* VIO CKO */ | |
326 | VIO_CKO1_MARK, /* needs fixup */ | |
327 | VIO_CKO2_MARK, | |
328 | VIO_CKO_1_MARK, | |
329 | VIO_CKO_MARK, | |
330 | ||
331 | /* VIO0 */ | |
332 | VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, | |
333 | VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, | |
334 | VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, | |
335 | VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK, | |
336 | VIO0_FIELD_MARK, | |
337 | ||
338 | VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */ | |
339 | VIO0_D14_PORT25_MARK, | |
340 | VIO0_D15_PORT24_MARK, | |
341 | ||
342 | VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */ | |
343 | VIO0_D14_PORT95_MARK, | |
344 | VIO0_D15_PORT96_MARK, | |
345 | ||
346 | /* VIO1 */ | |
347 | VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, | |
348 | VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, | |
349 | VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK, | |
350 | ||
351 | /* TPU0 */ | |
352 | TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK, | |
353 | TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */ | |
354 | TPU0TO2_PORT202_MARK, | |
355 | ||
356 | /* SSP1 0 */ | |
357 | STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK, | |
358 | STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK, | |
359 | STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK, | |
360 | ||
361 | /* SSP1 1 */ | |
362 | STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK, | |
363 | STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK, | |
364 | STP1_IPSYNC_MARK, | |
365 | ||
366 | STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */ | |
367 | STP1_IPEN_PORT187_MARK, | |
368 | ||
369 | STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */ | |
370 | STP1_IPEN_PORT193_MARK, | |
371 | ||
372 | /* SIM */ | |
373 | SIM_RST_MARK, SIM_CLK_MARK, | |
374 | SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */ | |
375 | SIM_D_PORT199_MARK, | |
376 | ||
377 | /* SDHI0 */ | |
378 | SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, | |
379 | SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK, | |
380 | ||
381 | /* SDHI1 */ | |
382 | SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, | |
383 | SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK, | |
384 | ||
385 | /* SDHI2 */ | |
386 | SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, | |
387 | SDHI2_CLK_MARK, SDHI2_CMD_MARK, | |
388 | ||
389 | SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */ | |
390 | SDHI2_WP_PORT25_MARK, | |
391 | ||
392 | SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */ | |
393 | SDHI2_CD_PORT202_MARK, | |
394 | ||
395 | /* MSIOF2 */ | |
396 | MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK, | |
397 | MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK, | |
398 | MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK, | |
399 | MSIOF2_RSCK_MARK, | |
400 | ||
401 | /* KEYSC */ | |
402 | KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, | |
403 | KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, | |
404 | KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, | |
405 | ||
406 | KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */ | |
407 | KEYIN1_PORT44_MARK, | |
408 | KEYIN2_PORT45_MARK, | |
409 | KEYIN3_PORT46_MARK, | |
410 | ||
411 | KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */ | |
412 | KEYIN1_PORT57_MARK, | |
413 | KEYIN2_PORT56_MARK, | |
414 | KEYIN3_PORT55_MARK, | |
415 | ||
416 | /* VOU */ | |
417 | DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK, | |
418 | DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK, | |
419 | DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK, | |
420 | DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK, | |
421 | DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK, | |
422 | ||
423 | /* MEMC */ | |
424 | MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK, | |
425 | MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK, | |
426 | MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, | |
427 | MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK, | |
428 | MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK, | |
429 | ||
430 | MEMC_CS1_MARK, /* MSEL4CR_6_0 */ | |
431 | MEMC_ADV_MARK, | |
432 | MEMC_WAIT_MARK, | |
433 | MEMC_BUSCLK_MARK, | |
434 | ||
435 | MEMC_A1_MARK, /* MSEL4CR_6_1 */ | |
436 | MEMC_DREQ0_MARK, | |
437 | MEMC_DREQ1_MARK, | |
438 | MEMC_A0_MARK, | |
439 | ||
440 | /* MMC */ | |
441 | MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, | |
442 | MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, | |
443 | MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK, | |
444 | MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */ | |
445 | ||
446 | MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, | |
447 | MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, | |
448 | MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK, | |
449 | MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */ | |
450 | ||
451 | /* MSIOF0 */ | |
452 | MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK, | |
453 | MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK, | |
454 | MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK, | |
455 | MSIOF0_TSYNC_MARK, | |
456 | ||
457 | /* MSIOF1 */ | |
458 | MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, | |
459 | MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, | |
460 | ||
461 | MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK, | |
462 | MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK, | |
463 | MSIOF1_TSYNC_PORT120_MARK, | |
464 | MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */ | |
465 | ||
466 | MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK, | |
467 | MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK, | |
468 | MSIOF1_RXD_PORT75_MARK, | |
469 | MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */ | |
470 | ||
471 | /* GPIO */ | |
472 | GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK, | |
473 | ||
474 | /* USB0 */ | |
475 | USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK, | |
476 | ||
477 | /* USB1 */ | |
478 | USB1_OCI_MARK, USB1_PPON_MARK, | |
479 | ||
480 | /* BBIF1 */ | |
481 | BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK, | |
482 | BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, | |
483 | BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK, | |
484 | ||
485 | /* BBIF2 */ | |
486 | BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */ | |
487 | BBIF2_RXD2_PORT60_MARK, | |
488 | BBIF2_TSYNC2_PORT6_MARK, | |
489 | BBIF2_TSCK2_PORT59_MARK, | |
490 | ||
491 | BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */ | |
492 | BBIF2_TXD2_PORT183_MARK, | |
493 | BBIF2_TSCK2_PORT89_MARK, | |
494 | BBIF2_TSYNC2_PORT184_MARK, | |
495 | ||
496 | /* BSC / FLCTL / PCMCIA */ | |
497 | CS0_MARK, CS2_MARK, CS4_MARK, | |
498 | CS5B_MARK, CS6A_MARK, | |
499 | CS5A_PORT105_MARK, /* CS5A PORT 19/105 */ | |
500 | CS5A_PORT19_MARK, | |
501 | IOIS16_MARK, /* ? */ | |
502 | ||
503 | A0_MARK, A1_MARK, A2_MARK, A3_MARK, | |
504 | A4_FOE_MARK, /* share with FLCTL */ | |
505 | A5_FCDE_MARK, /* share with FLCTL */ | |
506 | A6_MARK, A7_MARK, A8_MARK, A9_MARK, | |
507 | A10_MARK, A11_MARK, A12_MARK, A13_MARK, | |
508 | A14_MARK, A15_MARK, A16_MARK, A17_MARK, | |
509 | A18_MARK, A19_MARK, A20_MARK, A21_MARK, | |
510 | A22_MARK, A23_MARK, A24_MARK, A25_MARK, | |
511 | A26_MARK, | |
512 | ||
513 | D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */ | |
514 | D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */ | |
515 | D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */ | |
516 | D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */ | |
517 | D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */ | |
518 | D15_NAF15_MARK, /* share with FLCTL */ | |
519 | D16_MARK, D17_MARK, D18_MARK, D19_MARK, | |
520 | D20_MARK, D21_MARK, D22_MARK, D23_MARK, | |
521 | D24_MARK, D25_MARK, D26_MARK, D27_MARK, | |
522 | D28_MARK, D29_MARK, D30_MARK, D31_MARK, | |
523 | ||
524 | WE0_FWE_MARK, /* share with FLCTL */ | |
525 | WE1_MARK, | |
526 | WE2_ICIORD_MARK, /* share with PCMCIA */ | |
527 | WE3_ICIOWR_MARK, /* share with PCMCIA */ | |
528 | CKO_MARK, BS_MARK, RDWR_MARK, | |
529 | RD_FSC_MARK, /* share with FLCTL */ | |
530 | WAIT_PORT177_MARK, /* WAIT Port 90/177 */ | |
531 | WAIT_PORT90_MARK, | |
532 | ||
533 | FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */ | |
534 | ||
535 | /* IRDA */ | |
536 | IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK, | |
537 | ||
538 | /* ATAPI */ | |
539 | IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK, | |
540 | IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK, | |
541 | IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK, | |
542 | IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK, | |
543 | IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK, | |
544 | IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK, | |
545 | IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK, | |
546 | IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK, | |
547 | ||
548 | /* RMII */ | |
549 | RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK, | |
550 | RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK, | |
551 | RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK, | |
552 | RMII_REF50CK_MARK, /* for RMII */ | |
553 | RMII_REF125CK_MARK, /* for GMII */ | |
554 | ||
555 | /* GEther */ | |
556 | ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK, | |
557 | ET_ETXD2_MARK, ET_ETXD3_MARK, | |
558 | ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */ | |
559 | ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */ | |
560 | ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK, | |
561 | ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, | |
562 | ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */ | |
563 | ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */ | |
564 | ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK, | |
565 | ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK, | |
566 | ||
567 | /* DMA0 */ | |
568 | DREQ0_MARK, DACK0_MARK, | |
569 | ||
570 | /* DMA1 */ | |
571 | DREQ1_MARK, DACK1_MARK, | |
572 | ||
573 | /* SYSC */ | |
574 | RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK, | |
575 | ||
576 | /* IRREM */ | |
577 | IROUT_MARK, | |
578 | ||
579 | /* SDENC */ | |
580 | SDENC_CPG_MARK, SDENC_DV_CLKI_MARK, | |
581 | ||
582 | /* HDMI */ | |
583 | HDMI_HPD_MARK, HDMI_CEC_MARK, | |
584 | ||
585 | /* DEBUG */ | |
586 | EDEBGREQ_PULLUP_MARK, /* for JTAG */ | |
587 | EDEBGREQ_PULLDOWN_MARK, | |
588 | ||
589 | TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */ | |
590 | TRACEAUD_FROM_LCDC0_MARK, | |
591 | TRACEAUD_FROM_MEMC_MARK, | |
592 | ||
593 | PINMUX_MARK_END, | |
594 | }; | |
595 | ||
cd3c1bee | 596 | static const pinmux_enum_t pinmux_data[] = { |
d5b1521a LP |
597 | /* specify valid pin states for each pin in GPIO mode */ |
598 | ||
599 | /* I/O and Pull U/D */ | |
600 | PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), | |
601 | PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), | |
602 | PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), | |
603 | PORT_DATA_IO_PD(6), PORT_DATA_IO(7), | |
604 | PORT_DATA_IO(8), PORT_DATA_IO(9), | |
605 | ||
606 | PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), | |
607 | PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), | |
608 | PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), | |
609 | PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), | |
610 | PORT_DATA_IO(18), PORT_DATA_IO_PU(19), | |
611 | ||
612 | PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), | |
613 | PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), | |
614 | PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), | |
615 | PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), | |
616 | PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), | |
617 | ||
618 | PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), | |
619 | PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), | |
620 | PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), | |
621 | PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), | |
622 | PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), | |
623 | ||
624 | PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), | |
625 | PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), | |
626 | PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), | |
627 | PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), | |
628 | PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), | |
629 | ||
630 | PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), | |
631 | PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), | |
632 | PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), | |
633 | PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), | |
634 | PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), | |
635 | ||
636 | PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), | |
637 | PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), | |
638 | PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), | |
639 | PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), | |
640 | PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), | |
641 | ||
642 | PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), | |
643 | PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), | |
644 | PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), | |
645 | PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), | |
646 | PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), | |
647 | ||
648 | PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), | |
649 | PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), | |
650 | PORT_DATA_IO(84), PORT_DATA_IO_PD(85), | |
651 | PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), | |
652 | PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), | |
653 | ||
654 | PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), | |
655 | PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), | |
656 | PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), | |
657 | PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), | |
658 | PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), | |
659 | ||
660 | PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), | |
661 | PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), | |
662 | PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), | |
663 | PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), | |
664 | PORT_DATA_IO(108), PORT_DATA_IO(109), | |
665 | ||
666 | PORT_DATA_IO(110), PORT_DATA_IO(111), | |
667 | PORT_DATA_IO(112), PORT_DATA_IO(113), | |
668 | PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), | |
669 | PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), | |
670 | PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), | |
671 | ||
672 | PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), | |
673 | PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), | |
674 | PORT_DATA_IO_PD(124), PORT_DATA_IO(125), | |
675 | PORT_DATA_IO(126), PORT_DATA_IO(127), | |
676 | PORT_DATA_IO(128), PORT_DATA_IO(129), | |
677 | ||
678 | PORT_DATA_IO(130), PORT_DATA_IO(131), | |
679 | PORT_DATA_IO(132), PORT_DATA_IO(133), | |
680 | PORT_DATA_IO(134), PORT_DATA_IO(135), | |
681 | PORT_DATA_IO(136), PORT_DATA_IO(137), | |
682 | PORT_DATA_IO(138), PORT_DATA_IO(139), | |
683 | ||
684 | PORT_DATA_IO(140), PORT_DATA_IO(141), | |
685 | PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), | |
686 | PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), | |
687 | PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), | |
688 | PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), | |
689 | ||
690 | PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), | |
691 | PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), | |
692 | PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), | |
693 | PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), | |
694 | PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), | |
695 | ||
696 | PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), | |
697 | PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), | |
698 | PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), | |
699 | PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), | |
700 | PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), | |
701 | ||
702 | PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), | |
703 | PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), | |
704 | PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), | |
705 | PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), | |
706 | PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), | |
707 | ||
708 | PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), | |
709 | PORT_DATA_IO_PU(182), PORT_DATA_IO(183), | |
710 | PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), | |
711 | PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), | |
712 | PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), | |
713 | ||
714 | PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), | |
715 | PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), | |
716 | PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), | |
717 | PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), | |
718 | PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), | |
719 | ||
720 | PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), | |
721 | PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), | |
722 | PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), | |
723 | PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), | |
724 | PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), | |
725 | ||
726 | PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), | |
727 | ||
728 | /* Port0 */ | |
729 | PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), | |
730 | PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0), | |
731 | PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3), | |
732 | PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0), | |
733 | PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6), | |
734 | PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7), | |
735 | PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0), | |
736 | ||
737 | /* Port1 */ | |
738 | PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1), | |
739 | PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0), | |
740 | PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3), | |
741 | PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0), | |
742 | PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6), | |
743 | PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7), | |
744 | PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1), | |
745 | ||
746 | /* Port2 */ | |
747 | PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1), | |
748 | PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1), | |
749 | PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0), | |
750 | PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7), | |
751 | PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1), | |
752 | ||
753 | /* Port3 */ | |
754 | PINMUX_DATA(DBGMD21_MARK, PORT3_FN1), | |
755 | PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1), | |
756 | PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0), | |
757 | PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7), | |
758 | ||
759 | /* Port4 */ | |
760 | PINMUX_DATA(DBGMD20_MARK, PORT4_FN1), | |
761 | PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1), | |
762 | PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0), | |
763 | PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7), | |
764 | ||
765 | /* Port5 */ | |
766 | PINMUX_DATA(DBGMD11_MARK, PORT5_FN1), | |
767 | PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0), | |
768 | PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1), | |
769 | PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6), | |
770 | PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7), | |
771 | ||
772 | /* Port6 */ | |
773 | PINMUX_DATA(DBGMD10_MARK, PORT6_FN1), | |
774 | PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0), | |
775 | PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1), | |
776 | PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6), | |
777 | PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7), | |
778 | ||
779 | /* Port7 */ | |
780 | PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1), | |
781 | ||
782 | /* Port8 */ | |
783 | PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1), | |
784 | ||
785 | /* Port9 */ | |
786 | PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1), | |
787 | PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0), | |
788 | ||
789 | /* Port10 */ | |
790 | PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1), | |
791 | PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0), | |
792 | PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0), | |
793 | ||
794 | /* Port11 */ | |
795 | PINMUX_DATA(FSIACK_MARK, PORT11_FN1), | |
796 | PINMUX_DATA(FSIBCK_MARK, PORT11_FN2), | |
797 | PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0), | |
798 | ||
799 | /* Port12 */ | |
800 | PINMUX_DATA(FSIAILR_MARK, PORT12_FN1), | |
801 | PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0), | |
802 | PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6), | |
803 | PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7), | |
804 | PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1), | |
805 | ||
806 | /* Port13 */ | |
807 | PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1), | |
808 | PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0), | |
809 | PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7), | |
810 | PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0), | |
811 | ||
812 | /* Port14 */ | |
813 | PINMUX_DATA(FMSOILR_MARK, PORT14_FN1), | |
814 | PINMUX_DATA(FMSIILR_MARK, PORT14_FN2), | |
815 | PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3), | |
816 | PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7), | |
817 | PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1), | |
818 | ||
819 | /* Port15 */ | |
820 | PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1), | |
821 | PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2), | |
822 | PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3), | |
823 | PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7), | |
824 | PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0), | |
825 | ||
826 | /* Port16 */ | |
827 | PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1), | |
828 | PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2), | |
829 | ||
830 | /* Port17 */ | |
831 | PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1), | |
832 | PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2), | |
833 | ||
834 | /* Port18 */ | |
835 | PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1), | |
836 | PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1), | |
837 | ||
838 | /* Port19 */ | |
839 | PINMUX_DATA(FMSICK_MARK, PORT19_FN1), | |
840 | PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1), | |
841 | PINMUX_DATA(IRQ10_MARK, PORT19_FN0), | |
842 | ||
843 | /* Port20 */ | |
844 | PINMUX_DATA(FMSOCK_MARK, PORT20_FN1), | |
845 | PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0), | |
846 | PINMUX_DATA(IRQ1_MARK, PORT20_FN0), | |
847 | ||
848 | /* Port21 */ | |
849 | PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1), | |
850 | PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0), | |
851 | PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4), | |
852 | PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5), | |
853 | PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6), | |
854 | PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7), | |
855 | ||
856 | /* Port22 */ | |
857 | PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0), | |
858 | PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0), | |
859 | PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1), | |
860 | ||
861 | /* Port23 */ | |
862 | PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1), | |
863 | PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0), | |
864 | PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4), | |
865 | PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5), | |
866 | PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6), | |
867 | PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7), | |
868 | ||
869 | /* Port24 */ | |
870 | PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0), | |
871 | PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5), | |
872 | PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6), | |
873 | PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0), | |
874 | ||
875 | /* Port25 */ | |
876 | PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0), | |
877 | PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5), | |
878 | PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6), | |
879 | PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0), | |
880 | ||
881 | /* Port26 */ | |
882 | PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0), | |
883 | PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5), | |
884 | PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6), | |
885 | ||
886 | /* Port27 - Port39 Function */ | |
887 | PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1), | |
888 | PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1), | |
889 | PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1), | |
890 | PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1), | |
891 | PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1), | |
892 | PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1), | |
893 | PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1), | |
894 | PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1), | |
895 | PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1), | |
896 | PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1), | |
897 | PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1), | |
898 | PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1), | |
899 | PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1), | |
900 | ||
901 | /* Port38 IRQ */ | |
902 | PINMUX_DATA(IRQ25_MARK, PORT38_FN0), | |
903 | ||
904 | /* Port40 */ | |
905 | PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0), | |
906 | PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6), | |
907 | PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7), | |
908 | ||
909 | /* Port41 */ | |
910 | PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1), | |
911 | PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2), | |
912 | PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1), | |
913 | ||
914 | /* Port42 */ | |
915 | PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1), | |
916 | PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2), | |
917 | PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1), | |
918 | ||
919 | /* Port43 */ | |
920 | PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1), | |
921 | PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2), | |
922 | PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0), | |
923 | PINMUX_DATA(DV_D15_MARK, PORT43_FN6), | |
924 | ||
925 | /* Port44 */ | |
926 | PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1), | |
927 | PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2), | |
928 | PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0), | |
929 | PINMUX_DATA(DV_D14_MARK, PORT44_FN6), | |
930 | ||
931 | /* Port45 */ | |
932 | PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1), | |
933 | PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2), | |
934 | PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0), | |
935 | PINMUX_DATA(DV_D13_MARK, PORT45_FN6), | |
936 | ||
937 | /* Port46 */ | |
938 | PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1), | |
939 | PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0), | |
940 | PINMUX_DATA(DV_D12_MARK, PORT46_FN6), | |
941 | ||
942 | /* Port47 */ | |
943 | PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1), | |
944 | PINMUX_DATA(KEYIN4_MARK, PORT47_FN3), | |
945 | PINMUX_DATA(DV_D11_MARK, PORT47_FN6), | |
946 | ||
947 | /* Port48 */ | |
948 | PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1), | |
949 | PINMUX_DATA(KEYIN5_MARK, PORT48_FN3), | |
950 | PINMUX_DATA(DV_D10_MARK, PORT48_FN6), | |
951 | ||
952 | /* Port49 */ | |
953 | PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1), | |
954 | PINMUX_DATA(KEYIN6_MARK, PORT49_FN3), | |
955 | PINMUX_DATA(DV_D9_MARK, PORT49_FN6), | |
956 | PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1), | |
957 | ||
958 | /* Port50 */ | |
959 | PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1), | |
960 | PINMUX_DATA(KEYIN7_MARK, PORT50_FN3), | |
961 | PINMUX_DATA(DV_D8_MARK, PORT50_FN6), | |
962 | PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1), | |
963 | ||
964 | /* Port51 */ | |
965 | PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1), | |
966 | PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3), | |
967 | PINMUX_DATA(DV_D7_MARK, PORT51_FN6), | |
968 | ||
969 | /* Port52 */ | |
970 | PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1), | |
971 | PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3), | |
972 | PINMUX_DATA(DV_D6_MARK, PORT52_FN6), | |
973 | ||
974 | /* Port53 */ | |
975 | PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1), | |
976 | PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3), | |
977 | PINMUX_DATA(DV_D5_MARK, PORT53_FN6), | |
978 | ||
979 | /* Port54 */ | |
980 | PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1), | |
981 | PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3), | |
982 | PINMUX_DATA(DV_D4_MARK, PORT54_FN6), | |
983 | ||
984 | /* Port55 */ | |
985 | PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1), | |
986 | PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3), | |
987 | PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1), | |
988 | PINMUX_DATA(DV_D3_MARK, PORT55_FN6), | |
989 | ||
990 | /* Port56 */ | |
991 | PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1), | |
992 | PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3), | |
993 | PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1), | |
994 | PINMUX_DATA(DV_D2_MARK, PORT56_FN6), | |
995 | PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1), | |
996 | ||
997 | /* Port57 */ | |
998 | PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1), | |
999 | PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3), | |
1000 | PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1), | |
1001 | PINMUX_DATA(DV_D1_MARK, PORT57_FN6), | |
1002 | PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), | |
1003 | ||
1004 | /* Port58 */ | |
1005 | PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), | |
1006 | PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), | |
1007 | PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), | |
1008 | PINMUX_DATA(DV_D0_MARK, PORT58_FN6), | |
1009 | PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1), | |
1010 | ||
1011 | /* Port59 */ | |
1012 | PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1), | |
1013 | PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0), | |
1014 | PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6), | |
1015 | ||
1016 | /* Port60 */ | |
1017 | PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1), | |
1018 | PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0), | |
1019 | PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6), | |
1020 | ||
1021 | /* Port61 */ | |
1022 | PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1), | |
1023 | PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2), | |
1024 | ||
1025 | /* Port62 */ | |
1026 | PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1), | |
1027 | PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4), | |
1028 | PINMUX_DATA(DV_CLK_MARK, PORT62_FN6), | |
1029 | PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1), | |
1030 | ||
1031 | /* Port63 */ | |
1032 | PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1), | |
1033 | PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6), | |
1034 | PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1), | |
1035 | ||
1036 | /* Port64 */ | |
1037 | PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1), | |
1038 | PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4), | |
1039 | PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6), | |
1040 | PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1), | |
1041 | ||
1042 | /* Port65 */ | |
1043 | PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1), | |
1044 | PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2), | |
1045 | PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4), | |
1046 | ||
1047 | /* Port66 */ | |
1048 | PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1), | |
1049 | PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0), | |
1050 | PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0), | |
1051 | PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6), | |
1052 | ||
1053 | /* Port67 - Port73 Function1 */ | |
1054 | PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1), | |
1055 | PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1), | |
1056 | PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1), | |
1057 | PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1), | |
1058 | PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1), | |
1059 | PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1), | |
1060 | PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1), | |
1061 | ||
1062 | /* Port67 - Port73 Function2 */ | |
1063 | PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1), | |
1064 | PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2), | |
1065 | PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2), | |
1066 | PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2), | |
1067 | PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2), | |
1068 | PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1), | |
1069 | PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1), | |
1070 | ||
1071 | /* Port67 - Port73 Function4 */ | |
1072 | PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0), | |
1073 | PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0), | |
1074 | PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0), | |
1075 | PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0), | |
1076 | PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0), | |
1077 | PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0), | |
1078 | PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0), | |
1079 | ||
1080 | /* Port67 - Port73 Function6 */ | |
1081 | PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6), | |
1082 | PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6), | |
1083 | PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6), | |
1084 | PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6), | |
1085 | PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6), | |
1086 | PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6), | |
1087 | PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6), | |
1088 | ||
1089 | /* Port67 - Port71 IRQ */ | |
1090 | PINMUX_DATA(IRQ20_MARK, PORT67_FN0), | |
1091 | PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0), | |
1092 | PINMUX_DATA(IRQ17_MARK, PORT69_FN0), | |
1093 | PINMUX_DATA(IRQ18_MARK, PORT70_FN0), | |
1094 | PINMUX_DATA(IRQ19_MARK, PORT71_FN0), | |
1095 | ||
1096 | /* Port74 */ | |
1097 | PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1), | |
1098 | PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1), | |
1099 | PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0), | |
1100 | PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6), | |
1101 | PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7), | |
1102 | ||
1103 | /* Port75 */ | |
1104 | PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1), | |
1105 | PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1), | |
1106 | PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0), | |
1107 | PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6), | |
1108 | PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7), | |
1109 | ||
1110 | /* Port76 - Port80 Function */ | |
1111 | PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1), | |
1112 | PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1), | |
1113 | PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1), | |
1114 | PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1), | |
1115 | PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1), | |
1116 | ||
1117 | /* Port81 */ | |
1118 | PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1), | |
1119 | PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0), | |
1120 | ||
1121 | /* Port82 - Port88 Function */ | |
1122 | PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1), | |
1123 | PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1), | |
1124 | PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1), | |
1125 | PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1), | |
1126 | PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1), | |
1127 | PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1), | |
1128 | PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1), | |
1129 | ||
1130 | /* Port89 */ | |
1131 | PINMUX_DATA(DREQ0_MARK, PORT89_FN1), | |
1132 | PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1), | |
1133 | PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6), | |
1134 | ||
1135 | /* Port90 */ | |
1136 | PINMUX_DATA(DACK0_MARK, PORT90_FN1), | |
1137 | PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1), | |
1138 | PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6), | |
1139 | PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1), | |
1140 | ||
1141 | /* Port91 */ | |
1142 | PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1), | |
1143 | PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2), | |
1144 | PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0), | |
1145 | PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7), | |
1146 | ||
1147 | /* Port92 */ | |
1148 | PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1), | |
1149 | PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2), | |
1150 | PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0), | |
1151 | PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6), | |
1152 | PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7), | |
1153 | ||
1154 | /* Port93 */ | |
1155 | PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1), | |
1156 | PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2), | |
1157 | PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0), | |
1158 | PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6), | |
1159 | PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7), | |
1160 | ||
1161 | /* Port94 */ | |
1162 | PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1), | |
1163 | PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2), | |
1164 | PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0), | |
1165 | PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6), | |
1166 | PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7), | |
1167 | ||
1168 | /* Port95 */ | |
1169 | PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0), | |
1170 | PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1), | |
1171 | ||
1172 | PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2), | |
1173 | PINMUX_DATA(SIM_RST_MARK, PORT95_FN4), | |
1174 | PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1), | |
1175 | PINMUX_DATA(IRQ22_MARK, PORT95_FN0), | |
1176 | ||
1177 | /* Port96 */ | |
1178 | PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0), | |
1179 | PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1), | |
1180 | ||
1181 | PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2), | |
1182 | PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4), | |
1183 | PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1), | |
1184 | PINMUX_DATA(IRQ23_MARK, PORT96_FN0), | |
1185 | ||
1186 | /* Port97 */ | |
1187 | PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1), | |
1188 | PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2), | |
1189 | PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6), | |
1190 | PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7), | |
1191 | PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0), | |
1192 | ||
1193 | /* Port98 */ | |
1194 | PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1), | |
1195 | PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2), | |
1196 | PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7), | |
1197 | PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0), | |
1198 | ||
1199 | /* Port99 */ | |
1200 | PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1), | |
1201 | PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2), | |
1202 | PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6), | |
1203 | PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7), | |
1204 | PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0), | |
1205 | ||
1206 | /* Port100 */ | |
1207 | PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1), | |
1208 | PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2), | |
1209 | PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7), | |
1210 | PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0), | |
1211 | ||
1212 | /* Port101 */ | |
1213 | PINMUX_DATA(FCE0_MARK, PORT101_FN1), | |
1214 | ||
1215 | /* Port102 */ | |
1216 | PINMUX_DATA(FRB_MARK, PORT102_FN1), | |
1217 | PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0), | |
1218 | ||
1219 | /* Port103 */ | |
1220 | PINMUX_DATA(CS5B_MARK, PORT103_FN1), | |
1221 | PINMUX_DATA(FCE1_MARK, PORT103_FN2), | |
1222 | PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1), | |
1223 | ||
1224 | /* Port104 */ | |
1225 | PINMUX_DATA(CS6A_MARK, PORT104_FN1), | |
1226 | PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1), | |
1227 | PINMUX_DATA(IRQ11_MARK, PORT104_FN0), | |
1228 | ||
1229 | /* Port105 */ | |
1230 | PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0), | |
1231 | PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0), | |
1232 | ||
1233 | /* Port106 */ | |
1234 | PINMUX_DATA(IOIS16_MARK, PORT106_FN1), | |
1235 | PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6), | |
1236 | ||
1237 | /* Port107 - Port115 Function */ | |
1238 | PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1), | |
1239 | PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1), | |
1240 | PINMUX_DATA(CS0_MARK, PORT109_FN1), | |
1241 | PINMUX_DATA(CS2_MARK, PORT110_FN1), | |
1242 | PINMUX_DATA(CS4_MARK, PORT111_FN1), | |
1243 | PINMUX_DATA(WE1_MARK, PORT112_FN1), | |
1244 | PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1), | |
1245 | PINMUX_DATA(RDWR_MARK, PORT114_FN1), | |
1246 | PINMUX_DATA(RD_FSC_MARK, PORT115_FN1), | |
1247 | ||
1248 | /* Port116 */ | |
1249 | PINMUX_DATA(A25_MARK, PORT116_FN1), | |
1250 | PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2), | |
1251 | PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0), | |
1252 | PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0), | |
1253 | PINMUX_DATA(GPO1_MARK, PORT116_FN5), | |
1254 | ||
1255 | /* Port117 */ | |
1256 | PINMUX_DATA(A24_MARK, PORT117_FN1), | |
1257 | PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2), | |
1258 | PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0), | |
1259 | PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0), | |
1260 | PINMUX_DATA(GPO0_MARK, PORT117_FN5), | |
1261 | ||
1262 | /* Port118 */ | |
1263 | PINMUX_DATA(A23_MARK, PORT118_FN1), | |
1264 | PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2), | |
1265 | PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0), | |
1266 | PINMUX_DATA(GPI1_MARK, PORT118_FN5), | |
1267 | PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0), | |
1268 | ||
1269 | /* Port119 */ | |
1270 | PINMUX_DATA(A22_MARK, PORT119_FN1), | |
1271 | PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2), | |
1272 | PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0), | |
1273 | PINMUX_DATA(GPI0_MARK, PORT119_FN5), | |
1274 | PINMUX_DATA(IRQ8_MARK, PORT119_FN0), | |
1275 | ||
1276 | /* Port120 */ | |
1277 | PINMUX_DATA(A21_MARK, PORT120_FN1), | |
1278 | PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), | |
1279 | PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), | |
1280 | PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1), | |
1281 | ||
1282 | /* Port121 */ | |
1283 | PINMUX_DATA(A20_MARK, PORT121_FN1), | |
1284 | PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2), | |
1285 | PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0), | |
1286 | PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0), | |
1287 | ||
1288 | /* Port122 */ | |
1289 | PINMUX_DATA(A19_MARK, PORT122_FN1), | |
1290 | PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2), | |
1291 | ||
1292 | /* Port123 */ | |
1293 | PINMUX_DATA(A18_MARK, PORT123_FN1), | |
1294 | PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2), | |
1295 | ||
1296 | /* Port124 */ | |
1297 | PINMUX_DATA(A17_MARK, PORT124_FN1), | |
1298 | PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2), | |
1299 | ||
1300 | /* Port125 - Port141 Function */ | |
1301 | PINMUX_DATA(A16_MARK, PORT125_FN1), | |
1302 | PINMUX_DATA(A15_MARK, PORT126_FN1), | |
1303 | PINMUX_DATA(A14_MARK, PORT127_FN1), | |
1304 | PINMUX_DATA(A13_MARK, PORT128_FN1), | |
1305 | PINMUX_DATA(A12_MARK, PORT129_FN1), | |
1306 | PINMUX_DATA(A11_MARK, PORT130_FN1), | |
1307 | PINMUX_DATA(A10_MARK, PORT131_FN1), | |
1308 | PINMUX_DATA(A9_MARK, PORT132_FN1), | |
1309 | PINMUX_DATA(A8_MARK, PORT133_FN1), | |
1310 | PINMUX_DATA(A7_MARK, PORT134_FN1), | |
1311 | PINMUX_DATA(A6_MARK, PORT135_FN1), | |
1312 | PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1), | |
1313 | PINMUX_DATA(A4_FOE_MARK, PORT137_FN1), | |
1314 | PINMUX_DATA(A3_MARK, PORT138_FN1), | |
1315 | PINMUX_DATA(A2_MARK, PORT139_FN1), | |
1316 | PINMUX_DATA(A1_MARK, PORT140_FN1), | |
1317 | PINMUX_DATA(CKO_MARK, PORT141_FN1), | |
1318 | ||
1319 | /* Port142 - Port157 Function1 */ | |
1320 | PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1), | |
1321 | PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1), | |
1322 | PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1), | |
1323 | PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1), | |
1324 | PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1), | |
1325 | PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1), | |
1326 | PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1), | |
1327 | PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1), | |
1328 | PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1), | |
1329 | PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1), | |
1330 | PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1), | |
1331 | PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1), | |
1332 | PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1), | |
1333 | PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1), | |
1334 | PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1), | |
1335 | PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1), | |
1336 | ||
1337 | /* Port142 - Port149 Function3 */ | |
1338 | PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1), | |
1339 | PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1), | |
1340 | PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1), | |
1341 | PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1), | |
1342 | PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1), | |
1343 | PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1), | |
1344 | PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1), | |
1345 | PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1), | |
1346 | ||
1347 | /* Port158 */ | |
1348 | PINMUX_DATA(D31_MARK, PORT158_FN1), | |
1349 | PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1), | |
1350 | PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3), | |
1351 | PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1), | |
1352 | PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5), | |
1353 | PINMUX_DATA(IDE_D15_MARK, PORT158_FN6), | |
1354 | ||
1355 | /* Port159 */ | |
1356 | PINMUX_DATA(D30_MARK, PORT159_FN1), | |
1357 | PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1), | |
1358 | PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3), | |
1359 | PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1), | |
1360 | PINMUX_DATA(IDE_D14_MARK, PORT159_FN6), | |
1361 | ||
1362 | /* Port160 */ | |
1363 | PINMUX_DATA(D29_MARK, PORT160_FN1), | |
1364 | PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1), | |
1365 | PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1), | |
1366 | PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5), | |
1367 | PINMUX_DATA(IDE_D13_MARK, PORT160_FN6), | |
1368 | ||
1369 | /* Port161 */ | |
1370 | PINMUX_DATA(D28_MARK, PORT161_FN1), | |
1371 | PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1), | |
1372 | PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3), | |
1373 | PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1), | |
1374 | PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5), | |
1375 | PINMUX_DATA(IDE_D12_MARK, PORT161_FN6), | |
1376 | ||
1377 | /* Port162 */ | |
1378 | PINMUX_DATA(D27_MARK, PORT162_FN1), | |
1379 | PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1), | |
1380 | PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1), | |
1381 | PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5), | |
1382 | PINMUX_DATA(IDE_D11_MARK, PORT162_FN6), | |
1383 | ||
1384 | /* Port163 */ | |
1385 | PINMUX_DATA(D26_MARK, PORT163_FN1), | |
1386 | PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2), | |
1387 | PINMUX_DATA(ET_COL_MARK, PORT163_FN3), | |
1388 | PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1), | |
1389 | PINMUX_DATA(IROUT_MARK, PORT163_FN5), | |
1390 | PINMUX_DATA(IDE_D10_MARK, PORT163_FN6), | |
1391 | ||
1392 | /* Port164 */ | |
1393 | PINMUX_DATA(D25_MARK, PORT164_FN1), | |
1394 | PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2), | |
1395 | PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3), | |
1396 | PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4), | |
1397 | PINMUX_DATA(IDE_D9_MARK, PORT164_FN6), | |
1398 | ||
1399 | /* Port165 */ | |
1400 | PINMUX_DATA(D24_MARK, PORT165_FN1), | |
1401 | PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2), | |
1402 | PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1), | |
1403 | PINMUX_DATA(IDE_D8_MARK, PORT165_FN6), | |
1404 | ||
1405 | /* Port166 - Port171 Function1 */ | |
1406 | PINMUX_DATA(D21_MARK, PORT166_FN1), | |
1407 | PINMUX_DATA(D20_MARK, PORT167_FN1), | |
1408 | PINMUX_DATA(D19_MARK, PORT168_FN1), | |
1409 | PINMUX_DATA(D18_MARK, PORT169_FN1), | |
1410 | PINMUX_DATA(D17_MARK, PORT170_FN1), | |
1411 | PINMUX_DATA(D16_MARK, PORT171_FN1), | |
1412 | ||
1413 | /* Port166 - Port171 Function3 */ | |
1414 | PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3), | |
1415 | PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3), | |
1416 | PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3), | |
1417 | PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3), | |
1418 | PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3), | |
1419 | PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3), | |
1420 | ||
1421 | /* Port166 - Port171 Function6 */ | |
1422 | PINMUX_DATA(IDE_D5_MARK, PORT166_FN6), | |
1423 | PINMUX_DATA(IDE_D4_MARK, PORT167_FN6), | |
1424 | PINMUX_DATA(IDE_D3_MARK, PORT168_FN6), | |
1425 | PINMUX_DATA(IDE_D2_MARK, PORT169_FN6), | |
1426 | PINMUX_DATA(IDE_D1_MARK, PORT170_FN6), | |
1427 | PINMUX_DATA(IDE_D0_MARK, PORT171_FN6), | |
1428 | ||
1429 | /* Port167 - Port171 IRQ */ | |
1430 | PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0), | |
1431 | PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0), | |
1432 | PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0), | |
1433 | PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0), | |
1434 | PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0), | |
1435 | ||
1436 | /* Port172 */ | |
1437 | PINMUX_DATA(D23_MARK, PORT172_FN1), | |
1438 | PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1), | |
1439 | PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3), | |
1440 | PINMUX_DATA(IDE_D7_MARK, PORT172_FN6), | |
1441 | PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1), | |
1442 | ||
1443 | /* Port173 */ | |
1444 | PINMUX_DATA(D22_MARK, PORT173_FN1), | |
1445 | PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1), | |
1446 | PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3), | |
1447 | PINMUX_DATA(IDE_D6_MARK, PORT173_FN6), | |
1448 | PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1), | |
1449 | ||
1450 | /* Port174 */ | |
1451 | PINMUX_DATA(A26_MARK, PORT174_FN1), | |
1452 | PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2), | |
1453 | PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3), | |
1454 | PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0), | |
1455 | ||
1456 | /* Port175 */ | |
1457 | PINMUX_DATA(A0_MARK, PORT175_FN1), | |
1458 | PINMUX_DATA(BS_MARK, PORT175_FN2), | |
1459 | PINMUX_DATA(ET_WOL_MARK, PORT175_FN3), | |
1460 | PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0), | |
1461 | ||
1462 | /* Port176 */ | |
1463 | PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3), | |
1464 | ||
1465 | /* Port177 */ | |
1466 | PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0), | |
1467 | PINMUX_DATA(ET_LINK_MARK, PORT177_FN3), | |
1468 | PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6), | |
1469 | PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1), | |
1470 | ||
1471 | /* Port178 */ | |
1472 | PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1), | |
1473 | PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5), | |
1474 | PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6), | |
1475 | ||
1476 | /* Port179 */ | |
1477 | PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1), | |
1478 | PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5), | |
1479 | PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6), | |
1480 | ||
1481 | /* Port180 */ | |
1482 | PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1), | |
1483 | PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4), | |
1484 | PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5), | |
1485 | PINMUX_DATA(IDE_INT_MARK, PORT180_FN6), | |
1486 | PINMUX_DATA(IRQ24_MARK, PORT180_FN0), | |
1487 | ||
1488 | /* Port181 */ | |
1489 | PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1), | |
1490 | PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5), | |
1491 | PINMUX_DATA(IDE_RST_MARK, PORT181_FN6), | |
1492 | ||
1493 | /* Port182 */ | |
1494 | PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1), | |
1495 | PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5), | |
1496 | PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6), | |
1497 | ||
1498 | /* Port183 */ | |
1499 | PINMUX_DATA(DREQ1_MARK, PORT183_FN1), | |
1500 | PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1), | |
1501 | PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3), | |
1502 | ||
1503 | /* Port184 */ | |
1504 | PINMUX_DATA(DACK1_MARK, PORT184_FN1), | |
1505 | PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1), | |
1506 | PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3), | |
1507 | ||
1508 | /* Port185 - Port192 Function1 */ | |
1509 | PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1), | |
1510 | PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0), | |
1511 | PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0), | |
1512 | PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1), | |
1513 | PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0), | |
1514 | PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0), | |
1515 | PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0), | |
1516 | ||
1517 | /* Port185 - Port192 Function3 */ | |
1518 | PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3), | |
1519 | PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3), | |
1520 | PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3), | |
1521 | PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3), | |
1522 | PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3), | |
1523 | PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3), | |
1524 | PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3), | |
1525 | PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3), | |
1526 | ||
1527 | /* Port185 - Port192 Function6 */ | |
1528 | PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6), | |
1529 | PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0), | |
1530 | PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0), | |
1531 | PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6), | |
1532 | PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6), | |
1533 | PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6), | |
1534 | PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6), | |
1535 | PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6), | |
1536 | ||
1537 | /* Port193 */ | |
1538 | PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1), | |
1539 | PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3), | |
1540 | PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */ | |
1541 | PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7), | |
1542 | ||
1543 | /* Port194 */ | |
1544 | PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1), | |
1545 | PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3), | |
1546 | PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */ | |
1547 | PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7), | |
1548 | ||
1549 | /* Port195 */ | |
1550 | PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1), | |
1551 | PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3), | |
1552 | PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6), | |
1553 | PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7), | |
1554 | ||
1555 | /* Port196 */ | |
1556 | PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1), | |
1557 | PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3), | |
1558 | PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6), | |
1559 | PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7), | |
1560 | ||
1561 | /* Port197 */ | |
1562 | PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1), | |
1563 | PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5), | |
1564 | PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6), | |
1565 | PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7), | |
1566 | ||
1567 | /* Port198 */ | |
1568 | PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1), | |
1569 | PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5), | |
1570 | PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6), | |
1571 | PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7), | |
1572 | ||
1573 | /* Port199 */ | |
1574 | PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1), | |
1575 | PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1), | |
1576 | PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3), | |
1577 | PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1), | |
1578 | PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6), | |
1579 | PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7), | |
1580 | ||
1581 | /* Port200 */ | |
1582 | PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1), | |
1583 | PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2), | |
1584 | PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3), | |
1585 | PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6), | |
1586 | PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7), | |
1587 | ||
1588 | /* Port201 */ | |
1589 | PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0), | |
1590 | PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1), | |
1591 | ||
1592 | PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2), | |
1593 | PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3), | |
1594 | PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6), | |
1595 | PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7), | |
1596 | ||
1597 | /* Port202 */ | |
1598 | PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0), | |
1599 | PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1), | |
1600 | ||
1601 | PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1), | |
1602 | PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3), | |
1603 | PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1), | |
1604 | PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6), | |
1605 | PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1), | |
1606 | PINMUX_DATA(IRQ21_MARK, PORT202_FN0), | |
1607 | ||
1608 | /* Port203 - Port208 Function1 */ | |
1609 | PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1), | |
1610 | PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1), | |
1611 | PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1), | |
1612 | PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1), | |
1613 | PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1), | |
1614 | PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1), | |
1615 | ||
1616 | /* Port203 - Port208 Function3 */ | |
1617 | PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3), | |
1618 | PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3), | |
1619 | PINMUX_DATA(ET_CRS_MARK, PORT205_FN3), | |
1620 | PINMUX_DATA(ET_MDC_MARK, PORT206_FN3), | |
1621 | PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3), | |
1622 | PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3), | |
1623 | ||
1624 | /* Port203 - Port208 Function6 */ | |
1625 | PINMUX_DATA(IDE_A2_MARK, PORT203_FN6), | |
1626 | PINMUX_DATA(IDE_A1_MARK, PORT204_FN6), | |
1627 | PINMUX_DATA(IDE_A0_MARK, PORT205_FN6), | |
1628 | PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6), | |
1629 | PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6), | |
1630 | PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6), | |
1631 | ||
1632 | /* Port203 - Port208 Function7 */ | |
1633 | PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1), | |
1634 | PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1), | |
1635 | PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1), | |
1636 | PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1), | |
1637 | PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1), | |
1638 | PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1), | |
1639 | ||
1640 | /* Port209 */ | |
1641 | PINMUX_DATA(VBUS_MARK, PORT209_FN1), | |
1642 | PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0), | |
1643 | ||
1644 | /* Port210 */ | |
1645 | PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), | |
1646 | PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1), | |
1647 | ||
1648 | /* Port211 */ | |
1649 | PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), | |
1650 | PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1), | |
1651 | ||
1652 | /* LCDC select */ | |
1653 | PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), | |
1654 | PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), | |
1655 | ||
1656 | /* SDENC */ | |
1657 | PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), | |
1658 | PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), | |
1659 | ||
1660 | /* SYSC */ | |
1661 | PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0), | |
1662 | PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1), | |
1663 | ||
1664 | /* DEBUG */ | |
1665 | PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0), | |
1666 | PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1), | |
1667 | ||
1668 | PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0), | |
1669 | PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1), | |
1670 | PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), | |
1671 | }; | |
1672 | ||
a3db40a6 | 1673 | static struct sh_pfc_pin pinmux_pins[] = { |
d5b1521a | 1674 | GPIO_PORT_ALL(), |
a373ed0a LP |
1675 | }; |
1676 | ||
09bbc1fd BH |
1677 | /* - INTC ------------------------------------------------------------------- */ |
1678 | IRQC_PINS_MUX(0, 0, 2); | |
1679 | IRQC_PINS_MUX(0, 1, 13); | |
1680 | IRQC_PIN_MUX(1, 20); | |
1681 | IRQC_PINS_MUX(2, 0, 11); | |
1682 | IRQC_PINS_MUX(2, 1, 12); | |
1683 | IRQC_PINS_MUX(3, 0, 10); | |
1684 | IRQC_PINS_MUX(3, 1, 14); | |
1685 | IRQC_PINS_MUX(4, 0, 15); | |
1686 | IRQC_PINS_MUX(4, 1, 172); | |
1687 | IRQC_PINS_MUX(5, 0, 0); | |
1688 | IRQC_PINS_MUX(5, 1, 1); | |
1689 | IRQC_PINS_MUX(6, 0, 121); | |
1690 | IRQC_PINS_MUX(6, 1, 173); | |
1691 | IRQC_PINS_MUX(7, 0, 120); | |
1692 | IRQC_PINS_MUX(7, 1, 209); | |
1693 | IRQC_PIN_MUX(8, 119); | |
1694 | IRQC_PINS_MUX(9, 0, 118); | |
1695 | IRQC_PINS_MUX(9, 1, 210); | |
1696 | IRQC_PIN_MUX(10, 19); | |
1697 | IRQC_PIN_MUX(11, 104); | |
1698 | IRQC_PINS_MUX(12, 0, 42); | |
1699 | IRQC_PINS_MUX(12, 1, 97); | |
1700 | IRQC_PINS_MUX(13, 0, 64); | |
1701 | IRQC_PINS_MUX(13, 1, 98); | |
1702 | IRQC_PINS_MUX(14, 0, 63); | |
1703 | IRQC_PINS_MUX(14, 1, 99); | |
1704 | IRQC_PINS_MUX(15, 0, 62); | |
1705 | IRQC_PINS_MUX(15, 1, 100); | |
1706 | IRQC_PINS_MUX(16, 0, 68); | |
1707 | IRQC_PINS_MUX(16, 1, 211); | |
1708 | IRQC_PIN_MUX(17, 69); | |
1709 | IRQC_PIN_MUX(18, 70); | |
1710 | IRQC_PIN_MUX(19, 71); | |
1711 | IRQC_PIN_MUX(20, 67); | |
1712 | IRQC_PIN_MUX(21, 202); | |
1713 | IRQC_PIN_MUX(22, 95); | |
1714 | IRQC_PIN_MUX(23, 96); | |
1715 | IRQC_PIN_MUX(24, 180); | |
1716 | IRQC_PIN_MUX(25, 38); | |
1717 | IRQC_PINS_MUX(26, 0, 58); | |
1718 | IRQC_PINS_MUX(26, 1, 81); | |
1719 | IRQC_PINS_MUX(27, 0, 57); | |
1720 | IRQC_PINS_MUX(27, 1, 168); | |
1721 | IRQC_PINS_MUX(28, 0, 56); | |
1722 | IRQC_PINS_MUX(28, 1, 169); | |
1723 | IRQC_PINS_MUX(29, 0, 50); | |
1724 | IRQC_PINS_MUX(29, 1, 170); | |
1725 | IRQC_PINS_MUX(30, 0, 49); | |
1726 | IRQC_PINS_MUX(30, 1, 171); | |
1727 | IRQC_PINS_MUX(31, 0, 41); | |
1728 | IRQC_PINS_MUX(31, 1, 167); | |
1729 | ||
06c7dd86 LP |
1730 | /* - LCD0 ------------------------------------------------------------------- */ |
1731 | static const unsigned int lcd0_data8_pins[] = { | |
1732 | /* D[0:7] */ | |
1733 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1734 | }; | |
1735 | static const unsigned int lcd0_data8_mux[] = { | |
1736 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1737 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1738 | }; | |
1739 | static const unsigned int lcd0_data9_pins[] = { | |
1740 | /* D[0:8] */ | |
1741 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1742 | 50, | |
1743 | }; | |
1744 | static const unsigned int lcd0_data9_mux[] = { | |
1745 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1746 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1747 | LCD0_D8_MARK, | |
1748 | }; | |
1749 | static const unsigned int lcd0_data12_pins[] = { | |
1750 | /* D[0:11] */ | |
1751 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1752 | 50, 49, 48, 47, | |
1753 | }; | |
1754 | static const unsigned int lcd0_data12_mux[] = { | |
1755 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1756 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1757 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
1758 | }; | |
1759 | static const unsigned int lcd0_data16_pins[] = { | |
1760 | /* D[0:15] */ | |
1761 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1762 | 50, 49, 48, 47, 46, 45, 44, 43, | |
1763 | }; | |
1764 | static const unsigned int lcd0_data16_mux[] = { | |
1765 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1766 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1767 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
1768 | LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, | |
1769 | }; | |
1770 | static const unsigned int lcd0_data18_pins[] = { | |
1771 | /* D[0:17] */ | |
1772 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1773 | 50, 49, 48, 47, 46, 45, 44, 43, | |
1774 | 42, 41, | |
1775 | }; | |
1776 | static const unsigned int lcd0_data18_mux[] = { | |
1777 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1778 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1779 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
1780 | LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, | |
1781 | LCD0_D16_MARK, LCD0_D17_MARK, | |
1782 | }; | |
1783 | static const unsigned int lcd0_data24_0_pins[] = { | |
1784 | /* D[0:23] */ | |
1785 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1786 | 50, 49, 48, 47, 46, 45, 44, 43, | |
1787 | 42, 41, 40, 4, 3, 2, 0, 1, | |
1788 | }; | |
1789 | static const unsigned int lcd0_data24_0_mux[] = { | |
1790 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1791 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1792 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
1793 | LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, | |
1794 | LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK, | |
1795 | LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK, | |
1796 | LCD0_D23_PORT1_MARK, | |
1797 | }; | |
1798 | static const unsigned int lcd0_data24_1_pins[] = { | |
1799 | /* D[0:23] */ | |
1800 | 58, 57, 56, 55, 54, 53, 52, 51, | |
1801 | 50, 49, 48, 47, 46, 45, 44, 43, | |
1802 | 42, 41, 163, 162, 161, 158, 160, 159, | |
1803 | }; | |
1804 | static const unsigned int lcd0_data24_1_mux[] = { | |
1805 | LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, | |
1806 | LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, | |
1807 | LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, | |
1808 | LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK, | |
1809 | LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK, | |
1810 | LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK, | |
1811 | }; | |
1812 | static const unsigned int lcd0_display_pins[] = { | |
1813 | /* DON, VCPWC, VEPWC */ | |
1814 | 61, 59, 60, | |
1815 | }; | |
1816 | static const unsigned int lcd0_display_mux[] = { | |
1817 | LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, | |
1818 | }; | |
1819 | static const unsigned int lcd0_lclk_0_pins[] = { | |
1820 | /* LCLK */ | |
1821 | 102, | |
1822 | }; | |
1823 | static const unsigned int lcd0_lclk_0_mux[] = { | |
1824 | LCD0_LCLK_PORT102_MARK, | |
1825 | }; | |
1826 | static const unsigned int lcd0_lclk_1_pins[] = { | |
1827 | /* LCLK */ | |
1828 | 165, | |
1829 | }; | |
1830 | static const unsigned int lcd0_lclk_1_mux[] = { | |
1831 | LCD0_LCLK_PORT165_MARK, | |
1832 | }; | |
1833 | static const unsigned int lcd0_sync_pins[] = { | |
1834 | /* VSYN, HSYN, DCK, DISP */ | |
1835 | 63, 64, 62, 65, | |
1836 | }; | |
1837 | static const unsigned int lcd0_sync_mux[] = { | |
1838 | LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK, | |
1839 | }; | |
1840 | static const unsigned int lcd0_sys_pins[] = { | |
1841 | /* CS, WR, RD, RS */ | |
1842 | 64, 62, 164, 65, | |
1843 | }; | |
1844 | static const unsigned int lcd0_sys_mux[] = { | |
1845 | LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK, | |
1846 | }; | |
1847 | /* - LCD1 ------------------------------------------------------------------- */ | |
1848 | static const unsigned int lcd1_data8_pins[] = { | |
1849 | /* D[0:7] */ | |
1850 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1851 | }; | |
1852 | static const unsigned int lcd1_data8_mux[] = { | |
1853 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1854 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1855 | }; | |
1856 | static const unsigned int lcd1_data9_pins[] = { | |
1857 | /* D[0:8] */ | |
1858 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1859 | 93, | |
1860 | }; | |
1861 | static const unsigned int lcd1_data9_mux[] = { | |
1862 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1863 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1864 | LCD1_D8_MARK, | |
1865 | }; | |
1866 | static const unsigned int lcd1_data12_pins[] = { | |
1867 | /* D[0:12] */ | |
1868 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1869 | 93, 94, 21, 201, | |
1870 | }; | |
1871 | static const unsigned int lcd1_data12_mux[] = { | |
1872 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1873 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1874 | LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, | |
1875 | }; | |
1876 | static const unsigned int lcd1_data16_pins[] = { | |
1877 | /* D[0:15] */ | |
1878 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1879 | 93, 94, 21, 201, 200, 199, 196, 195, | |
1880 | }; | |
1881 | static const unsigned int lcd1_data16_mux[] = { | |
1882 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1883 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1884 | LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, | |
1885 | LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, | |
1886 | }; | |
1887 | static const unsigned int lcd1_data18_pins[] = { | |
1888 | /* D[0:17] */ | |
1889 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1890 | 93, 94, 21, 201, 200, 199, 196, 195, | |
1891 | 194, 193, | |
1892 | }; | |
1893 | static const unsigned int lcd1_data18_mux[] = { | |
1894 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1895 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1896 | LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, | |
1897 | LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, | |
1898 | LCD1_D16_MARK, LCD1_D17_MARK, | |
1899 | }; | |
1900 | static const unsigned int lcd1_data24_pins[] = { | |
1901 | /* D[0:23] */ | |
1902 | 4, 3, 2, 1, 0, 91, 92, 23, | |
1903 | 93, 94, 21, 201, 200, 199, 196, 195, | |
1904 | 194, 193, 198, 197, 75, 74, 15, 14, | |
1905 | }; | |
1906 | static const unsigned int lcd1_data24_mux[] = { | |
1907 | LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, | |
1908 | LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, | |
1909 | LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, | |
1910 | LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, | |
1911 | LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, | |
1912 | LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, | |
1913 | }; | |
1914 | static const unsigned int lcd1_display_pins[] = { | |
1915 | /* DON, VCPWC, VEPWC */ | |
1916 | 100, 5, 6, | |
1917 | }; | |
1918 | static const unsigned int lcd1_display_mux[] = { | |
1919 | LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK, | |
1920 | }; | |
1921 | static const unsigned int lcd1_lclk_pins[] = { | |
1922 | /* LCLK */ | |
1923 | 40, | |
1924 | }; | |
1925 | static const unsigned int lcd1_lclk_mux[] = { | |
1926 | LCD1_LCLK_MARK, | |
1927 | }; | |
1928 | static const unsigned int lcd1_sync_pins[] = { | |
1929 | /* VSYN, HSYN, DCK, DISP */ | |
1930 | 98, 97, 99, 12, | |
1931 | }; | |
1932 | static const unsigned int lcd1_sync_mux[] = { | |
1933 | LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK, | |
1934 | }; | |
1935 | static const unsigned int lcd1_sys_pins[] = { | |
1936 | /* CS, WR, RD, RS */ | |
1937 | 97, 99, 13, 12, | |
1938 | }; | |
1939 | static const unsigned int lcd1_sys_mux[] = { | |
1940 | LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK, | |
1941 | }; | |
8b2810b9 GL |
1942 | /* - MMCIF ------------------------------------------------------------------ */ |
1943 | static const unsigned int mmc0_data1_0_pins[] = { | |
1944 | /* D[0] */ | |
1945 | 68, | |
1946 | }; | |
1947 | static const unsigned int mmc0_data1_0_mux[] = { | |
1948 | MMC0_D0_PORT68_MARK, | |
1949 | }; | |
1950 | static const unsigned int mmc0_data4_0_pins[] = { | |
1951 | /* D[0:3] */ | |
1952 | 68, 69, 70, 71, | |
1953 | }; | |
1954 | static const unsigned int mmc0_data4_0_mux[] = { | |
1955 | MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, | |
1956 | }; | |
1957 | static const unsigned int mmc0_data8_0_pins[] = { | |
1958 | /* D[0:7] */ | |
1959 | 68, 69, 70, 71, 72, 73, 74, 75, | |
1960 | }; | |
1961 | static const unsigned int mmc0_data8_0_mux[] = { | |
1962 | MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK, | |
1963 | MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, | |
1964 | }; | |
1965 | static const unsigned int mmc0_ctrl_0_pins[] = { | |
1966 | /* CMD, CLK */ | |
1967 | 67, 66, | |
1968 | }; | |
1969 | static const unsigned int mmc0_ctrl_0_mux[] = { | |
1970 | MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK, | |
1971 | }; | |
1972 | ||
1973 | static const unsigned int mmc0_data1_1_pins[] = { | |
1974 | /* D[0] */ | |
1975 | 149, | |
1976 | }; | |
1977 | static const unsigned int mmc0_data1_1_mux[] = { | |
1978 | MMC1_D0_PORT149_MARK, | |
1979 | }; | |
1980 | static const unsigned int mmc0_data4_1_pins[] = { | |
1981 | /* D[0:3] */ | |
1982 | 149, 148, 147, 146, | |
1983 | }; | |
1984 | static const unsigned int mmc0_data4_1_mux[] = { | |
1985 | MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, | |
1986 | }; | |
1987 | static const unsigned int mmc0_data8_1_pins[] = { | |
1988 | /* D[0:7] */ | |
1989 | 149, 148, 147, 146, 145, 144, 143, 142, | |
1990 | }; | |
1991 | static const unsigned int mmc0_data8_1_mux[] = { | |
1992 | MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK, | |
1993 | MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, | |
1994 | }; | |
1995 | static const unsigned int mmc0_ctrl_1_pins[] = { | |
1996 | /* CMD, CLK */ | |
1997 | 104, 103, | |
1998 | }; | |
1999 | static const unsigned int mmc0_ctrl_1_mux[] = { | |
2000 | MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK, | |
2001 | }; | |
2002 | /* - SDHI0 ------------------------------------------------------------------ */ | |
2003 | static const unsigned int sdhi0_data1_pins[] = { | |
2004 | /* D0 */ | |
2005 | 77, | |
2006 | }; | |
2007 | static const unsigned int sdhi0_data1_mux[] = { | |
2008 | SDHI0_D0_MARK, | |
2009 | }; | |
2010 | static const unsigned int sdhi0_data4_pins[] = { | |
2011 | /* D[0:3] */ | |
2012 | 77, 78, 79, 80, | |
2013 | }; | |
2014 | static const unsigned int sdhi0_data4_mux[] = { | |
2015 | SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, | |
2016 | }; | |
2017 | static const unsigned int sdhi0_ctrl_pins[] = { | |
2018 | /* CMD, CLK */ | |
2019 | 76, 82, | |
2020 | }; | |
2021 | static const unsigned int sdhi0_ctrl_mux[] = { | |
2022 | SDHI0_CMD_MARK, SDHI0_CLK_MARK, | |
2023 | }; | |
2024 | static const unsigned int sdhi0_cd_pins[] = { | |
2025 | /* CD */ | |
2026 | 81, | |
2027 | }; | |
2028 | static const unsigned int sdhi0_cd_mux[] = { | |
2029 | SDHI0_CD_MARK, | |
2030 | }; | |
2031 | static const unsigned int sdhi0_wp_pins[] = { | |
2032 | /* WP */ | |
2033 | 83, | |
2034 | }; | |
2035 | static const unsigned int sdhi0_wp_mux[] = { | |
2036 | SDHI0_WP_MARK, | |
2037 | }; | |
2038 | /* - SDHI1 ------------------------------------------------------------------ */ | |
2039 | static const unsigned int sdhi1_data1_pins[] = { | |
2040 | /* D0 */ | |
2041 | 68, | |
2042 | }; | |
2043 | static const unsigned int sdhi1_data1_mux[] = { | |
2044 | SDHI1_D0_MARK, | |
2045 | }; | |
2046 | static const unsigned int sdhi1_data4_pins[] = { | |
2047 | /* D[0:3] */ | |
2048 | 68, 69, 70, 71, | |
2049 | }; | |
2050 | static const unsigned int sdhi1_data4_mux[] = { | |
2051 | SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, | |
2052 | }; | |
2053 | static const unsigned int sdhi1_ctrl_pins[] = { | |
2054 | /* CMD, CLK */ | |
2055 | 67, 66, | |
2056 | }; | |
2057 | static const unsigned int sdhi1_ctrl_mux[] = { | |
2058 | SDHI1_CMD_MARK, SDHI1_CLK_MARK, | |
2059 | }; | |
2060 | static const unsigned int sdhi1_cd_pins[] = { | |
2061 | /* CD */ | |
2062 | 72, | |
2063 | }; | |
2064 | static const unsigned int sdhi1_cd_mux[] = { | |
2065 | SDHI1_CD_MARK, | |
2066 | }; | |
2067 | static const unsigned int sdhi1_wp_pins[] = { | |
2068 | /* WP */ | |
2069 | 73, | |
2070 | }; | |
2071 | static const unsigned int sdhi1_wp_mux[] = { | |
2072 | SDHI1_WP_MARK, | |
2073 | }; | |
2074 | /* - SDHI2 ------------------------------------------------------------------ */ | |
2075 | static const unsigned int sdhi2_data1_pins[] = { | |
2076 | /* D0 */ | |
2077 | 205, | |
2078 | }; | |
2079 | static const unsigned int sdhi2_data1_mux[] = { | |
2080 | SDHI2_D0_MARK, | |
2081 | }; | |
2082 | static const unsigned int sdhi2_data4_pins[] = { | |
2083 | /* D[0:3] */ | |
2084 | 205, 206, 207, 208, | |
2085 | }; | |
2086 | static const unsigned int sdhi2_data4_mux[] = { | |
2087 | SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, | |
2088 | }; | |
2089 | static const unsigned int sdhi2_ctrl_pins[] = { | |
2090 | /* CMD, CLK */ | |
2091 | 204, 203, | |
2092 | }; | |
2093 | static const unsigned int sdhi2_ctrl_mux[] = { | |
2094 | SDHI2_CMD_MARK, SDHI2_CLK_MARK, | |
2095 | }; | |
2096 | static const unsigned int sdhi2_cd_0_pins[] = { | |
2097 | /* CD */ | |
2098 | 202, | |
2099 | }; | |
2100 | static const unsigned int sdhi2_cd_0_mux[] = { | |
2101 | SDHI2_CD_PORT202_MARK, | |
2102 | }; | |
2103 | static const unsigned int sdhi2_wp_0_pins[] = { | |
2104 | /* WP */ | |
2105 | 177, | |
2106 | }; | |
2107 | static const unsigned int sdhi2_wp_0_mux[] = { | |
2108 | SDHI2_WP_PORT177_MARK, | |
2109 | }; | |
2110 | static const unsigned int sdhi2_cd_1_pins[] = { | |
2111 | /* CD */ | |
2112 | 24, | |
2113 | }; | |
2114 | static const unsigned int sdhi2_cd_1_mux[] = { | |
2115 | SDHI2_CD_PORT24_MARK, | |
2116 | }; | |
2117 | static const unsigned int sdhi2_wp_1_pins[] = { | |
2118 | /* WP */ | |
2119 | 25, | |
2120 | }; | |
2121 | static const unsigned int sdhi2_wp_1_mux[] = { | |
2122 | SDHI2_WP_PORT25_MARK, | |
2123 | }; | |
06c7dd86 LP |
2124 | |
2125 | static const struct sh_pfc_pin_group pinmux_groups[] = { | |
09bbc1fd BH |
2126 | SH_PFC_PIN_GROUP(intc_irq0_0), |
2127 | SH_PFC_PIN_GROUP(intc_irq0_1), | |
2128 | SH_PFC_PIN_GROUP(intc_irq1), | |
2129 | SH_PFC_PIN_GROUP(intc_irq2_0), | |
2130 | SH_PFC_PIN_GROUP(intc_irq2_1), | |
2131 | SH_PFC_PIN_GROUP(intc_irq3_0), | |
2132 | SH_PFC_PIN_GROUP(intc_irq3_1), | |
2133 | SH_PFC_PIN_GROUP(intc_irq4_0), | |
2134 | SH_PFC_PIN_GROUP(intc_irq4_1), | |
2135 | SH_PFC_PIN_GROUP(intc_irq5_0), | |
2136 | SH_PFC_PIN_GROUP(intc_irq5_1), | |
2137 | SH_PFC_PIN_GROUP(intc_irq6_0), | |
2138 | SH_PFC_PIN_GROUP(intc_irq6_1), | |
2139 | SH_PFC_PIN_GROUP(intc_irq7_0), | |
2140 | SH_PFC_PIN_GROUP(intc_irq7_1), | |
2141 | SH_PFC_PIN_GROUP(intc_irq8), | |
2142 | SH_PFC_PIN_GROUP(intc_irq9_0), | |
2143 | SH_PFC_PIN_GROUP(intc_irq9_1), | |
2144 | SH_PFC_PIN_GROUP(intc_irq10), | |
2145 | SH_PFC_PIN_GROUP(intc_irq11), | |
2146 | SH_PFC_PIN_GROUP(intc_irq12_0), | |
2147 | SH_PFC_PIN_GROUP(intc_irq12_1), | |
2148 | SH_PFC_PIN_GROUP(intc_irq13_0), | |
2149 | SH_PFC_PIN_GROUP(intc_irq13_1), | |
2150 | SH_PFC_PIN_GROUP(intc_irq14_0), | |
2151 | SH_PFC_PIN_GROUP(intc_irq14_1), | |
2152 | SH_PFC_PIN_GROUP(intc_irq15_0), | |
2153 | SH_PFC_PIN_GROUP(intc_irq15_1), | |
2154 | SH_PFC_PIN_GROUP(intc_irq16_0), | |
2155 | SH_PFC_PIN_GROUP(intc_irq16_1), | |
2156 | SH_PFC_PIN_GROUP(intc_irq17), | |
2157 | SH_PFC_PIN_GROUP(intc_irq18), | |
2158 | SH_PFC_PIN_GROUP(intc_irq19), | |
2159 | SH_PFC_PIN_GROUP(intc_irq20), | |
2160 | SH_PFC_PIN_GROUP(intc_irq21), | |
2161 | SH_PFC_PIN_GROUP(intc_irq22), | |
2162 | SH_PFC_PIN_GROUP(intc_irq23), | |
2163 | SH_PFC_PIN_GROUP(intc_irq24), | |
2164 | SH_PFC_PIN_GROUP(intc_irq25), | |
2165 | SH_PFC_PIN_GROUP(intc_irq26_0), | |
2166 | SH_PFC_PIN_GROUP(intc_irq26_1), | |
2167 | SH_PFC_PIN_GROUP(intc_irq27_0), | |
2168 | SH_PFC_PIN_GROUP(intc_irq27_1), | |
2169 | SH_PFC_PIN_GROUP(intc_irq28_0), | |
2170 | SH_PFC_PIN_GROUP(intc_irq28_1), | |
2171 | SH_PFC_PIN_GROUP(intc_irq29_0), | |
2172 | SH_PFC_PIN_GROUP(intc_irq29_1), | |
2173 | SH_PFC_PIN_GROUP(intc_irq30_0), | |
2174 | SH_PFC_PIN_GROUP(intc_irq30_1), | |
2175 | SH_PFC_PIN_GROUP(intc_irq31_0), | |
2176 | SH_PFC_PIN_GROUP(intc_irq31_1), | |
06c7dd86 LP |
2177 | SH_PFC_PIN_GROUP(lcd0_data8), |
2178 | SH_PFC_PIN_GROUP(lcd0_data9), | |
2179 | SH_PFC_PIN_GROUP(lcd0_data12), | |
2180 | SH_PFC_PIN_GROUP(lcd0_data16), | |
2181 | SH_PFC_PIN_GROUP(lcd0_data18), | |
2182 | SH_PFC_PIN_GROUP(lcd0_data24_0), | |
2183 | SH_PFC_PIN_GROUP(lcd0_data24_1), | |
2184 | SH_PFC_PIN_GROUP(lcd0_display), | |
2185 | SH_PFC_PIN_GROUP(lcd0_lclk_0), | |
2186 | SH_PFC_PIN_GROUP(lcd0_lclk_1), | |
2187 | SH_PFC_PIN_GROUP(lcd0_sync), | |
2188 | SH_PFC_PIN_GROUP(lcd0_sys), | |
2189 | SH_PFC_PIN_GROUP(lcd1_data8), | |
2190 | SH_PFC_PIN_GROUP(lcd1_data9), | |
2191 | SH_PFC_PIN_GROUP(lcd1_data12), | |
2192 | SH_PFC_PIN_GROUP(lcd1_data16), | |
2193 | SH_PFC_PIN_GROUP(lcd1_data18), | |
2194 | SH_PFC_PIN_GROUP(lcd1_data24), | |
2195 | SH_PFC_PIN_GROUP(lcd1_display), | |
2196 | SH_PFC_PIN_GROUP(lcd1_lclk), | |
2197 | SH_PFC_PIN_GROUP(lcd1_sync), | |
2198 | SH_PFC_PIN_GROUP(lcd1_sys), | |
8b2810b9 GL |
2199 | SH_PFC_PIN_GROUP(mmc0_data1_0), |
2200 | SH_PFC_PIN_GROUP(mmc0_data4_0), | |
2201 | SH_PFC_PIN_GROUP(mmc0_data8_0), | |
2202 | SH_PFC_PIN_GROUP(mmc0_ctrl_0), | |
2203 | SH_PFC_PIN_GROUP(mmc0_data1_1), | |
2204 | SH_PFC_PIN_GROUP(mmc0_data4_1), | |
2205 | SH_PFC_PIN_GROUP(mmc0_data8_1), | |
2206 | SH_PFC_PIN_GROUP(mmc0_ctrl_1), | |
2207 | SH_PFC_PIN_GROUP(sdhi0_data1), | |
2208 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
2209 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
2210 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
2211 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
2212 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
2213 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
2214 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
2215 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
2216 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
2217 | SH_PFC_PIN_GROUP(sdhi2_data1), | |
2218 | SH_PFC_PIN_GROUP(sdhi2_data4), | |
2219 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | |
2220 | SH_PFC_PIN_GROUP(sdhi2_cd_0), | |
2221 | SH_PFC_PIN_GROUP(sdhi2_wp_0), | |
2222 | SH_PFC_PIN_GROUP(sdhi2_cd_1), | |
2223 | SH_PFC_PIN_GROUP(sdhi2_wp_1), | |
06c7dd86 LP |
2224 | }; |
2225 | ||
09bbc1fd BH |
2226 | static const char * const intc_groups[] = { |
2227 | "intc_irq0_0", | |
2228 | "intc_irq0_1", | |
2229 | "intc_irq1", | |
2230 | "intc_irq2_0", | |
2231 | "intc_irq2_1", | |
2232 | "intc_irq3_0", | |
2233 | "intc_irq3_1", | |
2234 | "intc_irq4_0", | |
2235 | "intc_irq4_1", | |
2236 | "intc_irq5_0", | |
2237 | "intc_irq5_1", | |
2238 | "intc_irq6_0", | |
2239 | "intc_irq6_1", | |
2240 | "intc_irq7_0", | |
2241 | "intc_irq7_1", | |
2242 | "intc_irq8", | |
2243 | "intc_irq9_0", | |
2244 | "intc_irq9_1", | |
2245 | "intc_irq10", | |
2246 | "intc_irq11", | |
2247 | "intc_irq12_0", | |
2248 | "intc_irq12_1", | |
2249 | "intc_irq13_0", | |
2250 | "intc_irq13_1", | |
2251 | "intc_irq14_0", | |
2252 | "intc_irq14_1", | |
2253 | "intc_irq15_0", | |
2254 | "intc_irq15_1", | |
2255 | "intc_irq16_0", | |
2256 | "intc_irq16_1", | |
2257 | "intc_irq17", | |
2258 | "intc_irq18", | |
2259 | "intc_irq19", | |
2260 | "intc_irq20", | |
2261 | "intc_irq21", | |
2262 | "intc_irq22", | |
2263 | "intc_irq23", | |
2264 | "intc_irq24", | |
2265 | "intc_irq25", | |
2266 | "intc_irq26_0", | |
2267 | "intc_irq26_1", | |
2268 | "intc_irq27_0", | |
2269 | "intc_irq27_1", | |
2270 | "intc_irq28_0", | |
2271 | "intc_irq28_1", | |
2272 | "intc_irq29_0", | |
2273 | "intc_irq29_1", | |
2274 | "intc_irq30_0", | |
2275 | "intc_irq30_1", | |
2276 | "intc_irq31_0", | |
2277 | "intc_irq31_1", | |
2278 | }; | |
2279 | ||
06c7dd86 LP |
2280 | static const char * const lcd0_groups[] = { |
2281 | "lcd0_data8", | |
2282 | "lcd0_data9", | |
2283 | "lcd0_data12", | |
2284 | "lcd0_data16", | |
2285 | "lcd0_data18", | |
2286 | "lcd0_data24_0", | |
2287 | "lcd0_data24_1", | |
2288 | "lcd0_display", | |
2289 | "lcd0_lclk_0", | |
2290 | "lcd0_lclk_1", | |
2291 | "lcd0_sync", | |
2292 | "lcd0_sys", | |
2293 | }; | |
2294 | ||
2295 | static const char * const lcd1_groups[] = { | |
2296 | "lcd1_data8", | |
2297 | "lcd1_data9", | |
2298 | "lcd1_data12", | |
2299 | "lcd1_data16", | |
2300 | "lcd1_data18", | |
2301 | "lcd1_data24", | |
2302 | "lcd1_display", | |
2303 | "lcd1_lclk", | |
2304 | "lcd1_sync", | |
2305 | "lcd1_sys", | |
2306 | }; | |
2307 | ||
8b2810b9 GL |
2308 | static const char * const mmc0_groups[] = { |
2309 | "mmc0_data1_0", | |
2310 | "mmc0_data4_0", | |
2311 | "mmc0_data8_0", | |
2312 | "mmc0_ctrl_0", | |
2313 | "mmc0_data1_1", | |
2314 | "mmc0_data4_1", | |
2315 | "mmc0_data8_1", | |
2316 | "mmc0_ctrl_1", | |
2317 | }; | |
2318 | ||
2319 | static const char * const sdhi0_groups[] = { | |
2320 | "sdhi0_data1", | |
2321 | "sdhi0_data4", | |
2322 | "sdhi0_ctrl", | |
2323 | "sdhi0_cd", | |
2324 | "sdhi0_wp", | |
2325 | }; | |
2326 | ||
2327 | static const char * const sdhi1_groups[] = { | |
2328 | "sdhi1_data1", | |
2329 | "sdhi1_data4", | |
2330 | "sdhi1_ctrl", | |
2331 | "sdhi1_cd", | |
2332 | "sdhi1_wp", | |
2333 | }; | |
2334 | ||
2335 | static const char * const sdhi2_groups[] = { | |
2336 | "sdhi2_data1", | |
2337 | "sdhi2_data4", | |
2338 | "sdhi2_ctrl", | |
2339 | "sdhi2_cd_0", | |
2340 | "sdhi2_wp_0", | |
2341 | "sdhi2_cd_1", | |
2342 | "sdhi2_wp_1", | |
2343 | }; | |
2344 | ||
06c7dd86 LP |
2345 | static const struct sh_pfc_function pinmux_functions[] = { |
2346 | SH_PFC_FUNCTION(lcd0), | |
2347 | SH_PFC_FUNCTION(lcd1), | |
8b2810b9 GL |
2348 | SH_PFC_FUNCTION(mmc0), |
2349 | SH_PFC_FUNCTION(sdhi0), | |
2350 | SH_PFC_FUNCTION(sdhi1), | |
2351 | SH_PFC_FUNCTION(sdhi2), | |
06c7dd86 LP |
2352 | }; |
2353 | ||
a373ed0a | 2354 | #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) |
d5b1521a | 2355 | |
cd3c1bee | 2356 | static const struct pinmux_func pinmux_func_gpios[] = { |
d5b1521a LP |
2357 | /* IRQ */ |
2358 | GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), | |
2359 | GPIO_FN(IRQ1), | |
2360 | GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), | |
2361 | GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), | |
2362 | GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), | |
2363 | GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), | |
2364 | GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), | |
2365 | GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), | |
2366 | GPIO_FN(IRQ8), | |
2367 | GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), | |
2368 | GPIO_FN(IRQ10), | |
2369 | GPIO_FN(IRQ11), | |
2370 | GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), | |
2371 | GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), | |
2372 | GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), | |
2373 | GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), | |
2374 | GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), | |
2375 | GPIO_FN(IRQ17), | |
2376 | GPIO_FN(IRQ18), | |
2377 | GPIO_FN(IRQ19), | |
2378 | GPIO_FN(IRQ20), | |
2379 | GPIO_FN(IRQ21), | |
2380 | GPIO_FN(IRQ22), | |
2381 | GPIO_FN(IRQ23), | |
2382 | GPIO_FN(IRQ24), | |
2383 | GPIO_FN(IRQ25), | |
2384 | GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), | |
2385 | GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), | |
2386 | GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), | |
2387 | GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), | |
2388 | GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), | |
2389 | GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), | |
2390 | ||
2391 | /* Function */ | |
2392 | ||
2393 | /* DBGT */ | |
2394 | GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), | |
2395 | GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), | |
2396 | GPIO_FN(DBGMD21), | |
2397 | ||
2398 | /* FSI-A */ | |
2399 | GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ | |
2400 | GPIO_FN(FSIAISLD_PORT5), | |
2401 | GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ | |
2402 | GPIO_FN(FSIASPDIF_PORT18), | |
2403 | GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), | |
2404 | GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), | |
2405 | GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), | |
2406 | ||
2407 | /* FSI-B */ | |
2408 | GPIO_FN(FSIBCK), | |
2409 | ||
2410 | /* FMSI */ | |
2411 | GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ | |
2412 | GPIO_FN(FMSISLD_PORT6), | |
2413 | GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), | |
2414 | GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), | |
2415 | GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), | |
2416 | GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), | |
2417 | ||
2418 | /* SCIFA0 */ | |
2419 | GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), | |
2420 | GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), | |
2421 | ||
2422 | /* SCIFA1 */ | |
2423 | GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), | |
2424 | GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), | |
2425 | ||
2426 | /* SCIFA2 */ | |
2427 | GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ | |
2428 | GPIO_FN(SCIFA2_SCK_PORT199), | |
2429 | GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), | |
2430 | GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), | |
2431 | ||
2432 | /* SCIFA3 */ | |
2433 | GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ | |
2434 | GPIO_FN(SCIFA3_SCK_PORT116), | |
2435 | GPIO_FN(SCIFA3_CTS_PORT117), | |
2436 | GPIO_FN(SCIFA3_RXD_PORT174), | |
2437 | GPIO_FN(SCIFA3_TXD_PORT175), | |
2438 | ||
2439 | GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ | |
2440 | GPIO_FN(SCIFA3_SCK_PORT158), | |
2441 | GPIO_FN(SCIFA3_CTS_PORT162), | |
2442 | GPIO_FN(SCIFA3_RXD_PORT159), | |
2443 | GPIO_FN(SCIFA3_TXD_PORT160), | |
2444 | ||
2445 | /* SCIFA4 */ | |
2446 | GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ | |
2447 | GPIO_FN(SCIFA4_TXD_PORT13), | |
2448 | ||
2449 | GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ | |
2450 | GPIO_FN(SCIFA4_TXD_PORT203), | |
2451 | ||
2452 | GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ | |
2453 | GPIO_FN(SCIFA4_TXD_PORT93), | |
2454 | ||
2455 | GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ | |
2456 | GPIO_FN(SCIFA4_SCK_PORT205), | |
2457 | ||
2458 | /* SCIFA5 */ | |
2459 | GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ | |
2460 | GPIO_FN(SCIFA5_RXD_PORT10), | |
2461 | ||
2462 | GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ | |
2463 | GPIO_FN(SCIFA5_TXD_PORT208), | |
2464 | ||
2465 | GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ | |
2466 | GPIO_FN(SCIFA5_RXD_PORT92), | |
2467 | ||
2468 | GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ | |
2469 | GPIO_FN(SCIFA5_SCK_PORT206), | |
2470 | ||
2471 | /* SCIFA6 */ | |
2472 | GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), | |
2473 | ||
2474 | /* SCIFA7 */ | |
2475 | GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), | |
2476 | ||
2477 | /* SCIFAB */ | |
2478 | GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ | |
2479 | GPIO_FN(SCIFB_RXD_PORT191), | |
2480 | GPIO_FN(SCIFB_TXD_PORT192), | |
2481 | GPIO_FN(SCIFB_RTS_PORT186), | |
2482 | GPIO_FN(SCIFB_CTS_PORT187), | |
2483 | ||
2484 | GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ | |
2485 | GPIO_FN(SCIFB_RXD_PORT3), | |
2486 | GPIO_FN(SCIFB_TXD_PORT4), | |
2487 | GPIO_FN(SCIFB_RTS_PORT172), | |
2488 | GPIO_FN(SCIFB_CTS_PORT173), | |
2489 | ||
d5b1521a LP |
2490 | /* RSPI */ |
2491 | GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), | |
2492 | GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), | |
2493 | GPIO_FN(RSPI_MISO_A), | |
2494 | ||
2495 | /* VIO CKO */ | |
2496 | GPIO_FN(VIO_CKO1), | |
2497 | GPIO_FN(VIO_CKO2), | |
2498 | GPIO_FN(VIO_CKO_1), | |
2499 | GPIO_FN(VIO_CKO), | |
2500 | ||
2501 | /* VIO0 */ | |
2502 | GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), | |
2503 | GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), | |
2504 | GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), | |
2505 | GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), | |
2506 | GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), | |
2507 | GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), | |
2508 | ||
2509 | GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ | |
2510 | GPIO_FN(VIO0_D14_PORT25), | |
2511 | GPIO_FN(VIO0_D15_PORT24), | |
2512 | ||
2513 | GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ | |
2514 | GPIO_FN(VIO0_D14_PORT95), | |
2515 | GPIO_FN(VIO0_D15_PORT96), | |
2516 | ||
2517 | /* VIO1 */ | |
2518 | GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), | |
2519 | GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), | |
2520 | GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), | |
2521 | GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), | |
2522 | ||
2523 | /* TPU0 */ | |
2524 | GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), | |
2525 | GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ | |
2526 | GPIO_FN(TPU0TO2_PORT202), | |
2527 | ||
2528 | /* SSP1 0 */ | |
2529 | GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), | |
2530 | GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), | |
2531 | GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), | |
2532 | GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), | |
2533 | ||
2534 | /* SSP1 1 */ | |
2535 | GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), | |
2536 | GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), | |
2537 | GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), | |
2538 | ||
2539 | GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ | |
2540 | GPIO_FN(STP1_IPEN_PORT187), | |
2541 | ||
2542 | GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ | |
2543 | GPIO_FN(STP1_IPEN_PORT193), | |
2544 | ||
2545 | /* SIM */ | |
2546 | GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), | |
2547 | GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ | |
2548 | GPIO_FN(SIM_D_PORT199), | |
2549 | ||
d5b1521a LP |
2550 | /* MSIOF2 */ |
2551 | GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), | |
2552 | GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), | |
2553 | GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), | |
2554 | GPIO_FN(MSIOF2_RSCK), | |
2555 | ||
2556 | /* KEYSC */ | |
2557 | GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), | |
2558 | GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), | |
2559 | GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), | |
2560 | GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), | |
2561 | GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), | |
2562 | ||
2563 | GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ | |
2564 | GPIO_FN(KEYIN1_PORT44), | |
2565 | GPIO_FN(KEYIN2_PORT45), | |
2566 | GPIO_FN(KEYIN3_PORT46), | |
2567 | ||
2568 | GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ | |
2569 | GPIO_FN(KEYIN1_PORT57), | |
2570 | GPIO_FN(KEYIN2_PORT56), | |
2571 | GPIO_FN(KEYIN3_PORT55), | |
2572 | ||
2573 | /* VOU */ | |
2574 | GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), | |
2575 | GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), | |
2576 | GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), | |
2577 | GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), | |
2578 | GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), | |
2579 | GPIO_FN(DV_D15), GPIO_FN(DV_CLK), | |
2580 | GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), | |
2581 | ||
2582 | /* MEMC */ | |
2583 | GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), | |
2584 | GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), | |
2585 | GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), | |
2586 | GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), | |
2587 | GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), | |
2588 | GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), | |
2589 | GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), | |
2590 | GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), | |
2591 | GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), | |
2592 | GPIO_FN(MEMC_A0), | |
2593 | ||
d5b1521a LP |
2594 | /* MSIOF0 */ |
2595 | GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), | |
2596 | GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), | |
2597 | GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), | |
2598 | GPIO_FN(MSIOF0_TSYNC), | |
2599 | ||
2600 | /* MSIOF1 */ | |
2601 | GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), | |
2602 | GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), | |
2603 | ||
2604 | GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), | |
2605 | GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), | |
2606 | GPIO_FN(MSIOF1_TSYNC_PORT120), | |
2607 | GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ | |
2608 | ||
2609 | GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), | |
2610 | GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), | |
2611 | GPIO_FN(MSIOF1_RXD_PORT75), | |
2612 | GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ | |
2613 | ||
2614 | /* GPIO */ | |
2615 | GPIO_FN(GPO0), GPIO_FN(GPI0), | |
2616 | GPIO_FN(GPO1), GPIO_FN(GPI1), | |
2617 | ||
2618 | /* USB0 */ | |
2619 | GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), | |
2620 | ||
2621 | /* USB1 */ | |
2622 | GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), | |
2623 | ||
2624 | /* BBIF1 */ | |
2625 | GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), | |
2626 | GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), | |
2627 | GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), | |
2628 | ||
2629 | /* BBIF2 */ | |
2630 | GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ | |
2631 | GPIO_FN(BBIF2_RXD2_PORT60), | |
2632 | GPIO_FN(BBIF2_TSYNC2_PORT6), | |
2633 | GPIO_FN(BBIF2_TSCK2_PORT59), | |
2634 | ||
2635 | GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ | |
2636 | GPIO_FN(BBIF2_TXD2_PORT183), | |
2637 | GPIO_FN(BBIF2_TSCK2_PORT89), | |
2638 | GPIO_FN(BBIF2_TSYNC2_PORT184), | |
2639 | ||
2640 | /* BSC / FLCTL / PCMCIA */ | |
2641 | GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), | |
2642 | GPIO_FN(CS5B), GPIO_FN(CS6A), | |
2643 | GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ | |
2644 | GPIO_FN(CS5A_PORT19), | |
2645 | GPIO_FN(IOIS16), /* ? */ | |
2646 | ||
2647 | GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), | |
2648 | GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ | |
2649 | GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), | |
2650 | GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), | |
2651 | GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), | |
2652 | GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), | |
2653 | GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), | |
2654 | GPIO_FN(A26), | |
2655 | ||
2656 | GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ | |
2657 | GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ | |
2658 | GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ | |
2659 | GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ | |
2660 | GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ | |
2661 | GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ | |
2662 | GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ | |
2663 | GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ | |
2664 | GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), | |
2665 | GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), | |
2666 | GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), | |
2667 | GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), | |
2668 | ||
2669 | GPIO_FN(WE0_FWE), /* share with FLCTL */ | |
2670 | GPIO_FN(WE1), | |
2671 | GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ | |
2672 | GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ | |
2673 | GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), | |
2674 | GPIO_FN(RD_FSC), /* share with FLCTL */ | |
2675 | GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ | |
2676 | GPIO_FN(WAIT_PORT90), | |
2677 | ||
2678 | GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ | |
2679 | ||
2680 | /* IRDA */ | |
2681 | GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), | |
2682 | ||
2683 | /* ATAPI */ | |
2684 | GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), | |
2685 | GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), | |
2686 | GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), | |
2687 | GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), | |
2688 | GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), | |
2689 | GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), | |
2690 | GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), | |
2691 | GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), | |
2692 | GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), | |
2693 | GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), | |
2694 | ||
2695 | /* RMII */ | |
2696 | GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), | |
2697 | GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), | |
2698 | GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), | |
2699 | GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ | |
2700 | ||
2701 | /* GEther */ | |
2702 | GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), | |
2703 | GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), | |
2704 | GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ | |
2705 | GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ | |
2706 | GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), | |
2707 | GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), | |
2708 | GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), | |
2709 | GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ | |
2710 | GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ | |
2711 | GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), | |
2712 | GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), | |
2713 | GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), | |
2714 | ||
2715 | /* DMA0 */ | |
2716 | GPIO_FN(DREQ0), GPIO_FN(DACK0), | |
2717 | ||
2718 | /* DMA1 */ | |
2719 | GPIO_FN(DREQ1), GPIO_FN(DACK1), | |
2720 | ||
2721 | /* SYSC */ | |
2722 | GPIO_FN(RESETOUTS), | |
2723 | ||
2724 | /* IRREM */ | |
2725 | GPIO_FN(IROUT), | |
2726 | ||
2727 | /* LCDC */ | |
2728 | GPIO_FN(LCDC0_SELECT), | |
2729 | GPIO_FN(LCDC1_SELECT), | |
2730 | ||
2731 | /* SDENC */ | |
2732 | GPIO_FN(SDENC_CPG), | |
2733 | GPIO_FN(SDENC_DV_CLKI), | |
2734 | ||
2735 | /* HDMI */ | |
2736 | GPIO_FN(HDMI_HPD), | |
2737 | GPIO_FN(HDMI_CEC), | |
2738 | ||
2739 | /* SYSC */ | |
2740 | GPIO_FN(RESETP_PULLUP), | |
2741 | GPIO_FN(RESETP_PLAIN), | |
2742 | ||
2743 | /* DEBUG */ | |
2744 | GPIO_FN(EDEBGREQ_PULLDOWN), | |
2745 | GPIO_FN(EDEBGREQ_PULLUP), | |
2746 | ||
2747 | GPIO_FN(TRACEAUD_FROM_VIO), | |
2748 | GPIO_FN(TRACEAUD_FROM_LCDC0), | |
2749 | GPIO_FN(TRACEAUD_FROM_MEMC), | |
2750 | }; | |
2751 | ||
cd3c1bee | 2752 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
d5b1521a LP |
2753 | PORTCR(0, 0xe6050000), /* PORT0CR */ |
2754 | PORTCR(1, 0xe6050001), /* PORT1CR */ | |
2755 | PORTCR(2, 0xe6050002), /* PORT2CR */ | |
2756 | PORTCR(3, 0xe6050003), /* PORT3CR */ | |
2757 | PORTCR(4, 0xe6050004), /* PORT4CR */ | |
2758 | PORTCR(5, 0xe6050005), /* PORT5CR */ | |
2759 | PORTCR(6, 0xe6050006), /* PORT6CR */ | |
2760 | PORTCR(7, 0xe6050007), /* PORT7CR */ | |
2761 | PORTCR(8, 0xe6050008), /* PORT8CR */ | |
2762 | PORTCR(9, 0xe6050009), /* PORT9CR */ | |
2763 | PORTCR(10, 0xe605000a), /* PORT10CR */ | |
2764 | PORTCR(11, 0xe605000b), /* PORT11CR */ | |
2765 | PORTCR(12, 0xe605000c), /* PORT12CR */ | |
2766 | PORTCR(13, 0xe605000d), /* PORT13CR */ | |
2767 | PORTCR(14, 0xe605000e), /* PORT14CR */ | |
2768 | PORTCR(15, 0xe605000f), /* PORT15CR */ | |
2769 | PORTCR(16, 0xe6050010), /* PORT16CR */ | |
2770 | PORTCR(17, 0xe6050011), /* PORT17CR */ | |
2771 | PORTCR(18, 0xe6050012), /* PORT18CR */ | |
2772 | PORTCR(19, 0xe6050013), /* PORT19CR */ | |
2773 | PORTCR(20, 0xe6050014), /* PORT20CR */ | |
2774 | PORTCR(21, 0xe6050015), /* PORT21CR */ | |
2775 | PORTCR(22, 0xe6050016), /* PORT22CR */ | |
2776 | PORTCR(23, 0xe6050017), /* PORT23CR */ | |
2777 | PORTCR(24, 0xe6050018), /* PORT24CR */ | |
2778 | PORTCR(25, 0xe6050019), /* PORT25CR */ | |
2779 | PORTCR(26, 0xe605001a), /* PORT26CR */ | |
2780 | PORTCR(27, 0xe605001b), /* PORT27CR */ | |
2781 | PORTCR(28, 0xe605001c), /* PORT28CR */ | |
2782 | PORTCR(29, 0xe605001d), /* PORT29CR */ | |
2783 | PORTCR(30, 0xe605001e), /* PORT30CR */ | |
2784 | PORTCR(31, 0xe605001f), /* PORT31CR */ | |
2785 | PORTCR(32, 0xe6050020), /* PORT32CR */ | |
2786 | PORTCR(33, 0xe6050021), /* PORT33CR */ | |
2787 | PORTCR(34, 0xe6050022), /* PORT34CR */ | |
2788 | PORTCR(35, 0xe6050023), /* PORT35CR */ | |
2789 | PORTCR(36, 0xe6050024), /* PORT36CR */ | |
2790 | PORTCR(37, 0xe6050025), /* PORT37CR */ | |
2791 | PORTCR(38, 0xe6050026), /* PORT38CR */ | |
2792 | PORTCR(39, 0xe6050027), /* PORT39CR */ | |
2793 | PORTCR(40, 0xe6050028), /* PORT40CR */ | |
2794 | PORTCR(41, 0xe6050029), /* PORT41CR */ | |
2795 | PORTCR(42, 0xe605002a), /* PORT42CR */ | |
2796 | PORTCR(43, 0xe605002b), /* PORT43CR */ | |
2797 | PORTCR(44, 0xe605002c), /* PORT44CR */ | |
2798 | PORTCR(45, 0xe605002d), /* PORT45CR */ | |
2799 | PORTCR(46, 0xe605002e), /* PORT46CR */ | |
2800 | PORTCR(47, 0xe605002f), /* PORT47CR */ | |
2801 | PORTCR(48, 0xe6050030), /* PORT48CR */ | |
2802 | PORTCR(49, 0xe6050031), /* PORT49CR */ | |
2803 | PORTCR(50, 0xe6050032), /* PORT50CR */ | |
2804 | PORTCR(51, 0xe6050033), /* PORT51CR */ | |
2805 | PORTCR(52, 0xe6050034), /* PORT52CR */ | |
2806 | PORTCR(53, 0xe6050035), /* PORT53CR */ | |
2807 | PORTCR(54, 0xe6050036), /* PORT54CR */ | |
2808 | PORTCR(55, 0xe6050037), /* PORT55CR */ | |
2809 | PORTCR(56, 0xe6050038), /* PORT56CR */ | |
2810 | PORTCR(57, 0xe6050039), /* PORT57CR */ | |
2811 | PORTCR(58, 0xe605003a), /* PORT58CR */ | |
2812 | PORTCR(59, 0xe605003b), /* PORT59CR */ | |
2813 | PORTCR(60, 0xe605003c), /* PORT60CR */ | |
2814 | PORTCR(61, 0xe605003d), /* PORT61CR */ | |
2815 | PORTCR(62, 0xe605003e), /* PORT62CR */ | |
2816 | PORTCR(63, 0xe605003f), /* PORT63CR */ | |
2817 | PORTCR(64, 0xe6050040), /* PORT64CR */ | |
2818 | PORTCR(65, 0xe6050041), /* PORT65CR */ | |
2819 | PORTCR(66, 0xe6050042), /* PORT66CR */ | |
2820 | PORTCR(67, 0xe6050043), /* PORT67CR */ | |
2821 | PORTCR(68, 0xe6050044), /* PORT68CR */ | |
2822 | PORTCR(69, 0xe6050045), /* PORT69CR */ | |
2823 | PORTCR(70, 0xe6050046), /* PORT70CR */ | |
2824 | PORTCR(71, 0xe6050047), /* PORT71CR */ | |
2825 | PORTCR(72, 0xe6050048), /* PORT72CR */ | |
2826 | PORTCR(73, 0xe6050049), /* PORT73CR */ | |
2827 | PORTCR(74, 0xe605004a), /* PORT74CR */ | |
2828 | PORTCR(75, 0xe605004b), /* PORT75CR */ | |
2829 | PORTCR(76, 0xe605004c), /* PORT76CR */ | |
2830 | PORTCR(77, 0xe605004d), /* PORT77CR */ | |
2831 | PORTCR(78, 0xe605004e), /* PORT78CR */ | |
2832 | PORTCR(79, 0xe605004f), /* PORT79CR */ | |
2833 | PORTCR(80, 0xe6050050), /* PORT80CR */ | |
2834 | PORTCR(81, 0xe6050051), /* PORT81CR */ | |
2835 | PORTCR(82, 0xe6050052), /* PORT82CR */ | |
2836 | PORTCR(83, 0xe6050053), /* PORT83CR */ | |
2837 | ||
2838 | PORTCR(84, 0xe6051054), /* PORT84CR */ | |
2839 | PORTCR(85, 0xe6051055), /* PORT85CR */ | |
2840 | PORTCR(86, 0xe6051056), /* PORT86CR */ | |
2841 | PORTCR(87, 0xe6051057), /* PORT87CR */ | |
2842 | PORTCR(88, 0xe6051058), /* PORT88CR */ | |
2843 | PORTCR(89, 0xe6051059), /* PORT89CR */ | |
2844 | PORTCR(90, 0xe605105a), /* PORT90CR */ | |
2845 | PORTCR(91, 0xe605105b), /* PORT91CR */ | |
2846 | PORTCR(92, 0xe605105c), /* PORT92CR */ | |
2847 | PORTCR(93, 0xe605105d), /* PORT93CR */ | |
2848 | PORTCR(94, 0xe605105e), /* PORT94CR */ | |
2849 | PORTCR(95, 0xe605105f), /* PORT95CR */ | |
2850 | PORTCR(96, 0xe6051060), /* PORT96CR */ | |
2851 | PORTCR(97, 0xe6051061), /* PORT97CR */ | |
2852 | PORTCR(98, 0xe6051062), /* PORT98CR */ | |
2853 | PORTCR(99, 0xe6051063), /* PORT99CR */ | |
2854 | PORTCR(100, 0xe6051064), /* PORT100CR */ | |
2855 | PORTCR(101, 0xe6051065), /* PORT101CR */ | |
2856 | PORTCR(102, 0xe6051066), /* PORT102CR */ | |
2857 | PORTCR(103, 0xe6051067), /* PORT103CR */ | |
2858 | PORTCR(104, 0xe6051068), /* PORT104CR */ | |
2859 | PORTCR(105, 0xe6051069), /* PORT105CR */ | |
2860 | PORTCR(106, 0xe605106a), /* PORT106CR */ | |
2861 | PORTCR(107, 0xe605106b), /* PORT107CR */ | |
2862 | PORTCR(108, 0xe605106c), /* PORT108CR */ | |
2863 | PORTCR(109, 0xe605106d), /* PORT109CR */ | |
2864 | PORTCR(110, 0xe605106e), /* PORT110CR */ | |
2865 | PORTCR(111, 0xe605106f), /* PORT111CR */ | |
2866 | PORTCR(112, 0xe6051070), /* PORT112CR */ | |
2867 | PORTCR(113, 0xe6051071), /* PORT113CR */ | |
2868 | PORTCR(114, 0xe6051072), /* PORT114CR */ | |
2869 | ||
2870 | PORTCR(115, 0xe6052073), /* PORT115CR */ | |
2871 | PORTCR(116, 0xe6052074), /* PORT116CR */ | |
2872 | PORTCR(117, 0xe6052075), /* PORT117CR */ | |
2873 | PORTCR(118, 0xe6052076), /* PORT118CR */ | |
2874 | PORTCR(119, 0xe6052077), /* PORT119CR */ | |
2875 | PORTCR(120, 0xe6052078), /* PORT120CR */ | |
2876 | PORTCR(121, 0xe6052079), /* PORT121CR */ | |
2877 | PORTCR(122, 0xe605207a), /* PORT122CR */ | |
2878 | PORTCR(123, 0xe605207b), /* PORT123CR */ | |
2879 | PORTCR(124, 0xe605207c), /* PORT124CR */ | |
2880 | PORTCR(125, 0xe605207d), /* PORT125CR */ | |
2881 | PORTCR(126, 0xe605207e), /* PORT126CR */ | |
2882 | PORTCR(127, 0xe605207f), /* PORT127CR */ | |
2883 | PORTCR(128, 0xe6052080), /* PORT128CR */ | |
2884 | PORTCR(129, 0xe6052081), /* PORT129CR */ | |
2885 | PORTCR(130, 0xe6052082), /* PORT130CR */ | |
2886 | PORTCR(131, 0xe6052083), /* PORT131CR */ | |
2887 | PORTCR(132, 0xe6052084), /* PORT132CR */ | |
2888 | PORTCR(133, 0xe6052085), /* PORT133CR */ | |
2889 | PORTCR(134, 0xe6052086), /* PORT134CR */ | |
2890 | PORTCR(135, 0xe6052087), /* PORT135CR */ | |
2891 | PORTCR(136, 0xe6052088), /* PORT136CR */ | |
2892 | PORTCR(137, 0xe6052089), /* PORT137CR */ | |
2893 | PORTCR(138, 0xe605208a), /* PORT138CR */ | |
2894 | PORTCR(139, 0xe605208b), /* PORT139CR */ | |
2895 | PORTCR(140, 0xe605208c), /* PORT140CR */ | |
2896 | PORTCR(141, 0xe605208d), /* PORT141CR */ | |
2897 | PORTCR(142, 0xe605208e), /* PORT142CR */ | |
2898 | PORTCR(143, 0xe605208f), /* PORT143CR */ | |
2899 | PORTCR(144, 0xe6052090), /* PORT144CR */ | |
2900 | PORTCR(145, 0xe6052091), /* PORT145CR */ | |
2901 | PORTCR(146, 0xe6052092), /* PORT146CR */ | |
2902 | PORTCR(147, 0xe6052093), /* PORT147CR */ | |
2903 | PORTCR(148, 0xe6052094), /* PORT148CR */ | |
2904 | PORTCR(149, 0xe6052095), /* PORT149CR */ | |
2905 | PORTCR(150, 0xe6052096), /* PORT150CR */ | |
2906 | PORTCR(151, 0xe6052097), /* PORT151CR */ | |
2907 | PORTCR(152, 0xe6052098), /* PORT152CR */ | |
2908 | PORTCR(153, 0xe6052099), /* PORT153CR */ | |
2909 | PORTCR(154, 0xe605209a), /* PORT154CR */ | |
2910 | PORTCR(155, 0xe605209b), /* PORT155CR */ | |
2911 | PORTCR(156, 0xe605209c), /* PORT156CR */ | |
2912 | PORTCR(157, 0xe605209d), /* PORT157CR */ | |
2913 | PORTCR(158, 0xe605209e), /* PORT158CR */ | |
2914 | PORTCR(159, 0xe605209f), /* PORT159CR */ | |
2915 | PORTCR(160, 0xe60520a0), /* PORT160CR */ | |
2916 | PORTCR(161, 0xe60520a1), /* PORT161CR */ | |
2917 | PORTCR(162, 0xe60520a2), /* PORT162CR */ | |
2918 | PORTCR(163, 0xe60520a3), /* PORT163CR */ | |
2919 | PORTCR(164, 0xe60520a4), /* PORT164CR */ | |
2920 | PORTCR(165, 0xe60520a5), /* PORT165CR */ | |
2921 | PORTCR(166, 0xe60520a6), /* PORT166CR */ | |
2922 | PORTCR(167, 0xe60520a7), /* PORT167CR */ | |
2923 | PORTCR(168, 0xe60520a8), /* PORT168CR */ | |
2924 | PORTCR(169, 0xe60520a9), /* PORT169CR */ | |
2925 | PORTCR(170, 0xe60520aa), /* PORT170CR */ | |
2926 | PORTCR(171, 0xe60520ab), /* PORT171CR */ | |
2927 | PORTCR(172, 0xe60520ac), /* PORT172CR */ | |
2928 | PORTCR(173, 0xe60520ad), /* PORT173CR */ | |
2929 | PORTCR(174, 0xe60520ae), /* PORT174CR */ | |
2930 | PORTCR(175, 0xe60520af), /* PORT175CR */ | |
2931 | PORTCR(176, 0xe60520b0), /* PORT176CR */ | |
2932 | PORTCR(177, 0xe60520b1), /* PORT177CR */ | |
2933 | PORTCR(178, 0xe60520b2), /* PORT178CR */ | |
2934 | PORTCR(179, 0xe60520b3), /* PORT179CR */ | |
2935 | PORTCR(180, 0xe60520b4), /* PORT180CR */ | |
2936 | PORTCR(181, 0xe60520b5), /* PORT181CR */ | |
2937 | PORTCR(182, 0xe60520b6), /* PORT182CR */ | |
2938 | PORTCR(183, 0xe60520b7), /* PORT183CR */ | |
2939 | PORTCR(184, 0xe60520b8), /* PORT184CR */ | |
2940 | PORTCR(185, 0xe60520b9), /* PORT185CR */ | |
2941 | PORTCR(186, 0xe60520ba), /* PORT186CR */ | |
2942 | PORTCR(187, 0xe60520bb), /* PORT187CR */ | |
2943 | PORTCR(188, 0xe60520bc), /* PORT188CR */ | |
2944 | PORTCR(189, 0xe60520bd), /* PORT189CR */ | |
2945 | PORTCR(190, 0xe60520be), /* PORT190CR */ | |
2946 | PORTCR(191, 0xe60520bf), /* PORT191CR */ | |
2947 | PORTCR(192, 0xe60520c0), /* PORT192CR */ | |
2948 | PORTCR(193, 0xe60520c1), /* PORT193CR */ | |
2949 | PORTCR(194, 0xe60520c2), /* PORT194CR */ | |
2950 | PORTCR(195, 0xe60520c3), /* PORT195CR */ | |
2951 | PORTCR(196, 0xe60520c4), /* PORT196CR */ | |
2952 | PORTCR(197, 0xe60520c5), /* PORT197CR */ | |
2953 | PORTCR(198, 0xe60520c6), /* PORT198CR */ | |
2954 | PORTCR(199, 0xe60520c7), /* PORT199CR */ | |
2955 | PORTCR(200, 0xe60520c8), /* PORT200CR */ | |
2956 | PORTCR(201, 0xe60520c9), /* PORT201CR */ | |
2957 | PORTCR(202, 0xe60520ca), /* PORT202CR */ | |
2958 | PORTCR(203, 0xe60520cb), /* PORT203CR */ | |
2959 | PORTCR(204, 0xe60520cc), /* PORT204CR */ | |
2960 | PORTCR(205, 0xe60520cd), /* PORT205CR */ | |
2961 | PORTCR(206, 0xe60520ce), /* PORT206CR */ | |
2962 | PORTCR(207, 0xe60520cf), /* PORT207CR */ | |
2963 | PORTCR(208, 0xe60520d0), /* PORT208CR */ | |
2964 | PORTCR(209, 0xe60520d1), /* PORT209CR */ | |
2965 | ||
2966 | PORTCR(210, 0xe60530d2), /* PORT210CR */ | |
2967 | PORTCR(211, 0xe60530d3), /* PORT211CR */ | |
2968 | ||
2969 | { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { | |
2970 | MSEL1CR_31_0, MSEL1CR_31_1, | |
2971 | MSEL1CR_30_0, MSEL1CR_30_1, | |
2972 | MSEL1CR_29_0, MSEL1CR_29_1, | |
2973 | MSEL1CR_28_0, MSEL1CR_28_1, | |
2974 | MSEL1CR_27_0, MSEL1CR_27_1, | |
2975 | MSEL1CR_26_0, MSEL1CR_26_1, | |
2976 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
2977 | 0, 0, 0, 0, 0, 0, 0, 0, | |
2978 | MSEL1CR_16_0, MSEL1CR_16_1, | |
2979 | MSEL1CR_15_0, MSEL1CR_15_1, | |
2980 | MSEL1CR_14_0, MSEL1CR_14_1, | |
2981 | MSEL1CR_13_0, MSEL1CR_13_1, | |
2982 | MSEL1CR_12_0, MSEL1CR_12_1, | |
2983 | 0, 0, 0, 0, | |
2984 | MSEL1CR_9_0, MSEL1CR_9_1, | |
2985 | 0, 0, | |
2986 | MSEL1CR_7_0, MSEL1CR_7_1, | |
2987 | MSEL1CR_6_0, MSEL1CR_6_1, | |
2988 | MSEL1CR_5_0, MSEL1CR_5_1, | |
2989 | MSEL1CR_4_0, MSEL1CR_4_1, | |
2990 | MSEL1CR_3_0, MSEL1CR_3_1, | |
2991 | MSEL1CR_2_0, MSEL1CR_2_1, | |
2992 | 0, 0, | |
2993 | MSEL1CR_0_0, MSEL1CR_0_1, | |
2994 | } | |
2995 | }, | |
2996 | { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { | |
2997 | 0, 0, 0, 0, 0, 0, 0, 0, | |
2998 | 0, 0, 0, 0, 0, 0, 0, 0, | |
2999 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3000 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3001 | MSEL3CR_15_0, MSEL3CR_15_1, | |
3002 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3003 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3004 | MSEL3CR_6_0, MSEL3CR_6_1, | |
3005 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3006 | 0, 0, 0, 0, | |
3007 | } | |
3008 | }, | |
3009 | { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { | |
3010 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3011 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3012 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3013 | MSEL4CR_19_0, MSEL4CR_19_1, | |
3014 | MSEL4CR_18_0, MSEL4CR_18_1, | |
3015 | 0, 0, 0, 0, | |
3016 | MSEL4CR_15_0, MSEL4CR_15_1, | |
3017 | 0, 0, 0, 0, 0, 0, 0, 0, | |
3018 | MSEL4CR_10_0, MSEL4CR_10_1, | |
3019 | 0, 0, 0, 0, 0, 0, | |
3020 | MSEL4CR_6_0, MSEL4CR_6_1, | |
3021 | 0, 0, | |
3022 | MSEL4CR_4_0, MSEL4CR_4_1, | |
3023 | 0, 0, 0, 0, | |
3024 | MSEL4CR_1_0, MSEL4CR_1_1, | |
3025 | 0, 0, | |
3026 | } | |
3027 | }, | |
3028 | { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { | |
3029 | MSEL5CR_31_0, MSEL5CR_31_1, | |
3030 | MSEL5CR_30_0, MSEL5CR_30_1, | |
3031 | MSEL5CR_29_0, MSEL5CR_29_1, | |
3032 | 0, 0, | |
3033 | MSEL5CR_27_0, MSEL5CR_27_1, | |
3034 | 0, 0, | |
3035 | MSEL5CR_25_0, MSEL5CR_25_1, | |
3036 | 0, 0, | |
3037 | MSEL5CR_23_0, MSEL5CR_23_1, | |
3038 | 0, 0, | |
3039 | MSEL5CR_21_0, MSEL5CR_21_1, | |
3040 | 0, 0, | |
3041 | MSEL5CR_19_0, MSEL5CR_19_1, | |
3042 | 0, 0, | |
3043 | MSEL5CR_17_0, MSEL5CR_17_1, | |
3044 | 0, 0, | |
3045 | MSEL5CR_15_0, MSEL5CR_15_1, | |
3046 | MSEL5CR_14_0, MSEL5CR_14_1, | |
3047 | MSEL5CR_13_0, MSEL5CR_13_1, | |
3048 | MSEL5CR_12_0, MSEL5CR_12_1, | |
3049 | MSEL5CR_11_0, MSEL5CR_11_1, | |
3050 | MSEL5CR_10_0, MSEL5CR_10_1, | |
3051 | 0, 0, | |
3052 | MSEL5CR_8_0, MSEL5CR_8_1, | |
3053 | MSEL5CR_7_0, MSEL5CR_7_1, | |
3054 | MSEL5CR_6_0, MSEL5CR_6_1, | |
3055 | MSEL5CR_5_0, MSEL5CR_5_1, | |
3056 | MSEL5CR_4_0, MSEL5CR_4_1, | |
3057 | MSEL5CR_3_0, MSEL5CR_3_1, | |
3058 | MSEL5CR_2_0, MSEL5CR_2_1, | |
3059 | 0, 0, | |
3060 | MSEL5CR_0_0, MSEL5CR_0_1, | |
3061 | } | |
3062 | }, | |
3063 | { }, | |
3064 | }; | |
3065 | ||
cd3c1bee | 3066 | static const struct pinmux_data_reg pinmux_data_regs[] = { |
d5b1521a LP |
3067 | { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { |
3068 | PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, | |
3069 | PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, | |
3070 | PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, | |
3071 | PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, | |
3072 | PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, | |
3073 | PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, | |
3074 | PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, | |
3075 | PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } | |
3076 | }, | |
3077 | { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) { | |
3078 | PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, | |
3079 | PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, | |
3080 | PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, | |
3081 | PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, | |
3082 | PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, | |
3083 | PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, | |
3084 | PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, | |
3085 | PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } | |
3086 | }, | |
3087 | { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) { | |
3088 | 0, 0, 0, 0, | |
3089 | 0, 0, 0, 0, | |
3090 | 0, 0, 0, 0, | |
3091 | PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, | |
3092 | PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, | |
3093 | PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, | |
3094 | PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, | |
3095 | PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } | |
3096 | }, | |
3097 | { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) { | |
3098 | PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, | |
3099 | PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, | |
3100 | PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, | |
3101 | 0, 0, 0, 0, | |
3102 | 0, 0, 0, 0, | |
3103 | 0, 0, 0, 0, | |
3104 | 0, 0, 0, 0, | |
3105 | 0, 0, 0, 0 } | |
3106 | }, | |
3107 | { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) { | |
3108 | 0, 0, 0, 0, | |
3109 | 0, 0, 0, 0, | |
3110 | 0, 0, 0, 0, | |
3111 | 0, PORT114_DATA, PORT113_DATA, PORT112_DATA, | |
3112 | PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, | |
3113 | PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, | |
3114 | PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, | |
3115 | PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } | |
3116 | }, | |
3117 | { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) { | |
3118 | PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, | |
3119 | PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, | |
3120 | PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, | |
3121 | PORT115_DATA, 0, 0, 0, | |
3122 | 0, 0, 0, 0, | |
3123 | 0, 0, 0, 0, | |
3124 | 0, 0, 0, 0, | |
3125 | 0, 0, 0, 0 } | |
3126 | }, | |
3127 | { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) { | |
3128 | PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, | |
3129 | PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, | |
3130 | PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, | |
3131 | PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, | |
3132 | PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, | |
3133 | PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, | |
3134 | PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, | |
3135 | PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } | |
3136 | }, | |
3137 | { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) { | |
3138 | PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, | |
3139 | PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, | |
3140 | PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, | |
3141 | PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, | |
3142 | PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, | |
3143 | PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, | |
3144 | PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, | |
3145 | PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } | |
3146 | }, | |
3147 | { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) { | |
3148 | 0, 0, 0, 0, | |
3149 | 0, 0, 0, 0, | |
3150 | 0, 0, 0, 0, | |
3151 | 0, 0, PORT209_DATA, PORT208_DATA, | |
3152 | PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, | |
3153 | PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, | |
3154 | PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, | |
3155 | PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } | |
3156 | }, | |
3157 | { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) { | |
3158 | 0, 0, 0, 0, | |
3159 | 0, 0, 0, 0, | |
3160 | 0, 0, 0, 0, | |
3161 | PORT211_DATA, PORT210_DATA, 0, 0, | |
3162 | 0, 0, 0, 0, | |
3163 | 0, 0, 0, 0, | |
3164 | 0, 0, 0, 0, | |
3165 | 0, 0, 0, 0 } | |
3166 | }, | |
3167 | { }, | |
3168 | }; | |
3169 | ||
cd3c1bee | 3170 | static const struct pinmux_irq pinmux_irqs[] = { |
0b7d7820 BH |
3171 | PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ |
3172 | PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ | |
3173 | PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ | |
3174 | PINMUX_IRQ(irq_pin(3), GPIO_PORT10, GPIO_PORT14), /* IRQ3A */ | |
3175 | PINMUX_IRQ(irq_pin(4), GPIO_PORT15, GPIO_PORT172),/* IRQ4A */ | |
3176 | PINMUX_IRQ(irq_pin(5), GPIO_PORT0, GPIO_PORT1), /* IRQ5A */ | |
3177 | PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */ | |
3178 | PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */ | |
3179 | PINMUX_IRQ(irq_pin(8), GPIO_PORT119), /* IRQ8A */ | |
3180 | PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */ | |
3181 | PINMUX_IRQ(irq_pin(10), GPIO_PORT19), /* IRQ10A */ | |
3182 | PINMUX_IRQ(irq_pin(11), GPIO_PORT104), /* IRQ11A */ | |
3183 | PINMUX_IRQ(irq_pin(12), GPIO_PORT42, GPIO_PORT97), /* IRQ12A */ | |
3184 | PINMUX_IRQ(irq_pin(13), GPIO_PORT64, GPIO_PORT98), /* IRQ13A */ | |
3185 | PINMUX_IRQ(irq_pin(14), GPIO_PORT63, GPIO_PORT99), /* IRQ14A */ | |
3186 | PINMUX_IRQ(irq_pin(15), GPIO_PORT62, GPIO_PORT100),/* IRQ15A */ | |
3187 | PINMUX_IRQ(irq_pin(16), GPIO_PORT68, GPIO_PORT211),/* IRQ16A */ | |
3188 | PINMUX_IRQ(irq_pin(17), GPIO_PORT69), /* IRQ17A */ | |
3189 | PINMUX_IRQ(irq_pin(18), GPIO_PORT70), /* IRQ18A */ | |
3190 | PINMUX_IRQ(irq_pin(19), GPIO_PORT71), /* IRQ19A */ | |
3191 | PINMUX_IRQ(irq_pin(20), GPIO_PORT67), /* IRQ20A */ | |
3192 | PINMUX_IRQ(irq_pin(21), GPIO_PORT202), /* IRQ21A */ | |
3193 | PINMUX_IRQ(irq_pin(22), GPIO_PORT95), /* IRQ22A */ | |
3194 | PINMUX_IRQ(irq_pin(23), GPIO_PORT96), /* IRQ23A */ | |
3195 | PINMUX_IRQ(irq_pin(24), GPIO_PORT180), /* IRQ24A */ | |
3196 | PINMUX_IRQ(irq_pin(25), GPIO_PORT38), /* IRQ25A */ | |
3197 | PINMUX_IRQ(irq_pin(26), GPIO_PORT58, GPIO_PORT81), /* IRQ26A */ | |
3198 | PINMUX_IRQ(irq_pin(27), GPIO_PORT57, GPIO_PORT168),/* IRQ27A */ | |
3199 | PINMUX_IRQ(irq_pin(28), GPIO_PORT56, GPIO_PORT169),/* IRQ28A */ | |
3200 | PINMUX_IRQ(irq_pin(29), GPIO_PORT50, GPIO_PORT170),/* IRQ29A */ | |
3201 | PINMUX_IRQ(irq_pin(30), GPIO_PORT49, GPIO_PORT171),/* IRQ30A */ | |
3202 | PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ | |
d5b1521a LP |
3203 | }; |
3204 | ||
cd3c1bee | 3205 | const struct sh_pfc_soc_info r8a7740_pinmux_info = { |
d5b1521a | 3206 | .name = "r8a7740_pfc", |
d5b1521a LP |
3207 | .input = { PINMUX_INPUT_BEGIN, |
3208 | PINMUX_INPUT_END }, | |
3209 | .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, | |
3210 | PINMUX_INPUT_PULLUP_END }, | |
3211 | .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, | |
3212 | PINMUX_INPUT_PULLDOWN_END }, | |
3213 | .output = { PINMUX_OUTPUT_BEGIN, | |
3214 | PINMUX_OUTPUT_END }, | |
d5b1521a LP |
3215 | .function = { PINMUX_FUNCTION_BEGIN, |
3216 | PINMUX_FUNCTION_END }, | |
3217 | ||
a373ed0a LP |
3218 | .pins = pinmux_pins, |
3219 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
06c7dd86 LP |
3220 | .groups = pinmux_groups, |
3221 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
3222 | .functions = pinmux_functions, | |
3223 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
3224 | ||
a373ed0a LP |
3225 | .func_gpios = pinmux_func_gpios, |
3226 | .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), | |
d7a7ca57 | 3227 | |
d5b1521a LP |
3228 | .cfg_regs = pinmux_config_regs, |
3229 | .data_regs = pinmux_data_regs, | |
3230 | ||
3231 | .gpio_data = pinmux_data, | |
3232 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | |
3233 | ||
3234 | .gpio_irq = pinmux_irqs, | |
3235 | .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), | |
3236 | }; |