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Commit | Line | Data |
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58c229e1 KM |
1 | /* |
2 | * R8A7790 processor support | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Electronics Corporation | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * Copyright (C) 2012 Renesas Solutions Corp. | |
7 | * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; version 2 of the | |
12 | * License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
22 | */ | |
1627769b | 23 | |
60d8fcef | 24 | #include <linux/io.h> |
58c229e1 | 25 | #include <linux/kernel.h> |
1627769b | 26 | |
58c229e1 KM |
27 | #include "core.h" |
28 | #include "sh_pfc.h" | |
29 | ||
60d8fcef WS |
30 | /* |
31 | * All pins assigned to GPIO bank 3 can be used for SD interfaces in | |
32 | * which case they support both 3.3V and 1.8V signalling. | |
33 | */ | |
ed3e2604 LP |
34 | #define CPU_ALL_PORT(fn, sfx) \ |
35 | PORT_GP_32(0, fn, sfx), \ | |
b5599df2 LP |
36 | PORT_GP_30(1, fn, sfx), \ |
37 | PORT_GP_30(2, fn, sfx), \ | |
60d8fcef | 38 | PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \ |
ed3e2604 LP |
39 | PORT_GP_32(4, fn, sfx), \ |
40 | PORT_GP_32(5, fn, sfx) | |
41 | ||
58c229e1 KM |
42 | enum { |
43 | PINMUX_RESERVED = 0, | |
44 | ||
45 | PINMUX_DATA_BEGIN, | |
46 | GP_ALL(DATA), | |
47 | PINMUX_DATA_END, | |
48 | ||
58c229e1 KM |
49 | PINMUX_FUNCTION_BEGIN, |
50 | GP_ALL(FN), | |
51 | ||
52 | /* GPSR0 */ | |
53 | FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12, | |
54 | FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27, | |
55 | FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12, | |
56 | FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26, | |
57 | FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9, | |
58 | FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22, | |
59 | FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8, | |
60 | FN_IP3_14_12, FN_IP3_17_15, | |
61 | ||
62 | /* GPSR1 */ | |
63 | FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26, | |
64 | FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9, | |
65 | FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21, | |
66 | FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6, | |
67 | FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18, | |
68 | FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0, | |
69 | FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11, | |
70 | ||
71 | /* GPSR2 */ | |
72 | FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, | |
73 | FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14, | |
74 | FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22, | |
75 | FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7, | |
76 | FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23, | |
77 | FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6, | |
78 | FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13, | |
79 | ||
80 | /* GPSR3 */ | |
81 | FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4, | |
82 | FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18, | |
83 | FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26, | |
84 | FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11, | |
85 | FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26, | |
86 | FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9, | |
87 | FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18, | |
88 | ||
89 | /* GPSR4 */ | |
90 | FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30, | |
91 | FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8, | |
92 | FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20, | |
93 | FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0, | |
94 | FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13, | |
95 | FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26, | |
96 | FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9, | |
97 | FN_IP14_15_12, FN_IP14_18_16, | |
98 | ||
99 | /* GPSR5 */ | |
100 | FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28, | |
101 | FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12, | |
102 | FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20, | |
103 | FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0, | |
104 | FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7, | |
105 | FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0, | |
106 | FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22, | |
107 | ||
108 | /* IPSR0 */ | |
109 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | |
110 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, | |
111 | FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, | |
112 | FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B, | |
113 | FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4, | |
114 | FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | |
115 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5, | |
116 | FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | |
117 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6, | |
c4721249 SK |
118 | FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
119 | FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, | |
05bcb07b | 120 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1, |
9f2edd41 | 121 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, |
58c229e1 KM |
122 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
123 | ||
124 | /* IPSR1 */ | |
9f2edd41 | 125 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, |
58c229e1 | 126 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10, |
9f2edd41 | 127 | FN_SCIFA1_TXD_C, FN_AVB_TXD2, |
58c229e1 | 128 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11, |
9f2edd41 | 129 | FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, |
58c229e1 KM |
130 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
131 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | |
132 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | |
133 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | |
134 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14, | |
135 | FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | |
136 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | |
137 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | |
138 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | |
139 | FN_A0, FN_PWM3, FN_A1, FN_PWM4, | |
140 | ||
141 | /* IPSR2 */ | |
142 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3, | |
143 | FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B, | |
144 | FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, | |
145 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7, | |
146 | FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | |
147 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | |
1ddb66cd | 148 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
58c229e1 | 149 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, |
1ddb66cd | 150 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
58c229e1 KM |
151 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, |
152 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, | |
153 | ||
154 | /* IPSR3 */ | |
155 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | |
156 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, | |
157 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | |
158 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | |
159 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | |
160 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | |
161 | FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B, | |
162 | FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B, | |
163 | FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N, | |
164 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18, | |
165 | FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B, | |
166 | FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK, | |
167 | FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | |
168 | ||
169 | /* IPSR4 */ | |
170 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, | |
171 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, | |
172 | FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7, | |
173 | FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3, | |
174 | FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | |
175 | FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6, | |
176 | FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N, | |
177 | FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | |
178 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | |
179 | FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B, | |
180 | FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B, | |
181 | FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK, | |
182 | FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B, | |
183 | FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | |
184 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, | |
185 | ||
186 | /* IPSR5 */ | |
187 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | |
188 | FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | |
c4721249 SK |
189 | FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
190 | FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX, | |
58c229e1 | 191 | FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2, |
c4721249 SK |
192 | FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
193 | FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B, | |
58c229e1 KM |
194 | FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N, |
195 | FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3, | |
196 | FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | |
197 | FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK, | |
198 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, | |
199 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | |
200 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, | |
201 | FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | |
202 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | |
203 | FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N, | |
204 | FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C, | |
205 | FN_SSI_WS78_B, | |
206 | ||
207 | /* IPSR6 */ | |
208 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | |
209 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, | |
210 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | |
211 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1, | |
212 | FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C, | |
213 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, | |
214 | FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | |
215 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, | |
9f2edd41 | 216 | FN_ETH_CRS_DV, FN_STP_ISCLK_0_B, |
c4721249 | 217 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
9f2edd41 | 218 | FN_I2C2_SCL_E, FN_ETH_RX_ER, |
58c229e1 | 219 | FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C, |
9f2edd41 | 220 | FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0, |
58c229e1 KM |
221 | FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C, |
222 | FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1, | |
9f2edd41 | 223 | FN_HRX0_E, FN_STP_ISSYNC_0_B, |
58c229e1 | 224 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, |
9f2edd41 | 225 | FN_RX1_E, FN_ETH_LINK, FN_HTX0_E, |
58c229e1 | 226 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, |
9f2edd41 | 227 | FN_ETH_REF_CLK, FN_HCTS0_N_E, |
58c229e1 KM |
228 | FN_STP_IVCXO27_1_B, FN_HRX0_F, |
229 | ||
230 | /* IPSR7 */ | |
9f2edd41 | 231 | FN_ETH_MDIO, FN_HRTS0_N_E, |
58c229e1 | 232 | FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1, |
14da999b | 233 | FN_HTX0_F, FN_BPFCLK_G, |
9f2edd41 SK |
234 | FN_ETH_TX_EN, FN_SIM0_CLK_C, |
235 | FN_HRTS0_N_F, FN_ETH_MAGIC, | |
236 | FN_SIM0_RST_C, FN_ETH_TXD0, | |
58c229e1 | 237 | FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C, |
9f2edd41 | 238 | FN_ETH_MDC, FN_STP_ISD_1_B, |
58c229e1 KM |
239 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0, |
240 | FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | |
241 | FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C, | |
242 | FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C, | |
243 | FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, | |
f0681209 | 244 | FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1, |
58c229e1 | 245 | FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK, |
9f2edd41 | 246 | FN_ATACS00_N, FN_AVB_RXD1, |
58c229e1 | 247 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, |
58c229e1 KM |
248 | |
249 | /* IPSR8 */ | |
250 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, | |
9f2edd41 | 251 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, |
58c229e1 KM |
252 | FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, |
253 | FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, | |
254 | FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, | |
255 | FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, | |
9f2edd41 SK |
256 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, |
257 | FN_VI1_CLK, FN_AVB_RX_DV, | |
258 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, | |
259 | FN_AVB_CRS, FN_VI1_DATA1_VI1_B1, | |
260 | FN_SCIFA1_RXD_D, FN_AVB_MDC, | |
58c229e1 | 261 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, |
9f2edd41 | 262 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, |
58c229e1 | 263 | FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, |
9f2edd41 | 264 | FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5, |
58c229e1 KM |
265 | FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, |
266 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD, | |
267 | FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, | |
268 | ||
269 | /* IPSR9 */ | |
270 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, | |
271 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, | |
272 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, | |
273 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, | |
274 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | |
c4721249 SK |
275 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
276 | FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP, | |
58c229e1 | 277 | FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, |
c4721249 SK |
278 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
279 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK, | |
9f2edd41 SK |
280 | FN_AVB_TX_EN, FN_SD1_CMD, |
281 | FN_AVB_TX_ER, FN_SCIFB0_SCK_B, | |
282 | FN_SD1_DAT0, FN_AVB_TX_CLK, | |
58c229e1 | 283 | FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK, |
9f2edd41 SK |
284 | FN_SCIFB0_TXD_B, FN_SD1_DAT2, |
285 | FN_AVB_COL, FN_SCIFB0_CTS_N_B, | |
286 | FN_SD1_DAT3, FN_AVB_RXD0, | |
58c229e1 KM |
287 | FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6, |
288 | FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B, | |
c4721249 | 289 | FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B, |
58c229e1 KM |
290 | FN_VI3_CLK_B, |
291 | ||
292 | /* IPSR10 */ | |
293 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | |
c4721249 | 294 | FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
58c229e1 KM |
295 | FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, |
296 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | |
297 | FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | |
298 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | |
299 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | |
300 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | |
301 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | |
302 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | |
14da999b | 303 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, |
58c229e1 KM |
304 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, |
305 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | |
14da999b | 306 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, |
58c229e1 KM |
307 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, |
308 | FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3, | |
309 | FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | |
310 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, | |
311 | FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4, | |
312 | FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | |
313 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | |
314 | FN_GLO_I0_B, FN_VI3_DATA6_B, | |
315 | ||
316 | /* IPSR11 */ | |
317 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | |
318 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | |
319 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, | |
320 | FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD, | |
321 | FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, | |
322 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2, | |
323 | FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3, | |
324 | FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | |
325 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP, | |
326 | FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | |
14da999b SK |
327 | FN_FMIN_E, FN_FMIN_F, |
328 | FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, | |
c4721249 | 329 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, |
7d2b2854 | 330 | FN_I2C2_SDA_B, FN_MLB_DAT, |
58c229e1 | 331 | FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
14da999b | 332 | FN_SSI_SCK0129, FN_CAN_CLK_B, |
58c229e1 KM |
333 | FN_MOUT0, |
334 | ||
335 | /* IPSR12 */ | |
336 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, | |
337 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, | |
338 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, | |
339 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | |
340 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | |
341 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34, | |
342 | FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | |
343 | FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0, | |
344 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, | |
345 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | |
346 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, | |
347 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | |
348 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, | |
349 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | |
350 | FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK, | |
351 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | |
352 | FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD, | |
353 | FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | |
354 | FN_CAN_DEBUGOUT4, | |
355 | ||
356 | /* IPSR13 */ | |
357 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | |
358 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6, | |
14da999b | 359 | FN_SCIFB1_CTS_N, FN_BPFCLK_D, |
58c229e1 | 360 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, |
14da999b | 361 | FN_BPFCLK_F, FN_SSI_WS6, |
58c229e1 KM |
362 | FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, |
363 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6, | |
14da999b | 364 | FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5, |
58c229e1 KM |
365 | FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1, |
366 | FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6, | |
367 | FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1, | |
368 | FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7, | |
369 | FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7, | |
370 | FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | |
371 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, | |
14da999b SK |
372 | FN_BPFCLK_E, FN_SSI_SDATA7_B, |
373 | FN_FMIN_G, FN_SSI_SDATA8, | |
58c229e1 KM |
374 | FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, |
375 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9, | |
376 | FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | |
377 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA, | |
378 | FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, | |
379 | ||
380 | /* IPSR14 */ | |
381 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | |
382 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | |
383 | FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, | |
c4721249 SK |
384 | FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C, |
385 | FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0, | |
58c229e1 KM |
386 | FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1, |
387 | FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N, | |
388 | FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3, | |
c4721249 | 389 | FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
bcec7475 | 390 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
58c229e1 KM |
391 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, |
392 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | |
393 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, | |
394 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | |
395 | FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK, | |
396 | FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK, | |
bcec7475 | 397 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
58c229e1 KM |
398 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
399 | FN_HRTS0_N_C, | |
400 | ||
401 | /* IPSR15 */ | |
1ddb66cd | 402 | FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
58c229e1 | 403 | FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN, |
1ddb66cd SK |
404 | FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL, |
405 | FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, | |
c4721249 | 406 | FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0, |
58c229e1 KM |
407 | FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0, |
408 | FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3, | |
409 | FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, | |
410 | FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, | |
411 | FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | |
412 | FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0, | |
413 | FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23, | |
5de880dd | 414 | FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0, |
58c229e1 KM |
415 | FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1, |
416 | FN_DU2_DG6, FN_LCDOUT14, | |
417 | ||
418 | /* IPSR16 */ | |
419 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | |
420 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, | |
421 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | |
5de880dd | 422 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, |
58c229e1 KM |
423 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC, |
424 | FN_TCLK1_B, | |
425 | ||
426 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | |
427 | FN_SEL_SCIF1_4, | |
428 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, | |
429 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, | |
430 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3, | |
431 | FN_SEL_SCIFB1_4, | |
432 | FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6, | |
433 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3, | |
434 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | |
435 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | |
436 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | |
437 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, | |
438 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
439 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, | |
440 | FN_SEL_VI3_0, FN_SEL_VI3_1, | |
441 | FN_SEL_VI2_0, FN_SEL_VI2_1, | |
442 | FN_SEL_VI1_0, FN_SEL_VI1_1, | |
443 | FN_SEL_VI0_0, FN_SEL_VI0_1, | |
444 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, | |
445 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
446 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
447 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | |
448 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, | |
449 | ||
450 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | |
451 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
452 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | |
453 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
454 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | |
455 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, | |
456 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
1ddb66cd | 457 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, |
58c229e1 KM |
458 | FN_SEL_ADI_0, FN_SEL_ADI_1, |
459 | FN_SEL_SSP_0, FN_SEL_SSP_1, | |
460 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | |
461 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, | |
462 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3, | |
463 | FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, | |
464 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, | |
58c229e1 KM |
465 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, |
466 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, | |
467 | ||
468 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | |
469 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | |
470 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, | |
471 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | |
472 | FN_SEL_IIC2_4, | |
473 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, | |
474 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | |
475 | FN_SEL_I2C2_4, | |
476 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, | |
477 | PINMUX_FUNCTION_END, | |
478 | ||
479 | PINMUX_MARK_BEGIN, | |
480 | ||
481 | VI1_DATA7_VI1_B7_MARK, | |
482 | ||
483 | USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, | |
484 | USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK, | |
485 | DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK, | |
486 | ||
487 | D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK, | |
488 | D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK, | |
489 | VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK, | |
490 | VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK, | |
491 | VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK, | |
492 | SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK, | |
493 | VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK, | |
494 | SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK, | |
495 | VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK, | |
c4721249 SK |
496 | IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK, |
497 | I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK, | |
05bcb07b | 498 | VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK, |
9f2edd41 | 499 | D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, |
58c229e1 KM |
500 | VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK, |
501 | ||
9f2edd41 | 502 | D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, |
58c229e1 | 503 | VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK, |
9f2edd41 | 504 | SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, |
58c229e1 | 505 | VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK, |
9f2edd41 | 506 | SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, |
58c229e1 KM |
507 | VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK, |
508 | D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK, | |
509 | VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK, | |
510 | D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK, | |
511 | VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK, | |
512 | SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK, | |
513 | VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK, | |
514 | D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK, | |
515 | VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK, | |
516 | A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK, | |
517 | ||
518 | A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK, | |
519 | PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK, | |
520 | TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK, | |
521 | A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK, | |
522 | SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK, | |
523 | A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK, | |
1ddb66cd | 524 | VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK, |
58c229e1 | 525 | A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK, |
1ddb66cd | 526 | VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK, |
58c229e1 KM |
527 | A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK, |
528 | VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK, | |
529 | ||
530 | A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK, | |
531 | VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK, | |
532 | A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK, | |
533 | VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK, | |
534 | A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK, | |
535 | MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK, | |
536 | VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK, | |
537 | ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK, | |
538 | ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK, | |
539 | A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK, | |
540 | AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK, | |
541 | ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK, | |
542 | VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK, | |
543 | ||
544 | A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK, | |
545 | A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK, | |
546 | VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK, | |
547 | VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK, | |
548 | VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK, | |
549 | VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK, | |
550 | VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK, | |
551 | VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK, | |
552 | CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK, | |
553 | VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK, | |
554 | VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK, | |
555 | MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK, | |
556 | HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK, | |
557 | VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK, | |
558 | VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK, | |
559 | ||
560 | EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK, | |
561 | VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK, | |
562 | EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK, | |
c4721249 SK |
563 | VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK, |
564 | INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK, | |
58c229e1 | 565 | MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK, |
c4721249 SK |
566 | VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK, |
567 | I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK, | |
58c229e1 KM |
568 | CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK, |
569 | CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK, | |
570 | VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK, | |
571 | INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK, | |
572 | VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK, | |
573 | WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK, | |
574 | VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK, | |
575 | IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK, | |
576 | VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK, | |
577 | MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK, | |
578 | VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK, | |
579 | SSI_WS78_B_MARK, | |
580 | ||
581 | DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK, | |
582 | VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK, | |
583 | DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK, | |
584 | SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK, | |
585 | INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK, | |
586 | DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK, | |
587 | MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK, | |
588 | SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK, | |
9f2edd41 | 589 | ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK, |
c4721249 | 590 | TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK, |
9f2edd41 | 591 | I2C2_SCL_E_MARK, ETH_RX_ER_MARK, |
58c229e1 | 592 | STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK, |
9f2edd41 | 593 | IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK, |
58c229e1 KM |
594 | STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK, |
595 | SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK, | |
9f2edd41 | 596 | HRX0_E_MARK, STP_ISSYNC_0_B_MARK, |
58c229e1 | 597 | TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK, |
9f2edd41 | 598 | RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK, |
58c229e1 | 599 | STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK, |
9f2edd41 | 600 | ETH_REF_CLK_MARK, HCTS0_N_E_MARK, |
58c229e1 KM |
601 | STP_IVCXO27_1_B_MARK, HRX0_F_MARK, |
602 | ||
9f2edd41 | 603 | ETH_MDIO_MARK, HRTS0_N_E_MARK, |
58c229e1 | 604 | SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK, |
14da999b | 605 | HTX0_F_MARK, BPFCLK_G_MARK, |
9f2edd41 SK |
606 | ETH_TX_EN_MARK, SIM0_CLK_C_MARK, |
607 | HRTS0_N_F_MARK, ETH_MAGIC_MARK, | |
608 | SIM0_RST_C_MARK, ETH_TXD0_MARK, | |
58c229e1 | 609 | STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK, |
9f2edd41 | 610 | ETH_MDC_MARK, STP_ISD_1_B_MARK, |
58c229e1 KM |
611 | TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK, |
612 | SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK, | |
613 | GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK, | |
614 | STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK, | |
615 | PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK, | |
f0681209 | 616 | PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK, |
58c229e1 | 617 | AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK, |
9f2edd41 | 618 | ATACS00_N_MARK, AVB_RXD1_MARK, |
58c229e1 | 619 | VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK, |
58c229e1 KM |
620 | |
621 | VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK, | |
9f2edd41 | 622 | VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK, |
58c229e1 KM |
623 | AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK, |
624 | AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK, | |
625 | AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK, | |
626 | AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK, | |
9f2edd41 SK |
627 | VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK, |
628 | VI1_CLK_MARK, AVB_RX_DV_MARK, | |
629 | VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK, | |
630 | AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK, | |
631 | SCIFA1_RXD_D_MARK, AVB_MDC_MARK, | |
58c229e1 | 632 | VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK, |
9f2edd41 | 633 | VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK, |
58c229e1 | 634 | AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK, |
9f2edd41 | 635 | AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK, |
58c229e1 KM |
636 | AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK, |
637 | SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK, | |
638 | SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK, | |
639 | ||
640 | SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK, | |
641 | SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK, | |
642 | SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK, | |
643 | SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK, | |
644 | SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK, | |
c4721249 SK |
645 | GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK, |
646 | I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK, | |
58c229e1 | 647 | MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK, |
c4721249 SK |
648 | GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK, |
649 | I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK, | |
9f2edd41 SK |
650 | AVB_TX_EN_MARK, SD1_CMD_MARK, |
651 | AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK, | |
652 | SD1_DAT0_MARK, AVB_TX_CLK_MARK, | |
58c229e1 | 653 | SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK, |
9f2edd41 SK |
654 | SCIFB0_TXD_B_MARK, SD1_DAT2_MARK, |
655 | AVB_COL_MARK, SCIFB0_CTS_N_B_MARK, | |
656 | SD1_DAT3_MARK, AVB_RXD0_MARK, | |
58c229e1 KM |
657 | SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK, |
658 | TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK, | |
c4721249 | 659 | IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK, |
58c229e1 KM |
660 | VI3_CLK_B_MARK, |
661 | ||
662 | SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK, | |
c4721249 | 663 | GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK, |
58c229e1 KM |
664 | SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK, |
665 | VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK, | |
666 | VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK, | |
667 | VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK, | |
668 | TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK, | |
669 | SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK, | |
670 | VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK, | |
671 | TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK, | |
14da999b | 672 | SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, |
58c229e1 KM |
673 | VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK, |
674 | TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK, | |
14da999b | 675 | SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, |
58c229e1 KM |
676 | VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK, |
677 | GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK, | |
678 | MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK, | |
679 | HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK, | |
680 | VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK, | |
681 | TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK, | |
682 | VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK, | |
683 | GLO_I0_B_MARK, VI3_DATA6_B_MARK, | |
684 | ||
685 | SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK, | |
686 | GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK, | |
687 | TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK, | |
688 | SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK, | |
689 | MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK, | |
690 | SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK, | |
691 | MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK, | |
692 | SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK, | |
693 | VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK, | |
694 | MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK, | |
14da999b SK |
695 | FMIN_E_MARK, FMIN_F_MARK, |
696 | MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK, | |
c4721249 | 697 | MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK, |
7d2b2854 | 698 | I2C2_SDA_B_MARK, MLB_DAT_MARK, |
58c229e1 | 699 | SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK, |
14da999b | 700 | SSI_SCK0129_MARK, CAN_CLK_B_MARK, |
58c229e1 KM |
701 | MOUT0_MARK, |
702 | ||
703 | SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK, | |
704 | SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK, | |
705 | SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK, | |
706 | SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK, | |
707 | SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK, | |
708 | MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK, | |
709 | STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK, | |
710 | CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK, | |
711 | SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK, | |
712 | SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK, | |
713 | MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK, | |
714 | SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK, | |
715 | MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK, | |
716 | SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK, | |
717 | CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK, | |
718 | IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK, | |
719 | CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK, | |
720 | IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK, | |
721 | CAN_DEBUGOUT4_MARK, | |
722 | ||
723 | SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK, | |
724 | LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK, | |
14da999b | 725 | SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, |
58c229e1 | 726 | DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK, |
14da999b | 727 | BPFCLK_F_MARK, SSI_WS6_MARK, |
58c229e1 KM |
728 | SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK, |
729 | LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK, | |
14da999b | 730 | FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK, |
58c229e1 KM |
731 | CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK, |
732 | SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK, | |
733 | CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK, | |
734 | SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK, | |
735 | LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK, | |
736 | STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK, | |
737 | TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK, | |
14da999b SK |
738 | BPFCLK_E_MARK, SSI_SDATA7_B_MARK, |
739 | FMIN_G_MARK, SSI_SDATA8_MARK, | |
58c229e1 KM |
740 | STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK, |
741 | CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK, | |
742 | STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK, | |
743 | SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK, | |
744 | SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK, | |
745 | ||
746 | AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK, | |
747 | DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK, | |
748 | REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK, | |
c4721249 SK |
749 | MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK, |
750 | I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK, | |
58c229e1 KM |
751 | DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK, |
752 | TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK, | |
753 | HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK, | |
c4721249 | 754 | LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK, |
bcec7475 | 755 | SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK, |
58c229e1 KM |
756 | MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK, |
757 | SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK, | |
758 | DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, | |
759 | SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK, | |
760 | LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK, | |
761 | CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK, | |
bcec7475 | 762 | SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK, |
58c229e1 KM |
763 | MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK, |
764 | HRTS0_N_C_MARK, | |
765 | ||
1ddb66cd | 766 | SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK, |
58c229e1 | 767 | LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK, |
1ddb66cd SK |
768 | TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK, |
769 | SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK, | |
c4721249 | 770 | IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK, |
58c229e1 KM |
771 | DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK, |
772 | DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK, | |
773 | LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK, | |
774 | LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK, | |
775 | LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK, | |
776 | DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK, | |
777 | SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK, | |
5de880dd | 778 | HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK, |
58c229e1 KM |
779 | DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK, |
780 | DU2_DG6_MARK, LCDOUT14_MARK, | |
781 | ||
782 | MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK, | |
783 | DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK, | |
784 | MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK, | |
5de880dd | 785 | ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, |
58c229e1 KM |
786 | USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, |
787 | TCLK1_B_MARK, | |
f6aaaac9 | 788 | |
a16b81dc WS |
789 | IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK, |
790 | IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK, | |
58c229e1 KM |
791 | PINMUX_MARK_END, |
792 | }; | |
793 | ||
533743dc | 794 | static const u16 pinmux_data[] = { |
58c229e1 KM |
795 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ |
796 | ||
01af9ecb GU |
797 | PINMUX_SINGLE(VI1_DATA7_VI1_B7), |
798 | PINMUX_SINGLE(USB0_PWEN), | |
799 | PINMUX_SINGLE(USB0_OVC_VBUS), | |
800 | PINMUX_SINGLE(USB2_PWEN), | |
801 | PINMUX_SINGLE(USB2_OVC), | |
802 | PINMUX_SINGLE(AVS1), | |
803 | PINMUX_SINGLE(AVS2), | |
804 | PINMUX_SINGLE(DU_DOTCLKIN0), | |
805 | PINMUX_SINGLE(DU_DOTCLKIN2), | |
58c229e1 | 806 | |
e01678e3 | 807 | PINMUX_IPSR_GPSR(IP0_2_0, D0), |
af5132dd KM |
808 | PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1), |
809 | PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0), | |
810 | PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0), | |
811 | PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1), | |
e01678e3 | 812 | PINMUX_IPSR_GPSR(IP0_5_3, D1), |
af5132dd KM |
813 | PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1), |
814 | PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0), | |
815 | PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0), | |
816 | PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1), | |
e01678e3 | 817 | PINMUX_IPSR_GPSR(IP0_8_6, D2), |
af5132dd KM |
818 | PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1), |
819 | PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0), | |
820 | PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0), | |
821 | PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1), | |
e01678e3 | 822 | PINMUX_IPSR_GPSR(IP0_11_9, D3), |
af5132dd KM |
823 | PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1), |
824 | PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0), | |
825 | PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0), | |
826 | PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1), | |
e01678e3 | 827 | PINMUX_IPSR_GPSR(IP0_15_12, D4), |
af5132dd KM |
828 | PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5), |
829 | PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2), | |
830 | PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0), | |
831 | PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0), | |
832 | PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1), | |
833 | PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1), | |
e01678e3 | 834 | PINMUX_IPSR_GPSR(IP0_19_16, D5), |
af5132dd KM |
835 | PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5), |
836 | PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2), | |
837 | PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0), | |
838 | PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0), | |
839 | PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1), | |
840 | PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1), | |
e01678e3 | 841 | PINMUX_IPSR_GPSR(IP0_22_20, D6), |
af5132dd KM |
842 | PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2), |
843 | PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0), | |
844 | PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0), | |
845 | PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1), | |
846 | PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2), | |
e01678e3 | 847 | PINMUX_IPSR_GPSR(IP0_26_23, D7), |
af5132dd KM |
848 | PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1), |
849 | PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2), | |
850 | PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0), | |
851 | PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0), | |
852 | PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1), | |
853 | PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2), | |
854 | PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0), | |
e01678e3 | 855 | PINMUX_IPSR_GPSR(IP0_30_27, D8), |
af5132dd | 856 | PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2), |
e01678e3 | 857 | PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0), |
af5132dd KM |
858 | PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0), |
859 | PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1), | |
860 | PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0), | |
58c229e1 | 861 | |
e01678e3 | 862 | PINMUX_IPSR_GPSR(IP1_3_0, D9), |
af5132dd | 863 | PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2), |
e01678e3 | 864 | PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1), |
af5132dd KM |
865 | PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0), |
866 | PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1), | |
867 | PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0), | |
e01678e3 | 868 | PINMUX_IPSR_GPSR(IP1_7_4, D10), |
af5132dd | 869 | PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2), |
e01678e3 | 870 | PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2), |
af5132dd KM |
871 | PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0), |
872 | PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1), | |
873 | PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0), | |
e01678e3 | 874 | PINMUX_IPSR_GPSR(IP1_11_8, D11), |
af5132dd | 875 | PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2), |
e01678e3 | 876 | PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3), |
af5132dd KM |
877 | PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0), |
878 | PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1), | |
879 | PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0), | |
e01678e3 | 880 | PINMUX_IPSR_GPSR(IP1_14_12, D12), |
af5132dd | 881 | PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2), |
e01678e3 | 882 | PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4), |
af5132dd KM |
883 | PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0), |
884 | PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1), | |
885 | PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0), | |
e01678e3 GU |
886 | PINMUX_IPSR_GPSR(IP1_17_15, D13), |
887 | PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5), | |
af5132dd KM |
888 | PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0), |
889 | PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1), | |
890 | PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0), | |
e01678e3 | 891 | PINMUX_IPSR_GPSR(IP1_21_18, D14), |
af5132dd | 892 | PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2), |
e01678e3 | 893 | PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6), |
af5132dd KM |
894 | PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1), |
895 | PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0), | |
896 | PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1), | |
897 | PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0), | |
e01678e3 | 898 | PINMUX_IPSR_GPSR(IP1_25_22, D15), |
af5132dd | 899 | PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2), |
e01678e3 | 900 | PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7), |
af5132dd KM |
901 | PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1), |
902 | PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0), | |
903 | PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1), | |
904 | PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0), | |
e01678e3 GU |
905 | PINMUX_IPSR_GPSR(IP1_27_26, A0), |
906 | PINMUX_IPSR_GPSR(IP1_27_26, PWM3), | |
907 | PINMUX_IPSR_GPSR(IP1_29_28, A1), | |
908 | PINMUX_IPSR_GPSR(IP1_29_28, PWM4), | |
58c229e1 | 909 | |
e01678e3 GU |
910 | PINMUX_IPSR_GPSR(IP2_2_0, A2), |
911 | PINMUX_IPSR_GPSR(IP2_2_0, PWM5), | |
af5132dd | 912 | PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1), |
e01678e3 GU |
913 | PINMUX_IPSR_GPSR(IP2_5_3, A3), |
914 | PINMUX_IPSR_GPSR(IP2_5_3, PWM6), | |
af5132dd | 915 | PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1), |
e01678e3 | 916 | PINMUX_IPSR_GPSR(IP2_8_6, A4), |
af5132dd | 917 | PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1), |
e01678e3 GU |
918 | PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0), |
919 | PINMUX_IPSR_GPSR(IP2_11_9, A5), | |
af5132dd | 920 | PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1), |
e01678e3 GU |
921 | PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1), |
922 | PINMUX_IPSR_GPSR(IP2_14_12, A6), | |
af5132dd | 923 | PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1), |
e01678e3 GU |
924 | PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2), |
925 | PINMUX_IPSR_GPSR(IP2_17_15, A7), | |
af5132dd | 926 | PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1), |
e01678e3 GU |
927 | PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B), |
928 | PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3), | |
929 | PINMUX_IPSR_GPSR(IP2_21_18, A8), | |
af5132dd KM |
930 | PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1), |
931 | PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1), | |
932 | PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0), | |
933 | PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1), | |
934 | PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2), | |
935 | PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1), | |
936 | PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1), | |
e01678e3 | 937 | PINMUX_IPSR_GPSR(IP2_25_22, A9), |
af5132dd KM |
938 | PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1), |
939 | PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1), | |
940 | PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0), | |
941 | PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1), | |
942 | PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2), | |
943 | PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1), | |
944 | PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1), | |
e01678e3 | 945 | PINMUX_IPSR_GPSR(IP2_28_26, A10), |
af5132dd | 946 | PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1), |
e01678e3 | 947 | PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC), |
af5132dd KM |
948 | PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0), |
949 | PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1), | |
950 | PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1), | |
58c229e1 | 951 | |
e01678e3 | 952 | PINMUX_IPSR_GPSR(IP3_3_0, A11), |
af5132dd | 953 | PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1), |
e01678e3 | 954 | PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK), |
af5132dd KM |
955 | PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0), |
956 | PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1), | |
e01678e3 | 957 | PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0), |
af5132dd | 958 | PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1), |
e01678e3 | 959 | PINMUX_IPSR_GPSR(IP3_7_4, A12), |
af5132dd | 960 | PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1), |
e01678e3 | 961 | PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD), |
af5132dd KM |
962 | PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0), |
963 | PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1), | |
e01678e3 | 964 | PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1), |
af5132dd | 965 | PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1), |
e01678e3 | 966 | PINMUX_IPSR_GPSR(IP3_11_8, A13), |
af5132dd | 967 | PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1), |
e01678e3 GU |
968 | PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2), |
969 | PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD), | |
af5132dd KM |
970 | PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0), |
971 | PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1), | |
e01678e3 | 972 | PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2), |
af5132dd | 973 | PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1), |
e01678e3 | 974 | PINMUX_IPSR_GPSR(IP3_14_12, A14), |
af5132dd | 975 | PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1), |
e01678e3 GU |
976 | PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N), |
977 | PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1), | |
978 | PINMUX_IPSR_GPSR(IP3_17_15, A15), | |
af5132dd | 979 | PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1), |
e01678e3 GU |
980 | PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N), |
981 | PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2), | |
982 | PINMUX_IPSR_GPSR(IP3_19_18, A16), | |
983 | PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N), | |
984 | PINMUX_IPSR_GPSR(IP3_22_20, A17), | |
af5132dd | 985 | PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1), |
e01678e3 GU |
986 | PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N), |
987 | PINMUX_IPSR_GPSR(IP3_25_23, A18), | |
af5132dd | 988 | PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1), |
e01678e3 GU |
989 | PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N), |
990 | PINMUX_IPSR_GPSR(IP3_28_26, A19), | |
af5132dd | 991 | PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1), |
e01678e3 | 992 | PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N), |
af5132dd | 993 | PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1), |
e01678e3 GU |
994 | PINMUX_IPSR_GPSR(IP3_31_29, A20), |
995 | PINMUX_IPSR_GPSR(IP3_31_29, SPCLK), | |
af5132dd KM |
996 | PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0), |
997 | PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1), | |
e01678e3 | 998 | PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4), |
58c229e1 | 999 | |
e01678e3 GU |
1000 | PINMUX_IPSR_GPSR(IP4_2_0, A21), |
1001 | PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0), | |
af5132dd KM |
1002 | PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0), |
1003 | PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1), | |
e01678e3 GU |
1004 | PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5), |
1005 | PINMUX_IPSR_GPSR(IP4_5_3, A22), | |
1006 | PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1), | |
af5132dd KM |
1007 | PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0), |
1008 | PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1), | |
e01678e3 GU |
1009 | PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6), |
1010 | PINMUX_IPSR_GPSR(IP4_8_6, A23), | |
1011 | PINMUX_IPSR_GPSR(IP4_8_6, IO2), | |
af5132dd KM |
1012 | PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0), |
1013 | PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1), | |
e01678e3 GU |
1014 | PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7), |
1015 | PINMUX_IPSR_GPSR(IP4_11_9, A24), | |
1016 | PINMUX_IPSR_GPSR(IP4_11_9, IO3), | |
af5132dd KM |
1017 | PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0), |
1018 | PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1), | |
1019 | PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0), | |
1020 | PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1), | |
e01678e3 GU |
1021 | PINMUX_IPSR_GPSR(IP4_14_12, A25), |
1022 | PINMUX_IPSR_GPSR(IP4_14_12, SSL), | |
af5132dd KM |
1023 | PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0), |
1024 | PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1), | |
1025 | PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0), | |
1026 | PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1), | |
e01678e3 | 1027 | PINMUX_IPSR_GPSR(IP4_17_15, CS0_N), |
af5132dd KM |
1028 | PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0), |
1029 | PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1), | |
e01678e3 | 1030 | PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3), |
af5132dd | 1031 | PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1), |
e01678e3 GU |
1032 | PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26), |
1033 | PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN), | |
af5132dd KM |
1034 | PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0), |
1035 | PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1), | |
1036 | PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0), | |
1037 | PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1), | |
e01678e3 | 1038 | PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N), |
af5132dd KM |
1039 | PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1), |
1040 | PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0), | |
1041 | PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1), | |
e01678e3 | 1042 | PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0), |
af5132dd KM |
1043 | PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1), |
1044 | PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1), | |
e01678e3 GU |
1045 | PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N), |
1046 | PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK), | |
af5132dd KM |
1047 | PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1), |
1048 | PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0), | |
1049 | PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1), | |
e01678e3 GU |
1050 | PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1), |
1051 | PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N), | |
1052 | PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN), | |
af5132dd | 1053 | PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1), |
e01678e3 | 1054 | PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB), |
af5132dd KM |
1055 | PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0), |
1056 | PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1), | |
e01678e3 | 1057 | PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2), |
58c229e1 | 1058 | |
e01678e3 GU |
1059 | PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N), |
1060 | PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG), | |
1061 | PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD), | |
af5132dd KM |
1062 | PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0), |
1063 | PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1), | |
e01678e3 GU |
1064 | PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3), |
1065 | PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N), | |
af5132dd | 1066 | PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1), |
e01678e3 | 1067 | PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N), |
af5132dd KM |
1068 | PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0), |
1069 | PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0), | |
1070 | PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1), | |
e01678e3 | 1071 | PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N), |
af5132dd | 1072 | PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0), |
e01678e3 | 1073 | PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N), |
af5132dd KM |
1074 | PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0), |
1075 | PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1), | |
e01678e3 | 1076 | PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N), |
af5132dd KM |
1077 | PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0), |
1078 | PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1), | |
e01678e3 | 1079 | PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4), |
af5132dd | 1080 | PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0), |
e01678e3 | 1081 | PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N), |
af5132dd | 1082 | PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0), |
e01678e3 | 1083 | PINMUX_IPSR_GPSR(IP5_12_10, BS_N), |
af5132dd KM |
1084 | PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0), |
1085 | PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1), | |
1086 | PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0), | |
e01678e3 | 1087 | PINMUX_IPSR_GPSR(IP5_12_10, DRACK0), |
af5132dd | 1088 | PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2), |
e01678e3 | 1089 | PINMUX_IPSR_GPSR(IP5_14_13, RD_N), |
af5132dd KM |
1090 | PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0), |
1091 | PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1), | |
e01678e3 | 1092 | PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N), |
af5132dd KM |
1093 | PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0), |
1094 | PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1), | |
e01678e3 | 1095 | PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5), |
af5132dd | 1096 | PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1), |
e01678e3 GU |
1097 | PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N), |
1098 | PINMUX_IPSR_GPSR(IP5_20_18, WE0_N), | |
af5132dd KM |
1099 | PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0), |
1100 | PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0), | |
1101 | PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0), | |
1102 | PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1), | |
1103 | PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1), | |
e01678e3 | 1104 | PINMUX_IPSR_GPSR(IP5_23_21, WE1_N), |
af5132dd KM |
1105 | PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0), |
1106 | PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0), | |
1107 | PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0), | |
1108 | PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1), | |
e01678e3 | 1109 | PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6), |
af5132dd KM |
1110 | PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1), |
1111 | PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2), | |
1112 | PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0), | |
e01678e3 GU |
1113 | PINMUX_IPSR_GPSR(IP5_26_24, IRQ3), |
1114 | PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N), | |
af5132dd KM |
1115 | PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0), |
1116 | PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1), | |
1117 | PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1), | |
1118 | PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1), | |
e01678e3 | 1119 | PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N), |
af5132dd KM |
1120 | PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0), |
1121 | PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1), | |
e01678e3 | 1122 | PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7), |
af5132dd KM |
1123 | PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2), |
1124 | PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1), | |
58c229e1 | 1125 | |
e01678e3 GU |
1126 | PINMUX_IPSR_GPSR(IP6_2_0, DACK0), |
1127 | PINMUX_IPSR_GPSR(IP6_2_0, IRQ0), | |
1128 | PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N), | |
af5132dd KM |
1129 | PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1), |
1130 | PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0), | |
1131 | PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1), | |
1132 | PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2), | |
e01678e3 | 1133 | PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N), |
af5132dd KM |
1134 | PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0), |
1135 | PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1), | |
1136 | PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2), | |
1137 | PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1), | |
e01678e3 GU |
1138 | PINMUX_IPSR_GPSR(IP6_8_6, DACK1), |
1139 | PINMUX_IPSR_GPSR(IP6_8_6, IRQ1), | |
1140 | PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N), | |
af5132dd KM |
1141 | PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1), |
1142 | PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2), | |
e01678e3 | 1143 | PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N), |
af5132dd KM |
1144 | PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1), |
1145 | PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1), | |
1146 | PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1), | |
e01678e3 GU |
1147 | PINMUX_IPSR_GPSR(IP6_13_11, DACK2), |
1148 | PINMUX_IPSR_GPSR(IP6_13_11, IRQ2), | |
1149 | PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N), | |
af5132dd KM |
1150 | PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1), |
1151 | PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1), | |
1152 | PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1), | |
e01678e3 | 1153 | PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV), |
af5132dd KM |
1154 | PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1), |
1155 | PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3), | |
1156 | PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2), | |
1157 | PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4), | |
1158 | PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4), | |
e01678e3 | 1159 | PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER), |
af5132dd KM |
1160 | PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1), |
1161 | PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3), | |
1162 | PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2), | |
1163 | PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4), | |
1164 | PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4), | |
e01678e3 | 1165 | PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0), |
af5132dd KM |
1166 | PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1), |
1167 | PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3), | |
1168 | PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2), | |
1169 | PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6), | |
1170 | PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4), | |
e01678e3 | 1171 | PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1), |
af5132dd KM |
1172 | PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4), |
1173 | PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1), | |
1174 | PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3), | |
1175 | PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2), | |
1176 | PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6), | |
1177 | PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4), | |
e01678e3 | 1178 | PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK), |
af5132dd KM |
1179 | PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4), |
1180 | PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1), | |
1181 | PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6), | |
1182 | PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4), | |
e01678e3 | 1183 | PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK), |
af5132dd KM |
1184 | PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4), |
1185 | PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1), | |
1186 | PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5), | |
58c229e1 | 1187 | |
e01678e3 | 1188 | PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO), |
af5132dd KM |
1189 | PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4), |
1190 | PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2), | |
1191 | PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5), | |
e01678e3 | 1192 | PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1), |
af5132dd KM |
1193 | PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5), |
1194 | PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6), | |
e01678e3 | 1195 | PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN), |
af5132dd KM |
1196 | PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2), |
1197 | PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5), | |
e01678e3 | 1198 | PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC), |
af5132dd | 1199 | PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2), |
e01678e3 | 1200 | PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0), |
af5132dd KM |
1201 | PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1), |
1202 | PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2), | |
1203 | PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2), | |
e01678e3 | 1204 | PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC), |
af5132dd KM |
1205 | PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1), |
1206 | PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2), | |
1207 | PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2), | |
e01678e3 | 1208 | PINMUX_IPSR_GPSR(IP7_18_16, PWM0), |
af5132dd KM |
1209 | PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2), |
1210 | PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1), | |
1211 | PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2), | |
1212 | PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2), | |
e01678e3 | 1213 | PINMUX_IPSR_GPSR(IP7_21_19, PWM1), |
af5132dd KM |
1214 | PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2), |
1215 | PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1), | |
1216 | PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2), | |
1217 | PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2), | |
e01678e3 GU |
1218 | PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N), |
1219 | PINMUX_IPSR_GPSR(IP7_24_22, PWM2), | |
1220 | PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0), | |
af5132dd | 1221 | PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2), |
e01678e3 | 1222 | PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N), |
af5132dd | 1223 | PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2), |
e01678e3 GU |
1224 | PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1), |
1225 | PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC), | |
1226 | PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C), | |
af5132dd | 1227 | PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0), |
e01678e3 GU |
1228 | PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N), |
1229 | PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1), | |
af5132dd | 1230 | PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0), |
e01678e3 GU |
1231 | PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N), |
1232 | PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2), | |
58c229e1 | 1233 | |
af5132dd | 1234 | PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0), |
e01678e3 GU |
1235 | PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N), |
1236 | PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3), | |
af5132dd | 1237 | PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0), |
e01678e3 GU |
1238 | PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N), |
1239 | PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4), | |
af5132dd | 1240 | PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0), |
e01678e3 GU |
1241 | PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N), |
1242 | PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5), | |
af5132dd | 1243 | PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0), |
e01678e3 GU |
1244 | PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N), |
1245 | PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6), | |
af5132dd | 1246 | PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0), |
e01678e3 GU |
1247 | PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1), |
1248 | PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7), | |
af5132dd | 1249 | PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0), |
e01678e3 | 1250 | PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER), |
af5132dd | 1251 | PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0), |
e01678e3 | 1252 | PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK), |
af5132dd | 1253 | PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0), |
e01678e3 | 1254 | PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV), |
af5132dd KM |
1255 | PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0), |
1256 | PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3), | |
e01678e3 | 1257 | PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS), |
af5132dd KM |
1258 | PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0), |
1259 | PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3), | |
e01678e3 | 1260 | PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC), |
af5132dd KM |
1261 | PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0), |
1262 | PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3), | |
e01678e3 | 1263 | PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO), |
af5132dd KM |
1264 | PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0), |
1265 | PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3), | |
e01678e3 | 1266 | PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK), |
af5132dd KM |
1267 | PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0), |
1268 | PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3), | |
e01678e3 | 1269 | PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC), |
af5132dd | 1270 | PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0), |
e01678e3 | 1271 | PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT), |
af5132dd | 1272 | PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0), |
e01678e3 GU |
1273 | PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK), |
1274 | PINMUX_IPSR_GPSR(IP8_28, SD0_CLK), | |
af5132dd | 1275 | PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1), |
e01678e3 | 1276 | PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD), |
af5132dd KM |
1277 | PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1), |
1278 | PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1), | |
58c229e1 | 1279 | |
e01678e3 | 1280 | PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0), |
af5132dd KM |
1281 | PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1), |
1282 | PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1), | |
e01678e3 | 1283 | PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1), |
af5132dd KM |
1284 | PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1), |
1285 | PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1), | |
e01678e3 | 1286 | PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2), |
af5132dd KM |
1287 | PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1), |
1288 | PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1), | |
e01678e3 | 1289 | PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3), |
af5132dd KM |
1290 | PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1), |
1291 | PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1), | |
e01678e3 GU |
1292 | PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD), |
1293 | PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6), | |
af5132dd | 1294 | PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1), |
e01678e3 | 1295 | PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP), |
af5132dd KM |
1296 | PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0), |
1297 | PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1), | |
1298 | PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1), | |
1299 | PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1), | |
1300 | PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1), | |
e01678e3 GU |
1301 | PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP), |
1302 | PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7), | |
af5132dd | 1303 | PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1), |
e01678e3 | 1304 | PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN), |
af5132dd KM |
1305 | PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0), |
1306 | PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1), | |
1307 | PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1), | |
1308 | PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1), | |
1309 | PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1), | |
e01678e3 GU |
1310 | PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK), |
1311 | PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN), | |
1312 | PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD), | |
1313 | PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER), | |
af5132dd | 1314 | PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1), |
e01678e3 GU |
1315 | PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0), |
1316 | PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK), | |
af5132dd | 1317 | PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1), |
e01678e3 GU |
1318 | PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1), |
1319 | PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK), | |
af5132dd | 1320 | PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1), |
e01678e3 GU |
1321 | PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2), |
1322 | PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL), | |
af5132dd | 1323 | PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1), |
e01678e3 GU |
1324 | PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3), |
1325 | PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0), | |
af5132dd | 1326 | PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1), |
e01678e3 GU |
1327 | PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD), |
1328 | PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6), | |
af5132dd | 1329 | PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0), |
e01678e3 | 1330 | PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP), |
af5132dd KM |
1331 | PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0), |
1332 | PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1), | |
1333 | PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3), | |
1334 | PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3), | |
1335 | PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1), | |
1336 | PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1), | |
58c229e1 | 1337 | |
e01678e3 GU |
1338 | PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP), |
1339 | PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7), | |
af5132dd | 1340 | PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0), |
e01678e3 | 1341 | PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN), |
af5132dd KM |
1342 | PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0), |
1343 | PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1), | |
1344 | PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3), | |
1345 | PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3), | |
1346 | PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1), | |
e01678e3 GU |
1347 | PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK), |
1348 | PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK), | |
af5132dd KM |
1349 | PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0), |
1350 | PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1), | |
1351 | PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2), | |
1352 | PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1), | |
1353 | PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1), | |
e01678e3 GU |
1354 | PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD), |
1355 | PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD), | |
af5132dd KM |
1356 | PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0), |
1357 | PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1), | |
1358 | PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4), | |
1359 | PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3), | |
1360 | PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2), | |
1361 | PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1), | |
1362 | PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1), | |
e01678e3 GU |
1363 | PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0), |
1364 | PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0), | |
af5132dd KM |
1365 | PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1), |
1366 | PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1), | |
1367 | PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4), | |
1368 | PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3), | |
1369 | PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2), | |
1370 | PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1), | |
1371 | PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1), | |
e01678e3 GU |
1372 | PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1), |
1373 | PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1), | |
af5132dd KM |
1374 | PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1), |
1375 | PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1), | |
1376 | PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4), | |
1377 | PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3), | |
1378 | PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2), | |
1379 | PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1), | |
1380 | PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1), | |
e01678e3 GU |
1381 | PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2), |
1382 | PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2), | |
af5132dd KM |
1383 | PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1), |
1384 | PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1), | |
1385 | PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3), | |
1386 | PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1), | |
1387 | PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1), | |
1388 | PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1), | |
e01678e3 GU |
1389 | PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3), |
1390 | PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3), | |
af5132dd KM |
1391 | PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0), |
1392 | PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1), | |
1393 | PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3), | |
1394 | PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1), | |
1395 | PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1), | |
1396 | PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1), | |
e01678e3 GU |
1397 | PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD), |
1398 | PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4), | |
af5132dd | 1399 | PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1), |
e01678e3 | 1400 | PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP), |
af5132dd KM |
1401 | PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0), |
1402 | PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1), | |
1403 | PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3), | |
1404 | PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1), | |
1405 | PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1), | |
1406 | PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1), | |
58c229e1 | 1407 | |
e01678e3 GU |
1408 | PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP), |
1409 | PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5), | |
af5132dd | 1410 | PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1), |
e01678e3 | 1411 | PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN), |
af5132dd KM |
1412 | PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0), |
1413 | PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1), | |
1414 | PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3), | |
1415 | PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1), | |
1416 | PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1), | |
1417 | PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1), | |
e01678e3 GU |
1418 | PINMUX_IPSR_GPSR(IP11_4, SD3_CLK), |
1419 | PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK), | |
1420 | PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD), | |
1421 | PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD), | |
1422 | PINMUX_IPSR_GPSR(IP11_6_5, MTS_N), | |
1423 | PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0), | |
1424 | PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0), | |
1425 | PINMUX_IPSR_GPSR(IP11_8_7, STM_N), | |
1426 | PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1), | |
1427 | PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1), | |
1428 | PINMUX_IPSR_GPSR(IP11_10_9, MDATA), | |
1429 | PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2), | |
1430 | PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2), | |
1431 | PINMUX_IPSR_GPSR(IP11_12_11, SDATA), | |
1432 | PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3), | |
1433 | PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3), | |
1434 | PINMUX_IPSR_GPSR(IP11_14_13, SCKZ), | |
1435 | PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD), | |
1436 | PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4), | |
af5132dd | 1437 | PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0), |
e01678e3 | 1438 | PINMUX_IPSR_GPSR(IP11_17_15, VSP), |
af5132dd KM |
1439 | PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0), |
1440 | PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1), | |
e01678e3 GU |
1441 | PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP), |
1442 | PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5), | |
af5132dd KM |
1443 | PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0), |
1444 | PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0), | |
1445 | PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2), | |
1446 | PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4), | |
1447 | PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5), | |
e01678e3 | 1448 | PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK), |
af5132dd KM |
1449 | PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1), |
1450 | PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1), | |
e01678e3 | 1451 | PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG), |
af5132dd KM |
1452 | PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3), |
1453 | PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2), | |
1454 | PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1), | |
1455 | PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1), | |
e01678e3 | 1456 | PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT), |
af5132dd KM |
1457 | PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3), |
1458 | PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2), | |
1459 | PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2), | |
e01678e3 | 1460 | PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129), |
af5132dd | 1461 | PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1), |
e01678e3 | 1462 | PINMUX_IPSR_GPSR(IP11_31_30, MOUT0), |
58c229e1 | 1463 | |
e01678e3 | 1464 | PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129), |
af5132dd | 1465 | PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1), |
e01678e3 GU |
1466 | PINMUX_IPSR_GPSR(IP12_1_0, MOUT1), |
1467 | PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0), | |
af5132dd | 1468 | PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1), |
e01678e3 GU |
1469 | PINMUX_IPSR_GPSR(IP12_3_2, MOUT2), |
1470 | PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1), | |
af5132dd | 1471 | PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1), |
e01678e3 GU |
1472 | PINMUX_IPSR_GPSR(IP12_5_4, MOUT5), |
1473 | PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2), | |
af5132dd | 1474 | PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1), |
e01678e3 GU |
1475 | PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1), |
1476 | PINMUX_IPSR_GPSR(IP12_7_6, MOUT6), | |
1477 | PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34), | |
1478 | PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0), | |
af5132dd KM |
1479 | PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0), |
1480 | PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0), | |
e01678e3 GU |
1481 | PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER), |
1482 | PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34), | |
af5132dd KM |
1483 | PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0), |
1484 | PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0), | |
e01678e3 GU |
1485 | PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC), |
1486 | PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0), | |
1487 | PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3), | |
af5132dd KM |
1488 | PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0), |
1489 | PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0), | |
1490 | PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0), | |
e01678e3 GU |
1491 | PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK), |
1492 | PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4), | |
af5132dd KM |
1493 | PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0), |
1494 | PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0), | |
1495 | PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0), | |
1496 | PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2), | |
e01678e3 GU |
1497 | PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0), |
1498 | PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4), | |
af5132dd KM |
1499 | PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0), |
1500 | PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0), | |
1501 | PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0), | |
1502 | PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2), | |
e01678e3 GU |
1503 | PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1), |
1504 | PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4), | |
af5132dd KM |
1505 | PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0), |
1506 | PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0), | |
e01678e3 | 1507 | PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2), |
af5132dd KM |
1508 | PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0), |
1509 | PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0), | |
1510 | PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1), | |
e01678e3 GU |
1511 | PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC), |
1512 | PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS), | |
1513 | PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3), | |
af5132dd KM |
1514 | PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0), |
1515 | PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0), | |
1516 | PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1), | |
e01678e3 GU |
1517 | PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC), |
1518 | PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE), | |
1519 | PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4), | |
58c229e1 | 1520 | |
af5132dd KM |
1521 | PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0), |
1522 | PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0), | |
1523 | PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1), | |
e01678e3 GU |
1524 | PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2), |
1525 | PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2), | |
1526 | PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5), | |
af5132dd KM |
1527 | PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0), |
1528 | PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0), | |
1529 | PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3), | |
e01678e3 GU |
1530 | PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3), |
1531 | PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3), | |
1532 | PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6), | |
af5132dd KM |
1533 | PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5), |
1534 | PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0), | |
1535 | PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0), | |
1536 | PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3), | |
e01678e3 GU |
1537 | PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4), |
1538 | PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4), | |
1539 | PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7), | |
af5132dd KM |
1540 | PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0), |
1541 | PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3), | |
e01678e3 GU |
1542 | PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5), |
1543 | PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5), | |
1544 | PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8), | |
af5132dd KM |
1545 | PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0), |
1546 | PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0), | |
1547 | PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0), | |
1548 | PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0), | |
e01678e3 GU |
1549 | PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6), |
1550 | PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6), | |
1551 | PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9), | |
af5132dd KM |
1552 | PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0), |
1553 | PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0), | |
1554 | PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0), | |
e01678e3 GU |
1555 | PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N), |
1556 | PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7), | |
1557 | PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7), | |
1558 | PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10), | |
af5132dd KM |
1559 | PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0), |
1560 | PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0), | |
1561 | PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0), | |
e01678e3 GU |
1562 | PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N), |
1563 | PINMUX_IPSR_GPSR(IP13_22_19, TCLK2), | |
1564 | PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS), | |
1565 | PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11), | |
af5132dd KM |
1566 | PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4), |
1567 | PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1), | |
1568 | PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6), | |
1569 | PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0), | |
1570 | PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0), | |
1571 | PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0), | |
1572 | PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2), | |
e01678e3 | 1573 | PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12), |
af5132dd | 1574 | PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1), |
e01678e3 | 1575 | PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9), |
af5132dd KM |
1576 | PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0), |
1577 | PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0), | |
e01678e3 | 1578 | PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1), |
af5132dd | 1579 | PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2), |
e01678e3 GU |
1580 | PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13), |
1581 | PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA), | |
af5132dd | 1582 | PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0), |
e01678e3 | 1583 | PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14), |
58c229e1 | 1584 | |
e01678e3 | 1585 | PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB), |
af5132dd KM |
1586 | PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0), |
1587 | PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3), | |
e01678e3 | 1588 | PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE), |
af5132dd | 1589 | PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2), |
e01678e3 GU |
1590 | PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15), |
1591 | PINMUX_IPSR_GPSR(IP14_2_0, REMOCON), | |
af5132dd KM |
1592 | PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0), |
1593 | PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0), | |
e01678e3 GU |
1594 | PINMUX_IPSR_GPSR(IP14_5_3, SCK0), |
1595 | PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2), | |
1596 | PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2), | |
1597 | PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10), | |
af5132dd KM |
1598 | PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2), |
1599 | PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2), | |
1600 | PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0), | |
1601 | PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0), | |
1602 | PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0), | |
e01678e3 GU |
1603 | PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0), |
1604 | PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0), | |
af5132dd KM |
1605 | PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0), |
1606 | PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0), | |
1607 | PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0), | |
e01678e3 GU |
1608 | PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1), |
1609 | PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1), | |
af5132dd KM |
1610 | PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0), |
1611 | PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0), | |
e01678e3 | 1612 | PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N), |
af5132dd | 1613 | PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0), |
e01678e3 GU |
1614 | PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3), |
1615 | PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11), | |
1616 | PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B), | |
af5132dd KM |
1617 | PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2), |
1618 | PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2), | |
1619 | PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0), | |
1620 | PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0), | |
e01678e3 GU |
1621 | PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N), |
1622 | PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1), | |
1623 | PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0), | |
1624 | PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8), | |
1625 | PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B), | |
af5132dd KM |
1626 | PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0), |
1627 | PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0), | |
1628 | PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0), | |
e01678e3 GU |
1629 | PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE), |
1630 | PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE), | |
af5132dd KM |
1631 | PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0), |
1632 | PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0), | |
1633 | PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0), | |
e01678e3 GU |
1634 | PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1), |
1635 | PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9), | |
af5132dd KM |
1636 | PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0), |
1637 | PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0), | |
e01678e3 | 1638 | PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N), |
af5132dd | 1639 | PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0), |
e01678e3 GU |
1640 | PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT), |
1641 | PINMUX_IPSR_GPSR(IP14_27_25, QCLK), | |
af5132dd KM |
1642 | PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0), |
1643 | PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0), | |
e01678e3 | 1644 | PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N), |
af5132dd | 1645 | PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0), |
e01678e3 GU |
1646 | PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT), |
1647 | PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE), | |
af5132dd | 1648 | PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2), |
58c229e1 | 1649 | |
af5132dd KM |
1650 | PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0), |
1651 | PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0), | |
e01678e3 | 1652 | PINMUX_IPSR_GPSR(IP15_2_0, SCK2), |
af5132dd | 1653 | PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0), |
e01678e3 GU |
1654 | PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7), |
1655 | PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15), | |
af5132dd KM |
1656 | PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1), |
1657 | PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0), | |
1658 | PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0), | |
1659 | PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0), | |
e01678e3 GU |
1660 | PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0), |
1661 | PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16), | |
af5132dd KM |
1662 | PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0), |
1663 | PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0), | |
1664 | PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0), | |
1665 | PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0), | |
1666 | PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0), | |
e01678e3 GU |
1667 | PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1), |
1668 | PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17), | |
af5132dd KM |
1669 | PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0), |
1670 | PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0), | |
e01678e3 | 1671 | PINMUX_IPSR_GPSR(IP15_11_9, HSCK0), |
af5132dd | 1672 | PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0), |
e01678e3 GU |
1673 | PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4), |
1674 | PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12), | |
af5132dd KM |
1675 | PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2), |
1676 | PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0), | |
e01678e3 GU |
1677 | PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2), |
1678 | PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18), | |
af5132dd | 1679 | PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0), |
e01678e3 GU |
1680 | PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3), |
1681 | PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19), | |
af5132dd | 1682 | PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0), |
e01678e3 GU |
1683 | PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9), |
1684 | PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4), | |
1685 | PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20), | |
af5132dd | 1686 | PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0), |
e01678e3 GU |
1687 | PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9), |
1688 | PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5), | |
1689 | PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21), | |
af5132dd KM |
1690 | PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0), |
1691 | PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0), | |
e01678e3 GU |
1692 | PINMUX_IPSR_GPSR(IP15_22_20, ADICLK), |
1693 | PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6), | |
1694 | PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22), | |
1695 | PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC), | |
af5132dd | 1696 | PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0), |
e01678e3 GU |
1697 | PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2), |
1698 | PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA), | |
1699 | PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7), | |
1700 | PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23), | |
af5132dd KM |
1701 | PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1), |
1702 | PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0), | |
e01678e3 GU |
1703 | PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0), |
1704 | PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5), | |
1705 | PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13), | |
af5132dd | 1706 | PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0), |
e01678e3 GU |
1707 | PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1), |
1708 | PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6), | |
1709 | PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14), | |
58c229e1 | 1710 | |
af5132dd | 1711 | PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0), |
e01678e3 GU |
1712 | PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT), |
1713 | PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2), | |
1714 | PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP), | |
1715 | PINMUX_IPSR_GPSR(IP16_2_0, QPOLA), | |
af5132dd KM |
1716 | PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2), |
1717 | PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1), | |
1718 | PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0), | |
1719 | PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0), | |
e01678e3 GU |
1720 | PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2), |
1721 | PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP), | |
1722 | PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE), | |
1723 | PINMUX_IPSR_GPSR(IP16_5_3, QPOLB), | |
af5132dd | 1724 | PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2), |
e01678e3 GU |
1725 | PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN), |
1726 | PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D), | |
1727 | PINMUX_IPSR_GPSR(IP16_7, USB1_OVC), | |
af5132dd | 1728 | PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1), |
f6aaaac9 | 1729 | |
a16b81dc WS |
1730 | PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0), |
1731 | PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0), | |
35a493de WS |
1732 | PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1), |
1733 | PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1), | |
1734 | ||
a16b81dc WS |
1735 | PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0), |
1736 | PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0), | |
f6aaaac9 GL |
1737 | PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1), |
1738 | PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1), | |
58c229e1 KM |
1739 | }; |
1740 | ||
f6aaaac9 GL |
1741 | /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */ |
1742 | #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r)) | |
1743 | #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) | |
1744 | #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) | |
1745 | ||
44a45b55 | 1746 | static const struct sh_pfc_pin pinmux_pins[] = { |
58c229e1 | 1747 | PINMUX_GPIO_GP_ALL(), |
f6aaaac9 GL |
1748 | |
1749 | /* Pins not associated with a GPIO port */ | |
35a493de WS |
1750 | SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15), |
1751 | SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15), | |
f6aaaac9 | 1752 | SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), |
35a493de | 1753 | SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15), |
58c229e1 KM |
1754 | }; |
1755 | ||
fcec5b22 KM |
1756 | /* - AUDIO CLOCK ------------------------------------------------------------ */ |
1757 | static const unsigned int audio_clk_a_pins[] = { | |
1758 | /* CLK A */ | |
1759 | RCAR_GP_PIN(4, 25), | |
1760 | }; | |
1761 | static const unsigned int audio_clk_a_mux[] = { | |
1762 | AUDIO_CLKA_MARK, | |
1763 | }; | |
1764 | static const unsigned int audio_clk_b_pins[] = { | |
1765 | /* CLK B */ | |
1766 | RCAR_GP_PIN(4, 26), | |
1767 | }; | |
1768 | static const unsigned int audio_clk_b_mux[] = { | |
1769 | AUDIO_CLKB_MARK, | |
1770 | }; | |
1771 | static const unsigned int audio_clk_c_pins[] = { | |
1772 | /* CLK C */ | |
1773 | RCAR_GP_PIN(5, 27), | |
1774 | }; | |
1775 | static const unsigned int audio_clk_c_mux[] = { | |
1776 | AUDIO_CLKC_MARK, | |
1777 | }; | |
1778 | static const unsigned int audio_clkout_pins[] = { | |
1779 | /* CLK OUT */ | |
1780 | RCAR_GP_PIN(5, 16), | |
1781 | }; | |
1782 | static const unsigned int audio_clkout_mux[] = { | |
1783 | AUDIO_CLKOUT_MARK, | |
1784 | }; | |
1785 | static const unsigned int audio_clkout_b_pins[] = { | |
1786 | /* CLK OUT B */ | |
1787 | RCAR_GP_PIN(0, 23), | |
1788 | }; | |
1789 | static const unsigned int audio_clkout_b_mux[] = { | |
1790 | AUDIO_CLKOUT_B_MARK, | |
1791 | }; | |
1792 | static const unsigned int audio_clkout_c_pins[] = { | |
1793 | /* CLK OUT C */ | |
1794 | RCAR_GP_PIN(5, 27), | |
1795 | }; | |
1796 | static const unsigned int audio_clkout_c_mux[] = { | |
1797 | AUDIO_CLKOUT_C_MARK, | |
1798 | }; | |
1799 | static const unsigned int audio_clkout_d_pins[] = { | |
1800 | /* CLK OUT D */ | |
1801 | RCAR_GP_PIN(5, 20), | |
1802 | }; | |
1803 | static const unsigned int audio_clkout_d_mux[] = { | |
1804 | AUDIO_CLKOUT_D_MARK, | |
1805 | }; | |
19ef697d SS |
1806 | /* - AVB -------------------------------------------------------------------- */ |
1807 | static const unsigned int avb_link_pins[] = { | |
1808 | RCAR_GP_PIN(3, 11), | |
1809 | }; | |
1810 | static const unsigned int avb_link_mux[] = { | |
1811 | AVB_LINK_MARK, | |
1812 | }; | |
1813 | static const unsigned int avb_magic_pins[] = { | |
1814 | RCAR_GP_PIN(2, 14), | |
1815 | }; | |
1816 | static const unsigned int avb_magic_mux[] = { | |
1817 | AVB_MAGIC_MARK, | |
1818 | }; | |
1819 | static const unsigned int avb_phy_int_pins[] = { | |
1820 | RCAR_GP_PIN(2, 15), | |
1821 | }; | |
1822 | static const unsigned int avb_phy_int_mux[] = { | |
1823 | AVB_PHY_INT_MARK, | |
1824 | }; | |
1825 | static const unsigned int avb_mdio_pins[] = { | |
1826 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
1827 | }; | |
1828 | static const unsigned int avb_mdio_mux[] = { | |
1829 | AVB_MDC_MARK, AVB_MDIO_MARK, | |
1830 | }; | |
1831 | static const unsigned int avb_mii_pins[] = { | |
1832 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
1833 | RCAR_GP_PIN(0, 11), | |
1834 | ||
1835 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | |
1836 | RCAR_GP_PIN(2, 2), | |
1837 | ||
1838 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), | |
1839 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10), | |
1840 | RCAR_GP_PIN(3, 12), | |
1841 | }; | |
1842 | static const unsigned int avb_mii_mux[] = { | |
1843 | AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, | |
1844 | AVB_TXD3_MARK, | |
1845 | ||
1846 | AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, | |
1847 | AVB_RXD3_MARK, | |
1848 | ||
1849 | AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, | |
1850 | AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK, | |
1851 | AVB_COL_MARK, | |
1852 | }; | |
1853 | static const unsigned int avb_gmii_pins[] = { | |
1854 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
1855 | RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
1856 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
1857 | ||
1858 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1), | |
1859 | RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), | |
1860 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
1861 | ||
1862 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), | |
1863 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16), | |
1864 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10), | |
1865 | RCAR_GP_PIN(3, 12), | |
1866 | }; | |
1867 | static const unsigned int avb_gmii_mux[] = { | |
1868 | AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK, | |
1869 | AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK, | |
1870 | AVB_TXD6_MARK, AVB_TXD7_MARK, | |
1871 | ||
1872 | AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK, | |
1873 | AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, | |
1874 | AVB_RXD6_MARK, AVB_RXD7_MARK, | |
1875 | ||
1876 | AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK, | |
1877 | AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, | |
1878 | AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, | |
1879 | AVB_COL_MARK, | |
1880 | }; | |
62783b71 LP |
1881 | /* - DU RGB ----------------------------------------------------------------- */ |
1882 | static const unsigned int du_rgb666_pins[] = { | |
1883 | /* R[7:2], G[7:2], B[7:2] */ | |
1884 | RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), | |
1885 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), | |
1886 | RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), | |
1887 | RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), | |
1888 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11), | |
1889 | RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8), | |
1890 | }; | |
1891 | static const unsigned int du_rgb666_mux[] = { | |
1892 | DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, | |
1893 | DU2_DR3_MARK, DU2_DR2_MARK, | |
1894 | DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, | |
1895 | DU2_DG3_MARK, DU2_DG2_MARK, | |
1896 | DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, | |
1897 | DU2_DB3_MARK, DU2_DB2_MARK, | |
1898 | }; | |
1899 | static const unsigned int du_rgb888_pins[] = { | |
1900 | /* R[7:0], G[7:0], B[7:0] */ | |
1901 | RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), | |
1902 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), | |
1903 | RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4), | |
1904 | RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7), | |
1905 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1), | |
1906 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), | |
1907 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), | |
1908 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), | |
1909 | }; | |
1910 | static const unsigned int du_rgb888_mux[] = { | |
1911 | DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK, | |
1912 | DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK, | |
1913 | DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK, | |
1914 | DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK, | |
1915 | DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK, | |
1916 | DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK, | |
1917 | }; | |
1918 | static const unsigned int du_clk_out_0_pins[] = { | |
1919 | /* CLKOUT */ | |
1920 | RCAR_GP_PIN(5, 2), | |
1921 | }; | |
1922 | static const unsigned int du_clk_out_0_mux[] = { | |
1923 | DU0_DOTCLKOUT_MARK | |
1924 | }; | |
1925 | static const unsigned int du_clk_out_1_pins[] = { | |
1926 | /* CLKOUT */ | |
1927 | RCAR_GP_PIN(5, 3), | |
1928 | }; | |
1929 | static const unsigned int du_clk_out_1_mux[] = { | |
1930 | DU1_DOTCLKOUT_MARK | |
1931 | }; | |
1932 | static const unsigned int du_sync_0_pins[] = { | |
1933 | /* VSYNC, HSYNC, DISP */ | |
1934 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0), | |
1935 | }; | |
1936 | static const unsigned int du_sync_0_mux[] = { | |
1937 | DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, | |
1938 | DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK | |
1939 | }; | |
1940 | static const unsigned int du_sync_1_pins[] = { | |
1941 | /* VSYNC, HSYNC, DISP */ | |
1942 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16), | |
1943 | }; | |
1944 | static const unsigned int du_sync_1_mux[] = { | |
1945 | DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, | |
1946 | DU2_DISP_MARK | |
1947 | }; | |
1948 | static const unsigned int du_cde_pins[] = { | |
1949 | /* CDE */ | |
1950 | RCAR_GP_PIN(5, 17), | |
1951 | }; | |
1952 | static const unsigned int du_cde_mux[] = { | |
1953 | DU2_CDE_MARK, | |
1954 | }; | |
1955 | /* - DU0 -------------------------------------------------------------------- */ | |
1956 | static const unsigned int du0_clk_in_pins[] = { | |
1957 | /* CLKIN */ | |
1958 | RCAR_GP_PIN(5, 26), | |
1959 | }; | |
1960 | static const unsigned int du0_clk_in_mux[] = { | |
1961 | DU_DOTCLKIN0_MARK | |
1962 | }; | |
1963 | /* - DU1 -------------------------------------------------------------------- */ | |
1964 | static const unsigned int du1_clk_in_pins[] = { | |
1965 | /* CLKIN */ | |
1966 | RCAR_GP_PIN(5, 27), | |
1967 | }; | |
1968 | static const unsigned int du1_clk_in_mux[] = { | |
1969 | DU_DOTCLKIN1_MARK, | |
1970 | }; | |
1971 | /* - DU2 -------------------------------------------------------------------- */ | |
1972 | static const unsigned int du2_clk_in_pins[] = { | |
1973 | /* CLKIN */ | |
1974 | RCAR_GP_PIN(5, 28), | |
1975 | }; | |
1976 | static const unsigned int du2_clk_in_mux[] = { | |
1977 | DU_DOTCLKIN2_MARK, | |
1978 | }; | |
1627769b LP |
1979 | /* - ETH -------------------------------------------------------------------- */ |
1980 | static const unsigned int eth_link_pins[] = { | |
1981 | /* LINK */ | |
1982 | RCAR_GP_PIN(2, 22), | |
1983 | }; | |
1984 | static const unsigned int eth_link_mux[] = { | |
1985 | ETH_LINK_MARK, | |
1986 | }; | |
1987 | static const unsigned int eth_magic_pins[] = { | |
1988 | /* MAGIC */ | |
1989 | RCAR_GP_PIN(2, 27), | |
1990 | }; | |
1991 | static const unsigned int eth_magic_mux[] = { | |
1992 | ETH_MAGIC_MARK, | |
1993 | }; | |
1994 | static const unsigned int eth_mdio_pins[] = { | |
1995 | /* MDC, MDIO */ | |
1996 | RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24), | |
1997 | }; | |
1998 | static const unsigned int eth_mdio_mux[] = { | |
1999 | ETH_MDC_MARK, ETH_MDIO_MARK, | |
2000 | }; | |
2001 | static const unsigned int eth_rmii_pins[] = { | |
2002 | /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */ | |
2003 | RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19), | |
2004 | RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25), | |
2005 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23), | |
2006 | }; | |
2007 | static const unsigned int eth_rmii_mux[] = { | |
2008 | ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, | |
2009 | ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK, | |
2010 | }; | |
fbd0ca3d UH |
2011 | /* - HSCIF0 ----------------------------------------------------------------- */ |
2012 | static const unsigned int hscif0_data_pins[] = { | |
2013 | /* RX, TX */ | |
2014 | RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9), | |
2015 | }; | |
2016 | static const unsigned int hscif0_data_mux[] = { | |
2017 | HRX0_MARK, HTX0_MARK, | |
2018 | }; | |
2019 | static const unsigned int hscif0_clk_pins[] = { | |
2020 | /* SCK */ | |
2021 | RCAR_GP_PIN(5, 7), | |
2022 | }; | |
2023 | static const unsigned int hscif0_clk_mux[] = { | |
2024 | HSCK0_MARK, | |
2025 | }; | |
2026 | static const unsigned int hscif0_ctrl_pins[] = { | |
2027 | /* RTS, CTS */ | |
2028 | RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), | |
2029 | }; | |
2030 | static const unsigned int hscif0_ctrl_mux[] = { | |
2031 | HRTS0_N_MARK, HCTS0_N_MARK, | |
2032 | }; | |
2033 | static const unsigned int hscif0_data_b_pins[] = { | |
2034 | /* RX, TX */ | |
2035 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12), | |
2036 | }; | |
2037 | static const unsigned int hscif0_data_b_mux[] = { | |
2038 | HRX0_B_MARK, HTX0_B_MARK, | |
2039 | }; | |
2040 | static const unsigned int hscif0_ctrl_b_pins[] = { | |
2041 | /* RTS, CTS */ | |
2042 | RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), | |
2043 | }; | |
2044 | static const unsigned int hscif0_ctrl_b_mux[] = { | |
2045 | HRTS0_N_B_MARK, HCTS0_N_B_MARK, | |
2046 | }; | |
2047 | static const unsigned int hscif0_data_c_pins[] = { | |
2048 | /* RX, TX */ | |
2049 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), | |
2050 | }; | |
2051 | static const unsigned int hscif0_data_c_mux[] = { | |
2052 | HRX0_C_MARK, HTX0_C_MARK, | |
2053 | }; | |
2054 | static const unsigned int hscif0_ctrl_c_pins[] = { | |
2055 | /* RTS, CTS */ | |
2056 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7), | |
2057 | }; | |
2058 | static const unsigned int hscif0_ctrl_c_mux[] = { | |
2059 | HRTS0_N_C_MARK, HCTS0_N_C_MARK, | |
2060 | }; | |
2061 | static const unsigned int hscif0_data_d_pins[] = { | |
2062 | /* RX, TX */ | |
2063 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2064 | }; | |
2065 | static const unsigned int hscif0_data_d_mux[] = { | |
2066 | HRX0_D_MARK, HTX0_D_MARK, | |
2067 | }; | |
2068 | static const unsigned int hscif0_ctrl_d_pins[] = { | |
2069 | /* RTS, CTS */ | |
2070 | RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), | |
2071 | }; | |
2072 | static const unsigned int hscif0_ctrl_d_mux[] = { | |
2073 | HRTS0_N_D_MARK, HCTS0_N_D_MARK, | |
2074 | }; | |
2075 | static const unsigned int hscif0_data_e_pins[] = { | |
2076 | /* RX, TX */ | |
2077 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
2078 | }; | |
2079 | static const unsigned int hscif0_data_e_mux[] = { | |
2080 | HRX0_E_MARK, HTX0_E_MARK, | |
2081 | }; | |
2082 | static const unsigned int hscif0_ctrl_e_pins[] = { | |
2083 | /* RTS, CTS */ | |
2084 | RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23), | |
2085 | }; | |
2086 | static const unsigned int hscif0_ctrl_e_mux[] = { | |
2087 | HRTS0_N_E_MARK, HCTS0_N_E_MARK, | |
2088 | }; | |
2089 | static const unsigned int hscif0_data_f_pins[] = { | |
2090 | /* RX, TX */ | |
2091 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25), | |
2092 | }; | |
2093 | static const unsigned int hscif0_data_f_mux[] = { | |
2094 | HRX0_F_MARK, HTX0_F_MARK, | |
2095 | }; | |
2096 | static const unsigned int hscif0_ctrl_f_pins[] = { | |
2097 | /* RTS, CTS */ | |
2098 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24), | |
2099 | }; | |
2100 | static const unsigned int hscif0_ctrl_f_mux[] = { | |
2101 | HRTS0_N_F_MARK, HCTS0_N_F_MARK, | |
2102 | }; | |
2103 | /* - HSCIF1 ----------------------------------------------------------------- */ | |
2104 | static const unsigned int hscif1_data_pins[] = { | |
2105 | /* RX, TX */ | |
2106 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2107 | }; | |
2108 | static const unsigned int hscif1_data_mux[] = { | |
2109 | HRX1_MARK, HTX1_MARK, | |
2110 | }; | |
2111 | static const unsigned int hscif1_clk_pins[] = { | |
2112 | /* SCK */ | |
2113 | RCAR_GP_PIN(4, 27), | |
2114 | }; | |
2115 | static const unsigned int hscif1_clk_mux[] = { | |
2116 | HSCK1_MARK, | |
2117 | }; | |
2118 | static const unsigned int hscif1_ctrl_pins[] = { | |
2119 | /* RTS, CTS */ | |
2120 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
2121 | }; | |
2122 | static const unsigned int hscif1_ctrl_mux[] = { | |
2123 | HRTS1_N_MARK, HCTS1_N_MARK, | |
2124 | }; | |
2125 | static const unsigned int hscif1_data_b_pins[] = { | |
2126 | /* RX, TX */ | |
2127 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18), | |
2128 | }; | |
2129 | static const unsigned int hscif1_data_b_mux[] = { | |
2130 | HRX1_B_MARK, HTX1_B_MARK, | |
2131 | }; | |
2132 | static const unsigned int hscif1_clk_b_pins[] = { | |
2133 | /* SCK */ | |
2134 | RCAR_GP_PIN(1, 28), | |
2135 | }; | |
2136 | static const unsigned int hscif1_clk_b_mux[] = { | |
2137 | HSCK1_B_MARK, | |
2138 | }; | |
2139 | static const unsigned int hscif1_ctrl_b_pins[] = { | |
2140 | /* RTS, CTS */ | |
2141 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), | |
2142 | }; | |
2143 | static const unsigned int hscif1_ctrl_b_mux[] = { | |
2144 | HRTS1_N_B_MARK, HCTS1_N_B_MARK, | |
2145 | }; | |
35a493de WS |
2146 | /* - I2C0 ------------------------------------------------------------------- */ |
2147 | static const unsigned int i2c0_pins[] = { | |
2148 | /* SCL, SDA */ | |
2149 | PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), | |
2150 | }; | |
2151 | static const unsigned int i2c0_mux[] = { | |
2152 | I2C0_SCL_MARK, I2C0_SDA_MARK, | |
2153 | }; | |
70702bfc UH |
2154 | /* - I2C1 ------------------------------------------------------------------- */ |
2155 | static const unsigned int i2c1_pins[] = { | |
2156 | /* SCL, SDA */ | |
2157 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
2158 | }; | |
2159 | static const unsigned int i2c1_mux[] = { | |
2160 | I2C1_SCL_MARK, I2C1_SDA_MARK, | |
2161 | }; | |
2162 | static const unsigned int i2c1_b_pins[] = { | |
2163 | /* SCL, SDA */ | |
2164 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
2165 | }; | |
2166 | static const unsigned int i2c1_b_mux[] = { | |
2167 | I2C1_SCL_B_MARK, I2C1_SDA_B_MARK, | |
2168 | }; | |
2169 | static const unsigned int i2c1_c_pins[] = { | |
2170 | /* SCL, SDA */ | |
2171 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), | |
2172 | }; | |
2173 | static const unsigned int i2c1_c_mux[] = { | |
2174 | I2C1_SCL_C_MARK, I2C1_SDA_C_MARK, | |
2175 | }; | |
2176 | /* - I2C2 ------------------------------------------------------------------- */ | |
2177 | static const unsigned int i2c2_pins[] = { | |
2178 | /* SCL, SDA */ | |
2179 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2180 | }; | |
2181 | static const unsigned int i2c2_mux[] = { | |
2182 | I2C2_SCL_MARK, I2C2_SDA_MARK, | |
2183 | }; | |
2184 | static const unsigned int i2c2_b_pins[] = { | |
2185 | /* SCL, SDA */ | |
2186 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
2187 | }; | |
2188 | static const unsigned int i2c2_b_mux[] = { | |
2189 | I2C2_SCL_B_MARK, I2C2_SDA_B_MARK, | |
2190 | }; | |
2191 | static const unsigned int i2c2_c_pins[] = { | |
2192 | /* SCL, SDA */ | |
2193 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | |
2194 | }; | |
2195 | static const unsigned int i2c2_c_mux[] = { | |
2196 | I2C2_SCL_C_MARK, I2C2_SDA_C_MARK, | |
2197 | }; | |
2198 | static const unsigned int i2c2_d_pins[] = { | |
2199 | /* SCL, SDA */ | |
2200 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | |
2201 | }; | |
2202 | static const unsigned int i2c2_d_mux[] = { | |
2203 | I2C2_SCL_D_MARK, I2C2_SDA_D_MARK, | |
2204 | }; | |
2205 | static const unsigned int i2c2_e_pins[] = { | |
2206 | /* SCL, SDA */ | |
2207 | RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), | |
2208 | }; | |
2209 | static const unsigned int i2c2_e_mux[] = { | |
2210 | I2C2_SCL_E_MARK, I2C2_SDA_E_MARK, | |
2211 | }; | |
f6aaaac9 GL |
2212 | /* - I2C3 ------------------------------------------------------------------- */ |
2213 | static const unsigned int i2c3_pins[] = { | |
2214 | /* SCL, SDA */ | |
2215 | PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), | |
2216 | }; | |
2217 | static const unsigned int i2c3_mux[] = { | |
2218 | I2C3_SCL_MARK, I2C3_SDA_MARK, | |
2219 | }; | |
a16b81dc WS |
2220 | /* - IIC0 (I2C4) ------------------------------------------------------------ */ |
2221 | static const unsigned int iic0_pins[] = { | |
2222 | /* SCL, SDA */ | |
2223 | PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15), | |
2224 | }; | |
2225 | static const unsigned int iic0_mux[] = { | |
2226 | IIC0_SCL_MARK, IIC0_SDA_MARK, | |
2227 | }; | |
2228 | /* - IIC1 (I2C5) ------------------------------------------------------------ */ | |
2229 | static const unsigned int iic1_pins[] = { | |
2230 | /* SCL, SDA */ | |
2231 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), | |
2232 | }; | |
2233 | static const unsigned int iic1_mux[] = { | |
2234 | IIC1_SCL_MARK, IIC1_SDA_MARK, | |
2235 | }; | |
2236 | static const unsigned int iic1_b_pins[] = { | |
2237 | /* SCL, SDA */ | |
2238 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
2239 | }; | |
2240 | static const unsigned int iic1_b_mux[] = { | |
2241 | IIC1_SCL_B_MARK, IIC1_SDA_B_MARK, | |
2242 | }; | |
2243 | static const unsigned int iic1_c_pins[] = { | |
2244 | /* SCL, SDA */ | |
2245 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), | |
2246 | }; | |
2247 | static const unsigned int iic1_c_mux[] = { | |
2248 | IIC1_SCL_C_MARK, IIC1_SDA_C_MARK, | |
2249 | }; | |
2250 | /* - IIC2 (I2C6) ------------------------------------------------------------ */ | |
2251 | static const unsigned int iic2_pins[] = { | |
2252 | /* SCL, SDA */ | |
2253 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2254 | }; | |
2255 | static const unsigned int iic2_mux[] = { | |
2256 | IIC2_SCL_MARK, IIC2_SDA_MARK, | |
2257 | }; | |
2258 | static const unsigned int iic2_b_pins[] = { | |
2259 | /* SCL, SDA */ | |
2260 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), | |
2261 | }; | |
2262 | static const unsigned int iic2_b_mux[] = { | |
2263 | IIC2_SCL_B_MARK, IIC2_SDA_B_MARK, | |
2264 | }; | |
2265 | static const unsigned int iic2_c_pins[] = { | |
2266 | /* SCL, SDA */ | |
2267 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | |
2268 | }; | |
2269 | static const unsigned int iic2_c_mux[] = { | |
2270 | IIC2_SCL_C_MARK, IIC2_SDA_C_MARK, | |
2271 | }; | |
2272 | static const unsigned int iic2_d_pins[] = { | |
2273 | /* SCL, SDA */ | |
2274 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | |
2275 | }; | |
2276 | static const unsigned int iic2_d_mux[] = { | |
2277 | IIC2_SCL_D_MARK, IIC2_SDA_D_MARK, | |
2278 | }; | |
2279 | static const unsigned int iic2_e_pins[] = { | |
2280 | /* SCL, SDA */ | |
2281 | RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19), | |
2282 | }; | |
2283 | static const unsigned int iic2_e_mux[] = { | |
2284 | IIC2_SCL_E_MARK, IIC2_SDA_E_MARK, | |
2285 | }; | |
2286 | /* - IIC3 (I2C7) ------------------------------------------------------------ */ | |
2287 | static const unsigned int iic3_pins[] = { | |
2288 | /* SCL, SDA */ | |
2289 | PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15), | |
2290 | }; | |
2291 | static const unsigned int iic3_mux[] = { | |
2292 | IIC3_SCL_MARK, IIC3_SDA_MARK, | |
2293 | }; | |
457c11d3 LP |
2294 | /* - INTC ------------------------------------------------------------------- */ |
2295 | static const unsigned int intc_irq0_pins[] = { | |
2296 | /* IRQ */ | |
2297 | RCAR_GP_PIN(1, 25), | |
2298 | }; | |
2299 | static const unsigned int intc_irq0_mux[] = { | |
2300 | IRQ0_MARK, | |
2301 | }; | |
2302 | static const unsigned int intc_irq1_pins[] = { | |
2303 | /* IRQ */ | |
2304 | RCAR_GP_PIN(1, 27), | |
2305 | }; | |
2306 | static const unsigned int intc_irq1_mux[] = { | |
2307 | IRQ1_MARK, | |
2308 | }; | |
2309 | static const unsigned int intc_irq2_pins[] = { | |
2310 | /* IRQ */ | |
2311 | RCAR_GP_PIN(1, 29), | |
2312 | }; | |
2313 | static const unsigned int intc_irq2_mux[] = { | |
2314 | IRQ2_MARK, | |
2315 | }; | |
2316 | static const unsigned int intc_irq3_pins[] = { | |
2317 | /* IRQ */ | |
2318 | RCAR_GP_PIN(1, 23), | |
2319 | }; | |
2320 | static const unsigned int intc_irq3_mux[] = { | |
2321 | IRQ3_MARK, | |
2322 | }; | |
e29a4c3a SS |
2323 | /* - MLB+ ------------------------------------------------------------------- */ |
2324 | static const unsigned int mlb_3pin_pins[] = { | |
2325 | RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
2326 | }; | |
2327 | static const unsigned int mlb_3pin_mux[] = { | |
2328 | MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, | |
2329 | }; | |
457c11d3 LP |
2330 | /* - MMCIF0 ----------------------------------------------------------------- */ |
2331 | static const unsigned int mmc0_data1_pins[] = { | |
2332 | /* D[0] */ | |
2333 | RCAR_GP_PIN(3, 18), | |
2334 | }; | |
2335 | static const unsigned int mmc0_data1_mux[] = { | |
2336 | MMC0_D0_MARK, | |
2337 | }; | |
2338 | static const unsigned int mmc0_data4_pins[] = { | |
2339 | /* D[0:3] */ | |
2340 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
2341 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2342 | }; | |
2343 | static const unsigned int mmc0_data4_mux[] = { | |
2344 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | |
2345 | }; | |
2346 | static const unsigned int mmc0_data8_pins[] = { | |
2347 | /* D[0:7] */ | |
2348 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
2349 | RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
2350 | RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23), | |
2351 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), | |
2352 | }; | |
2353 | static const unsigned int mmc0_data8_mux[] = { | |
2354 | MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK, | |
2355 | MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK, | |
2356 | }; | |
2357 | static const unsigned int mmc0_ctrl_pins[] = { | |
2358 | /* CLK, CMD */ | |
2359 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | |
2360 | }; | |
2361 | static const unsigned int mmc0_ctrl_mux[] = { | |
2362 | MMC0_CLK_MARK, MMC0_CMD_MARK, | |
2363 | }; | |
2364 | /* - MMCIF1 ----------------------------------------------------------------- */ | |
2365 | static const unsigned int mmc1_data1_pins[] = { | |
2366 | /* D[0] */ | |
2367 | RCAR_GP_PIN(3, 26), | |
2368 | }; | |
2369 | static const unsigned int mmc1_data1_mux[] = { | |
2370 | MMC1_D0_MARK, | |
2371 | }; | |
2372 | static const unsigned int mmc1_data4_pins[] = { | |
2373 | /* D[0:3] */ | |
2374 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | |
2375 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
2376 | }; | |
2377 | static const unsigned int mmc1_data4_mux[] = { | |
2378 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | |
2379 | }; | |
2380 | static const unsigned int mmc1_data8_pins[] = { | |
2381 | /* D[0:7] */ | |
2382 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), | |
2383 | RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
2384 | RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31), | |
2385 | RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), | |
2386 | }; | |
2387 | static const unsigned int mmc1_data8_mux[] = { | |
2388 | MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK, | |
2389 | MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK, | |
2390 | }; | |
2391 | static const unsigned int mmc1_ctrl_pins[] = { | |
2392 | /* CLK, CMD */ | |
2393 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | |
2394 | }; | |
2395 | static const unsigned int mmc1_ctrl_mux[] = { | |
2396 | MMC1_CLK_MARK, MMC1_CMD_MARK, | |
2397 | }; | |
4f47cc5e KH |
2398 | /* - MSIOF0 ----------------------------------------------------------------- */ |
2399 | static const unsigned int msiof0_clk_pins[] = { | |
2400 | /* SCK */ | |
2401 | RCAR_GP_PIN(5, 12), | |
2402 | }; | |
2403 | static const unsigned int msiof0_clk_mux[] = { | |
2404 | MSIOF0_SCK_MARK, | |
2405 | }; | |
2406 | static const unsigned int msiof0_sync_pins[] = { | |
2407 | /* SYNC */ | |
2408 | RCAR_GP_PIN(5, 13), | |
2409 | }; | |
2410 | static const unsigned int msiof0_sync_mux[] = { | |
2411 | MSIOF0_SYNC_MARK, | |
2412 | }; | |
2413 | static const unsigned int msiof0_ss1_pins[] = { | |
2414 | /* SS1 */ | |
2415 | RCAR_GP_PIN(5, 14), | |
2416 | }; | |
2417 | static const unsigned int msiof0_ss1_mux[] = { | |
2418 | MSIOF0_SS1_MARK, | |
2419 | }; | |
2420 | static const unsigned int msiof0_ss2_pins[] = { | |
2421 | /* SS2 */ | |
2422 | RCAR_GP_PIN(5, 16), | |
2423 | }; | |
2424 | static const unsigned int msiof0_ss2_mux[] = { | |
2425 | MSIOF0_SS2_MARK, | |
2426 | }; | |
2427 | static const unsigned int msiof0_rx_pins[] = { | |
2428 | /* RXD */ | |
2429 | RCAR_GP_PIN(5, 17), | |
2430 | }; | |
2431 | static const unsigned int msiof0_rx_mux[] = { | |
2432 | MSIOF0_RXD_MARK, | |
2433 | }; | |
2434 | static const unsigned int msiof0_tx_pins[] = { | |
2435 | /* TXD */ | |
2436 | RCAR_GP_PIN(5, 15), | |
2437 | }; | |
2438 | static const unsigned int msiof0_tx_mux[] = { | |
2439 | MSIOF0_TXD_MARK, | |
2440 | }; | |
7033168d GU |
2441 | |
2442 | static const unsigned int msiof0_clk_b_pins[] = { | |
2443 | /* SCK */ | |
2444 | RCAR_GP_PIN(1, 23), | |
2445 | }; | |
2446 | static const unsigned int msiof0_clk_b_mux[] = { | |
2447 | MSIOF0_SCK_B_MARK, | |
2448 | }; | |
2449 | static const unsigned int msiof0_ss1_b_pins[] = { | |
2450 | /* SS1 */ | |
2451 | RCAR_GP_PIN(1, 12), | |
2452 | }; | |
2453 | static const unsigned int msiof0_ss1_b_mux[] = { | |
2454 | MSIOF0_SS1_B_MARK, | |
2455 | }; | |
2456 | static const unsigned int msiof0_ss2_b_pins[] = { | |
2457 | /* SS2 */ | |
2458 | RCAR_GP_PIN(1, 10), | |
2459 | }; | |
2460 | static const unsigned int msiof0_ss2_b_mux[] = { | |
2461 | MSIOF0_SS2_B_MARK, | |
2462 | }; | |
2463 | static const unsigned int msiof0_rx_b_pins[] = { | |
2464 | /* RXD */ | |
2465 | RCAR_GP_PIN(1, 29), | |
2466 | }; | |
2467 | static const unsigned int msiof0_rx_b_mux[] = { | |
2468 | MSIOF0_RXD_B_MARK, | |
2469 | }; | |
2470 | static const unsigned int msiof0_tx_b_pins[] = { | |
2471 | /* TXD */ | |
2472 | RCAR_GP_PIN(1, 28), | |
2473 | }; | |
2474 | static const unsigned int msiof0_tx_b_mux[] = { | |
2475 | MSIOF0_TXD_B_MARK, | |
2476 | }; | |
4f47cc5e KH |
2477 | /* - MSIOF1 ----------------------------------------------------------------- */ |
2478 | static const unsigned int msiof1_clk_pins[] = { | |
2479 | /* SCK */ | |
2480 | RCAR_GP_PIN(4, 8), | |
2481 | }; | |
2482 | static const unsigned int msiof1_clk_mux[] = { | |
2483 | MSIOF1_SCK_MARK, | |
2484 | }; | |
2485 | static const unsigned int msiof1_sync_pins[] = { | |
2486 | /* SYNC */ | |
2487 | RCAR_GP_PIN(4, 9), | |
2488 | }; | |
2489 | static const unsigned int msiof1_sync_mux[] = { | |
2490 | MSIOF1_SYNC_MARK, | |
2491 | }; | |
2492 | static const unsigned int msiof1_ss1_pins[] = { | |
2493 | /* SS1 */ | |
2494 | RCAR_GP_PIN(4, 10), | |
2495 | }; | |
2496 | static const unsigned int msiof1_ss1_mux[] = { | |
2497 | MSIOF1_SS1_MARK, | |
2498 | }; | |
2499 | static const unsigned int msiof1_ss2_pins[] = { | |
2500 | /* SS2 */ | |
2501 | RCAR_GP_PIN(4, 11), | |
2502 | }; | |
2503 | static const unsigned int msiof1_ss2_mux[] = { | |
2504 | MSIOF1_SS2_MARK, | |
2505 | }; | |
2506 | static const unsigned int msiof1_rx_pins[] = { | |
2507 | /* RXD */ | |
2508 | RCAR_GP_PIN(4, 13), | |
2509 | }; | |
2510 | static const unsigned int msiof1_rx_mux[] = { | |
2511 | MSIOF1_RXD_MARK, | |
2512 | }; | |
2513 | static const unsigned int msiof1_tx_pins[] = { | |
2514 | /* TXD */ | |
2515 | RCAR_GP_PIN(4, 12), | |
2516 | }; | |
2517 | static const unsigned int msiof1_tx_mux[] = { | |
2518 | MSIOF1_TXD_MARK, | |
2519 | }; | |
7033168d GU |
2520 | |
2521 | static const unsigned int msiof1_clk_b_pins[] = { | |
2522 | /* SCK */ | |
2523 | RCAR_GP_PIN(1, 16), | |
2524 | }; | |
2525 | static const unsigned int msiof1_clk_b_mux[] = { | |
2526 | MSIOF1_SCK_B_MARK, | |
2527 | }; | |
2528 | static const unsigned int msiof1_ss1_b_pins[] = { | |
2529 | /* SS1 */ | |
2530 | RCAR_GP_PIN(0, 18), | |
2531 | }; | |
2532 | static const unsigned int msiof1_ss1_b_mux[] = { | |
2533 | MSIOF1_SS1_B_MARK, | |
2534 | }; | |
2535 | static const unsigned int msiof1_ss2_b_pins[] = { | |
2536 | /* SS2 */ | |
2537 | RCAR_GP_PIN(0, 19), | |
2538 | }; | |
2539 | static const unsigned int msiof1_ss2_b_mux[] = { | |
2540 | MSIOF1_SS2_B_MARK, | |
2541 | }; | |
2542 | static const unsigned int msiof1_rx_b_pins[] = { | |
2543 | /* RXD */ | |
2544 | RCAR_GP_PIN(1, 17), | |
2545 | }; | |
2546 | static const unsigned int msiof1_rx_b_mux[] = { | |
2547 | MSIOF1_RXD_B_MARK, | |
2548 | }; | |
2549 | static const unsigned int msiof1_tx_b_pins[] = { | |
2550 | /* TXD */ | |
2551 | RCAR_GP_PIN(0, 20), | |
2552 | }; | |
2553 | static const unsigned int msiof1_tx_b_mux[] = { | |
2554 | MSIOF1_TXD_B_MARK, | |
2555 | }; | |
4f47cc5e KH |
2556 | /* - MSIOF2 ----------------------------------------------------------------- */ |
2557 | static const unsigned int msiof2_clk_pins[] = { | |
2558 | /* SCK */ | |
2559 | RCAR_GP_PIN(0, 27), | |
2560 | }; | |
2561 | static const unsigned int msiof2_clk_mux[] = { | |
2562 | MSIOF2_SCK_MARK, | |
2563 | }; | |
2564 | static const unsigned int msiof2_sync_pins[] = { | |
2565 | /* SYNC */ | |
2566 | RCAR_GP_PIN(0, 26), | |
2567 | }; | |
2568 | static const unsigned int msiof2_sync_mux[] = { | |
2569 | MSIOF2_SYNC_MARK, | |
2570 | }; | |
2571 | static const unsigned int msiof2_ss1_pins[] = { | |
2572 | /* SS1 */ | |
2573 | RCAR_GP_PIN(0, 30), | |
2574 | }; | |
2575 | static const unsigned int msiof2_ss1_mux[] = { | |
2576 | MSIOF2_SS1_MARK, | |
2577 | }; | |
2578 | static const unsigned int msiof2_ss2_pins[] = { | |
2579 | /* SS2 */ | |
2580 | RCAR_GP_PIN(0, 31), | |
2581 | }; | |
2582 | static const unsigned int msiof2_ss2_mux[] = { | |
2583 | MSIOF2_SS2_MARK, | |
2584 | }; | |
2585 | static const unsigned int msiof2_rx_pins[] = { | |
2586 | /* RXD */ | |
2587 | RCAR_GP_PIN(0, 29), | |
2588 | }; | |
2589 | static const unsigned int msiof2_rx_mux[] = { | |
2590 | MSIOF2_RXD_MARK, | |
2591 | }; | |
2592 | static const unsigned int msiof2_tx_pins[] = { | |
2593 | /* TXD */ | |
2594 | RCAR_GP_PIN(0, 28), | |
2595 | }; | |
2596 | static const unsigned int msiof2_tx_mux[] = { | |
2597 | MSIOF2_TXD_MARK, | |
2598 | }; | |
2599 | /* - MSIOF3 ----------------------------------------------------------------- */ | |
2600 | static const unsigned int msiof3_clk_pins[] = { | |
2601 | /* SCK */ | |
2602 | RCAR_GP_PIN(5, 4), | |
2603 | }; | |
2604 | static const unsigned int msiof3_clk_mux[] = { | |
2605 | MSIOF3_SCK_MARK, | |
2606 | }; | |
2607 | static const unsigned int msiof3_sync_pins[] = { | |
2608 | /* SYNC */ | |
2609 | RCAR_GP_PIN(4, 30), | |
2610 | }; | |
2611 | static const unsigned int msiof3_sync_mux[] = { | |
2612 | MSIOF3_SYNC_MARK, | |
2613 | }; | |
2614 | static const unsigned int msiof3_ss1_pins[] = { | |
2615 | /* SS1 */ | |
2616 | RCAR_GP_PIN(4, 31), | |
2617 | }; | |
2618 | static const unsigned int msiof3_ss1_mux[] = { | |
2619 | MSIOF3_SS1_MARK, | |
2620 | }; | |
2621 | static const unsigned int msiof3_ss2_pins[] = { | |
2622 | /* SS2 */ | |
2623 | RCAR_GP_PIN(4, 27), | |
2624 | }; | |
2625 | static const unsigned int msiof3_ss2_mux[] = { | |
2626 | MSIOF3_SS2_MARK, | |
2627 | }; | |
2628 | static const unsigned int msiof3_rx_pins[] = { | |
2629 | /* RXD */ | |
2630 | RCAR_GP_PIN(5, 2), | |
2631 | }; | |
2632 | static const unsigned int msiof3_rx_mux[] = { | |
2633 | MSIOF3_RXD_MARK, | |
2634 | }; | |
2635 | static const unsigned int msiof3_tx_pins[] = { | |
2636 | /* TXD */ | |
2637 | RCAR_GP_PIN(5, 3), | |
2638 | }; | |
2639 | static const unsigned int msiof3_tx_mux[] = { | |
2640 | MSIOF3_TXD_MARK, | |
2641 | }; | |
7033168d GU |
2642 | |
2643 | static const unsigned int msiof3_clk_b_pins[] = { | |
2644 | /* SCK */ | |
2645 | RCAR_GP_PIN(0, 0), | |
2646 | }; | |
2647 | static const unsigned int msiof3_clk_b_mux[] = { | |
2648 | MSIOF3_SCK_B_MARK, | |
2649 | }; | |
2650 | static const unsigned int msiof3_sync_b_pins[] = { | |
2651 | /* SYNC */ | |
2652 | RCAR_GP_PIN(0, 1), | |
2653 | }; | |
2654 | static const unsigned int msiof3_sync_b_mux[] = { | |
2655 | MSIOF3_SYNC_B_MARK, | |
2656 | }; | |
2657 | static const unsigned int msiof3_rx_b_pins[] = { | |
2658 | /* RXD */ | |
2659 | RCAR_GP_PIN(0, 2), | |
2660 | }; | |
2661 | static const unsigned int msiof3_rx_b_mux[] = { | |
2662 | MSIOF3_RXD_B_MARK, | |
2663 | }; | |
2664 | static const unsigned int msiof3_tx_b_pins[] = { | |
2665 | /* TXD */ | |
2666 | RCAR_GP_PIN(0, 3), | |
2667 | }; | |
2668 | static const unsigned int msiof3_tx_b_mux[] = { | |
2669 | MSIOF3_TXD_B_MARK, | |
2670 | }; | |
5c89c15b YS |
2671 | /* - PWM -------------------------------------------------------------------- */ |
2672 | static const unsigned int pwm0_pins[] = { | |
2673 | RCAR_GP_PIN(5, 29), | |
2674 | }; | |
2675 | static const unsigned int pwm0_mux[] = { | |
2676 | PWM0_MARK, | |
2677 | }; | |
2678 | static const unsigned int pwm0_b_pins[] = { | |
2679 | RCAR_GP_PIN(4, 30), | |
2680 | }; | |
2681 | static const unsigned int pwm0_b_mux[] = { | |
2682 | PWM0_B_MARK, | |
2683 | }; | |
2684 | static const unsigned int pwm1_pins[] = { | |
2685 | RCAR_GP_PIN(5, 30), | |
2686 | }; | |
2687 | static const unsigned int pwm1_mux[] = { | |
2688 | PWM1_MARK, | |
2689 | }; | |
2690 | static const unsigned int pwm1_b_pins[] = { | |
2691 | RCAR_GP_PIN(4, 31), | |
2692 | }; | |
2693 | static const unsigned int pwm1_b_mux[] = { | |
2694 | PWM1_B_MARK, | |
2695 | }; | |
2696 | static const unsigned int pwm2_pins[] = { | |
2697 | RCAR_GP_PIN(5, 31), | |
2698 | }; | |
2699 | static const unsigned int pwm2_mux[] = { | |
2700 | PWM2_MARK, | |
2701 | }; | |
2702 | static const unsigned int pwm3_pins[] = { | |
2703 | RCAR_GP_PIN(0, 16), | |
2704 | }; | |
2705 | static const unsigned int pwm3_mux[] = { | |
2706 | PWM3_MARK, | |
2707 | }; | |
2708 | static const unsigned int pwm4_pins[] = { | |
2709 | RCAR_GP_PIN(0, 17), | |
2710 | }; | |
2711 | static const unsigned int pwm4_mux[] = { | |
2712 | PWM4_MARK, | |
2713 | }; | |
2714 | static const unsigned int pwm5_pins[] = { | |
2715 | RCAR_GP_PIN(0, 18), | |
2716 | }; | |
2717 | static const unsigned int pwm5_mux[] = { | |
2718 | PWM5_MARK, | |
2719 | }; | |
2720 | static const unsigned int pwm6_pins[] = { | |
2721 | RCAR_GP_PIN(0, 19), | |
2722 | }; | |
2723 | static const unsigned int pwm6_mux[] = { | |
2724 | PWM6_MARK, | |
2725 | }; | |
202909cd GU |
2726 | /* - QSPI ------------------------------------------------------------------- */ |
2727 | static const unsigned int qspi_ctrl_pins[] = { | |
2728 | /* SPCLK, SSL */ | |
2729 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9), | |
2730 | }; | |
2731 | static const unsigned int qspi_ctrl_mux[] = { | |
2732 | SPCLK_MARK, SSL_MARK, | |
2733 | }; | |
2734 | static const unsigned int qspi_data2_pins[] = { | |
2735 | /* MOSI_IO0, MISO_IO1 */ | |
2736 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), | |
2737 | }; | |
2738 | static const unsigned int qspi_data2_mux[] = { | |
2739 | MOSI_IO0_MARK, MISO_IO1_MARK, | |
2740 | }; | |
2741 | static const unsigned int qspi_data4_pins[] = { | |
2742 | /* MOSI_IO0, MISO_IO1, IO2, IO3 */ | |
2743 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
2744 | RCAR_GP_PIN(1, 8), | |
2745 | }; | |
2746 | static const unsigned int qspi_data4_mux[] = { | |
2747 | MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK, | |
2748 | }; | |
457c11d3 LP |
2749 | /* - SCIF0 ------------------------------------------------------------------ */ |
2750 | static const unsigned int scif0_data_pins[] = { | |
2751 | /* RX, TX */ | |
2752 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2753 | }; | |
2754 | static const unsigned int scif0_data_mux[] = { | |
2755 | RX0_MARK, TX0_MARK, | |
2756 | }; | |
2757 | static const unsigned int scif0_clk_pins[] = { | |
2758 | /* SCK */ | |
2759 | RCAR_GP_PIN(4, 27), | |
2760 | }; | |
2761 | static const unsigned int scif0_clk_mux[] = { | |
2762 | SCK0_MARK, | |
2763 | }; | |
2764 | static const unsigned int scif0_ctrl_pins[] = { | |
2765 | /* RTS, CTS */ | |
2766 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
2767 | }; | |
2768 | static const unsigned int scif0_ctrl_mux[] = { | |
2769 | RTS0_N_MARK, CTS0_N_MARK, | |
2770 | }; | |
2771 | static const unsigned int scif0_data_b_pins[] = { | |
2772 | /* RX, TX */ | |
2773 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
2774 | }; | |
2775 | static const unsigned int scif0_data_b_mux[] = { | |
2776 | RX0_B_MARK, TX0_B_MARK, | |
2777 | }; | |
2778 | /* - SCIF1 ------------------------------------------------------------------ */ | |
2779 | static const unsigned int scif1_data_pins[] = { | |
2780 | /* RX, TX */ | |
2781 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | |
2782 | }; | |
2783 | static const unsigned int scif1_data_mux[] = { | |
2784 | RX1_MARK, TX1_MARK, | |
2785 | }; | |
2786 | static const unsigned int scif1_clk_pins[] = { | |
2787 | /* SCK */ | |
2788 | RCAR_GP_PIN(4, 20), | |
2789 | }; | |
2790 | static const unsigned int scif1_clk_mux[] = { | |
2791 | SCK1_MARK, | |
2792 | }; | |
2793 | static const unsigned int scif1_ctrl_pins[] = { | |
2794 | /* RTS, CTS */ | |
2795 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | |
2796 | }; | |
2797 | static const unsigned int scif1_ctrl_mux[] = { | |
2798 | RTS1_N_MARK, CTS1_N_MARK, | |
2799 | }; | |
2800 | static const unsigned int scif1_data_b_pins[] = { | |
2801 | /* RX, TX */ | |
2802 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
2803 | }; | |
2804 | static const unsigned int scif1_data_b_mux[] = { | |
2805 | RX1_B_MARK, TX1_B_MARK, | |
2806 | }; | |
2807 | static const unsigned int scif1_data_c_pins[] = { | |
2808 | /* RX, TX */ | |
2809 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
2810 | }; | |
2811 | static const unsigned int scif1_data_c_mux[] = { | |
2812 | RX1_C_MARK, TX1_C_MARK, | |
fbd0ca3d | 2813 | }; |
457c11d3 | 2814 | static const unsigned int scif1_data_d_pins[] = { |
fbd0ca3d | 2815 | /* RX, TX */ |
457c11d3 | 2816 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), |
fbd0ca3d | 2817 | }; |
457c11d3 LP |
2818 | static const unsigned int scif1_data_d_mux[] = { |
2819 | RX1_D_MARK, TX1_D_MARK, | |
fbd0ca3d | 2820 | }; |
457c11d3 | 2821 | static const unsigned int scif1_clk_d_pins[] = { |
fbd0ca3d | 2822 | /* SCK */ |
457c11d3 | 2823 | RCAR_GP_PIN(3, 17), |
fbd0ca3d | 2824 | }; |
457c11d3 LP |
2825 | static const unsigned int scif1_clk_d_mux[] = { |
2826 | SCK1_D_MARK, | |
fbd0ca3d | 2827 | }; |
457c11d3 LP |
2828 | static const unsigned int scif1_data_e_pins[] = { |
2829 | /* RX, TX */ | |
2830 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
fbd0ca3d | 2831 | }; |
457c11d3 LP |
2832 | static const unsigned int scif1_data_e_mux[] = { |
2833 | RX1_E_MARK, TX1_E_MARK, | |
2834 | }; | |
2835 | static const unsigned int scif1_clk_e_pins[] = { | |
2836 | /* SCK */ | |
2837 | RCAR_GP_PIN(2, 20), | |
2838 | }; | |
2839 | static const unsigned int scif1_clk_e_mux[] = { | |
2840 | SCK1_E_MARK, | |
fbd0ca3d | 2841 | }; |
2dbe7f2c LP |
2842 | /* - SCIF2 ------------------------------------------------------------------ */ |
2843 | static const unsigned int scif2_data_pins[] = { | |
2844 | /* RX, TX */ | |
2845 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5), | |
2846 | }; | |
2847 | static const unsigned int scif2_data_mux[] = { | |
2848 | RX2_MARK, TX2_MARK, | |
2849 | }; | |
2850 | static const unsigned int scif2_clk_pins[] = { | |
2851 | /* SCK */ | |
2852 | RCAR_GP_PIN(5, 4), | |
2853 | }; | |
2854 | static const unsigned int scif2_clk_mux[] = { | |
2855 | SCK2_MARK, | |
2856 | }; | |
2857 | static const unsigned int scif2_data_b_pins[] = { | |
2858 | /* RX, TX */ | |
2859 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
2860 | }; | |
2861 | static const unsigned int scif2_data_b_mux[] = { | |
2862 | RX2_B_MARK, TX2_B_MARK, | |
2863 | }; | |
45c6c85d LP |
2864 | /* - SCIFA0 ----------------------------------------------------------------- */ |
2865 | static const unsigned int scifa0_data_pins[] = { | |
2866 | /* RXD, TXD */ | |
2867 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29), | |
2868 | }; | |
2869 | static const unsigned int scifa0_data_mux[] = { | |
2870 | SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, | |
2871 | }; | |
2872 | static const unsigned int scifa0_clk_pins[] = { | |
2873 | /* SCK */ | |
2874 | RCAR_GP_PIN(4, 27), | |
2875 | }; | |
2876 | static const unsigned int scifa0_clk_mux[] = { | |
2877 | SCIFA0_SCK_MARK, | |
2878 | }; | |
2879 | static const unsigned int scifa0_ctrl_pins[] = { | |
2880 | /* RTS, CTS */ | |
2881 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30), | |
2882 | }; | |
2883 | static const unsigned int scifa0_ctrl_mux[] = { | |
2884 | SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK, | |
2885 | }; | |
2886 | static const unsigned int scifa0_data_b_pins[] = { | |
2887 | /* RXD, TXD */ | |
2888 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21), | |
2889 | }; | |
2890 | static const unsigned int scifa0_data_b_mux[] = { | |
2891 | SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK | |
2892 | }; | |
2893 | static const unsigned int scifa0_clk_b_pins[] = { | |
2894 | /* SCK */ | |
2895 | RCAR_GP_PIN(1, 19), | |
2896 | }; | |
2897 | static const unsigned int scifa0_clk_b_mux[] = { | |
2898 | SCIFA0_SCK_B_MARK, | |
2899 | }; | |
2900 | static const unsigned int scifa0_ctrl_b_pins[] = { | |
2901 | /* RTS, CTS */ | |
2902 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), | |
2903 | }; | |
2904 | static const unsigned int scifa0_ctrl_b_mux[] = { | |
2905 | SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK, | |
2906 | }; | |
2907 | /* - SCIFA1 ----------------------------------------------------------------- */ | |
2908 | static const unsigned int scifa1_data_pins[] = { | |
2909 | /* RXD, TXD */ | |
2910 | RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), | |
2911 | }; | |
2912 | static const unsigned int scifa1_data_mux[] = { | |
2913 | SCIFA1_RXD_MARK, SCIFA1_TXD_MARK, | |
2914 | }; | |
2915 | static const unsigned int scifa1_clk_pins[] = { | |
2916 | /* SCK */ | |
2917 | RCAR_GP_PIN(4, 20), | |
2918 | }; | |
2919 | static const unsigned int scifa1_clk_mux[] = { | |
2920 | SCIFA1_SCK_MARK, | |
2921 | }; | |
2922 | static const unsigned int scifa1_ctrl_pins[] = { | |
2923 | /* RTS, CTS */ | |
2924 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2), | |
2925 | }; | |
2926 | static const unsigned int scifa1_ctrl_mux[] = { | |
2927 | SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK, | |
2928 | }; | |
2929 | static const unsigned int scifa1_data_b_pins[] = { | |
2930 | /* RXD, TXD */ | |
2931 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21), | |
2932 | }; | |
2933 | static const unsigned int scifa1_data_b_mux[] = { | |
2934 | SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK, | |
2935 | }; | |
2936 | static const unsigned int scifa1_clk_b_pins[] = { | |
2937 | /* SCK */ | |
2938 | RCAR_GP_PIN(0, 23), | |
2939 | }; | |
2940 | static const unsigned int scifa1_clk_b_mux[] = { | |
2941 | SCIFA1_SCK_B_MARK, | |
2942 | }; | |
2943 | static const unsigned int scifa1_ctrl_b_pins[] = { | |
2944 | /* RTS, CTS */ | |
2945 | RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25), | |
2946 | }; | |
2947 | static const unsigned int scifa1_ctrl_b_mux[] = { | |
2948 | SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK, | |
2949 | }; | |
2950 | static const unsigned int scifa1_data_c_pins[] = { | |
2951 | /* RXD, TXD */ | |
2952 | RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), | |
2953 | }; | |
2954 | static const unsigned int scifa1_data_c_mux[] = { | |
2955 | SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK, | |
2956 | }; | |
2957 | static const unsigned int scifa1_clk_c_pins[] = { | |
2958 | /* SCK */ | |
2959 | RCAR_GP_PIN(0, 8), | |
2960 | }; | |
2961 | static const unsigned int scifa1_clk_c_mux[] = { | |
2962 | SCIFA1_SCK_C_MARK, | |
2963 | }; | |
2964 | static const unsigned int scifa1_ctrl_c_pins[] = { | |
2965 | /* RTS, CTS */ | |
2966 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), | |
2967 | }; | |
2968 | static const unsigned int scifa1_ctrl_c_mux[] = { | |
2969 | SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK, | |
2970 | }; | |
2971 | static const unsigned int scifa1_data_d_pins[] = { | |
2972 | /* RXD, TXD */ | |
2973 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), | |
2974 | }; | |
2975 | static const unsigned int scifa1_data_d_mux[] = { | |
2976 | SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK, | |
2977 | }; | |
2978 | static const unsigned int scifa1_clk_d_pins[] = { | |
2979 | /* SCK */ | |
2980 | RCAR_GP_PIN(2, 10), | |
2981 | }; | |
2982 | static const unsigned int scifa1_clk_d_mux[] = { | |
2983 | SCIFA1_SCK_D_MARK, | |
2984 | }; | |
2985 | static const unsigned int scifa1_ctrl_d_pins[] = { | |
2986 | /* RTS, CTS */ | |
2987 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13), | |
2988 | }; | |
2989 | static const unsigned int scifa1_ctrl_d_mux[] = { | |
2990 | SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK, | |
2991 | }; | |
2992 | /* - SCIFA2 ----------------------------------------------------------------- */ | |
2993 | static const unsigned int scifa2_data_pins[] = { | |
2994 | /* RXD, TXD */ | |
2995 | RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6), | |
2996 | }; | |
2997 | static const unsigned int scifa2_data_mux[] = { | |
2998 | SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, | |
2999 | }; | |
3000 | static const unsigned int scifa2_clk_pins[] = { | |
3001 | /* SCK */ | |
3002 | RCAR_GP_PIN(5, 4), | |
3003 | }; | |
3004 | static const unsigned int scifa2_clk_mux[] = { | |
3005 | SCIFA2_SCK_MARK, | |
3006 | }; | |
3007 | static const unsigned int scifa2_ctrl_pins[] = { | |
3008 | /* RTS, CTS */ | |
3009 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), | |
3010 | }; | |
3011 | static const unsigned int scifa2_ctrl_mux[] = { | |
3012 | SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK, | |
3013 | }; | |
3014 | static const unsigned int scifa2_data_b_pins[] = { | |
3015 | /* RXD, TXD */ | |
3016 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16), | |
3017 | }; | |
3018 | static const unsigned int scifa2_data_b_mux[] = { | |
3019 | SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK, | |
3020 | }; | |
3021 | static const unsigned int scifa2_data_c_pins[] = { | |
3022 | /* RXD, TXD */ | |
3023 | RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), | |
3024 | }; | |
3025 | static const unsigned int scifa2_data_c_mux[] = { | |
3026 | SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK, | |
3027 | }; | |
3028 | static const unsigned int scifa2_clk_c_pins[] = { | |
3029 | /* SCK */ | |
3030 | RCAR_GP_PIN(5, 29), | |
3031 | }; | |
3032 | static const unsigned int scifa2_clk_c_mux[] = { | |
3033 | SCIFA2_SCK_C_MARK, | |
3034 | }; | |
3035 | /* - SCIFB0 ----------------------------------------------------------------- */ | |
3036 | static const unsigned int scifb0_data_pins[] = { | |
3037 | /* RXD, TXD */ | |
3038 | RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10), | |
3039 | }; | |
3040 | static const unsigned int scifb0_data_mux[] = { | |
3041 | SCIFB0_RXD_MARK, SCIFB0_TXD_MARK, | |
3042 | }; | |
3043 | static const unsigned int scifb0_clk_pins[] = { | |
3044 | /* SCK */ | |
3045 | RCAR_GP_PIN(4, 8), | |
3046 | }; | |
3047 | static const unsigned int scifb0_clk_mux[] = { | |
3048 | SCIFB0_SCK_MARK, | |
3049 | }; | |
3050 | static const unsigned int scifb0_ctrl_pins[] = { | |
3051 | /* RTS, CTS */ | |
3052 | RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), | |
3053 | }; | |
3054 | static const unsigned int scifb0_ctrl_mux[] = { | |
3055 | SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK, | |
3056 | }; | |
3057 | static const unsigned int scifb0_data_b_pins[] = { | |
3058 | /* RXD, TXD */ | |
3059 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), | |
3060 | }; | |
3061 | static const unsigned int scifb0_data_b_mux[] = { | |
3062 | SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK, | |
3063 | }; | |
3064 | static const unsigned int scifb0_clk_b_pins[] = { | |
3065 | /* SCK */ | |
3066 | RCAR_GP_PIN(3, 9), | |
3067 | }; | |
3068 | static const unsigned int scifb0_clk_b_mux[] = { | |
3069 | SCIFB0_SCK_B_MARK, | |
3070 | }; | |
3071 | static const unsigned int scifb0_ctrl_b_pins[] = { | |
3072 | /* RTS, CTS */ | |
3073 | RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12), | |
3074 | }; | |
3075 | static const unsigned int scifb0_ctrl_b_mux[] = { | |
3076 | SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK, | |
3077 | }; | |
3078 | static const unsigned int scifb0_data_c_pins[] = { | |
3079 | /* RXD, TXD */ | |
3080 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
3081 | }; | |
3082 | static const unsigned int scifb0_data_c_mux[] = { | |
3083 | SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK, | |
3084 | }; | |
3085 | /* - SCIFB1 ----------------------------------------------------------------- */ | |
3086 | static const unsigned int scifb1_data_pins[] = { | |
3087 | /* RXD, TXD */ | |
3088 | RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16), | |
3089 | }; | |
3090 | static const unsigned int scifb1_data_mux[] = { | |
3091 | SCIFB1_RXD_MARK, SCIFB1_TXD_MARK, | |
3092 | }; | |
3093 | static const unsigned int scifb1_clk_pins[] = { | |
3094 | /* SCK */ | |
3095 | RCAR_GP_PIN(4, 14), | |
3096 | }; | |
3097 | static const unsigned int scifb1_clk_mux[] = { | |
3098 | SCIFB1_SCK_MARK, | |
3099 | }; | |
3100 | static const unsigned int scifb1_ctrl_pins[] = { | |
3101 | /* RTS, CTS */ | |
3102 | RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), | |
3103 | }; | |
3104 | static const unsigned int scifb1_ctrl_mux[] = { | |
3105 | SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK, | |
3106 | }; | |
3107 | static const unsigned int scifb1_data_b_pins[] = { | |
3108 | /* RXD, TXD */ | |
3109 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), | |
3110 | }; | |
3111 | static const unsigned int scifb1_data_b_mux[] = { | |
3112 | SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK, | |
3113 | }; | |
3114 | static const unsigned int scifb1_clk_b_pins[] = { | |
3115 | /* SCK */ | |
3116 | RCAR_GP_PIN(3, 1), | |
3117 | }; | |
3118 | static const unsigned int scifb1_clk_b_mux[] = { | |
3119 | SCIFB1_SCK_B_MARK, | |
3120 | }; | |
3121 | static const unsigned int scifb1_ctrl_b_pins[] = { | |
3122 | /* RTS, CTS */ | |
3123 | RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4), | |
3124 | }; | |
3125 | static const unsigned int scifb1_ctrl_b_mux[] = { | |
3126 | SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK, | |
3127 | }; | |
3128 | static const unsigned int scifb1_data_c_pins[] = { | |
3129 | /* RXD, TXD */ | |
3130 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
3131 | }; | |
3132 | static const unsigned int scifb1_data_c_mux[] = { | |
3133 | SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK, | |
3134 | }; | |
3135 | static const unsigned int scifb1_data_d_pins[] = { | |
3136 | /* RXD, TXD */ | |
3137 | RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2), | |
3138 | }; | |
3139 | static const unsigned int scifb1_data_d_mux[] = { | |
3140 | SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK, | |
3141 | }; | |
3142 | static const unsigned int scifb1_data_e_pins[] = { | |
3143 | /* RXD, TXD */ | |
3144 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), | |
3145 | }; | |
3146 | static const unsigned int scifb1_data_e_mux[] = { | |
3147 | SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK, | |
3148 | }; | |
3149 | static const unsigned int scifb1_clk_e_pins[] = { | |
3150 | /* SCK */ | |
3151 | RCAR_GP_PIN(3, 17), | |
3152 | }; | |
3153 | static const unsigned int scifb1_clk_e_mux[] = { | |
3154 | SCIFB1_SCK_E_MARK, | |
3155 | }; | |
3156 | static const unsigned int scifb1_data_f_pins[] = { | |
3157 | /* RXD, TXD */ | |
3158 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
3159 | }; | |
3160 | static const unsigned int scifb1_data_f_mux[] = { | |
3161 | SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK, | |
3162 | }; | |
3163 | static const unsigned int scifb1_data_g_pins[] = { | |
3164 | /* RXD, TXD */ | |
3165 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), | |
3166 | }; | |
3167 | static const unsigned int scifb1_data_g_mux[] = { | |
3168 | SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK, | |
3169 | }; | |
3170 | static const unsigned int scifb1_clk_g_pins[] = { | |
3171 | /* SCK */ | |
3172 | RCAR_GP_PIN(2, 20), | |
3173 | }; | |
3174 | static const unsigned int scifb1_clk_g_mux[] = { | |
3175 | SCIFB1_SCK_G_MARK, | |
066f0d6e | 3176 | }; |
45c6c85d LP |
3177 | /* - SCIFB2 ----------------------------------------------------------------- */ |
3178 | static const unsigned int scifb2_data_pins[] = { | |
3179 | /* RXD, TXD */ | |
3180 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), | |
066f0d6e | 3181 | }; |
45c6c85d LP |
3182 | static const unsigned int scifb2_data_mux[] = { |
3183 | SCIFB2_RXD_MARK, SCIFB2_TXD_MARK, | |
066f0d6e | 3184 | }; |
45c6c85d LP |
3185 | static const unsigned int scifb2_clk_pins[] = { |
3186 | /* SCK */ | |
3187 | RCAR_GP_PIN(4, 21), | |
066f0d6e | 3188 | }; |
45c6c85d LP |
3189 | static const unsigned int scifb2_clk_mux[] = { |
3190 | SCIFB2_SCK_MARK, | |
066f0d6e | 3191 | }; |
45c6c85d LP |
3192 | static const unsigned int scifb2_ctrl_pins[] = { |
3193 | /* RTS, CTS */ | |
3194 | RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), | |
066f0d6e | 3195 | }; |
45c6c85d LP |
3196 | static const unsigned int scifb2_ctrl_mux[] = { |
3197 | SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK, | |
066f0d6e | 3198 | }; |
45c6c85d LP |
3199 | static const unsigned int scifb2_data_b_pins[] = { |
3200 | /* RXD, TXD */ | |
3201 | RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30), | |
066f0d6e | 3202 | }; |
45c6c85d LP |
3203 | static const unsigned int scifb2_data_b_mux[] = { |
3204 | SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK, | |
066f0d6e | 3205 | }; |
45c6c85d LP |
3206 | static const unsigned int scifb2_clk_b_pins[] = { |
3207 | /* SCK */ | |
3208 | RCAR_GP_PIN(0, 31), | |
066f0d6e | 3209 | }; |
45c6c85d LP |
3210 | static const unsigned int scifb2_clk_b_mux[] = { |
3211 | SCIFB2_SCK_B_MARK, | |
066f0d6e | 3212 | }; |
45c6c85d LP |
3213 | static const unsigned int scifb2_ctrl_b_pins[] = { |
3214 | /* RTS, CTS */ | |
3215 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27), | |
066f0d6e | 3216 | }; |
45c6c85d LP |
3217 | static const unsigned int scifb2_ctrl_b_mux[] = { |
3218 | SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK, | |
066f0d6e | 3219 | }; |
45c6c85d LP |
3220 | static const unsigned int scifb2_data_c_pins[] = { |
3221 | /* RXD, TXD */ | |
3222 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
3223 | }; | |
3224 | static const unsigned int scifb2_data_c_mux[] = { | |
3225 | SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK, | |
066f0d6e | 3226 | }; |
53ec9ccd GU |
3227 | /* - SCIF Clock ------------------------------------------------------------- */ |
3228 | static const unsigned int scif_clk_pins[] = { | |
3229 | /* SCIF_CLK */ | |
3230 | RCAR_GP_PIN(4, 26), | |
3231 | }; | |
3232 | static const unsigned int scif_clk_mux[] = { | |
3233 | SCIF_CLK_MARK, | |
3234 | }; | |
3235 | static const unsigned int scif_clk_b_pins[] = { | |
3236 | /* SCIF_CLK */ | |
3237 | RCAR_GP_PIN(5, 4), | |
3238 | }; | |
3239 | static const unsigned int scif_clk_b_mux[] = { | |
3240 | SCIF_CLK_B_MARK, | |
3241 | }; | |
0a6ea54f | 3242 | /* - SDHI0 ------------------------------------------------------------------ */ |
066f0d6e GL |
3243 | static const unsigned int sdhi0_data1_pins[] = { |
3244 | /* D0 */ | |
3245 | RCAR_GP_PIN(3, 2), | |
3246 | }; | |
3247 | static const unsigned int sdhi0_data1_mux[] = { | |
3248 | SD0_DAT0_MARK, | |
3249 | }; | |
3250 | static const unsigned int sdhi0_data4_pins[] = { | |
3251 | /* D[0:3] */ | |
3252 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), | |
3253 | }; | |
3254 | static const unsigned int sdhi0_data4_mux[] = { | |
3255 | SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK, | |
3256 | }; | |
3257 | static const unsigned int sdhi0_ctrl_pins[] = { | |
3258 | /* CLK, CMD */ | |
3259 | RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1), | |
3260 | }; | |
3261 | static const unsigned int sdhi0_ctrl_mux[] = { | |
3262 | SD0_CLK_MARK, SD0_CMD_MARK, | |
3263 | }; | |
3264 | static const unsigned int sdhi0_cd_pins[] = { | |
3265 | /* CD */ | |
3266 | RCAR_GP_PIN(3, 6), | |
3267 | }; | |
3268 | static const unsigned int sdhi0_cd_mux[] = { | |
3269 | SD0_CD_MARK, | |
3270 | }; | |
3271 | static const unsigned int sdhi0_wp_pins[] = { | |
3272 | /* WP */ | |
3273 | RCAR_GP_PIN(3, 7), | |
3274 | }; | |
3275 | static const unsigned int sdhi0_wp_mux[] = { | |
3276 | SD0_WP_MARK, | |
3277 | }; | |
0a6ea54f | 3278 | /* - SDHI1 ------------------------------------------------------------------ */ |
066f0d6e GL |
3279 | static const unsigned int sdhi1_data1_pins[] = { |
3280 | /* D0 */ | |
3281 | RCAR_GP_PIN(3, 10), | |
3282 | }; | |
3283 | static const unsigned int sdhi1_data1_mux[] = { | |
3284 | SD1_DAT0_MARK, | |
3285 | }; | |
3286 | static const unsigned int sdhi1_data4_pins[] = { | |
3287 | /* D[0:3] */ | |
3288 | RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), | |
3289 | }; | |
3290 | static const unsigned int sdhi1_data4_mux[] = { | |
3291 | SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK, | |
3292 | }; | |
3293 | static const unsigned int sdhi1_ctrl_pins[] = { | |
3294 | /* CLK, CMD */ | |
3295 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), | |
3296 | }; | |
3297 | static const unsigned int sdhi1_ctrl_mux[] = { | |
3298 | SD1_CLK_MARK, SD1_CMD_MARK, | |
3299 | }; | |
3300 | static const unsigned int sdhi1_cd_pins[] = { | |
3301 | /* CD */ | |
3302 | RCAR_GP_PIN(3, 14), | |
3303 | }; | |
3304 | static const unsigned int sdhi1_cd_mux[] = { | |
3305 | SD1_CD_MARK, | |
3306 | }; | |
3307 | static const unsigned int sdhi1_wp_pins[] = { | |
3308 | /* WP */ | |
3309 | RCAR_GP_PIN(3, 15), | |
3310 | }; | |
3311 | static const unsigned int sdhi1_wp_mux[] = { | |
3312 | SD1_WP_MARK, | |
3313 | }; | |
0a6ea54f | 3314 | /* - SDHI2 ------------------------------------------------------------------ */ |
066f0d6e GL |
3315 | static const unsigned int sdhi2_data1_pins[] = { |
3316 | /* D0 */ | |
3317 | RCAR_GP_PIN(3, 18), | |
3318 | }; | |
3319 | static const unsigned int sdhi2_data1_mux[] = { | |
3320 | SD2_DAT0_MARK, | |
3321 | }; | |
3322 | static const unsigned int sdhi2_data4_pins[] = { | |
3323 | /* D[0:3] */ | |
3324 | RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21), | |
3325 | }; | |
3326 | static const unsigned int sdhi2_data4_mux[] = { | |
3327 | SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK, | |
3328 | }; | |
3329 | static const unsigned int sdhi2_ctrl_pins[] = { | |
3330 | /* CLK, CMD */ | |
3331 | RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), | |
3332 | }; | |
3333 | static const unsigned int sdhi2_ctrl_mux[] = { | |
3334 | SD2_CLK_MARK, SD2_CMD_MARK, | |
3335 | }; | |
3336 | static const unsigned int sdhi2_cd_pins[] = { | |
3337 | /* CD */ | |
3338 | RCAR_GP_PIN(3, 22), | |
3339 | }; | |
3340 | static const unsigned int sdhi2_cd_mux[] = { | |
3341 | SD2_CD_MARK, | |
3342 | }; | |
3343 | static const unsigned int sdhi2_wp_pins[] = { | |
3344 | /* WP */ | |
3345 | RCAR_GP_PIN(3, 23), | |
3346 | }; | |
3347 | static const unsigned int sdhi2_wp_mux[] = { | |
3348 | SD2_WP_MARK, | |
3349 | }; | |
0a6ea54f | 3350 | /* - SDHI3 ------------------------------------------------------------------ */ |
066f0d6e GL |
3351 | static const unsigned int sdhi3_data1_pins[] = { |
3352 | /* D0 */ | |
3353 | RCAR_GP_PIN(3, 26), | |
3354 | }; | |
3355 | static const unsigned int sdhi3_data1_mux[] = { | |
3356 | SD3_DAT0_MARK, | |
3357 | }; | |
3358 | static const unsigned int sdhi3_data4_pins[] = { | |
3359 | /* D[0:3] */ | |
3360 | RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29), | |
3361 | }; | |
3362 | static const unsigned int sdhi3_data4_mux[] = { | |
3363 | SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK, | |
3364 | }; | |
3365 | static const unsigned int sdhi3_ctrl_pins[] = { | |
3366 | /* CLK, CMD */ | |
3367 | RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25), | |
3368 | }; | |
3369 | static const unsigned int sdhi3_ctrl_mux[] = { | |
3370 | SD3_CLK_MARK, SD3_CMD_MARK, | |
3371 | }; | |
3372 | static const unsigned int sdhi3_cd_pins[] = { | |
3373 | /* CD */ | |
3374 | RCAR_GP_PIN(3, 30), | |
3375 | }; | |
3376 | static const unsigned int sdhi3_cd_mux[] = { | |
3377 | SD3_CD_MARK, | |
3378 | }; | |
3379 | static const unsigned int sdhi3_wp_pins[] = { | |
3380 | /* WP */ | |
3381 | RCAR_GP_PIN(3, 31), | |
3382 | }; | |
3383 | static const unsigned int sdhi3_wp_mux[] = { | |
3384 | SD3_WP_MARK, | |
3385 | }; | |
1d7b59a0 KM |
3386 | /* - SSI -------------------------------------------------------------------- */ |
3387 | static const unsigned int ssi0_data_pins[] = { | |
3388 | /* SDATA0 */ | |
3389 | RCAR_GP_PIN(4, 5), | |
3390 | }; | |
3391 | static const unsigned int ssi0_data_mux[] = { | |
3392 | SSI_SDATA0_MARK, | |
3393 | }; | |
3394 | static const unsigned int ssi0129_ctrl_pins[] = { | |
3395 | /* SCK, WS */ | |
3396 | RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4), | |
3397 | }; | |
3398 | static const unsigned int ssi0129_ctrl_mux[] = { | |
3399 | SSI_SCK0129_MARK, SSI_WS0129_MARK, | |
3400 | }; | |
3401 | static const unsigned int ssi1_data_pins[] = { | |
3402 | /* SDATA1 */ | |
3403 | RCAR_GP_PIN(4, 6), | |
3404 | }; | |
3405 | static const unsigned int ssi1_data_mux[] = { | |
3406 | SSI_SDATA1_MARK, | |
3407 | }; | |
3408 | static const unsigned int ssi1_ctrl_pins[] = { | |
3409 | /* SCK, WS */ | |
3410 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24), | |
3411 | }; | |
3412 | static const unsigned int ssi1_ctrl_mux[] = { | |
3413 | SSI_SCK1_MARK, SSI_WS1_MARK, | |
3414 | }; | |
3415 | static const unsigned int ssi2_data_pins[] = { | |
3416 | /* SDATA2 */ | |
3417 | RCAR_GP_PIN(4, 7), | |
3418 | }; | |
3419 | static const unsigned int ssi2_data_mux[] = { | |
3420 | SSI_SDATA2_MARK, | |
3421 | }; | |
3422 | static const unsigned int ssi2_ctrl_pins[] = { | |
3423 | /* SCK, WS */ | |
3424 | RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17), | |
3425 | }; | |
3426 | static const unsigned int ssi2_ctrl_mux[] = { | |
3427 | SSI_SCK2_MARK, SSI_WS2_MARK, | |
3428 | }; | |
3429 | static const unsigned int ssi3_data_pins[] = { | |
3430 | /* SDATA3 */ | |
3431 | RCAR_GP_PIN(4, 10), | |
3432 | }; | |
3433 | static const unsigned int ssi3_data_mux[] = { | |
3434 | SSI_SDATA3_MARK | |
3435 | }; | |
3436 | static const unsigned int ssi34_ctrl_pins[] = { | |
3437 | /* SCK, WS */ | |
3438 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), | |
3439 | }; | |
3440 | static const unsigned int ssi34_ctrl_mux[] = { | |
3441 | SSI_SCK34_MARK, SSI_WS34_MARK, | |
3442 | }; | |
3443 | static const unsigned int ssi4_data_pins[] = { | |
3444 | /* SDATA4 */ | |
3445 | RCAR_GP_PIN(4, 13), | |
3446 | }; | |
3447 | static const unsigned int ssi4_data_mux[] = { | |
3448 | SSI_SDATA4_MARK, | |
3449 | }; | |
3450 | static const unsigned int ssi4_ctrl_pins[] = { | |
3451 | /* SCK, WS */ | |
3452 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), | |
3453 | }; | |
3454 | static const unsigned int ssi4_ctrl_mux[] = { | |
3455 | SSI_SCK4_MARK, SSI_WS4_MARK, | |
3456 | }; | |
3457 | static const unsigned int ssi5_pins[] = { | |
3458 | /* SDATA5, SCK, WS */ | |
3459 | RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15), | |
3460 | }; | |
3461 | static const unsigned int ssi5_mux[] = { | |
3462 | SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK, | |
3463 | }; | |
3464 | static const unsigned int ssi5_b_pins[] = { | |
3465 | /* SDATA5, SCK, WS */ | |
3466 | RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
3467 | }; | |
3468 | static const unsigned int ssi5_b_mux[] = { | |
3469 | SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK | |
3470 | }; | |
3471 | static const unsigned int ssi5_c_pins[] = { | |
3472 | /* SDATA5, SCK, WS */ | |
3473 | RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12), | |
3474 | }; | |
3475 | static const unsigned int ssi5_c_mux[] = { | |
3476 | SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK, | |
3477 | }; | |
3478 | static const unsigned int ssi6_pins[] = { | |
3479 | /* SDATA6, SCK, WS */ | |
3480 | RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18), | |
3481 | }; | |
3482 | static const unsigned int ssi6_mux[] = { | |
3483 | SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK, | |
3484 | }; | |
3485 | static const unsigned int ssi6_b_pins[] = { | |
3486 | /* SDATA6, SCK, WS */ | |
3487 | RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27), | |
3488 | }; | |
3489 | static const unsigned int ssi6_b_mux[] = { | |
3490 | SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK, | |
3491 | }; | |
3492 | static const unsigned int ssi7_data_pins[] = { | |
3493 | /* SDATA7 */ | |
3494 | RCAR_GP_PIN(4, 22), | |
3495 | }; | |
3496 | static const unsigned int ssi7_data_mux[] = { | |
3497 | SSI_SDATA7_MARK, | |
3498 | }; | |
3499 | static const unsigned int ssi7_b_data_pins[] = { | |
3500 | /* SDATA7 */ | |
3501 | RCAR_GP_PIN(4, 22), | |
3502 | }; | |
3503 | static const unsigned int ssi7_b_data_mux[] = { | |
3504 | SSI_SDATA7_B_MARK, | |
3505 | }; | |
3506 | static const unsigned int ssi7_c_data_pins[] = { | |
3507 | /* SDATA7 */ | |
3508 | RCAR_GP_PIN(1, 26), | |
3509 | }; | |
3510 | static const unsigned int ssi7_c_data_mux[] = { | |
3511 | SSI_SDATA7_C_MARK, | |
3512 | }; | |
3513 | static const unsigned int ssi78_ctrl_pins[] = { | |
3514 | /* SCK, WS */ | |
3515 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), | |
3516 | }; | |
3517 | static const unsigned int ssi78_ctrl_mux[] = { | |
3518 | SSI_SCK78_MARK, SSI_WS78_MARK, | |
3519 | }; | |
3520 | static const unsigned int ssi78_b_ctrl_pins[] = { | |
3521 | /* SCK, WS */ | |
3522 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24), | |
3523 | }; | |
3524 | static const unsigned int ssi78_b_ctrl_mux[] = { | |
3525 | SSI_SCK78_B_MARK, SSI_WS78_B_MARK, | |
3526 | }; | |
3527 | static const unsigned int ssi78_c_ctrl_pins[] = { | |
3528 | /* SCK, WS */ | |
3529 | RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25), | |
3530 | }; | |
3531 | static const unsigned int ssi78_c_ctrl_mux[] = { | |
3532 | SSI_SCK78_C_MARK, SSI_WS78_C_MARK, | |
3533 | }; | |
3534 | static const unsigned int ssi8_data_pins[] = { | |
3535 | /* SDATA8 */ | |
3536 | RCAR_GP_PIN(4, 23), | |
3537 | }; | |
3538 | static const unsigned int ssi8_data_mux[] = { | |
3539 | SSI_SDATA8_MARK, | |
3540 | }; | |
3541 | static const unsigned int ssi8_b_data_pins[] = { | |
3542 | /* SDATA8 */ | |
3543 | RCAR_GP_PIN(4, 23), | |
3544 | }; | |
3545 | static const unsigned int ssi8_b_data_mux[] = { | |
3546 | SSI_SDATA8_B_MARK, | |
3547 | }; | |
3548 | static const unsigned int ssi8_c_data_pins[] = { | |
3549 | /* SDATA8 */ | |
3550 | RCAR_GP_PIN(1, 27), | |
3551 | }; | |
3552 | static const unsigned int ssi8_c_data_mux[] = { | |
3553 | SSI_SDATA8_C_MARK, | |
3554 | }; | |
3555 | static const unsigned int ssi9_data_pins[] = { | |
3556 | /* SDATA9 */ | |
3557 | RCAR_GP_PIN(4, 24), | |
3558 | }; | |
3559 | static const unsigned int ssi9_data_mux[] = { | |
3560 | SSI_SDATA9_MARK, | |
3561 | }; | |
3562 | static const unsigned int ssi9_ctrl_pins[] = { | |
3563 | /* SCK, WS */ | |
3564 | RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), | |
3565 | }; | |
3566 | static const unsigned int ssi9_ctrl_mux[] = { | |
3567 | SSI_SCK9_MARK, SSI_WS9_MARK, | |
3568 | }; | |
457c11d3 LP |
3569 | /* - TPU0 ------------------------------------------------------------------- */ |
3570 | static const unsigned int tpu0_to0_pins[] = { | |
3571 | /* TO */ | |
3572 | RCAR_GP_PIN(0, 20), | |
3573 | }; | |
3574 | static const unsigned int tpu0_to0_mux[] = { | |
3575 | TPU0TO0_MARK, | |
3576 | }; | |
3577 | static const unsigned int tpu0_to1_pins[] = { | |
3578 | /* TO */ | |
3579 | RCAR_GP_PIN(0, 21), | |
3580 | }; | |
3581 | static const unsigned int tpu0_to1_mux[] = { | |
3582 | TPU0TO1_MARK, | |
3583 | }; | |
3584 | static const unsigned int tpu0_to2_pins[] = { | |
3585 | /* TO */ | |
3586 | RCAR_GP_PIN(0, 22), | |
3587 | }; | |
3588 | static const unsigned int tpu0_to2_mux[] = { | |
3589 | TPU0TO2_MARK, | |
3590 | }; | |
3591 | static const unsigned int tpu0_to3_pins[] = { | |
3592 | /* TO */ | |
3593 | RCAR_GP_PIN(0, 23), | |
3594 | }; | |
3595 | static const unsigned int tpu0_to3_mux[] = { | |
3596 | TPU0TO3_MARK, | |
3597 | }; | |
dac896e2 SU |
3598 | /* - USB0 ------------------------------------------------------------------- */ |
3599 | static const unsigned int usb0_pins[] = { | |
3600 | /* PWEN, OVC/VBUS */ | |
3601 | RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), | |
3602 | }; | |
3603 | static const unsigned int usb0_mux[] = { | |
3604 | USB0_PWEN_MARK, USB0_OVC_VBUS_MARK, | |
3605 | }; | |
97e00faa MD |
3606 | static const unsigned int usb0_ovc_vbus_pins[] = { |
3607 | /* OVC/VBUS */ | |
3608 | RCAR_GP_PIN(5, 19), | |
3609 | }; | |
3610 | static const unsigned int usb0_ovc_vbus_mux[] = { | |
3611 | USB0_OVC_VBUS_MARK, | |
3612 | }; | |
dac896e2 SU |
3613 | /* - USB1 ------------------------------------------------------------------- */ |
3614 | static const unsigned int usb1_pins[] = { | |
3615 | /* PWEN, OVC */ | |
3616 | RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21), | |
3617 | }; | |
3618 | static const unsigned int usb1_mux[] = { | |
3619 | USB1_PWEN_MARK, USB1_OVC_MARK, | |
3620 | }; | |
3621 | /* - USB2 ------------------------------------------------------------------- */ | |
3622 | static const unsigned int usb2_pins[] = { | |
3623 | /* PWEN, OVC */ | |
3624 | RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23), | |
3625 | }; | |
3626 | static const unsigned int usb2_mux[] = { | |
3627 | USB2_PWEN_MARK, USB2_OVC_MARK, | |
3628 | }; | |
e120cacf | 3629 | /* - VIN0 ------------------------------------------------------------------- */ |
64fe8abc VB |
3630 | static const union vin_data vin0_data_pins = { |
3631 | .data24 = { | |
3632 | /* B */ | |
3633 | RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), | |
3634 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), | |
3635 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
3636 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
3637 | /* G */ | |
3638 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | |
3639 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | |
3640 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | |
3641 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
3642 | /* R */ | |
3643 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
3644 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | |
3645 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
3646 | RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), | |
3647 | }, | |
3648 | }; | |
3649 | static const union vin_data vin0_data_mux = { | |
3650 | .data24 = { | |
3651 | /* B */ | |
3652 | VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, | |
3653 | VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, | |
3654 | VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, | |
3655 | VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, | |
3656 | /* G */ | |
3657 | VI0_G0_MARK, VI0_G1_MARK, | |
3658 | VI0_G2_MARK, VI0_G3_MARK, | |
3659 | VI0_G4_MARK, VI0_G5_MARK, | |
3660 | VI0_G6_MARK, VI0_G7_MARK, | |
3661 | /* R */ | |
3662 | VI0_R0_MARK, VI0_R1_MARK, | |
3663 | VI0_R2_MARK, VI0_R3_MARK, | |
3664 | VI0_R4_MARK, VI0_R5_MARK, | |
3665 | VI0_R6_MARK, VI0_R7_MARK, | |
3666 | }, | |
3667 | }; | |
3668 | static const unsigned int vin0_data18_pins[] = { | |
3669 | /* B */ | |
3670 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), | |
3671 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), | |
3672 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), | |
3673 | /* G */ | |
3674 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | |
3675 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | |
e120cacf | 3676 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), |
64fe8abc VB |
3677 | /* R */ |
3678 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | |
3679 | RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), | |
e120cacf SU |
3680 | RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), |
3681 | }; | |
64fe8abc VB |
3682 | static const unsigned int vin0_data18_mux[] = { |
3683 | /* B */ | |
3684 | VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK, | |
3685 | VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, | |
e120cacf | 3686 | VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, |
64fe8abc VB |
3687 | /* G */ |
3688 | VI0_G2_MARK, VI0_G3_MARK, | |
3689 | VI0_G4_MARK, VI0_G5_MARK, | |
3690 | VI0_G6_MARK, VI0_G7_MARK, | |
3691 | /* R */ | |
3692 | VI0_R2_MARK, VI0_R3_MARK, | |
3693 | VI0_R4_MARK, VI0_R5_MARK, | |
3694 | VI0_R6_MARK, VI0_R7_MARK, | |
e120cacf | 3695 | }; |
a9e4c7bb VB |
3696 | static const unsigned int vin0_sync_pins[] = { |
3697 | RCAR_GP_PIN(0, 12), /* HSYNC */ | |
3698 | RCAR_GP_PIN(0, 13), /* VSYNC */ | |
e120cacf | 3699 | }; |
a9e4c7bb | 3700 | static const unsigned int vin0_sync_mux[] = { |
e120cacf | 3701 | VI0_HSYNC_N_MARK, |
e120cacf SU |
3702 | VI0_VSYNC_N_MARK, |
3703 | }; | |
7a57be87 | 3704 | static const unsigned int vin0_field_pins[] = { |
e120cacf SU |
3705 | RCAR_GP_PIN(0, 15), |
3706 | }; | |
7a57be87 | 3707 | static const unsigned int vin0_field_mux[] = { |
e120cacf SU |
3708 | VI0_FIELD_MARK, |
3709 | }; | |
7a57be87 | 3710 | static const unsigned int vin0_clkenb_pins[] = { |
e120cacf SU |
3711 | RCAR_GP_PIN(0, 14), |
3712 | }; | |
7a57be87 | 3713 | static const unsigned int vin0_clkenb_mux[] = { |
e120cacf SU |
3714 | VI0_CLKENB_MARK, |
3715 | }; | |
3716 | static const unsigned int vin0_clk_pins[] = { | |
3717 | RCAR_GP_PIN(2, 0), | |
3718 | }; | |
3719 | static const unsigned int vin0_clk_mux[] = { | |
3720 | VI0_CLK_MARK, | |
3721 | }; | |
3722 | /* - VIN1 ------------------------------------------------------------------- */ | |
317a03a9 VB |
3723 | static const union vin_data vin1_data_pins = { |
3724 | .data24 = { | |
3725 | /* B */ | |
3726 | RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), | |
3727 | RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), | |
3728 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), | |
3729 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), | |
3730 | /* G */ | |
3731 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | |
3732 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), | |
3733 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), | |
3734 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), | |
3735 | /* R */ | |
3736 | RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), | |
3737 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), | |
3738 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), | |
3739 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), | |
3740 | }, | |
3741 | }; | |
3742 | static const union vin_data vin1_data_mux = { | |
3743 | .data24 = { | |
3744 | /* B */ | |
3745 | VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, | |
3746 | VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, | |
3747 | VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, | |
3748 | VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, | |
3749 | /* G */ | |
3750 | VI1_G0_MARK, VI1_G1_MARK, | |
3751 | VI1_G2_MARK, VI1_G3_MARK, | |
3752 | VI1_G4_MARK, VI1_G5_MARK, | |
3753 | VI1_G6_MARK, VI1_G7_MARK, | |
3754 | /* R */ | |
3755 | VI1_R0_MARK, VI1_R1_MARK, | |
3756 | VI1_R2_MARK, VI1_R3_MARK, | |
3757 | VI1_R4_MARK, VI1_R5_MARK, | |
3758 | VI1_R6_MARK, VI1_R7_MARK, | |
3759 | }, | |
3760 | }; | |
3761 | static const unsigned int vin1_data18_pins[] = { | |
3762 | /* B */ | |
3763 | RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13), | |
3764 | RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), | |
e120cacf | 3765 | RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), |
317a03a9 VB |
3766 | /* G */ |
3767 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), | |
3768 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12), | |
3769 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7), | |
3770 | /* R */ | |
3771 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4), | |
3772 | RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), | |
3773 | RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8), | |
e120cacf | 3774 | }; |
317a03a9 VB |
3775 | static const unsigned int vin1_data18_mux[] = { |
3776 | /* B */ | |
3777 | VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK, | |
3778 | VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, | |
e120cacf | 3779 | VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, |
317a03a9 VB |
3780 | /* G */ |
3781 | VI1_G2_MARK, VI1_G3_MARK, | |
3782 | VI1_G4_MARK, VI1_G5_MARK, | |
3783 | VI1_G6_MARK, VI1_G7_MARK, | |
3784 | /* R */ | |
3785 | VI1_R2_MARK, VI1_R3_MARK, | |
3786 | VI1_R4_MARK, VI1_R5_MARK, | |
3787 | VI1_R6_MARK, VI1_R7_MARK, | |
3788 | }; | |
3789 | static const unsigned int vin1_sync_pins[] = { | |
3790 | RCAR_GP_PIN(1, 24), /* HSYNC */ | |
3791 | RCAR_GP_PIN(1, 25), /* VSYNC */ | |
3792 | }; | |
3793 | static const unsigned int vin1_sync_mux[] = { | |
3794 | VI1_HSYNC_N_MARK, | |
3795 | VI1_VSYNC_N_MARK, | |
3796 | }; | |
3797 | static const unsigned int vin1_field_pins[] = { | |
3798 | RCAR_GP_PIN(1, 13), | |
3799 | }; | |
3800 | static const unsigned int vin1_field_mux[] = { | |
3801 | VI1_FIELD_MARK, | |
3802 | }; | |
3803 | static const unsigned int vin1_clkenb_pins[] = { | |
3804 | RCAR_GP_PIN(1, 26), | |
3805 | }; | |
3806 | static const unsigned int vin1_clkenb_mux[] = { | |
3807 | VI1_CLKENB_MARK, | |
e120cacf SU |
3808 | }; |
3809 | static const unsigned int vin1_clk_pins[] = { | |
3810 | RCAR_GP_PIN(2, 9), | |
3811 | }; | |
3812 | static const unsigned int vin1_clk_mux[] = { | |
3813 | VI1_CLK_MARK, | |
3814 | }; | |
054d4259 VB |
3815 | /* - VIN2 ----------------------------------------------------------------- */ |
3816 | static const union vin_data vin2_data_pins = { | |
3817 | .data24 = { | |
3818 | /* B */ | |
3819 | RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), | |
3820 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | |
3821 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
3822 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
3823 | /* G */ | |
3824 | RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28), | |
3825 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), | |
3826 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
3827 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
3828 | /* R */ | |
3829 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13), | |
3830 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | |
3831 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), | |
3832 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), | |
3833 | }, | |
3834 | }; | |
3835 | static const union vin_data vin2_data_mux = { | |
3836 | .data24 = { | |
3837 | /* B */ | |
3838 | VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, | |
3839 | VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, | |
3840 | VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, | |
3841 | VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, | |
3842 | /* G */ | |
3843 | VI2_G0_MARK, VI2_G1_MARK, | |
3844 | VI2_G2_MARK, VI2_G3_MARK, | |
3845 | VI2_G4_MARK, VI2_G5_MARK, | |
3846 | VI2_G6_MARK, VI2_G7_MARK, | |
3847 | /* R */ | |
3848 | VI2_R0_MARK, VI2_R1_MARK, | |
3849 | VI2_R2_MARK, VI2_R3_MARK, | |
3850 | VI2_R4_MARK, VI2_R5_MARK, | |
3851 | VI2_R6_MARK, VI2_R7_MARK, | |
3852 | }, | |
3853 | }; | |
3854 | static const unsigned int vin2_data18_pins[] = { | |
3855 | /* B */ | |
3856 | RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11), | |
3857 | RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13), | |
3858 | RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15), | |
3859 | /* G */ | |
3860 | RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10), | |
3861 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), | |
3862 | RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7), | |
3863 | /* R */ | |
3864 | RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15), | |
3865 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20), | |
3866 | RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24), | |
3867 | }; | |
3868 | static const unsigned int vin2_data18_mux[] = { | |
3869 | /* B */ | |
3870 | VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK, | |
3871 | VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK, | |
3872 | VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK, | |
3873 | /* G */ | |
3874 | VI2_G2_MARK, VI2_G3_MARK, | |
3875 | VI2_G4_MARK, VI2_G5_MARK, | |
3876 | VI2_G6_MARK, VI2_G7_MARK, | |
3877 | /* R */ | |
3878 | VI2_R2_MARK, VI2_R3_MARK, | |
3879 | VI2_R4_MARK, VI2_R5_MARK, | |
3880 | VI2_R6_MARK, VI2_R7_MARK, | |
3881 | }; | |
3882 | static const unsigned int vin2_sync_pins[] = { | |
3883 | RCAR_GP_PIN(1, 16), /* HSYNC */ | |
3884 | RCAR_GP_PIN(1, 21), /* VSYNC */ | |
3885 | }; | |
3886 | static const unsigned int vin2_sync_mux[] = { | |
3887 | VI2_HSYNC_N_MARK, | |
3888 | VI2_VSYNC_N_MARK, | |
3889 | }; | |
3890 | static const unsigned int vin2_field_pins[] = { | |
3891 | RCAR_GP_PIN(1, 9), | |
3892 | }; | |
3893 | static const unsigned int vin2_field_mux[] = { | |
3894 | VI2_FIELD_MARK, | |
3895 | }; | |
3896 | static const unsigned int vin2_clkenb_pins[] = { | |
3897 | RCAR_GP_PIN(1, 8), | |
3898 | }; | |
3899 | static const unsigned int vin2_clkenb_mux[] = { | |
3900 | VI2_CLKENB_MARK, | |
3901 | }; | |
3902 | static const unsigned int vin2_clk_pins[] = { | |
3903 | RCAR_GP_PIN(1, 11), | |
3904 | }; | |
3905 | static const unsigned int vin2_clk_mux[] = { | |
3906 | VI2_CLK_MARK, | |
3907 | }; | |
3908 | /* - VIN3 ----------------------------------------------------------------- */ | |
3909 | static const unsigned int vin3_data8_pins[] = { | |
3910 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), | |
3911 | RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), | |
3912 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), | |
3913 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7), | |
3914 | }; | |
3915 | static const unsigned int vin3_data8_mux[] = { | |
3916 | VI3_DATA0_MARK, VI3_DATA1_MARK, | |
3917 | VI3_DATA2_MARK, VI3_DATA3_MARK, | |
3918 | VI3_DATA4_MARK, VI3_DATA5_MARK, | |
3919 | VI3_DATA6_MARK, VI3_DATA7_MARK, | |
3920 | }; | |
3921 | static const unsigned int vin3_sync_pins[] = { | |
3922 | RCAR_GP_PIN(1, 16), /* HSYNC */ | |
3923 | RCAR_GP_PIN(1, 17), /* VSYNC */ | |
3924 | }; | |
3925 | static const unsigned int vin3_sync_mux[] = { | |
3926 | VI3_HSYNC_N_MARK, | |
646ae3ef | 3927 | VI3_VSYNC_N_MARK, |
054d4259 VB |
3928 | }; |
3929 | static const unsigned int vin3_field_pins[] = { | |
3930 | RCAR_GP_PIN(1, 15), | |
3931 | }; | |
3932 | static const unsigned int vin3_field_mux[] = { | |
3933 | VI3_FIELD_MARK, | |
3934 | }; | |
3935 | static const unsigned int vin3_clkenb_pins[] = { | |
3936 | RCAR_GP_PIN(1, 14), | |
3937 | }; | |
3938 | static const unsigned int vin3_clkenb_mux[] = { | |
3939 | VI3_CLKENB_MARK, | |
3940 | }; | |
3941 | static const unsigned int vin3_clk_pins[] = { | |
3942 | RCAR_GP_PIN(1, 23), | |
3943 | }; | |
3944 | static const unsigned int vin3_clk_mux[] = { | |
3945 | VI3_CLK_MARK, | |
3946 | }; | |
066f0d6e | 3947 | |
1627769b | 3948 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
fcec5b22 KM |
3949 | SH_PFC_PIN_GROUP(audio_clk_a), |
3950 | SH_PFC_PIN_GROUP(audio_clk_b), | |
3951 | SH_PFC_PIN_GROUP(audio_clk_c), | |
3952 | SH_PFC_PIN_GROUP(audio_clkout), | |
3953 | SH_PFC_PIN_GROUP(audio_clkout_b), | |
3954 | SH_PFC_PIN_GROUP(audio_clkout_c), | |
3955 | SH_PFC_PIN_GROUP(audio_clkout_d), | |
19ef697d SS |
3956 | SH_PFC_PIN_GROUP(avb_link), |
3957 | SH_PFC_PIN_GROUP(avb_magic), | |
3958 | SH_PFC_PIN_GROUP(avb_phy_int), | |
3959 | SH_PFC_PIN_GROUP(avb_mdio), | |
3960 | SH_PFC_PIN_GROUP(avb_mii), | |
3961 | SH_PFC_PIN_GROUP(avb_gmii), | |
62783b71 LP |
3962 | SH_PFC_PIN_GROUP(du_rgb666), |
3963 | SH_PFC_PIN_GROUP(du_rgb888), | |
3964 | SH_PFC_PIN_GROUP(du_clk_out_0), | |
3965 | SH_PFC_PIN_GROUP(du_clk_out_1), | |
3966 | SH_PFC_PIN_GROUP(du_sync_0), | |
3967 | SH_PFC_PIN_GROUP(du_sync_1), | |
3968 | SH_PFC_PIN_GROUP(du_cde), | |
3969 | SH_PFC_PIN_GROUP(du0_clk_in), | |
3970 | SH_PFC_PIN_GROUP(du1_clk_in), | |
3971 | SH_PFC_PIN_GROUP(du2_clk_in), | |
1627769b LP |
3972 | SH_PFC_PIN_GROUP(eth_link), |
3973 | SH_PFC_PIN_GROUP(eth_magic), | |
3974 | SH_PFC_PIN_GROUP(eth_mdio), | |
3975 | SH_PFC_PIN_GROUP(eth_rmii), | |
fbd0ca3d UH |
3976 | SH_PFC_PIN_GROUP(hscif0_data), |
3977 | SH_PFC_PIN_GROUP(hscif0_clk), | |
3978 | SH_PFC_PIN_GROUP(hscif0_ctrl), | |
3979 | SH_PFC_PIN_GROUP(hscif0_data_b), | |
3980 | SH_PFC_PIN_GROUP(hscif0_ctrl_b), | |
3981 | SH_PFC_PIN_GROUP(hscif0_data_c), | |
3982 | SH_PFC_PIN_GROUP(hscif0_ctrl_c), | |
3983 | SH_PFC_PIN_GROUP(hscif0_data_d), | |
3984 | SH_PFC_PIN_GROUP(hscif0_ctrl_d), | |
3985 | SH_PFC_PIN_GROUP(hscif0_data_e), | |
3986 | SH_PFC_PIN_GROUP(hscif0_ctrl_e), | |
3987 | SH_PFC_PIN_GROUP(hscif0_data_f), | |
3988 | SH_PFC_PIN_GROUP(hscif0_ctrl_f), | |
3989 | SH_PFC_PIN_GROUP(hscif1_data), | |
3990 | SH_PFC_PIN_GROUP(hscif1_clk), | |
3991 | SH_PFC_PIN_GROUP(hscif1_ctrl), | |
3992 | SH_PFC_PIN_GROUP(hscif1_data_b), | |
3993 | SH_PFC_PIN_GROUP(hscif1_clk_b), | |
3994 | SH_PFC_PIN_GROUP(hscif1_ctrl_b), | |
35a493de | 3995 | SH_PFC_PIN_GROUP(i2c0), |
70702bfc UH |
3996 | SH_PFC_PIN_GROUP(i2c1), |
3997 | SH_PFC_PIN_GROUP(i2c1_b), | |
3998 | SH_PFC_PIN_GROUP(i2c1_c), | |
3999 | SH_PFC_PIN_GROUP(i2c2), | |
4000 | SH_PFC_PIN_GROUP(i2c2_b), | |
4001 | SH_PFC_PIN_GROUP(i2c2_c), | |
4002 | SH_PFC_PIN_GROUP(i2c2_d), | |
4003 | SH_PFC_PIN_GROUP(i2c2_e), | |
f6aaaac9 | 4004 | SH_PFC_PIN_GROUP(i2c3), |
a16b81dc WS |
4005 | SH_PFC_PIN_GROUP(iic0), |
4006 | SH_PFC_PIN_GROUP(iic1), | |
4007 | SH_PFC_PIN_GROUP(iic1_b), | |
4008 | SH_PFC_PIN_GROUP(iic1_c), | |
4009 | SH_PFC_PIN_GROUP(iic2), | |
4010 | SH_PFC_PIN_GROUP(iic2_b), | |
4011 | SH_PFC_PIN_GROUP(iic2_c), | |
4012 | SH_PFC_PIN_GROUP(iic2_d), | |
4013 | SH_PFC_PIN_GROUP(iic2_e), | |
4014 | SH_PFC_PIN_GROUP(iic3), | |
04e7ce78 LP |
4015 | SH_PFC_PIN_GROUP(intc_irq0), |
4016 | SH_PFC_PIN_GROUP(intc_irq1), | |
4017 | SH_PFC_PIN_GROUP(intc_irq2), | |
4018 | SH_PFC_PIN_GROUP(intc_irq3), | |
e29a4c3a | 4019 | SH_PFC_PIN_GROUP(mlb_3pin), |
fbd0ca3d UH |
4020 | SH_PFC_PIN_GROUP(mmc0_data1), |
4021 | SH_PFC_PIN_GROUP(mmc0_data4), | |
4022 | SH_PFC_PIN_GROUP(mmc0_data8), | |
4023 | SH_PFC_PIN_GROUP(mmc0_ctrl), | |
4024 | SH_PFC_PIN_GROUP(mmc1_data1), | |
4025 | SH_PFC_PIN_GROUP(mmc1_data4), | |
4026 | SH_PFC_PIN_GROUP(mmc1_data8), | |
4027 | SH_PFC_PIN_GROUP(mmc1_ctrl), | |
4f47cc5e KH |
4028 | SH_PFC_PIN_GROUP(msiof0_clk), |
4029 | SH_PFC_PIN_GROUP(msiof0_sync), | |
4030 | SH_PFC_PIN_GROUP(msiof0_ss1), | |
4031 | SH_PFC_PIN_GROUP(msiof0_ss2), | |
4032 | SH_PFC_PIN_GROUP(msiof0_rx), | |
4033 | SH_PFC_PIN_GROUP(msiof0_tx), | |
7033168d GU |
4034 | SH_PFC_PIN_GROUP(msiof0_clk_b), |
4035 | SH_PFC_PIN_GROUP(msiof0_ss1_b), | |
4036 | SH_PFC_PIN_GROUP(msiof0_ss2_b), | |
4037 | SH_PFC_PIN_GROUP(msiof0_rx_b), | |
4038 | SH_PFC_PIN_GROUP(msiof0_tx_b), | |
4f47cc5e KH |
4039 | SH_PFC_PIN_GROUP(msiof1_clk), |
4040 | SH_PFC_PIN_GROUP(msiof1_sync), | |
4041 | SH_PFC_PIN_GROUP(msiof1_ss1), | |
4042 | SH_PFC_PIN_GROUP(msiof1_ss2), | |
4043 | SH_PFC_PIN_GROUP(msiof1_rx), | |
4044 | SH_PFC_PIN_GROUP(msiof1_tx), | |
7033168d GU |
4045 | SH_PFC_PIN_GROUP(msiof1_clk_b), |
4046 | SH_PFC_PIN_GROUP(msiof1_ss1_b), | |
4047 | SH_PFC_PIN_GROUP(msiof1_ss2_b), | |
4048 | SH_PFC_PIN_GROUP(msiof1_rx_b), | |
4049 | SH_PFC_PIN_GROUP(msiof1_tx_b), | |
4f47cc5e KH |
4050 | SH_PFC_PIN_GROUP(msiof2_clk), |
4051 | SH_PFC_PIN_GROUP(msiof2_sync), | |
4052 | SH_PFC_PIN_GROUP(msiof2_ss1), | |
4053 | SH_PFC_PIN_GROUP(msiof2_ss2), | |
4054 | SH_PFC_PIN_GROUP(msiof2_rx), | |
4055 | SH_PFC_PIN_GROUP(msiof2_tx), | |
4056 | SH_PFC_PIN_GROUP(msiof3_clk), | |
4057 | SH_PFC_PIN_GROUP(msiof3_sync), | |
4058 | SH_PFC_PIN_GROUP(msiof3_ss1), | |
4059 | SH_PFC_PIN_GROUP(msiof3_ss2), | |
4060 | SH_PFC_PIN_GROUP(msiof3_rx), | |
4061 | SH_PFC_PIN_GROUP(msiof3_tx), | |
7033168d GU |
4062 | SH_PFC_PIN_GROUP(msiof3_clk_b), |
4063 | SH_PFC_PIN_GROUP(msiof3_sync_b), | |
4064 | SH_PFC_PIN_GROUP(msiof3_rx_b), | |
4065 | SH_PFC_PIN_GROUP(msiof3_tx_b), | |
5c89c15b YS |
4066 | SH_PFC_PIN_GROUP(pwm0), |
4067 | SH_PFC_PIN_GROUP(pwm0_b), | |
4068 | SH_PFC_PIN_GROUP(pwm1), | |
4069 | SH_PFC_PIN_GROUP(pwm1_b), | |
4070 | SH_PFC_PIN_GROUP(pwm2), | |
4071 | SH_PFC_PIN_GROUP(pwm3), | |
4072 | SH_PFC_PIN_GROUP(pwm4), | |
4073 | SH_PFC_PIN_GROUP(pwm5), | |
4074 | SH_PFC_PIN_GROUP(pwm6), | |
202909cd GU |
4075 | SH_PFC_PIN_GROUP(qspi_ctrl), |
4076 | SH_PFC_PIN_GROUP(qspi_data2), | |
4077 | SH_PFC_PIN_GROUP(qspi_data4), | |
45c6c85d LP |
4078 | SH_PFC_PIN_GROUP(scif0_data), |
4079 | SH_PFC_PIN_GROUP(scif0_clk), | |
4080 | SH_PFC_PIN_GROUP(scif0_ctrl), | |
4081 | SH_PFC_PIN_GROUP(scif0_data_b), | |
4082 | SH_PFC_PIN_GROUP(scif1_data), | |
4083 | SH_PFC_PIN_GROUP(scif1_clk), | |
4084 | SH_PFC_PIN_GROUP(scif1_ctrl), | |
4085 | SH_PFC_PIN_GROUP(scif1_data_b), | |
4086 | SH_PFC_PIN_GROUP(scif1_data_c), | |
4087 | SH_PFC_PIN_GROUP(scif1_data_d), | |
4088 | SH_PFC_PIN_GROUP(scif1_clk_d), | |
4089 | SH_PFC_PIN_GROUP(scif1_data_e), | |
4090 | SH_PFC_PIN_GROUP(scif1_clk_e), | |
2dbe7f2c LP |
4091 | SH_PFC_PIN_GROUP(scif2_data), |
4092 | SH_PFC_PIN_GROUP(scif2_clk), | |
4093 | SH_PFC_PIN_GROUP(scif2_data_b), | |
45c6c85d LP |
4094 | SH_PFC_PIN_GROUP(scifa0_data), |
4095 | SH_PFC_PIN_GROUP(scifa0_clk), | |
4096 | SH_PFC_PIN_GROUP(scifa0_ctrl), | |
4097 | SH_PFC_PIN_GROUP(scifa0_data_b), | |
4098 | SH_PFC_PIN_GROUP(scifa0_clk_b), | |
4099 | SH_PFC_PIN_GROUP(scifa0_ctrl_b), | |
4100 | SH_PFC_PIN_GROUP(scifa1_data), | |
4101 | SH_PFC_PIN_GROUP(scifa1_clk), | |
4102 | SH_PFC_PIN_GROUP(scifa1_ctrl), | |
4103 | SH_PFC_PIN_GROUP(scifa1_data_b), | |
4104 | SH_PFC_PIN_GROUP(scifa1_clk_b), | |
4105 | SH_PFC_PIN_GROUP(scifa1_ctrl_b), | |
4106 | SH_PFC_PIN_GROUP(scifa1_data_c), | |
4107 | SH_PFC_PIN_GROUP(scifa1_clk_c), | |
4108 | SH_PFC_PIN_GROUP(scifa1_ctrl_c), | |
4109 | SH_PFC_PIN_GROUP(scifa1_data_d), | |
4110 | SH_PFC_PIN_GROUP(scifa1_clk_d), | |
4111 | SH_PFC_PIN_GROUP(scifa1_ctrl_d), | |
4112 | SH_PFC_PIN_GROUP(scifa2_data), | |
4113 | SH_PFC_PIN_GROUP(scifa2_clk), | |
4114 | SH_PFC_PIN_GROUP(scifa2_ctrl), | |
4115 | SH_PFC_PIN_GROUP(scifa2_data_b), | |
4116 | SH_PFC_PIN_GROUP(scifa2_data_c), | |
4117 | SH_PFC_PIN_GROUP(scifa2_clk_c), | |
4118 | SH_PFC_PIN_GROUP(scifb0_data), | |
4119 | SH_PFC_PIN_GROUP(scifb0_clk), | |
4120 | SH_PFC_PIN_GROUP(scifb0_ctrl), | |
4121 | SH_PFC_PIN_GROUP(scifb0_data_b), | |
4122 | SH_PFC_PIN_GROUP(scifb0_clk_b), | |
4123 | SH_PFC_PIN_GROUP(scifb0_ctrl_b), | |
4124 | SH_PFC_PIN_GROUP(scifb0_data_c), | |
4125 | SH_PFC_PIN_GROUP(scifb1_data), | |
4126 | SH_PFC_PIN_GROUP(scifb1_clk), | |
4127 | SH_PFC_PIN_GROUP(scifb1_ctrl), | |
4128 | SH_PFC_PIN_GROUP(scifb1_data_b), | |
4129 | SH_PFC_PIN_GROUP(scifb1_clk_b), | |
4130 | SH_PFC_PIN_GROUP(scifb1_ctrl_b), | |
4131 | SH_PFC_PIN_GROUP(scifb1_data_c), | |
4132 | SH_PFC_PIN_GROUP(scifb1_data_d), | |
4133 | SH_PFC_PIN_GROUP(scifb1_data_e), | |
4134 | SH_PFC_PIN_GROUP(scifb1_clk_e), | |
4135 | SH_PFC_PIN_GROUP(scifb1_data_f), | |
4136 | SH_PFC_PIN_GROUP(scifb1_data_g), | |
4137 | SH_PFC_PIN_GROUP(scifb1_clk_g), | |
4138 | SH_PFC_PIN_GROUP(scifb2_data), | |
4139 | SH_PFC_PIN_GROUP(scifb2_clk), | |
4140 | SH_PFC_PIN_GROUP(scifb2_ctrl), | |
4141 | SH_PFC_PIN_GROUP(scifb2_data_b), | |
4142 | SH_PFC_PIN_GROUP(scifb2_clk_b), | |
4143 | SH_PFC_PIN_GROUP(scifb2_ctrl_b), | |
4144 | SH_PFC_PIN_GROUP(scifb2_data_c), | |
53ec9ccd GU |
4145 | SH_PFC_PIN_GROUP(scif_clk), |
4146 | SH_PFC_PIN_GROUP(scif_clk_b), | |
066f0d6e GL |
4147 | SH_PFC_PIN_GROUP(sdhi0_data1), |
4148 | SH_PFC_PIN_GROUP(sdhi0_data4), | |
4149 | SH_PFC_PIN_GROUP(sdhi0_ctrl), | |
4150 | SH_PFC_PIN_GROUP(sdhi0_cd), | |
4151 | SH_PFC_PIN_GROUP(sdhi0_wp), | |
4152 | SH_PFC_PIN_GROUP(sdhi1_data1), | |
4153 | SH_PFC_PIN_GROUP(sdhi1_data4), | |
4154 | SH_PFC_PIN_GROUP(sdhi1_ctrl), | |
4155 | SH_PFC_PIN_GROUP(sdhi1_cd), | |
4156 | SH_PFC_PIN_GROUP(sdhi1_wp), | |
4157 | SH_PFC_PIN_GROUP(sdhi2_data1), | |
4158 | SH_PFC_PIN_GROUP(sdhi2_data4), | |
4159 | SH_PFC_PIN_GROUP(sdhi2_ctrl), | |
4160 | SH_PFC_PIN_GROUP(sdhi2_cd), | |
4161 | SH_PFC_PIN_GROUP(sdhi2_wp), | |
4162 | SH_PFC_PIN_GROUP(sdhi3_data1), | |
4163 | SH_PFC_PIN_GROUP(sdhi3_data4), | |
4164 | SH_PFC_PIN_GROUP(sdhi3_ctrl), | |
4165 | SH_PFC_PIN_GROUP(sdhi3_cd), | |
4166 | SH_PFC_PIN_GROUP(sdhi3_wp), | |
1d7b59a0 KM |
4167 | SH_PFC_PIN_GROUP(ssi0_data), |
4168 | SH_PFC_PIN_GROUP(ssi0129_ctrl), | |
4169 | SH_PFC_PIN_GROUP(ssi1_data), | |
4170 | SH_PFC_PIN_GROUP(ssi1_ctrl), | |
4171 | SH_PFC_PIN_GROUP(ssi2_data), | |
4172 | SH_PFC_PIN_GROUP(ssi2_ctrl), | |
4173 | SH_PFC_PIN_GROUP(ssi3_data), | |
4174 | SH_PFC_PIN_GROUP(ssi34_ctrl), | |
4175 | SH_PFC_PIN_GROUP(ssi4_data), | |
4176 | SH_PFC_PIN_GROUP(ssi4_ctrl), | |
4177 | SH_PFC_PIN_GROUP(ssi5), | |
4178 | SH_PFC_PIN_GROUP(ssi5_b), | |
4179 | SH_PFC_PIN_GROUP(ssi5_c), | |
4180 | SH_PFC_PIN_GROUP(ssi6), | |
4181 | SH_PFC_PIN_GROUP(ssi6_b), | |
4182 | SH_PFC_PIN_GROUP(ssi7_data), | |
4183 | SH_PFC_PIN_GROUP(ssi7_b_data), | |
4184 | SH_PFC_PIN_GROUP(ssi7_c_data), | |
4185 | SH_PFC_PIN_GROUP(ssi78_ctrl), | |
4186 | SH_PFC_PIN_GROUP(ssi78_b_ctrl), | |
4187 | SH_PFC_PIN_GROUP(ssi78_c_ctrl), | |
4188 | SH_PFC_PIN_GROUP(ssi8_data), | |
4189 | SH_PFC_PIN_GROUP(ssi8_b_data), | |
4190 | SH_PFC_PIN_GROUP(ssi8_c_data), | |
4191 | SH_PFC_PIN_GROUP(ssi9_data), | |
4192 | SH_PFC_PIN_GROUP(ssi9_ctrl), | |
fbd0ca3d UH |
4193 | SH_PFC_PIN_GROUP(tpu0_to0), |
4194 | SH_PFC_PIN_GROUP(tpu0_to1), | |
4195 | SH_PFC_PIN_GROUP(tpu0_to2), | |
4196 | SH_PFC_PIN_GROUP(tpu0_to3), | |
dac896e2 | 4197 | SH_PFC_PIN_GROUP(usb0), |
97e00faa | 4198 | SH_PFC_PIN_GROUP(usb0_ovc_vbus), |
dac896e2 SU |
4199 | SH_PFC_PIN_GROUP(usb1), |
4200 | SH_PFC_PIN_GROUP(usb2), | |
64fe8abc VB |
4201 | VIN_DATA_PIN_GROUP(vin0_data, 24), |
4202 | VIN_DATA_PIN_GROUP(vin0_data, 20), | |
4203 | SH_PFC_PIN_GROUP(vin0_data18), | |
4204 | VIN_DATA_PIN_GROUP(vin0_data, 16), | |
4205 | VIN_DATA_PIN_GROUP(vin0_data, 12), | |
4206 | VIN_DATA_PIN_GROUP(vin0_data, 10), | |
4207 | VIN_DATA_PIN_GROUP(vin0_data, 8), | |
4208 | VIN_DATA_PIN_GROUP(vin0_data, 4), | |
a9e4c7bb | 4209 | SH_PFC_PIN_GROUP(vin0_sync), |
7a57be87 VB |
4210 | SH_PFC_PIN_GROUP(vin0_field), |
4211 | SH_PFC_PIN_GROUP(vin0_clkenb), | |
e120cacf | 4212 | SH_PFC_PIN_GROUP(vin0_clk), |
317a03a9 VB |
4213 | VIN_DATA_PIN_GROUP(vin1_data, 24), |
4214 | VIN_DATA_PIN_GROUP(vin1_data, 20), | |
4215 | SH_PFC_PIN_GROUP(vin1_data18), | |
4216 | VIN_DATA_PIN_GROUP(vin1_data, 16), | |
4217 | VIN_DATA_PIN_GROUP(vin1_data, 12), | |
4218 | VIN_DATA_PIN_GROUP(vin1_data, 10), | |
4219 | VIN_DATA_PIN_GROUP(vin1_data, 8), | |
4220 | VIN_DATA_PIN_GROUP(vin1_data, 4), | |
4221 | SH_PFC_PIN_GROUP(vin1_sync), | |
4222 | SH_PFC_PIN_GROUP(vin1_field), | |
4223 | SH_PFC_PIN_GROUP(vin1_clkenb), | |
e120cacf | 4224 | SH_PFC_PIN_GROUP(vin1_clk), |
054d4259 VB |
4225 | VIN_DATA_PIN_GROUP(vin2_data, 24), |
4226 | SH_PFC_PIN_GROUP(vin2_data18), | |
4227 | VIN_DATA_PIN_GROUP(vin2_data, 16), | |
4228 | VIN_DATA_PIN_GROUP(vin2_data, 8), | |
4229 | VIN_DATA_PIN_GROUP(vin2_data, 4), | |
4230 | SH_PFC_PIN_GROUP(vin2_sync), | |
4231 | SH_PFC_PIN_GROUP(vin2_field), | |
4232 | SH_PFC_PIN_GROUP(vin2_clkenb), | |
4233 | SH_PFC_PIN_GROUP(vin2_clk), | |
4234 | SH_PFC_PIN_GROUP(vin3_data8), | |
4235 | SH_PFC_PIN_GROUP(vin3_sync), | |
4236 | SH_PFC_PIN_GROUP(vin3_field), | |
4237 | SH_PFC_PIN_GROUP(vin3_clkenb), | |
4238 | SH_PFC_PIN_GROUP(vin3_clk), | |
1627769b LP |
4239 | }; |
4240 | ||
fcec5b22 KM |
4241 | static const char * const audio_clk_groups[] = { |
4242 | "audio_clk_a", | |
4243 | "audio_clk_b", | |
4244 | "audio_clk_c", | |
4245 | "audio_clkout", | |
4246 | "audio_clkout_b", | |
4247 | "audio_clkout_c", | |
4248 | "audio_clkout_d", | |
4249 | }; | |
4250 | ||
19ef697d SS |
4251 | static const char * const avb_groups[] = { |
4252 | "avb_link", | |
4253 | "avb_magic", | |
4254 | "avb_phy_int", | |
4255 | "avb_mdio", | |
4256 | "avb_mii", | |
4257 | "avb_gmii", | |
4258 | }; | |
4259 | ||
62783b71 LP |
4260 | static const char * const du_groups[] = { |
4261 | "du_rgb666", | |
4262 | "du_rgb888", | |
4263 | "du_clk_out_0", | |
4264 | "du_clk_out_1", | |
4265 | "du_sync_0", | |
4266 | "du_sync_1", | |
4267 | "du_cde", | |
4268 | }; | |
4269 | ||
4270 | static const char * const du0_groups[] = { | |
4271 | "du0_clk_in", | |
4272 | }; | |
4273 | ||
4274 | static const char * const du1_groups[] = { | |
4275 | "du1_clk_in", | |
4276 | }; | |
4277 | ||
4278 | static const char * const du2_groups[] = { | |
4279 | "du2_clk_in", | |
4280 | }; | |
4281 | ||
1627769b LP |
4282 | static const char * const eth_groups[] = { |
4283 | "eth_link", | |
4284 | "eth_magic", | |
4285 | "eth_mdio", | |
4286 | "eth_rmii", | |
4287 | }; | |
4288 | ||
457c11d3 LP |
4289 | static const char * const hscif0_groups[] = { |
4290 | "hscif0_data", | |
4291 | "hscif0_clk", | |
4292 | "hscif0_ctrl", | |
4293 | "hscif0_data_b", | |
4294 | "hscif0_ctrl_b", | |
4295 | "hscif0_data_c", | |
4296 | "hscif0_ctrl_c", | |
4297 | "hscif0_data_d", | |
4298 | "hscif0_ctrl_d", | |
4299 | "hscif0_data_e", | |
4300 | "hscif0_ctrl_e", | |
4301 | "hscif0_data_f", | |
4302 | "hscif0_ctrl_f", | |
4303 | }; | |
4304 | ||
4305 | static const char * const hscif1_groups[] = { | |
4306 | "hscif1_data", | |
4307 | "hscif1_clk", | |
4308 | "hscif1_ctrl", | |
4309 | "hscif1_data_b", | |
4310 | "hscif1_clk_b", | |
4311 | "hscif1_ctrl_b", | |
4312 | }; | |
4313 | ||
35a493de WS |
4314 | static const char * const i2c0_groups[] = { |
4315 | "i2c0", | |
4316 | }; | |
4317 | ||
70702bfc UH |
4318 | static const char * const i2c1_groups[] = { |
4319 | "i2c1", | |
4320 | "i2c1_b", | |
4321 | "i2c1_c", | |
4322 | }; | |
4323 | ||
4324 | static const char * const i2c2_groups[] = { | |
4325 | "i2c2", | |
4326 | "i2c2_b", | |
4327 | "i2c2_c", | |
4328 | "i2c2_d", | |
4329 | "i2c2_e", | |
4330 | }; | |
4331 | ||
f6aaaac9 GL |
4332 | static const char * const i2c3_groups[] = { |
4333 | "i2c3", | |
4334 | }; | |
4335 | ||
a16b81dc WS |
4336 | static const char * const iic0_groups[] = { |
4337 | "iic0", | |
4338 | }; | |
4339 | ||
4340 | static const char * const iic1_groups[] = { | |
4341 | "iic1", | |
4342 | "iic1_b", | |
4343 | "iic1_c", | |
4344 | }; | |
4345 | ||
4346 | static const char * const iic2_groups[] = { | |
4347 | "iic2", | |
4348 | "iic2_b", | |
4349 | "iic2_c", | |
4350 | "iic2_d", | |
4351 | "iic2_e", | |
4352 | }; | |
4353 | ||
4354 | static const char * const iic3_groups[] = { | |
4355 | "iic3", | |
4356 | }; | |
4357 | ||
04e7ce78 LP |
4358 | static const char * const intc_groups[] = { |
4359 | "intc_irq0", | |
4360 | "intc_irq1", | |
4361 | "intc_irq2", | |
4362 | "intc_irq3", | |
4363 | }; | |
45c6c85d | 4364 | |
e29a4c3a SS |
4365 | static const char * const mlb_groups[] = { |
4366 | "mlb_3pin", | |
4367 | }; | |
4368 | ||
457c11d3 LP |
4369 | static const char * const mmc0_groups[] = { |
4370 | "mmc0_data1", | |
4371 | "mmc0_data4", | |
4372 | "mmc0_data8", | |
4373 | "mmc0_ctrl", | |
4374 | }; | |
4375 | ||
4376 | static const char * const mmc1_groups[] = { | |
4377 | "mmc1_data1", | |
4378 | "mmc1_data4", | |
4379 | "mmc1_data8", | |
4380 | "mmc1_ctrl", | |
4381 | }; | |
4382 | ||
4f47cc5e KH |
4383 | static const char * const msiof0_groups[] = { |
4384 | "msiof0_clk", | |
4385 | "msiof0_sync", | |
4386 | "msiof0_ss1", | |
4387 | "msiof0_ss2", | |
4388 | "msiof0_rx", | |
4389 | "msiof0_tx", | |
7033168d GU |
4390 | "msiof0_clk_b", |
4391 | "msiof0_ss1_b", | |
4392 | "msiof0_ss2_b", | |
4393 | "msiof0_rx_b", | |
4394 | "msiof0_tx_b", | |
4f47cc5e KH |
4395 | }; |
4396 | ||
4397 | static const char * const msiof1_groups[] = { | |
4398 | "msiof1_clk", | |
4399 | "msiof1_sync", | |
4400 | "msiof1_ss1", | |
4401 | "msiof1_ss2", | |
4402 | "msiof1_rx", | |
4403 | "msiof1_tx", | |
7033168d GU |
4404 | "msiof1_clk_b", |
4405 | "msiof1_ss1_b", | |
4406 | "msiof1_ss2_b", | |
4407 | "msiof1_rx_b", | |
4408 | "msiof1_tx_b", | |
4f47cc5e KH |
4409 | }; |
4410 | ||
4411 | static const char * const msiof2_groups[] = { | |
4412 | "msiof2_clk", | |
4413 | "msiof2_sync", | |
4414 | "msiof2_ss1", | |
4415 | "msiof2_ss2", | |
4416 | "msiof2_rx", | |
4417 | "msiof2_tx", | |
4418 | }; | |
4419 | ||
4420 | static const char * const msiof3_groups[] = { | |
4421 | "msiof3_clk", | |
4422 | "msiof3_sync", | |
4423 | "msiof3_ss1", | |
4424 | "msiof3_ss2", | |
4425 | "msiof3_rx", | |
4426 | "msiof3_tx", | |
7033168d GU |
4427 | "msiof3_clk_b", |
4428 | "msiof3_sync_b", | |
4429 | "msiof3_rx_b", | |
4430 | "msiof3_tx_b", | |
4f47cc5e KH |
4431 | }; |
4432 | ||
5c89c15b YS |
4433 | static const char * const pwm0_groups[] = { |
4434 | "pwm0", | |
4435 | "pwm0_b", | |
4436 | }; | |
4437 | ||
4438 | static const char * const pwm1_groups[] = { | |
4439 | "pwm1", | |
4440 | "pwm1_b", | |
4441 | }; | |
4442 | ||
4443 | static const char * const pwm2_groups[] = { | |
4444 | "pwm2", | |
4445 | }; | |
4446 | ||
4447 | static const char * const pwm3_groups[] = { | |
4448 | "pwm3", | |
4449 | }; | |
4450 | ||
4451 | static const char * const pwm4_groups[] = { | |
4452 | "pwm4", | |
4453 | }; | |
4454 | ||
4455 | static const char * const pwm5_groups[] = { | |
4456 | "pwm5", | |
4457 | }; | |
4458 | ||
4459 | static const char * const pwm6_groups[] = { | |
4460 | "pwm6", | |
4461 | }; | |
4462 | ||
202909cd GU |
4463 | static const char * const qspi_groups[] = { |
4464 | "qspi_ctrl", | |
4465 | "qspi_data2", | |
4466 | "qspi_data4", | |
4467 | }; | |
4468 | ||
45c6c85d LP |
4469 | static const char * const scif0_groups[] = { |
4470 | "scif0_data", | |
4471 | "scif0_clk", | |
4472 | "scif0_ctrl", | |
4473 | "scif0_data_b", | |
4474 | }; | |
4475 | ||
4476 | static const char * const scif1_groups[] = { | |
4477 | "scif1_data", | |
4478 | "scif1_clk", | |
4479 | "scif1_ctrl", | |
4480 | "scif1_data_b", | |
4481 | "scif1_data_c", | |
4482 | "scif1_data_d", | |
4483 | "scif1_clk_d", | |
4484 | "scif1_data_e", | |
4485 | "scif1_clk_e", | |
4486 | }; | |
4487 | ||
2dbe7f2c LP |
4488 | static const char * const scif2_groups[] = { |
4489 | "scif2_data", | |
4490 | "scif2_clk", | |
4491 | "scif2_data_b", | |
fbd0ca3d UH |
4492 | }; |
4493 | ||
45c6c85d LP |
4494 | static const char * const scifa0_groups[] = { |
4495 | "scifa0_data", | |
4496 | "scifa0_clk", | |
4497 | "scifa0_ctrl", | |
4498 | "scifa0_data_b", | |
4499 | "scifa0_clk_b", | |
4500 | "scifa0_ctrl_b", | |
4501 | }; | |
4502 | ||
4503 | static const char * const scifa1_groups[] = { | |
4504 | "scifa1_data", | |
4505 | "scifa1_clk", | |
4506 | "scifa1_ctrl", | |
4507 | "scifa1_data_b", | |
4508 | "scifa1_clk_b", | |
4509 | "scifa1_ctrl_b", | |
4510 | "scifa1_data_c", | |
4511 | "scifa1_clk_c", | |
4512 | "scifa1_ctrl_c", | |
4513 | "scifa1_data_d", | |
4514 | "scifa1_clk_d", | |
4515 | "scifa1_ctrl_d", | |
4516 | }; | |
4517 | ||
4518 | static const char * const scifa2_groups[] = { | |
4519 | "scifa2_data", | |
4520 | "scifa2_clk", | |
4521 | "scifa2_ctrl", | |
4522 | "scifa2_data_b", | |
4523 | "scifa2_data_c", | |
4524 | "scifa2_clk_c", | |
4525 | }; | |
4526 | ||
4527 | static const char * const scifb0_groups[] = { | |
4528 | "scifb0_data", | |
4529 | "scifb0_clk", | |
4530 | "scifb0_ctrl", | |
4531 | "scifb0_data_b", | |
4532 | "scifb0_clk_b", | |
4533 | "scifb0_ctrl_b", | |
4534 | "scifb0_data_c", | |
4535 | }; | |
4536 | ||
4537 | static const char * const scifb1_groups[] = { | |
4538 | "scifb1_data", | |
4539 | "scifb1_clk", | |
4540 | "scifb1_ctrl", | |
4541 | "scifb1_data_b", | |
4542 | "scifb1_clk_b", | |
4543 | "scifb1_ctrl_b", | |
4544 | "scifb1_data_c", | |
4545 | "scifb1_data_d", | |
4546 | "scifb1_data_e", | |
4547 | "scifb1_clk_e", | |
4548 | "scifb1_data_f", | |
4549 | "scifb1_data_g", | |
4550 | "scifb1_clk_g", | |
4551 | }; | |
4552 | ||
4553 | static const char * const scifb2_groups[] = { | |
4554 | "scifb2_data", | |
4555 | "scifb2_clk", | |
4556 | "scifb2_ctrl", | |
4557 | "scifb2_data_b", | |
4558 | "scifb2_clk_b", | |
4559 | "scifb2_ctrl_b", | |
4560 | "scifb2_data_c", | |
4561 | }; | |
4562 | ||
53ec9ccd GU |
4563 | static const char * const scif_clk_groups[] = { |
4564 | "scif_clk", | |
4565 | "scif_clk_b", | |
4566 | }; | |
4567 | ||
066f0d6e GL |
4568 | static const char * const sdhi0_groups[] = { |
4569 | "sdhi0_data1", | |
4570 | "sdhi0_data4", | |
4571 | "sdhi0_ctrl", | |
4572 | "sdhi0_cd", | |
4573 | "sdhi0_wp", | |
4574 | }; | |
4575 | ||
4576 | static const char * const sdhi1_groups[] = { | |
4577 | "sdhi1_data1", | |
4578 | "sdhi1_data4", | |
4579 | "sdhi1_ctrl", | |
4580 | "sdhi1_cd", | |
4581 | "sdhi1_wp", | |
4582 | }; | |
4583 | ||
4584 | static const char * const sdhi2_groups[] = { | |
4585 | "sdhi2_data1", | |
4586 | "sdhi2_data4", | |
4587 | "sdhi2_ctrl", | |
4588 | "sdhi2_cd", | |
4589 | "sdhi2_wp", | |
4590 | }; | |
4591 | ||
4592 | static const char * const sdhi3_groups[] = { | |
4593 | "sdhi3_data1", | |
4594 | "sdhi3_data4", | |
4595 | "sdhi3_ctrl", | |
4596 | "sdhi3_cd", | |
4597 | "sdhi3_wp", | |
4598 | }; | |
4599 | ||
1d7b59a0 KM |
4600 | static const char * const ssi_groups[] = { |
4601 | "ssi0_data", | |
4602 | "ssi0129_ctrl", | |
4603 | "ssi1_data", | |
4604 | "ssi1_ctrl", | |
4605 | "ssi2_data", | |
4606 | "ssi2_ctrl", | |
4607 | "ssi3_data", | |
4608 | "ssi34_ctrl", | |
4609 | "ssi4_data", | |
4610 | "ssi4_ctrl", | |
4611 | "ssi5", | |
4612 | "ssi5_b", | |
4613 | "ssi5_c", | |
4614 | "ssi6", | |
4615 | "ssi6_b", | |
4616 | "ssi7_data", | |
4617 | "ssi7_b_data", | |
4618 | "ssi7_c_data", | |
4619 | "ssi78_ctrl", | |
4620 | "ssi78_b_ctrl", | |
4621 | "ssi78_c_ctrl", | |
4622 | "ssi8_data", | |
4623 | "ssi8_b_data", | |
4624 | "ssi8_c_data", | |
4625 | "ssi9_data", | |
4626 | "ssi9_ctrl", | |
4627 | }; | |
4628 | ||
457c11d3 LP |
4629 | static const char * const tpu0_groups[] = { |
4630 | "tpu0_to0", | |
4631 | "tpu0_to1", | |
4632 | "tpu0_to2", | |
4633 | "tpu0_to3", | |
4634 | }; | |
4635 | ||
dac896e2 SU |
4636 | static const char * const usb0_groups[] = { |
4637 | "usb0", | |
97e00faa | 4638 | "usb0_ovc_vbus", |
dac896e2 SU |
4639 | }; |
4640 | ||
4641 | static const char * const usb1_groups[] = { | |
4642 | "usb1", | |
4643 | }; | |
4644 | ||
4645 | static const char * const usb2_groups[] = { | |
4646 | "usb2", | |
4647 | }; | |
4648 | ||
e120cacf | 4649 | static const char * const vin0_groups[] = { |
64fe8abc VB |
4650 | "vin0_data24", |
4651 | "vin0_data20", | |
4652 | "vin0_data18", | |
4653 | "vin0_data16", | |
4654 | "vin0_data12", | |
4655 | "vin0_data10", | |
4656 | "vin0_data8", | |
4657 | "vin0_data4", | |
a9e4c7bb | 4658 | "vin0_sync", |
7a57be87 VB |
4659 | "vin0_field", |
4660 | "vin0_clkenb", | |
e120cacf SU |
4661 | "vin0_clk", |
4662 | }; | |
4663 | ||
4664 | static const char * const vin1_groups[] = { | |
317a03a9 VB |
4665 | "vin1_data24", |
4666 | "vin1_data20", | |
4667 | "vin1_data18", | |
4668 | "vin1_data16", | |
4669 | "vin1_data12", | |
4670 | "vin1_data10", | |
4671 | "vin1_data8", | |
4672 | "vin1_data4", | |
4673 | "vin1_sync", | |
4674 | "vin1_field", | |
4675 | "vin1_clkenb", | |
e120cacf SU |
4676 | "vin1_clk", |
4677 | }; | |
4678 | ||
054d4259 VB |
4679 | static const char * const vin2_groups[] = { |
4680 | "vin2_data24", | |
4681 | "vin2_data18", | |
4682 | "vin2_data16", | |
4683 | "vin2_data8", | |
4684 | "vin2_data4", | |
4685 | "vin2_sync", | |
4686 | "vin2_field", | |
4687 | "vin2_clkenb", | |
4688 | "vin2_clk", | |
4689 | }; | |
4690 | ||
4691 | static const char * const vin3_groups[] = { | |
4692 | "vin3_data8", | |
4693 | "vin3_sync", | |
4694 | "vin3_field", | |
4695 | "vin3_clkenb", | |
4696 | "vin3_clk", | |
4697 | }; | |
4698 | ||
60d8fcef WS |
4699 | #define IOCTRL6 0x8c |
4700 | ||
4701 | static int r8a7790_get_io_voltage(struct sh_pfc *pfc, unsigned int pin) | |
4702 | { | |
4703 | u32 data, mask; | |
4704 | ||
4705 | if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin)) | |
4706 | return -EINVAL; | |
4707 | ||
4708 | data = ioread32(pfc->windows->virt + IOCTRL6), | |
4709 | /* Bits in IOCTRL6 are numbered in opposite order to pins */ | |
4710 | mask = 0x80000000 >> (pin & 0x1f); | |
4711 | ||
4712 | return (data & mask) ? 3300 : 1800; | |
4713 | } | |
4714 | ||
4715 | static int r8a7790_set_io_voltage(struct sh_pfc *pfc, unsigned int pin, u16 mV) | |
4716 | { | |
4717 | u32 data, mask; | |
4718 | ||
4719 | if (WARN(pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31), "invalid pin %#x", pin)) | |
4720 | return -EINVAL; | |
4721 | ||
4722 | if (mV != 1800 && mV != 3300) | |
4723 | return -EINVAL; | |
4724 | ||
4725 | data = ioread32(pfc->windows->virt + IOCTRL6); | |
4726 | /* Bits in IOCTRL6 are numbered in opposite order to pins */ | |
4727 | mask = 0x80000000 >> (pin & 0x1f); | |
4728 | ||
4729 | if (mV == 3300) | |
4730 | data |= mask; | |
4731 | else | |
4732 | data &= ~mask; | |
4733 | ||
4734 | iowrite32(~data, pfc->windows->virt); /* unlock reg */ | |
4735 | iowrite32(data, pfc->windows->virt + IOCTRL6); | |
4736 | ||
4737 | return 0; | |
4738 | } | |
4739 | ||
1627769b | 4740 | static const struct sh_pfc_function pinmux_functions[] = { |
fcec5b22 | 4741 | SH_PFC_FUNCTION(audio_clk), |
19ef697d | 4742 | SH_PFC_FUNCTION(avb), |
62783b71 LP |
4743 | SH_PFC_FUNCTION(du), |
4744 | SH_PFC_FUNCTION(du0), | |
4745 | SH_PFC_FUNCTION(du1), | |
4746 | SH_PFC_FUNCTION(du2), | |
1627769b | 4747 | SH_PFC_FUNCTION(eth), |
fbd0ca3d UH |
4748 | SH_PFC_FUNCTION(hscif0), |
4749 | SH_PFC_FUNCTION(hscif1), | |
35a493de | 4750 | SH_PFC_FUNCTION(i2c0), |
70702bfc UH |
4751 | SH_PFC_FUNCTION(i2c1), |
4752 | SH_PFC_FUNCTION(i2c2), | |
f6aaaac9 | 4753 | SH_PFC_FUNCTION(i2c3), |
a16b81dc WS |
4754 | SH_PFC_FUNCTION(iic0), |
4755 | SH_PFC_FUNCTION(iic1), | |
4756 | SH_PFC_FUNCTION(iic2), | |
4757 | SH_PFC_FUNCTION(iic3), | |
04e7ce78 | 4758 | SH_PFC_FUNCTION(intc), |
e29a4c3a | 4759 | SH_PFC_FUNCTION(mlb), |
fbd0ca3d UH |
4760 | SH_PFC_FUNCTION(mmc0), |
4761 | SH_PFC_FUNCTION(mmc1), | |
4f47cc5e KH |
4762 | SH_PFC_FUNCTION(msiof0), |
4763 | SH_PFC_FUNCTION(msiof1), | |
4764 | SH_PFC_FUNCTION(msiof2), | |
4765 | SH_PFC_FUNCTION(msiof3), | |
5c89c15b YS |
4766 | SH_PFC_FUNCTION(pwm0), |
4767 | SH_PFC_FUNCTION(pwm1), | |
4768 | SH_PFC_FUNCTION(pwm2), | |
4769 | SH_PFC_FUNCTION(pwm3), | |
4770 | SH_PFC_FUNCTION(pwm4), | |
4771 | SH_PFC_FUNCTION(pwm5), | |
4772 | SH_PFC_FUNCTION(pwm6), | |
202909cd | 4773 | SH_PFC_FUNCTION(qspi), |
45c6c85d LP |
4774 | SH_PFC_FUNCTION(scif0), |
4775 | SH_PFC_FUNCTION(scif1), | |
2dbe7f2c | 4776 | SH_PFC_FUNCTION(scif2), |
45c6c85d LP |
4777 | SH_PFC_FUNCTION(scifa0), |
4778 | SH_PFC_FUNCTION(scifa1), | |
4779 | SH_PFC_FUNCTION(scifa2), | |
4780 | SH_PFC_FUNCTION(scifb0), | |
4781 | SH_PFC_FUNCTION(scifb1), | |
4782 | SH_PFC_FUNCTION(scifb2), | |
53ec9ccd | 4783 | SH_PFC_FUNCTION(scif_clk), |
066f0d6e GL |
4784 | SH_PFC_FUNCTION(sdhi0), |
4785 | SH_PFC_FUNCTION(sdhi1), | |
4786 | SH_PFC_FUNCTION(sdhi2), | |
4787 | SH_PFC_FUNCTION(sdhi3), | |
1d7b59a0 | 4788 | SH_PFC_FUNCTION(ssi), |
fbd0ca3d | 4789 | SH_PFC_FUNCTION(tpu0), |
dac896e2 SU |
4790 | SH_PFC_FUNCTION(usb0), |
4791 | SH_PFC_FUNCTION(usb1), | |
4792 | SH_PFC_FUNCTION(usb2), | |
e120cacf SU |
4793 | SH_PFC_FUNCTION(vin0), |
4794 | SH_PFC_FUNCTION(vin1), | |
054d4259 VB |
4795 | SH_PFC_FUNCTION(vin2), |
4796 | SH_PFC_FUNCTION(vin3), | |
1627769b LP |
4797 | }; |
4798 | ||
44a45b55 | 4799 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
58c229e1 KM |
4800 | { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { |
4801 | GP_0_31_FN, FN_IP3_17_15, | |
4802 | GP_0_30_FN, FN_IP3_14_12, | |
4803 | GP_0_29_FN, FN_IP3_11_8, | |
4804 | GP_0_28_FN, FN_IP3_7_4, | |
4805 | GP_0_27_FN, FN_IP3_3_0, | |
4806 | GP_0_26_FN, FN_IP2_28_26, | |
4807 | GP_0_25_FN, FN_IP2_25_22, | |
4808 | GP_0_24_FN, FN_IP2_21_18, | |
4809 | GP_0_23_FN, FN_IP2_17_15, | |
4810 | GP_0_22_FN, FN_IP2_14_12, | |
4811 | GP_0_21_FN, FN_IP2_11_9, | |
4812 | GP_0_20_FN, FN_IP2_8_6, | |
4813 | GP_0_19_FN, FN_IP2_5_3, | |
4814 | GP_0_18_FN, FN_IP2_2_0, | |
4815 | GP_0_17_FN, FN_IP1_29_28, | |
4816 | GP_0_16_FN, FN_IP1_27_26, | |
4817 | GP_0_15_FN, FN_IP1_25_22, | |
4818 | GP_0_14_FN, FN_IP1_21_18, | |
4819 | GP_0_13_FN, FN_IP1_17_15, | |
4820 | GP_0_12_FN, FN_IP1_14_12, | |
4821 | GP_0_11_FN, FN_IP1_11_8, | |
4822 | GP_0_10_FN, FN_IP1_7_4, | |
4823 | GP_0_9_FN, FN_IP1_3_0, | |
4824 | GP_0_8_FN, FN_IP0_30_27, | |
4825 | GP_0_7_FN, FN_IP0_26_23, | |
4826 | GP_0_6_FN, FN_IP0_22_20, | |
4827 | GP_0_5_FN, FN_IP0_19_16, | |
4828 | GP_0_4_FN, FN_IP0_15_12, | |
4829 | GP_0_3_FN, FN_IP0_11_9, | |
4830 | GP_0_2_FN, FN_IP0_8_6, | |
4831 | GP_0_1_FN, FN_IP0_5_3, | |
4832 | GP_0_0_FN, FN_IP0_2_0 } | |
4833 | }, | |
4834 | { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { | |
4835 | 0, 0, | |
4836 | 0, 0, | |
4837 | GP_1_29_FN, FN_IP6_13_11, | |
4838 | GP_1_28_FN, FN_IP6_10_9, | |
4839 | GP_1_27_FN, FN_IP6_8_6, | |
4840 | GP_1_26_FN, FN_IP6_5_3, | |
4841 | GP_1_25_FN, FN_IP6_2_0, | |
4842 | GP_1_24_FN, FN_IP5_29_27, | |
4843 | GP_1_23_FN, FN_IP5_26_24, | |
4844 | GP_1_22_FN, FN_IP5_23_21, | |
4845 | GP_1_21_FN, FN_IP5_20_18, | |
4846 | GP_1_20_FN, FN_IP5_17_15, | |
4847 | GP_1_19_FN, FN_IP5_14_13, | |
4848 | GP_1_18_FN, FN_IP5_12_10, | |
4849 | GP_1_17_FN, FN_IP5_9_6, | |
4850 | GP_1_16_FN, FN_IP5_5_3, | |
4851 | GP_1_15_FN, FN_IP5_2_0, | |
4852 | GP_1_14_FN, FN_IP4_29_27, | |
4853 | GP_1_13_FN, FN_IP4_26_24, | |
4854 | GP_1_12_FN, FN_IP4_23_21, | |
4855 | GP_1_11_FN, FN_IP4_20_18, | |
4856 | GP_1_10_FN, FN_IP4_17_15, | |
4857 | GP_1_9_FN, FN_IP4_14_12, | |
4858 | GP_1_8_FN, FN_IP4_11_9, | |
4859 | GP_1_7_FN, FN_IP4_8_6, | |
4860 | GP_1_6_FN, FN_IP4_5_3, | |
4861 | GP_1_5_FN, FN_IP4_2_0, | |
4862 | GP_1_4_FN, FN_IP3_31_29, | |
4863 | GP_1_3_FN, FN_IP3_28_26, | |
4864 | GP_1_2_FN, FN_IP3_25_23, | |
4865 | GP_1_1_FN, FN_IP3_22_20, | |
4866 | GP_1_0_FN, FN_IP3_19_18, } | |
4867 | }, | |
4868 | { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { | |
4869 | 0, 0, | |
4870 | 0, 0, | |
4871 | GP_2_29_FN, FN_IP7_15_13, | |
4872 | GP_2_28_FN, FN_IP7_12_10, | |
4873 | GP_2_27_FN, FN_IP7_9_8, | |
4874 | GP_2_26_FN, FN_IP7_7_6, | |
4875 | GP_2_25_FN, FN_IP7_5_3, | |
4876 | GP_2_24_FN, FN_IP7_2_0, | |
4877 | GP_2_23_FN, FN_IP6_31_29, | |
4878 | GP_2_22_FN, FN_IP6_28_26, | |
4879 | GP_2_21_FN, FN_IP6_25_23, | |
4880 | GP_2_20_FN, FN_IP6_22_20, | |
4881 | GP_2_19_FN, FN_IP6_19_17, | |
4882 | GP_2_18_FN, FN_IP6_16_14, | |
4883 | GP_2_17_FN, FN_VI1_DATA7_VI1_B7, | |
4884 | GP_2_16_FN, FN_IP8_27, | |
4885 | GP_2_15_FN, FN_IP8_26, | |
4886 | GP_2_14_FN, FN_IP8_25_24, | |
4887 | GP_2_13_FN, FN_IP8_23_22, | |
4888 | GP_2_12_FN, FN_IP8_21_20, | |
4889 | GP_2_11_FN, FN_IP8_19_18, | |
4890 | GP_2_10_FN, FN_IP8_17_16, | |
4891 | GP_2_9_FN, FN_IP8_15_14, | |
4892 | GP_2_8_FN, FN_IP8_13_12, | |
4893 | GP_2_7_FN, FN_IP8_11_10, | |
4894 | GP_2_6_FN, FN_IP8_9_8, | |
4895 | GP_2_5_FN, FN_IP8_7_6, | |
4896 | GP_2_4_FN, FN_IP8_5_4, | |
4897 | GP_2_3_FN, FN_IP8_3_2, | |
4898 | GP_2_2_FN, FN_IP8_1_0, | |
4899 | GP_2_1_FN, FN_IP7_30_29, | |
4900 | GP_2_0_FN, FN_IP7_28_27 } | |
4901 | }, | |
4902 | { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { | |
4903 | GP_3_31_FN, FN_IP11_21_18, | |
4904 | GP_3_30_FN, FN_IP11_17_15, | |
4905 | GP_3_29_FN, FN_IP11_14_13, | |
4906 | GP_3_28_FN, FN_IP11_12_11, | |
4907 | GP_3_27_FN, FN_IP11_10_9, | |
4908 | GP_3_26_FN, FN_IP11_8_7, | |
4909 | GP_3_25_FN, FN_IP11_6_5, | |
4910 | GP_3_24_FN, FN_IP11_4, | |
4911 | GP_3_23_FN, FN_IP11_3_0, | |
4912 | GP_3_22_FN, FN_IP10_29_26, | |
4913 | GP_3_21_FN, FN_IP10_25_23, | |
4914 | GP_3_20_FN, FN_IP10_22_19, | |
4915 | GP_3_19_FN, FN_IP10_18_15, | |
4916 | GP_3_18_FN, FN_IP10_14_11, | |
4917 | GP_3_17_FN, FN_IP10_10_7, | |
4918 | GP_3_16_FN, FN_IP10_6_4, | |
4919 | GP_3_15_FN, FN_IP10_3_0, | |
4920 | GP_3_14_FN, FN_IP9_31_28, | |
4921 | GP_3_13_FN, FN_IP9_27_26, | |
4922 | GP_3_12_FN, FN_IP9_25_24, | |
4923 | GP_3_11_FN, FN_IP9_23_22, | |
4924 | GP_3_10_FN, FN_IP9_21_20, | |
4925 | GP_3_9_FN, FN_IP9_19_18, | |
4926 | GP_3_8_FN, FN_IP9_17_16, | |
4927 | GP_3_7_FN, FN_IP9_15_12, | |
4928 | GP_3_6_FN, FN_IP9_11_8, | |
4929 | GP_3_5_FN, FN_IP9_7_6, | |
4930 | GP_3_4_FN, FN_IP9_5_4, | |
4931 | GP_3_3_FN, FN_IP9_3_2, | |
4932 | GP_3_2_FN, FN_IP9_1_0, | |
4933 | GP_3_1_FN, FN_IP8_30_29, | |
4934 | GP_3_0_FN, FN_IP8_28 } | |
4935 | }, | |
4936 | { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { | |
4937 | GP_4_31_FN, FN_IP14_18_16, | |
4938 | GP_4_30_FN, FN_IP14_15_12, | |
4939 | GP_4_29_FN, FN_IP14_11_9, | |
4940 | GP_4_28_FN, FN_IP14_8_6, | |
4941 | GP_4_27_FN, FN_IP14_5_3, | |
4942 | GP_4_26_FN, FN_IP14_2_0, | |
4943 | GP_4_25_FN, FN_IP13_30_29, | |
4944 | GP_4_24_FN, FN_IP13_28_26, | |
4945 | GP_4_23_FN, FN_IP13_25_23, | |
4946 | GP_4_22_FN, FN_IP13_22_19, | |
4947 | GP_4_21_FN, FN_IP13_18_16, | |
4948 | GP_4_20_FN, FN_IP13_15_13, | |
4949 | GP_4_19_FN, FN_IP13_12_10, | |
4950 | GP_4_18_FN, FN_IP13_9_7, | |
4951 | GP_4_17_FN, FN_IP13_6_3, | |
4952 | GP_4_16_FN, FN_IP13_2_0, | |
4953 | GP_4_15_FN, FN_IP12_30_28, | |
4954 | GP_4_14_FN, FN_IP12_27_25, | |
4955 | GP_4_13_FN, FN_IP12_24_23, | |
4956 | GP_4_12_FN, FN_IP12_22_20, | |
4957 | GP_4_11_FN, FN_IP12_19_17, | |
4958 | GP_4_10_FN, FN_IP12_16_14, | |
4959 | GP_4_9_FN, FN_IP12_13_11, | |
4960 | GP_4_8_FN, FN_IP12_10_8, | |
4961 | GP_4_7_FN, FN_IP12_7_6, | |
4962 | GP_4_6_FN, FN_IP12_5_4, | |
4963 | GP_4_5_FN, FN_IP12_3_2, | |
4964 | GP_4_4_FN, FN_IP12_1_0, | |
4965 | GP_4_3_FN, FN_IP11_31_30, | |
4966 | GP_4_2_FN, FN_IP11_29_27, | |
4967 | GP_4_1_FN, FN_IP11_26_24, | |
4968 | GP_4_0_FN, FN_IP11_23_22 } | |
4969 | }, | |
4970 | { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { | |
4971 | GP_5_31_FN, FN_IP7_24_22, | |
4972 | GP_5_30_FN, FN_IP7_21_19, | |
4973 | GP_5_29_FN, FN_IP7_18_16, | |
4974 | GP_5_28_FN, FN_DU_DOTCLKIN2, | |
4975 | GP_5_27_FN, FN_IP7_26_25, | |
4976 | GP_5_26_FN, FN_DU_DOTCLKIN0, | |
4977 | GP_5_25_FN, FN_AVS2, | |
4978 | GP_5_24_FN, FN_AVS1, | |
4979 | GP_5_23_FN, FN_USB2_OVC, | |
4980 | GP_5_22_FN, FN_USB2_PWEN, | |
4981 | GP_5_21_FN, FN_IP16_7, | |
4982 | GP_5_20_FN, FN_IP16_6, | |
4983 | GP_5_19_FN, FN_USB0_OVC_VBUS, | |
4984 | GP_5_18_FN, FN_USB0_PWEN, | |
4985 | GP_5_17_FN, FN_IP16_5_3, | |
4986 | GP_5_16_FN, FN_IP16_2_0, | |
4987 | GP_5_15_FN, FN_IP15_29_28, | |
4988 | GP_5_14_FN, FN_IP15_27_26, | |
4989 | GP_5_13_FN, FN_IP15_25_23, | |
4990 | GP_5_12_FN, FN_IP15_22_20, | |
4991 | GP_5_11_FN, FN_IP15_19_18, | |
4992 | GP_5_10_FN, FN_IP15_17_16, | |
4993 | GP_5_9_FN, FN_IP15_15_14, | |
4994 | GP_5_8_FN, FN_IP15_13_12, | |
4995 | GP_5_7_FN, FN_IP15_11_9, | |
4996 | GP_5_6_FN, FN_IP15_8_6, | |
4997 | GP_5_5_FN, FN_IP15_5_3, | |
4998 | GP_5_4_FN, FN_IP15_2_0, | |
4999 | GP_5_3_FN, FN_IP14_30_28, | |
5000 | GP_5_2_FN, FN_IP14_27_25, | |
5001 | GP_5_1_FN, FN_IP14_24_22, | |
5002 | GP_5_0_FN, FN_IP14_21_19 } | |
5003 | }, | |
5004 | { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, | |
5005 | 1, 4, 4, 3, 4, 4, 3, 3, 3, 3) { | |
5006 | /* IP0_31 [1] */ | |
5007 | 0, 0, | |
5008 | /* IP0_30_27 [4] */ | |
9f2edd41 | 5009 | FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0, |
58c229e1 KM |
5010 | FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0, |
5011 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5012 | /* IP0_26_23 [4] */ | |
c4721249 SK |
5013 | FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C, |
5014 | FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, | |
05bcb07b | 5015 | FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 | 5016 | /* IP0_22_20 [3] */ |
c4721249 SK |
5017 | FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B, |
5018 | FN_I2C2_SCL_C, 0, 0, | |
58c229e1 KM |
5019 | /* IP0_19_16 [4] */ |
5020 | FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5, | |
5021 | FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, | |
5022 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5023 | /* IP0_15_12 [4] */ | |
5024 | FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4, | |
5025 | FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, | |
5026 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5027 | /* IP0_11_9 [3] */ | |
5028 | FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, | |
5029 | 0, 0, 0, | |
5030 | /* IP0_8_6 [3] */ | |
5031 | FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B, | |
5032 | 0, 0, 0, | |
5033 | /* IP0_5_3 [3] */ | |
5034 | FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B, | |
5035 | 0, 0, 0, | |
5036 | /* IP0_2_0 [3] */ | |
5037 | FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B, | |
5038 | 0, 0, 0, } | |
5039 | }, | |
5040 | { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32, | |
5041 | 2, 2, 2, 4, 4, 3, 3, 4, 4, 4) { | |
5042 | /* IP1_31_30 [2] */ | |
5043 | 0, 0, 0, 0, | |
5044 | /* IP1_29_28 [2] */ | |
5045 | FN_A1, FN_PWM4, 0, 0, | |
5046 | /* IP1_27_26 [2] */ | |
5047 | FN_A0, FN_PWM3, 0, 0, | |
5048 | /* IP1_25_22 [4] */ | |
5049 | FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B, | |
5050 | FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7, | |
5051 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5052 | /* IP1_21_18 [4] */ | |
5053 | FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B, | |
5054 | FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6, | |
5055 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5056 | /* IP1_17_15 [3] */ | |
5057 | FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N, | |
5058 | FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, | |
5059 | 0, 0, 0, | |
5060 | /* IP1_14_12 [3] */ | |
5061 | FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4, | |
5062 | FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4, | |
5063 | 0, 0, | |
5064 | /* IP1_11_8 [4] */ | |
9f2edd41 | 5065 | FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0, |
58c229e1 KM |
5066 | FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3, |
5067 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5068 | /* IP1_7_4 [4] */ | |
9f2edd41 | 5069 | FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0, |
58c229e1 KM |
5070 | FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, |
5071 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5072 | /* IP1_3_0 [4] */ | |
9f2edd41 | 5073 | FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0, |
58c229e1 KM |
5074 | FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, |
5075 | 0, 0, 0, 0, 0, 0, 0, 0, 0, } | |
5076 | }, | |
5077 | { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32, | |
5078 | 3, 3, 4, 4, 3, 3, 3, 3, 3, 3) { | |
5079 | /* IP2_31_29 [3] */ | |
5080 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5081 | /* IP2_28_26 [3] */ | |
5082 | FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6, | |
5083 | FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0, | |
5084 | /* IP2_25_22 [4] */ | |
5085 | FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5, | |
1ddb66cd | 5086 | FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B, |
58c229e1 KM |
5087 | 0, 0, 0, 0, 0, 0, 0, 0, |
5088 | /* IP2_21_18 [4] */ | |
5089 | FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4, | |
1ddb66cd | 5090 | FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B, |
58c229e1 KM |
5091 | 0, 0, 0, 0, 0, 0, 0, 0, |
5092 | /* IP2_17_15 [3] */ | |
5093 | FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3, | |
5094 | 0, 0, 0, 0, | |
5095 | /* IP2_14_12 [3] */ | |
5096 | FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0, | |
5097 | /* IP2_11_9 [3] */ | |
5098 | FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0, | |
5099 | /* IP2_8_6 [3] */ | |
5100 | FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0, | |
5101 | /* IP2_5_3 [3] */ | |
5102 | FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0, | |
5103 | /* IP2_2_0 [3] */ | |
5104 | FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, } | |
5105 | }, | |
5106 | { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32, | |
5107 | 3, 3, 3, 3, 2, 3, 3, 4, 4, 4) { | |
5108 | /* IP3_31_29 [3] */ | |
5109 | FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4, | |
5110 | 0, 0, 0, | |
5111 | /* IP3_28_26 [3] */ | |
5112 | FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B, | |
5113 | 0, 0, 0, 0, | |
5114 | /* IP3_25_23 [3] */ | |
5115 | FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0, | |
5116 | /* IP3_22_20 [3] */ | |
5117 | FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0, | |
5118 | /* IP3_19_18 [2] */ | |
5119 | FN_A16, FN_ATAWR1_N, 0, 0, | |
5120 | /* IP3_17_15 [3] */ | |
5121 | FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2, | |
5122 | 0, 0, 0, 0, | |
5123 | /* IP3_14_12 [3] */ | |
5124 | FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1, | |
5125 | 0, 0, 0, 0, | |
5126 | /* IP3_11_8 [4] */ | |
5127 | FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2, | |
5128 | FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2, | |
5129 | FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0, | |
5130 | /* IP3_7_4 [4] */ | |
5131 | FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1, | |
5132 | FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B, | |
5133 | 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
5134 | /* IP3_3_0 [4] */ | |
5135 | FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0, | |
5136 | FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0, | |
5137 | 0, 0, 0, 0, 0, 0, 0, 0, } | |
5138 | }, | |
5139 | { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32, | |
5140 | 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
5141 | /* IP4_31_30 [2] */ | |
5142 | 0, 0, 0, 0, | |
5143 | /* IP4_29_27 [3] */ | |
5144 | FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B, | |
5145 | FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0, | |
5146 | /* IP4_26_24 [3] */ | |
5147 | FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD, | |
5148 | FN_VI1_FIELD_B, FN_VI2_R1, 0, 0, | |
5149 | /* IP4_23_21 [3] */ | |
5150 | FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, | |
5151 | FN_HTX0_B, FN_MSIOF0_SS1_B, 0, | |
5152 | /* IP4_20_18 [3] */ | |
5153 | FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B, | |
5154 | FN_VI2_CLK, FN_VI2_CLK_B, 0, 0, | |
5155 | /* IP4_17_15 [3] */ | |
5156 | FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B, | |
5157 | 0, 0, 0, | |
5158 | /* IP4_14_12 [3] */ | |
5159 | FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD, | |
5160 | FN_VI2_FIELD_B, 0, 0, | |
5161 | /* IP4_11_9 [3] */ | |
5162 | FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB, | |
5163 | FN_VI2_CLKENB_B, 0, 0, | |
5164 | /* IP4_8_6 [3] */ | |
5165 | FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0, | |
5166 | /* IP4_5_3 [3] */ | |
5167 | FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0, | |
5168 | /* IP4_2_0 [3] */ | |
5169 | FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0, | |
5170 | } | |
5171 | }, | |
5172 | { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32, | |
5173 | 2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) { | |
5174 | /* IP5_31_30 [2] */ | |
5175 | 0, 0, 0, 0, | |
5176 | /* IP5_29_27 [3] */ | |
5177 | FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7, | |
5178 | FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0, | |
5179 | /* IP5_26_24 [3] */ | |
5180 | FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N, | |
5181 | FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B, | |
5182 | FN_MSIOF0_SCK_B, 0, | |
5183 | /* IP5_23_21 [3] */ | |
5184 | FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4, | |
34ce57e9 | 5185 | FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C, |
58c229e1 KM |
5186 | /* IP5_20_18 [3] */ |
5187 | FN_WE0_N, FN_IECLK, FN_CAN_CLK, | |
5188 | FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0, | |
5189 | /* IP5_17_15 [3] */ | |
5190 | FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B, | |
5191 | FN_INTC_IRQ4_N, 0, 0, | |
5192 | /* IP5_14_13 [2] */ | |
5193 | FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0, | |
5194 | /* IP5_12_10 [3] */ | |
5195 | FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C, | |
5196 | 0, 0, | |
5197 | /* IP5_9_6 [4] */ | |
5198 | FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, | |
c4721249 SK |
5199 | FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N, |
5200 | FN_I2C1_SDA, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
5201 | /* IP5_5_3 [3] */ |
5202 | FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N, | |
c4721249 SK |
5203 | FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B, |
5204 | FN_INTC_EN0_N, FN_I2C1_SCL, | |
58c229e1 KM |
5205 | /* IP5_2_0 [3] */ |
5206 | FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B, | |
5207 | FN_VI2_R3, 0, 0, } | |
5208 | }, | |
5209 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | |
5210 | 3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) { | |
5211 | /* IP6_31_29 [3] */ | |
9f2edd41 | 5212 | FN_ETH_REF_CLK, 0, FN_HCTS0_N_E, |
58c229e1 KM |
5213 | FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0, |
5214 | /* IP6_28_26 [3] */ | |
9f2edd41 | 5215 | FN_ETH_LINK, 0, FN_HTX0_E, |
58c229e1 KM |
5216 | FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0, |
5217 | /* IP6_25_23 [3] */ | |
9f2edd41 | 5218 | FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B, |
58c229e1 KM |
5219 | FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E, |
5220 | /* IP6_22_20 [3] */ | |
9f2edd41 | 5221 | FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D, |
58c229e1 KM |
5222 | FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0, |
5223 | /* IP6_19_17 [3] */ | |
9f2edd41 | 5224 | FN_ETH_RX_ER, 0, FN_STP_ISD_0_B, |
c4721249 | 5225 | FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0, |
58c229e1 | 5226 | /* IP6_16_14 [3] */ |
9f2edd41 | 5227 | FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B, |
c4721249 SK |
5228 | FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E, |
5229 | FN_I2C2_SCL_E, 0, | |
58c229e1 KM |
5230 | /* IP6_13_11 [3] */ |
5231 | FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N, | |
5232 | FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0, | |
5233 | /* IP6_10_9 [2] */ | |
5234 | FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B, | |
5235 | /* IP6_8_6 [3] */ | |
5236 | FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B, | |
5237 | FN_SSI_SDATA8_C, 0, 0, 0, | |
5238 | /* IP6_5_3 [3] */ | |
5239 | FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B, | |
5240 | FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0, | |
5241 | /* IP6_2_0 [3] */ | |
5242 | FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B, | |
5243 | FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, } | |
5244 | }, | |
5245 | { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, | |
5246 | 1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) { | |
5247 | /* IP7_31 [1] */ | |
5248 | 0, 0, | |
5249 | /* IP7_30_29 [2] */ | |
9f2edd41 | 5250 | FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0, |
58c229e1 | 5251 | /* IP7_28_27 [2] */ |
9f2edd41 | 5252 | FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0, |
58c229e1 | 5253 | /* IP7_26_25 [2] */ |
f0681209 | 5254 | FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0, |
58c229e1 KM |
5255 | /* IP7_24_22 [3] */ |
5256 | FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C, | |
5257 | 0, 0, 0, | |
5258 | /* IP7_21_19 [3] */ | |
5259 | FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, | |
5260 | FN_GLO_RFON_C, FN_PCMOE_N, 0, 0, | |
5261 | /* IP7_18_16 [3] */ | |
5262 | FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C, | |
5263 | FN_GLO_SS_C, 0, 0, 0, | |
5264 | /* IP7_15_13 [3] */ | |
9f2edd41 | 5265 | FN_ETH_MDC, 0, FN_STP_ISD_1_B, |
58c229e1 KM |
5266 | FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0, |
5267 | /* IP7_12_10 [3] */ | |
9f2edd41 | 5268 | FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, |
58c229e1 KM |
5269 | FN_GLO_SCLK_C, 0, 0, 0, |
5270 | /* IP7_9_8 [2] */ | |
9f2edd41 | 5271 | FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0, |
58c229e1 | 5272 | /* IP7_7_6 [2] */ |
9f2edd41 | 5273 | FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F, |
58c229e1 | 5274 | /* IP7_5_3 [3] */ |
14da999b | 5275 | FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0, |
58c229e1 | 5276 | /* IP7_2_0 [3] */ |
9f2edd41 | 5277 | FN_ETH_MDIO, 0, FN_HRTS0_N_E, |
58c229e1 KM |
5278 | FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, } |
5279 | }, | |
5280 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | |
5281 | 1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, | |
5282 | 2, 2, 2, 2, 2, 2, 2) { | |
5283 | /* IP8_31 [1] */ | |
5284 | 0, 0, | |
5285 | /* IP8_30_29 [2] */ | |
5286 | FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0, | |
5287 | /* IP8_28 [1] */ | |
5288 | FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, | |
5289 | /* IP8_27 [1] */ | |
5290 | FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK, | |
5291 | /* IP8_26 [1] */ | |
5292 | FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT, | |
5293 | /* IP8_25_24 [2] */ | |
5294 | FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D, | |
9f2edd41 | 5295 | FN_AVB_MAGIC, 0, |
58c229e1 KM |
5296 | /* IP8_23_22 [2] */ |
5297 | FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0, | |
5298 | /* IP8_21_20 [2] */ | |
9f2edd41 | 5299 | FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0, |
58c229e1 | 5300 | /* IP8_19_18 [2] */ |
9f2edd41 | 5301 | FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0, |
58c229e1 | 5302 | /* IP8_17_16 [2] */ |
9f2edd41 | 5303 | FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0, |
58c229e1 | 5304 | /* IP8_15_14 [2] */ |
9f2edd41 | 5305 | FN_VI1_CLK, FN_AVB_RX_DV, 0, 0, |
58c229e1 | 5306 | /* IP8_13_12 [2] */ |
9f2edd41 | 5307 | FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0, |
58c229e1 | 5308 | /* IP8_11_10 [2] */ |
9f2edd41 | 5309 | FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0, |
58c229e1 KM |
5310 | /* IP8_9_8 [2] */ |
5311 | FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0, | |
5312 | /* IP8_7_6 [2] */ | |
5313 | FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0, | |
5314 | /* IP8_5_4 [2] */ | |
5315 | FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0, | |
5316 | /* IP8_3_2 [2] */ | |
5317 | FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0, | |
5318 | /* IP8_1_0 [2] */ | |
9f2edd41 | 5319 | FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, } |
58c229e1 KM |
5320 | }, |
5321 | { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32, | |
5322 | 4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) { | |
5323 | /* IP9_31_28 [4] */ | |
5324 | FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP, | |
c4721249 | 5325 | FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D, |
58c229e1 KM |
5326 | FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0, |
5327 | /* IP9_27_26 [2] */ | |
9f2edd41 | 5328 | FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B, |
58c229e1 | 5329 | /* IP9_25_24 [2] */ |
9f2edd41 | 5330 | FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B, |
58c229e1 | 5331 | /* IP9_23_22 [2] */ |
9f2edd41 | 5332 | FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B, |
58c229e1 | 5333 | /* IP9_21_20 [2] */ |
9f2edd41 | 5334 | FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B, |
58c229e1 | 5335 | /* IP9_19_18 [2] */ |
9f2edd41 | 5336 | FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B, |
58c229e1 | 5337 | /* IP9_17_16 [2] */ |
9f2edd41 | 5338 | FN_SD1_CLK, FN_AVB_TX_EN, 0, 0, |
58c229e1 KM |
5339 | /* IP9_15_12 [4] */ |
5340 | FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN, | |
c4721249 SK |
5341 | FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B, |
5342 | FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
5343 | /* IP9_11_8 [4] */ |
5344 | FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP, | |
c4721249 SK |
5345 | FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B, |
5346 | FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
5347 | /* IP9_7_6 [2] */ |
5348 | FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0, | |
5349 | /* IP9_5_4 [2] */ | |
5350 | FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0, | |
5351 | /* IP9_3_2 [2] */ | |
5352 | FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0, | |
5353 | /* IP9_1_0 [2] */ | |
5354 | FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, } | |
5355 | }, | |
5356 | { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32, | |
5357 | 2, 4, 3, 4, 4, 4, 4, 3, 4) { | |
5358 | /* IP10_31_30 [2] */ | |
5359 | 0, 0, 0, 0, | |
5360 | /* IP10_29_26 [4] */ | |
5361 | FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0, | |
5362 | FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B, | |
5363 | FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0, | |
5364 | /* IP10_25_23 [3] */ | |
5365 | FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B, | |
5366 | FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B, | |
5367 | /* IP10_22_19 [4] */ | |
14da999b | 5368 | FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0, |
58c229e1 KM |
5369 | FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B, |
5370 | FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0, | |
5371 | /* IP10_18_15 [4] */ | |
14da999b | 5372 | FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0, |
58c229e1 KM |
5373 | FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D, |
5374 | FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B, | |
5375 | 0, 0, 0, 0, 0, 0, | |
5376 | /* IP10_14_11 [4] */ | |
5377 | FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B, | |
5378 | FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D, | |
5379 | FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B, | |
5380 | 0, 0, 0, 0, 0, 0, 0, | |
5381 | /* IP10_10_7 [4] */ | |
5382 | FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D, | |
5383 | FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D, | |
5384 | FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B, | |
5385 | 0, 0, 0, 0, 0, 0, 0, | |
5386 | /* IP10_6_4 [3] */ | |
5387 | FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK, | |
5388 | FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B, | |
5389 | FN_VI3_DATA0_B, 0, | |
5390 | /* IP10_3_0 [4] */ | |
5391 | FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN, | |
c4721249 | 5392 | FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D, |
58c229e1 KM |
5393 | FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, } |
5394 | }, | |
5395 | { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, | |
17babad6 | 5396 | 2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) { |
58c229e1 KM |
5397 | /* IP11_31_30 [2] */ |
5398 | FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0, | |
5399 | /* IP11_29_27 [3] */ | |
7d2b2854 | 5400 | FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C, |
14da999b | 5401 | 0, 0, 0, |
58c229e1 | 5402 | /* IP11_26_24 [3] */ |
c4721249 | 5403 | FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B, |
58c229e1 KM |
5404 | 0, 0, 0, |
5405 | /* IP11_23_22 [2] */ | |
c4721249 | 5406 | FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0, |
58c229e1 KM |
5407 | /* IP11_21_18 [4] */ |
5408 | FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C, | |
14da999b | 5409 | 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
5410 | /* IP11_17_15 [3] */ |
5411 | FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1, | |
5412 | FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0, | |
5413 | /* IP11_14_13 [2] */ | |
5414 | FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0, | |
5415 | /* IP11_12_11 [2] */ | |
5416 | FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0, | |
5417 | /* IP11_10_9 [2] */ | |
5418 | FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0, | |
5419 | /* IP11_8_7 [2] */ | |
5420 | FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0, | |
5421 | /* IP11_6_5 [2] */ | |
5422 | FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0, | |
5423 | /* IP11_4 [1] */ | |
5424 | FN_SD3_CLK, FN_MMC1_CLK, | |
5425 | /* IP11_3_0 [4] */ | |
5426 | FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN, | |
5427 | FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D, | |
5428 | FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, } | |
5429 | }, | |
5430 | { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32, | |
5431 | 1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) { | |
5432 | /* IP12_31 [1] */ | |
5433 | 0, 0, | |
5434 | /* IP12_30_28 [3] */ | |
5435 | FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B, | |
5436 | FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE, | |
5437 | FN_CAN_DEBUGOUT4, 0, 0, | |
5438 | /* IP12_27_25 [3] */ | |
5439 | FN_SSI_SCK5, FN_SCIFB1_SCK, | |
5440 | FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS, | |
5441 | FN_CAN_DEBUGOUT3, 0, 0, | |
5442 | /* IP12_24_23 [2] */ | |
5443 | FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD, | |
5444 | FN_CAN_DEBUGOUT2, | |
5445 | /* IP12_22_20 [3] */ | |
5446 | FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N, | |
5447 | FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0, | |
5448 | /* IP12_19_17 [3] */ | |
5449 | FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N, | |
5450 | FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0, | |
5451 | /* IP12_16_14 [3] */ | |
5452 | FN_SSI_SDATA3, FN_STP_ISCLK_0, | |
5453 | FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0, | |
5454 | /* IP12_13_11 [3] */ | |
5455 | FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC, | |
5456 | FN_CAN_STEP0, 0, 0, 0, | |
5457 | /* IP12_10_8 [3] */ | |
5458 | FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK, | |
5459 | FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0, | |
5460 | /* IP12_7_6 [2] */ | |
5461 | FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6, | |
5462 | /* IP12_5_4 [2] */ | |
5463 | FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0, | |
5464 | /* IP12_3_2 [2] */ | |
5465 | FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0, | |
5466 | /* IP12_1_0 [2] */ | |
5467 | FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, } | |
5468 | }, | |
5469 | { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32, | |
5470 | 1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) { | |
5471 | /* IP13_31 [1] */ | |
5472 | 0, 0, | |
5473 | /* IP13_30_29 [2] */ | |
5474 | FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0, | |
5475 | /* IP13_28_26 [3] */ | |
5476 | FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1, | |
5477 | FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0, | |
5478 | /* IP13_25_23 [3] */ | |
5479 | FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C, | |
5480 | FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0, | |
5481 | /* IP13_22_19 [4] */ | |
5482 | FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N, | |
5483 | FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E, | |
14da999b | 5484 | 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0, |
58c229e1 KM |
5485 | /* IP13_18_16 [3] */ |
5486 | FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, | |
5487 | FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0, | |
5488 | /* IP13_15_13 [3] */ | |
5489 | FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK, | |
5490 | FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0, | |
5491 | /* IP13_12_10 [3] */ | |
14da999b | 5492 | FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5, |
58c229e1 KM |
5493 | FN_CAN_DEBUGOUT8, 0, 0, |
5494 | /* IP13_9_7 [3] */ | |
5495 | FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4, | |
5496 | FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0, | |
5497 | /* IP13_6_3 [4] */ | |
14da999b | 5498 | FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0, |
58c229e1 | 5499 | FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6, |
14da999b | 5500 | FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
5501 | /* IP13_2_0 [3] */ |
5502 | FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2, | |
5503 | FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, } | |
5504 | }, | |
5505 | { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32, | |
5506 | 1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) { | |
5507 | /* IP14_30 [1] */ | |
5508 | 0, 0, | |
5509 | /* IP14_30_28 [3] */ | |
bcec7475 | 5510 | FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N, |
58c229e1 KM |
5511 | FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE, |
5512 | FN_HRTS0_N_C, 0, | |
5513 | /* IP14_27_25 [3] */ | |
5514 | FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD, | |
5515 | FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0, | |
5516 | /* IP14_24_22 [3] */ | |
5517 | FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1, | |
5518 | FN_LCDOUT9, 0, 0, 0, | |
5519 | /* IP14_21_19 [3] */ | |
5520 | FN_SCIFA1_RXD, FN_AD_DI, FN_RX1, | |
5521 | FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0, | |
5522 | /* IP14_18_16 [3] */ | |
bcec7475 | 5523 | FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N, |
58c229e1 KM |
5524 | FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0, |
5525 | /* IP14_15_12 [4] */ | |
5526 | FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, | |
c4721249 | 5527 | FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C, |
58c229e1 KM |
5528 | 0, 0, 0, 0, 0, 0, 0, |
5529 | /* IP14_11_9 [3] */ | |
5530 | FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1, | |
5531 | 0, 0, 0, | |
5532 | /* IP14_8_6 [3] */ | |
5533 | FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0, | |
5534 | 0, 0, 0, | |
5535 | /* IP14_5_3 [3] */ | |
5536 | FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2, | |
c4721249 | 5537 | FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C, |
58c229e1 KM |
5538 | /* IP14_2_0 [3] */ |
5539 | FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D, | |
5540 | FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15, | |
5541 | FN_REMOCON, 0, } | |
5542 | }, | |
5543 | { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32, | |
5544 | 2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) { | |
5545 | /* IP15_31_30 [2] */ | |
5546 | 0, 0, 0, 0, | |
5547 | /* IP15_29_28 [2] */ | |
5548 | FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14, | |
5549 | /* IP15_27_26 [2] */ | |
5550 | FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13, | |
5551 | /* IP15_25_23 [3] */ | |
5552 | FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA, | |
5de880dd | 5553 | FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0, |
58c229e1 KM |
5554 | /* IP15_22_20 [3] */ |
5555 | FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK, | |
5556 | FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0, | |
5557 | /* IP15_19_18 [2] */ | |
5558 | FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21, | |
5559 | /* IP15_17_16 [2] */ | |
5560 | FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20, | |
5561 | /* IP15_15_14 [2] */ | |
5562 | FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0, | |
5563 | /* IP15_13_12 [2] */ | |
5564 | FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0, | |
5565 | /* IP15_11_9 [3] */ | |
5566 | FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, | |
5567 | 0, 0, 0, | |
5568 | /* IP15_8_6 [3] */ | |
1ddb66cd | 5569 | FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17, |
c4721249 | 5570 | FN_IIC2_SDA, FN_I2C2_SDA, 0, |
58c229e1 | 5571 | /* IP15_5_3 [3] */ |
1ddb66cd | 5572 | FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16, |
c4721249 | 5573 | FN_IIC2_SCL, FN_I2C2_SCL, 0, |
58c229e1 | 5574 | /* IP15_2_0 [3] */ |
1ddb66cd | 5575 | FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7, |
58c229e1 KM |
5576 | FN_LCDOUT15, FN_SCIF_CLK_B, 0, } |
5577 | }, | |
5578 | { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32, | |
5579 | 4, 4, 4, 4, 4, 4, 1, 1, 3, 3) { | |
5580 | /* IP16_31_28 [4] */ | |
5581 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5582 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5583 | /* IP16_27_24 [4] */ | |
5584 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5585 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5586 | /* IP16_23_20 [4] */ | |
5587 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5588 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5589 | /* IP16_19_16 [4] */ | |
5590 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5591 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5592 | /* IP16_15_12 [4] */ | |
5593 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5594 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5595 | /* IP16_11_8 [4] */ | |
5596 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5597 | 0, 0, 0, 0, 0, 0, 0, 0, | |
5598 | /* IP16_7 [1] */ | |
5599 | FN_USB1_OVC, FN_TCLK1_B, | |
5600 | /* IP16_6 [1] */ | |
5601 | FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, | |
5602 | /* IP16_5_3 [3] */ | |
5603 | FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2, | |
5de880dd | 5604 | FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0, |
58c229e1 KM |
5605 | /* IP16_2_0 [3] */ |
5606 | FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2, | |
5607 | FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, } | |
5608 | }, | |
5609 | { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, | |
5610 | 3, 2, 2, 3, 2, 1, 1, 1, 2, 1, | |
5611 | 2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) { | |
5612 | /* SEL_SCIF1 [3] */ | |
5613 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, | |
5614 | FN_SEL_SCIF1_4, 0, 0, 0, | |
5615 | /* SEL_SCIFB [2] */ | |
5616 | FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0, | |
5617 | /* SEL_SCIFB2 [2] */ | |
5618 | FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0, | |
5619 | /* SEL_SCIFB1 [3] */ | |
5620 | FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, | |
5621 | FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5, | |
5622 | FN_SEL_SCIFB1_6, 0, | |
5623 | /* SEL_SCIFA1 [2] */ | |
5624 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, | |
5625 | FN_SEL_SCIFA1_3, | |
5626 | /* SEL_SCIF0 [1] */ | |
5627 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, | |
5628 | /* SEL_SCIFA [1] */ | |
5629 | FN_SEL_SCFA_0, FN_SEL_SCFA_1, | |
5630 | /* SEL_SOF1 [1] */ | |
5631 | FN_SEL_SOF1_0, FN_SEL_SOF1_1, | |
5632 | /* SEL_SSI7 [2] */ | |
5633 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0, | |
5634 | /* SEL_SSI6 [1] */ | |
5635 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
5636 | /* SEL_SSI5 [2] */ | |
5637 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0, | |
5638 | /* SEL_VI3 [1] */ | |
5639 | FN_SEL_VI3_0, FN_SEL_VI3_1, | |
5640 | /* SEL_VI2 [1] */ | |
5641 | FN_SEL_VI2_0, FN_SEL_VI2_1, | |
5642 | /* SEL_VI1 [1] */ | |
5643 | FN_SEL_VI1_0, FN_SEL_VI1_1, | |
5644 | /* SEL_VI0 [1] */ | |
5645 | FN_SEL_VI0_0, FN_SEL_VI0_1, | |
5646 | /* SEL_TSIF1 [2] */ | |
5647 | FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0, | |
5648 | /* RESERVED [1] */ | |
5649 | 0, 0, | |
5650 | /* SEL_LBS [1] */ | |
5651 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
5652 | /* SEL_TSIF0 [2] */ | |
5653 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
5654 | /* SEL_SOF3 [1] */ | |
5655 | FN_SEL_SOF3_0, FN_SEL_SOF3_1, | |
5656 | /* SEL_SOF0 [1] */ | |
5657 | FN_SEL_SOF0_0, FN_SEL_SOF0_1, } | |
5658 | }, | |
5659 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, | |
17babad6 GL |
5660 | 3, 1, 1, 1, 2, 1, 2, 1, 2, |
5661 | 1, 1, 1, 3, 3, 2, 3, 2, 2) { | |
7f35184b | 5662 | /* RESERVED [3] */ |
58c229e1 | 5663 | 0, 0, 0, 0, 0, 0, 0, 0, |
58c229e1 KM |
5664 | /* SEL_TMU1 [1] */ |
5665 | FN_SEL_TMU1_0, FN_SEL_TMU1_1, | |
5666 | /* SEL_HSCIF1 [1] */ | |
5667 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
5668 | /* SEL_SCIFCLK [1] */ | |
5669 | FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1, | |
5670 | /* SEL_CAN0 [2] */ | |
5671 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
5672 | /* SEL_CANCLK [1] */ | |
5673 | FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, | |
5674 | /* SEL_SCIFA2 [2] */ | |
5675 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0, | |
5676 | /* SEL_CAN1 [1] */ | |
5677 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
7f35184b | 5678 | /* RESERVED [2] */ |
17babad6 | 5679 | 0, 0, 0, 0, |
1ddb66cd SK |
5680 | /* SEL_SCIF2 [1] */ |
5681 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, | |
58c229e1 KM |
5682 | /* SEL_ADI [1] */ |
5683 | FN_SEL_ADI_0, FN_SEL_ADI_1, | |
5684 | /* SEL_SSP [1] */ | |
5685 | FN_SEL_SSP_0, FN_SEL_SSP_1, | |
5686 | /* SEL_FM [3] */ | |
5687 | FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, | |
5688 | FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0, | |
5689 | /* SEL_HSCIF0 [3] */ | |
5690 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, | |
5691 | FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0, | |
5692 | /* SEL_GPS [2] */ | |
5693 | FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0, | |
14da999b SK |
5694 | /* RESERVED [3] */ |
5695 | 0, 0, 0, 0, 0, 0, 0, 0, | |
58c229e1 KM |
5696 | /* SEL_SIM [2] */ |
5697 | FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0, | |
5698 | /* SEL_SSI8 [2] */ | |
5699 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, } | |
5700 | }, | |
5701 | { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, | |
5702 | 1, 1, 2, 4, 4, 2, 2, | |
5703 | 4, 2, 3, 2, 3, 2) { | |
5704 | /* SEL_IICDVFS [1] */ | |
5705 | FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1, | |
5706 | /* SEL_IIC0 [1] */ | |
5707 | FN_SEL_IIC0_0, FN_SEL_IIC0_1, | |
7f35184b | 5708 | /* RESERVED [2] */ |
58c229e1 | 5709 | 0, 0, 0, 0, |
7f35184b | 5710 | /* RESERVED [4] */ |
58c229e1 KM |
5711 | 0, 0, 0, 0, 0, 0, 0, 0, |
5712 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 5713 | /* RESERVED [4] */ |
58c229e1 KM |
5714 | 0, 0, 0, 0, 0, 0, 0, 0, |
5715 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 5716 | /* RESERVED [2] */ |
58c229e1 KM |
5717 | 0, 0, 0, 0, |
5718 | /* SEL_IEB [2] */ | |
5719 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, | |
7f35184b | 5720 | /* RESERVED [4] */ |
58c229e1 KM |
5721 | 0, 0, 0, 0, 0, 0, 0, 0, |
5722 | 0, 0, 0, 0, 0, 0, 0, 0, | |
7f35184b | 5723 | /* RESERVED [2] */ |
58c229e1 KM |
5724 | 0, 0, 0, 0, |
5725 | /* SEL_IIC2 [3] */ | |
5726 | FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3, | |
5727 | FN_SEL_IIC2_4, 0, 0, 0, | |
5728 | /* SEL_IIC1 [2] */ | |
5729 | FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0, | |
5730 | /* SEL_I2C2 [3] */ | |
5731 | FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3, | |
5732 | FN_SEL_I2C2_4, 0, 0, 0, | |
5733 | /* SEL_I2C1 [2] */ | |
5734 | FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, } | |
5735 | }, | |
58c229e1 KM |
5736 | { }, |
5737 | }; | |
5738 | ||
60d8fcef WS |
5739 | static const struct sh_pfc_soc_operations pinmux_ops = { |
5740 | .get_io_voltage = r8a7790_get_io_voltage, | |
5741 | .set_io_voltage = r8a7790_set_io_voltage, | |
5742 | }; | |
5743 | ||
58c229e1 KM |
5744 | const struct sh_pfc_soc_info r8a7790_pinmux_info = { |
5745 | .name = "r8a77900_pfc", | |
60d8fcef | 5746 | .ops = &pinmux_ops, |
58c229e1 KM |
5747 | .unlock_reg = 0xe6060000, /* PMMR */ |
5748 | ||
58c229e1 KM |
5749 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
5750 | ||
5751 | .pins = pinmux_pins, | |
5752 | .nr_pins = ARRAY_SIZE(pinmux_pins), | |
1627769b LP |
5753 | .groups = pinmux_groups, |
5754 | .nr_groups = ARRAY_SIZE(pinmux_groups), | |
5755 | .functions = pinmux_functions, | |
5756 | .nr_functions = ARRAY_SIZE(pinmux_functions), | |
58c229e1 | 5757 | |
58c229e1 | 5758 | .cfg_regs = pinmux_config_regs, |
58c229e1 | 5759 | |
b8b47d67 GU |
5760 | .pinmux_data = pinmux_data, |
5761 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), | |
58c229e1 | 5762 | }; |