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Merge branch 'smp-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524
UH		 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 64#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
b205914c
GU		 105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
b205914c
GU		 123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
b205914c
GU		 143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 146#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 148#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 151#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 169
170/* GPSR6 */
f9d13080
YS		 171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
bad7cc19
TK		 363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
371 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
b205914c
GU		 439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
b205914c 506#define PINMUX_MOD_SELS \
0b0ffc96 507\
b205914c
GU		 508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
0b0ffc96 510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 514MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 515MOD_SEL0_22 \
b205914c
GU		 516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 522 MOD_SEL1_15_14 \
b205914c
GU		 523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
0b0ffc96
TK		 525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
b205914c 528MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
b205914c
GU		 531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
0b0ffc96
TK		 535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
ea9c7405
NS		 538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 554
555enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562#define F_(x, y)
563#define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570#undef F_
571#undef FM
572
573#define F_(x, y)
574#define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
ea9c7405 579 PINMUX_STATIC
0b0ffc96
TK		 580 PINMUX_MARK_END,
581#undef F_
582#undef FM
583};
584
585static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
8d4df573
GU		 588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
590 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 592 PINMUX_SINGLE(I2C_SEL_0_1),
593 PINMUX_SINGLE(I2C_SEL_3_1),
594 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
0b0ffc96 602 /* IPSR0 */
e01678e3 603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
e01678e3 606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
e01678e3 610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
e01678e3 614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 621 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 622
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
626
e01678e3
GU		 627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
629 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 630 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 633 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 634
e01678e3
GU		 635 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
636 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
637 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 638 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 641 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 642
643 /* IPSR1 */
e01678e3
GU		 644 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
645 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
646 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 647 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 649 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 650
e01678e3
GU		 651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 658
e01678e3
GU		 659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 666
e01678e3
GU		 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 675
e01678e3
GU		 676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
e01678e3
GU		 693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
e01678e3
GU		 701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
e01678e3
GU		 708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
e01678e3
GU		 715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
e01678e3
GU		 722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 728
e01678e3
GU		 729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 736
e01678e3
GU		 737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 744
e01678e3
GU		 745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 752
e01678e3 753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
e01678e3 762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 766
e01678e3 767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 771
e01678e3 772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
e01678e3
GU		 782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 788
e01678e3
GU		 789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 795
e01678e3
GU		 796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 802
e01678e3
GU		 803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 809
e01678e3
GU		 810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 814
815 /* IPSR4 */
e01678e3
GU		 816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
fc8fd9be 834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
e01678e3
GU		 838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
e01678e3 847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
e01678e3 854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
e01678e3 862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
e01678e3 870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 883
e01678e3 884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 889
e01678e3 890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 895
e01678e3 896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 900
e01678e3 901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 905
e01678e3 906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 910
911 /* IPSR6 */
e01678e3 912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 916
b205914c
GU		 917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 921
b205914c
GU		 922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 926
b205914c
GU		 927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 933
b205914c
GU		 934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 939
b205914c
GU		 940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 947
b205914c
GU		 948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 955
b205914c
GU		 956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 962
b205914c
GU		 963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 970
b205914c
GU		 971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 978
b205914c
GU		 979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 986
b205914c
GU		 987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 994
b205914c
GU		 995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 999
b205914c
GU		 1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1004
b205914c
GU		 1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1010
b205914c
GU		 1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1015
b205914c
GU		 1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1019
b205914c
GU		 1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1025
b205914c
GU		 1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1032
b205914c
GU		 1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1039
b205914c
GU		 1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1046
b205914c
GU		 1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1053
b205914c
GU		 1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1057
b205914c
GU		 1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1060
b205914c
GU		 1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1063
b205914c
GU		 1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1066
b205914c
GU		 1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1069
b205914c
GU		 1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1072
b205914c
GU		 1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1076
b205914c
GU		 1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1079
b205914c
GU		 1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1083
b205914c
GU		 1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1086
b205914c
GU		 1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1089
b205914c
GU		 1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1092
b205914c
GU		 1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1095
b205914c
GU		 1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1103
b205914c
GU		 1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1107
b205914c
GU		 1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
1123 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1145
b205914c
GU		 1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1206
b205914c
GU		 1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1266
b205914c
GU		 1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c
GU		 1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1307
b205914c
GU		 1308 /* IPSR15 */
1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1310
1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1313
68e63892 1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1354
b205914c
GU		 1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1409
b205914c
GU		 1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
f9d13080 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
f9d13080 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1497
b205914c
GU		 1498/*
1499 * Static pins can not be muxed between different functions but
1500 * still needs a mark entry in the pinmux list. Add each static
1501 * pin to the list without an associated function. The sh-pfc
1502 * core will do the right thing and skip trying to mux then pin
1503 * while still applying configuration to it
1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
9b132ba3
KM		 1508};
1509
b205914c 1510/*
ecd54509 1511 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
b205914c
GU		 1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
6f4b74f3 1517#define PIN_NONE U16_MAX
b205914c
GU		 1518
1519static const struct sh_pfc_pin pinmux_pins[] = {
1520 PINMUX_GPIO_GP_ALL(),
76250a6c 1521
b205914c
GU		 1522 /*
1523 * Pins not associated with a GPIO port.
1524 *
1525 * The pin positions are different between different r8a7795
1526 * packages, all that is needed for the pfc driver is a unique
1527 * number for each pin. To this end use the pin layout from
1528 * R-Car H3SiP to calculate a unique number for each pin.
1529 */
1530 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1574};
1575
55bfea9f
KM		 1576/* - AUDIO CLOCK ------------------------------------------------------------ */
1577static const unsigned int audio_clk_a_a_pins[] = {
1578 /* CLK A */
1579 RCAR_GP_PIN(6, 22),
1580};
1581static const unsigned int audio_clk_a_a_mux[] = {
1582 AUDIO_CLKA_A_MARK,
1583};
1584static const unsigned int audio_clk_a_b_pins[] = {
1585 /* CLK A */
1586 RCAR_GP_PIN(5, 4),
1587};
1588static const unsigned int audio_clk_a_b_mux[] = {
1589 AUDIO_CLKA_B_MARK,
1590};
1591static const unsigned int audio_clk_a_c_pins[] = {
1592 /* CLK A */
1593 RCAR_GP_PIN(5, 19),
1594};
1595static const unsigned int audio_clk_a_c_mux[] = {
1596 AUDIO_CLKA_C_MARK,
1597};
1598static const unsigned int audio_clk_b_a_pins[] = {
1599 /* CLK B */
1600 RCAR_GP_PIN(5, 12),
1601};
1602static const unsigned int audio_clk_b_a_mux[] = {
1603 AUDIO_CLKB_A_MARK,
1604};
1605static const unsigned int audio_clk_b_b_pins[] = {
1606 /* CLK B */
1607 RCAR_GP_PIN(6, 23),
1608};
1609static const unsigned int audio_clk_b_b_mux[] = {
1610 AUDIO_CLKB_B_MARK,
1611};
1612static const unsigned int audio_clk_c_a_pins[] = {
1613 /* CLK C */
1614 RCAR_GP_PIN(5, 21),
1615};
1616static const unsigned int audio_clk_c_a_mux[] = {
1617 AUDIO_CLKC_A_MARK,
1618};
1619static const unsigned int audio_clk_c_b_pins[] = {
1620 /* CLK C */
1621 RCAR_GP_PIN(5, 0),
1622};
1623static const unsigned int audio_clk_c_b_mux[] = {
1624 AUDIO_CLKC_B_MARK,
1625};
1626static const unsigned int audio_clkout_a_pins[] = {
1627 /* CLKOUT */
1628 RCAR_GP_PIN(5, 18),
1629};
1630static const unsigned int audio_clkout_a_mux[] = {
1631 AUDIO_CLKOUT_A_MARK,
1632};
1633static const unsigned int audio_clkout_b_pins[] = {
1634 /* CLKOUT */
1635 RCAR_GP_PIN(6, 28),
1636};
1637static const unsigned int audio_clkout_b_mux[] = {
1638 AUDIO_CLKOUT_B_MARK,
1639};
1640static const unsigned int audio_clkout_c_pins[] = {
1641 /* CLKOUT */
1642 RCAR_GP_PIN(5, 3),
1643};
1644static const unsigned int audio_clkout_c_mux[] = {
1645 AUDIO_CLKOUT_C_MARK,
1646};
1647static const unsigned int audio_clkout_d_pins[] = {
1648 /* CLKOUT */
1649 RCAR_GP_PIN(5, 21),
1650};
1651static const unsigned int audio_clkout_d_mux[] = {
1652 AUDIO_CLKOUT_D_MARK,
1653};
1654static const unsigned int audio_clkout1_a_pins[] = {
1655 /* CLKOUT1 */
1656 RCAR_GP_PIN(5, 15),
1657};
1658static const unsigned int audio_clkout1_a_mux[] = {
1659 AUDIO_CLKOUT1_A_MARK,
1660};
1661static const unsigned int audio_clkout1_b_pins[] = {
1662 /* CLKOUT1 */
1663 RCAR_GP_PIN(6, 29),
1664};
1665static const unsigned int audio_clkout1_b_mux[] = {
1666 AUDIO_CLKOUT1_B_MARK,
1667};
1668static const unsigned int audio_clkout2_a_pins[] = {
1669 /* CLKOUT2 */
1670 RCAR_GP_PIN(5, 16),
1671};
1672static const unsigned int audio_clkout2_a_mux[] = {
1673 AUDIO_CLKOUT2_A_MARK,
1674};
1675static const unsigned int audio_clkout2_b_pins[] = {
1676 /* CLKOUT2 */
1677 RCAR_GP_PIN(6, 30),
1678};
1679static const unsigned int audio_clkout2_b_mux[] = {
1680 AUDIO_CLKOUT2_B_MARK,
1681};
1682static const unsigned int audio_clkout3_a_pins[] = {
1683 /* CLKOUT3 */
1684 RCAR_GP_PIN(5, 19),
1685};
1686static const unsigned int audio_clkout3_a_mux[] = {
1687 AUDIO_CLKOUT3_A_MARK,
1688};
1689static const unsigned int audio_clkout3_b_pins[] = {
1690 /* CLKOUT3 */
1691 RCAR_GP_PIN(6, 31),
1692};
1693static const unsigned int audio_clkout3_b_mux[] = {
1694 AUDIO_CLKOUT3_B_MARK,
1695};
1696
30c078de
GU		 1697/* - EtherAVB --------------------------------------------------------------- */
1698static const unsigned int avb_link_pins[] = {
1699 /* AVB_LINK */
1700 RCAR_GP_PIN(2, 12),
1701};
1702static const unsigned int avb_link_mux[] = {
1703 AVB_LINK_MARK,
1704};
1705static const unsigned int avb_magic_pins[] = {
1706 /* AVB_MAGIC_ */
1707 RCAR_GP_PIN(2, 10),
1708};
1709static const unsigned int avb_magic_mux[] = {
1710 AVB_MAGIC_MARK,
1711};
1712static const unsigned int avb_phy_int_pins[] = {
1713 /* AVB_PHY_INT */
1714 RCAR_GP_PIN(2, 11),
1715};
1716static const unsigned int avb_phy_int_mux[] = {
1717 AVB_PHY_INT_MARK,
1718};
1719static const unsigned int avb_mdc_pins[] = {
1720 /* AVB_MDC, AVB_MDIO */
1721 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1722};
1723static const unsigned int avb_mdc_mux[] = {
1724 AVB_MDC_MARK, AVB_MDIO_MARK,
1725};
1726static const unsigned int avb_mii_pins[] = {
1727 /*
1728 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1729 * AVB_TD1, AVB_TD2, AVB_TD3,
1730 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1731 * AVB_RD1, AVB_RD2, AVB_RD3,
1732 * AVB_TXCREFCLK
1733 */
1734 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1735 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1736 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1737 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1738 PIN_NUMBER('A', 12),
1739
1740};
1741static const unsigned int avb_mii_mux[] = {
1742 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1743 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1744 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1745 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1746 AVB_TXCREFCLK_MARK,
1747};
1748static const unsigned int avb_avtp_pps_pins[] = {
1749 /* AVB_AVTP_PPS */
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int avb_avtp_pps_mux[] = {
1753 AVB_AVTP_PPS_MARK,
1754};
1755static const unsigned int avb_avtp_match_a_pins[] = {
1756 /* AVB_AVTP_MATCH_A */
1757 RCAR_GP_PIN(2, 13),
1758};
1759static const unsigned int avb_avtp_match_a_mux[] = {
1760 AVB_AVTP_MATCH_A_MARK,
1761};
1762static const unsigned int avb_avtp_capture_a_pins[] = {
1763 /* AVB_AVTP_CAPTURE_A */
1764 RCAR_GP_PIN(2, 14),
1765};
1766static const unsigned int avb_avtp_capture_a_mux[] = {
1767 AVB_AVTP_CAPTURE_A_MARK,
1768};
1769static const unsigned int avb_avtp_match_b_pins[] = {
1770 /* AVB_AVTP_MATCH_B */
1771 RCAR_GP_PIN(1, 8),
1772};
1773static const unsigned int avb_avtp_match_b_mux[] = {
1774 AVB_AVTP_MATCH_B_MARK,
1775};
1776static const unsigned int avb_avtp_capture_b_pins[] = {
1777 /* AVB_AVTP_CAPTURE_B */
1778 RCAR_GP_PIN(1, 11),
1779};
1780static const unsigned int avb_avtp_capture_b_mux[] = {
1781 AVB_AVTP_CAPTURE_B_MARK,
1782};
1783
641b0ab8
DB		 1784/* - DRIF0 --------------------------------------------------------------- */
1785static const unsigned int drif0_ctrl_a_pins[] = {
1786 /* CLK, SYNC */
1787 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1788};
1789static const unsigned int drif0_ctrl_a_mux[] = {
1790 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1791};
1792static const unsigned int drif0_data0_a_pins[] = {
1793 /* D0 */
1794 RCAR_GP_PIN(6, 10),
1795};
1796static const unsigned int drif0_data0_a_mux[] = {
1797 RIF0_D0_A_MARK,
1798};
1799static const unsigned int drif0_data1_a_pins[] = {
1800 /* D1 */
1801 RCAR_GP_PIN(6, 7),
1802};
1803static const unsigned int drif0_data1_a_mux[] = {
1804 RIF0_D1_A_MARK,
1805};
1806static const unsigned int drif0_ctrl_b_pins[] = {
1807 /* CLK, SYNC */
1808 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1809};
1810static const unsigned int drif0_ctrl_b_mux[] = {
1811 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1812};
1813static const unsigned int drif0_data0_b_pins[] = {
1814 /* D0 */
1815 RCAR_GP_PIN(5, 1),
1816};
1817static const unsigned int drif0_data0_b_mux[] = {
1818 RIF0_D0_B_MARK,
1819};
1820static const unsigned int drif0_data1_b_pins[] = {
1821 /* D1 */
1822 RCAR_GP_PIN(5, 2),
1823};
1824static const unsigned int drif0_data1_b_mux[] = {
1825 RIF0_D1_B_MARK,
1826};
1827static const unsigned int drif0_ctrl_c_pins[] = {
1828 /* CLK, SYNC */
1829 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1830};
1831static const unsigned int drif0_ctrl_c_mux[] = {
1832 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1833};
1834static const unsigned int drif0_data0_c_pins[] = {
1835 /* D0 */
1836 RCAR_GP_PIN(5, 13),
1837};
1838static const unsigned int drif0_data0_c_mux[] = {
1839 RIF0_D0_C_MARK,
1840};
1841static const unsigned int drif0_data1_c_pins[] = {
1842 /* D1 */
1843 RCAR_GP_PIN(5, 14),
1844};
1845static const unsigned int drif0_data1_c_mux[] = {
1846 RIF0_D1_C_MARK,
1847};
1848/* - DRIF1 --------------------------------------------------------------- */
1849static const unsigned int drif1_ctrl_a_pins[] = {
1850 /* CLK, SYNC */
1851 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1852};
1853static const unsigned int drif1_ctrl_a_mux[] = {
1854 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1855};
1856static const unsigned int drif1_data0_a_pins[] = {
1857 /* D0 */
1858 RCAR_GP_PIN(6, 19),
1859};
1860static const unsigned int drif1_data0_a_mux[] = {
1861 RIF1_D0_A_MARK,
1862};
1863static const unsigned int drif1_data1_a_pins[] = {
1864 /* D1 */
1865 RCAR_GP_PIN(6, 20),
1866};
1867static const unsigned int drif1_data1_a_mux[] = {
1868 RIF1_D1_A_MARK,
1869};
1870static const unsigned int drif1_ctrl_b_pins[] = {
1871 /* CLK, SYNC */
1872 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1873};
1874static const unsigned int drif1_ctrl_b_mux[] = {
1875 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1876};
1877static const unsigned int drif1_data0_b_pins[] = {
1878 /* D0 */
1879 RCAR_GP_PIN(5, 7),
1880};
1881static const unsigned int drif1_data0_b_mux[] = {
1882 RIF1_D0_B_MARK,
1883};
1884static const unsigned int drif1_data1_b_pins[] = {
1885 /* D1 */
1886 RCAR_GP_PIN(5, 8),
1887};
1888static const unsigned int drif1_data1_b_mux[] = {
1889 RIF1_D1_B_MARK,
1890};
1891static const unsigned int drif1_ctrl_c_pins[] = {
1892 /* CLK, SYNC */
1893 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1894};
1895static const unsigned int drif1_ctrl_c_mux[] = {
1896 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1897};
1898static const unsigned int drif1_data0_c_pins[] = {
1899 /* D0 */
1900 RCAR_GP_PIN(5, 6),
1901};
1902static const unsigned int drif1_data0_c_mux[] = {
1903 RIF1_D0_C_MARK,
1904};
1905static const unsigned int drif1_data1_c_pins[] = {
1906 /* D1 */
1907 RCAR_GP_PIN(5, 10),
1908};
1909static const unsigned int drif1_data1_c_mux[] = {
1910 RIF1_D1_C_MARK,
1911};
1912/* - DRIF2 --------------------------------------------------------------- */
1913static const unsigned int drif2_ctrl_a_pins[] = {
1914 /* CLK, SYNC */
1915 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1916};
1917static const unsigned int drif2_ctrl_a_mux[] = {
1918 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1919};
1920static const unsigned int drif2_data0_a_pins[] = {
1921 /* D0 */
1922 RCAR_GP_PIN(6, 7),
1923};
1924static const unsigned int drif2_data0_a_mux[] = {
1925 RIF2_D0_A_MARK,
1926};
1927static const unsigned int drif2_data1_a_pins[] = {
1928 /* D1 */
1929 RCAR_GP_PIN(6, 10),
1930};
1931static const unsigned int drif2_data1_a_mux[] = {
1932 RIF2_D1_A_MARK,
1933};
1934static const unsigned int drif2_ctrl_b_pins[] = {
1935 /* CLK, SYNC */
1936 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1937};
1938static const unsigned int drif2_ctrl_b_mux[] = {
1939 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1940};
1941static const unsigned int drif2_data0_b_pins[] = {
1942 /* D0 */
1943 RCAR_GP_PIN(6, 30),
1944};
1945static const unsigned int drif2_data0_b_mux[] = {
1946 RIF2_D0_B_MARK,
1947};
1948static const unsigned int drif2_data1_b_pins[] = {
1949 /* D1 */
1950 RCAR_GP_PIN(6, 31),
1951};
1952static const unsigned int drif2_data1_b_mux[] = {
1953 RIF2_D1_B_MARK,
1954};
1955/* - DRIF3 --------------------------------------------------------------- */
1956static const unsigned int drif3_ctrl_a_pins[] = {
1957 /* CLK, SYNC */
1958 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1959};
1960static const unsigned int drif3_ctrl_a_mux[] = {
1961 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1962};
1963static const unsigned int drif3_data0_a_pins[] = {
1964 /* D0 */
1965 RCAR_GP_PIN(6, 19),
1966};
1967static const unsigned int drif3_data0_a_mux[] = {
1968 RIF3_D0_A_MARK,
1969};
1970static const unsigned int drif3_data1_a_pins[] = {
1971 /* D1 */
1972 RCAR_GP_PIN(6, 20),
1973};
1974static const unsigned int drif3_data1_a_mux[] = {
1975 RIF3_D1_A_MARK,
1976};
1977static const unsigned int drif3_ctrl_b_pins[] = {
1978 /* CLK, SYNC */
1979 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1980};
1981static const unsigned int drif3_ctrl_b_mux[] = {
1982 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1983};
1984static const unsigned int drif3_data0_b_pins[] = {
1985 /* D0 */
1986 RCAR_GP_PIN(6, 28),
1987};
1988static const unsigned int drif3_data0_b_mux[] = {
1989 RIF3_D0_B_MARK,
1990};
1991static const unsigned int drif3_data1_b_pins[] = {
1992 /* D1 */
1993 RCAR_GP_PIN(6, 29),
1994};
1995static const unsigned int drif3_data1_b_mux[] = {
1996 RIF3_D1_B_MARK,
1997};
1998
a20a6585
LP		 1999/* - DU --------------------------------------------------------------------- */
2000static const unsigned int du_rgb666_pins[] = {
2001 /* R[7:2], G[7:2], B[7:2] */
2002 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2003 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2004 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2005 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2006 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2007 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2008};
2009static const unsigned int du_rgb666_mux[] = {
2010 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2011 DU_DR3_MARK, DU_DR2_MARK,
2012 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2013 DU_DG3_MARK, DU_DG2_MARK,
2014 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2015 DU_DB3_MARK, DU_DB2_MARK,
2016};
2017static const unsigned int du_rgb888_pins[] = {
2018 /* R[7:0], G[7:0], B[7:0] */
2019 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2020 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2021 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2022 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2023 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2024 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2025 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2026 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2027 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2028};
2029static const unsigned int du_rgb888_mux[] = {
2030 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2031 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2032 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2033 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2034 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2035 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2036};
2037static const unsigned int du_clk_out_0_pins[] = {
2038 /* CLKOUT */
2039 RCAR_GP_PIN(1, 27),
2040};
2041static const unsigned int du_clk_out_0_mux[] = {
2042 DU_DOTCLKOUT0_MARK
2043};
2044static const unsigned int du_clk_out_1_pins[] = {
2045 /* CLKOUT */
2046 RCAR_GP_PIN(2, 3),
2047};
2048static const unsigned int du_clk_out_1_mux[] = {
2049 DU_DOTCLKOUT1_MARK
2050};
2051static const unsigned int du_sync_pins[] = {
2052 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2053 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2054};
2055static const unsigned int du_sync_mux[] = {
2056 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2057};
2058static const unsigned int du_oddf_pins[] = {
2059 /* EXDISP/EXODDF/EXCDE */
2060 RCAR_GP_PIN(2, 2),
2061};
2062static const unsigned int du_oddf_mux[] = {
2063 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2064};
2065static const unsigned int du_cde_pins[] = {
2066 /* CDE */
2067 RCAR_GP_PIN(2, 0),
2068};
2069static const unsigned int du_cde_mux[] = {
2070 DU_CDE_MARK,
2071};
2072static const unsigned int du_disp_pins[] = {
2073 /* DISP */
2074 RCAR_GP_PIN(2, 1),
2075};
2076static const unsigned int du_disp_mux[] = {
2077 DU_DISP_MARK,
2078};
2079
7a362e34
WS		 2080/* - HSCIF0 ----------------------------------------------------------------- */
2081static const unsigned int hscif0_data_pins[] = {
2082 /* RX, TX */
2083 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2084};
2085static const unsigned int hscif0_data_mux[] = {
2086 HRX0_MARK, HTX0_MARK,
2087};
2088static const unsigned int hscif0_clk_pins[] = {
2089 /* SCK */
2090 RCAR_GP_PIN(5, 12),
2091};
2092static const unsigned int hscif0_clk_mux[] = {
2093 HSCK0_MARK,
2094};
2095static const unsigned int hscif0_ctrl_pins[] = {
2096 /* RTS, CTS */
2097 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2098};
2099static const unsigned int hscif0_ctrl_mux[] = {
2100 HRTS0_N_MARK, HCTS0_N_MARK,
2101};
2102/* - HSCIF1 ----------------------------------------------------------------- */
2103static const unsigned int hscif1_data_a_pins[] = {
2104 /* RX, TX */
2105 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2106};
2107static const unsigned int hscif1_data_a_mux[] = {
2108 HRX1_A_MARK, HTX1_A_MARK,
2109};
2110static const unsigned int hscif1_clk_a_pins[] = {
2111 /* SCK */
2112 RCAR_GP_PIN(6, 21),
2113};
2114static const unsigned int hscif1_clk_a_mux[] = {
2115 HSCK1_A_MARK,
2116};
2117static const unsigned int hscif1_ctrl_a_pins[] = {
2118 /* RTS, CTS */
2119 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2120};
2121static const unsigned int hscif1_ctrl_a_mux[] = {
2122 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2123};
2124
2125static const unsigned int hscif1_data_b_pins[] = {
2126 /* RX, TX */
2127 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2128};
2129static const unsigned int hscif1_data_b_mux[] = {
2130 HRX1_B_MARK, HTX1_B_MARK,
2131};
2132static const unsigned int hscif1_clk_b_pins[] = {
2133 /* SCK */
2134 RCAR_GP_PIN(5, 0),
2135};
2136static const unsigned int hscif1_clk_b_mux[] = {
2137 HSCK1_B_MARK,
2138};
2139static const unsigned int hscif1_ctrl_b_pins[] = {
2140 /* RTS, CTS */
2141 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2142};
2143static const unsigned int hscif1_ctrl_b_mux[] = {
2144 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2145};
2146/* - HSCIF2 ----------------------------------------------------------------- */
2147static const unsigned int hscif2_data_a_pins[] = {
2148 /* RX, TX */
2149 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2150};
2151static const unsigned int hscif2_data_a_mux[] = {
2152 HRX2_A_MARK, HTX2_A_MARK,
2153};
2154static const unsigned int hscif2_clk_a_pins[] = {
2155 /* SCK */
2156 RCAR_GP_PIN(6, 10),
2157};
2158static const unsigned int hscif2_clk_a_mux[] = {
2159 HSCK2_A_MARK,
2160};
2161static const unsigned int hscif2_ctrl_a_pins[] = {
2162 /* RTS, CTS */
2163 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2164};
2165static const unsigned int hscif2_ctrl_a_mux[] = {
2166 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2167};
2168
2169static const unsigned int hscif2_data_b_pins[] = {
2170 /* RX, TX */
2171 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2172};
2173static const unsigned int hscif2_data_b_mux[] = {
2174 HRX2_B_MARK, HTX2_B_MARK,
2175};
2176static const unsigned int hscif2_clk_b_pins[] = {
2177 /* SCK */
2178 RCAR_GP_PIN(6, 21),
2179};
2180static const unsigned int hscif2_clk_b_mux[] = {
2181 HSCK2_B_MARK,
2182};
2183static const unsigned int hscif2_ctrl_b_pins[] = {
2184 /* RTS, CTS */
2185 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2186};
2187static const unsigned int hscif2_ctrl_b_mux[] = {
2188 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2189};
2190
2191static const unsigned int hscif2_data_c_pins[] = {
2192 /* RX, TX */
2193 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2194};
2195static const unsigned int hscif2_data_c_mux[] = {
2196 HRX2_C_MARK, HTX2_C_MARK,
2197};
2198static const unsigned int hscif2_clk_c_pins[] = {
2199 /* SCK */
2200 RCAR_GP_PIN(6, 24),
2201};
2202static const unsigned int hscif2_clk_c_mux[] = {
2203 HSCK2_C_MARK,
2204};
2205static const unsigned int hscif2_ctrl_c_pins[] = {
2206 /* RTS, CTS */
2207 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2208};
2209static const unsigned int hscif2_ctrl_c_mux[] = {
2210 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2211};
2212/* - HSCIF3 ----------------------------------------------------------------- */
2213static const unsigned int hscif3_data_a_pins[] = {
2214 /* RX, TX */
2215 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2216};
2217static const unsigned int hscif3_data_a_mux[] = {
2218 HRX3_A_MARK, HTX3_A_MARK,
2219};
2220static const unsigned int hscif3_clk_pins[] = {
2221 /* SCK */
2222 RCAR_GP_PIN(1, 22),
2223};
2224static const unsigned int hscif3_clk_mux[] = {
2225 HSCK3_MARK,
2226};
2227static const unsigned int hscif3_ctrl_pins[] = {
2228 /* RTS, CTS */
2229 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2230};
2231static const unsigned int hscif3_ctrl_mux[] = {
2232 HRTS3_N_MARK, HCTS3_N_MARK,
2233};
2234
2235static const unsigned int hscif3_data_b_pins[] = {
2236 /* RX, TX */
2237 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2238};
2239static const unsigned int hscif3_data_b_mux[] = {
2240 HRX3_B_MARK, HTX3_B_MARK,
2241};
2242static const unsigned int hscif3_data_c_pins[] = {
2243 /* RX, TX */
2244 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2245};
2246static const unsigned int hscif3_data_c_mux[] = {
2247 HRX3_C_MARK, HTX3_C_MARK,
2248};
2249static const unsigned int hscif3_data_d_pins[] = {
2250 /* RX, TX */
2251 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2252};
2253static const unsigned int hscif3_data_d_mux[] = {
2254 HRX3_D_MARK, HTX3_D_MARK,
2255};
2256/* - HSCIF4 ----------------------------------------------------------------- */
2257static const unsigned int hscif4_data_a_pins[] = {
2258 /* RX, TX */
2259 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2260};
2261static const unsigned int hscif4_data_a_mux[] = {
2262 HRX4_A_MARK, HTX4_A_MARK,
2263};
2264static const unsigned int hscif4_clk_pins[] = {
2265 /* SCK */
2266 RCAR_GP_PIN(1, 11),
2267};
2268static const unsigned int hscif4_clk_mux[] = {
2269 HSCK4_MARK,
2270};
2271static const unsigned int hscif4_ctrl_pins[] = {
2272 /* RTS, CTS */
2273 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2274};
2275static const unsigned int hscif4_ctrl_mux[] = {
2276 HRTS4_N_MARK, HCTS4_N_MARK,
2277};
2278
2279static const unsigned int hscif4_data_b_pins[] = {
2280 /* RX, TX */
2281 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2282};
2283static const unsigned int hscif4_data_b_mux[] = {
2284 HRX4_B_MARK, HTX4_B_MARK,
2285};
2286
f62d4c9e
WS		 2287/* - I2C -------------------------------------------------------------------- */
2288static const unsigned int i2c1_a_pins[] = {
2289 /* SDA, SCL */
2290 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2291};
2292static const unsigned int i2c1_a_mux[] = {
2293 SDA1_A_MARK, SCL1_A_MARK,
2294};
2295static const unsigned int i2c1_b_pins[] = {
2296 /* SDA, SCL */
2297 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2298};
2299static const unsigned int i2c1_b_mux[] = {
2300 SDA1_B_MARK, SCL1_B_MARK,
2301};
2302static const unsigned int i2c2_a_pins[] = {
2303 /* SDA, SCL */
2304 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2305};
2306static const unsigned int i2c2_a_mux[] = {
2307 SDA2_A_MARK, SCL2_A_MARK,
2308};
2309static const unsigned int i2c2_b_pins[] = {
2310 /* SDA, SCL */
2311 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2312};
2313static const unsigned int i2c2_b_mux[] = {
2314 SDA2_B_MARK, SCL2_B_MARK,
2315};
2316static const unsigned int i2c6_a_pins[] = {
2317 /* SDA, SCL */
2318 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2319};
2320static const unsigned int i2c6_a_mux[] = {
2321 SDA6_A_MARK, SCL6_A_MARK,
2322};
2323static const unsigned int i2c6_b_pins[] = {
2324 /* SDA, SCL */
2325 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2326};
2327static const unsigned int i2c6_b_mux[] = {
2328 SDA6_B_MARK, SCL6_B_MARK,
2329};
2330static const unsigned int i2c6_c_pins[] = {
2331 /* SDA, SCL */
2332 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2333};
2334static const unsigned int i2c6_c_mux[] = {
2335 SDA6_C_MARK, SCL6_C_MARK,
2336};
2337
8480e6ca
GU		 2338/* - INTC-EX ---------------------------------------------------------------- */
2339static const unsigned int intc_ex_irq0_pins[] = {
2340 /* IRQ0 */
2341 RCAR_GP_PIN(2, 0),
2342};
2343static const unsigned int intc_ex_irq0_mux[] = {
2344 IRQ0_MARK,
2345};
2346static const unsigned int intc_ex_irq1_pins[] = {
2347 /* IRQ1 */
2348 RCAR_GP_PIN(2, 1),
2349};
2350static const unsigned int intc_ex_irq1_mux[] = {
2351 IRQ1_MARK,
2352};
2353static const unsigned int intc_ex_irq2_pins[] = {
2354 /* IRQ2 */
2355 RCAR_GP_PIN(2, 2),
2356};
2357static const unsigned int intc_ex_irq2_mux[] = {
2358 IRQ2_MARK,
2359};
2360static const unsigned int intc_ex_irq3_pins[] = {
2361 /* IRQ3 */
2362 RCAR_GP_PIN(2, 3),
2363};
2364static const unsigned int intc_ex_irq3_mux[] = {
2365 IRQ3_MARK,
2366};
2367static const unsigned int intc_ex_irq4_pins[] = {
2368 /* IRQ4 */
2369 RCAR_GP_PIN(2, 4),
2370};
2371static const unsigned int intc_ex_irq4_mux[] = {
2372 IRQ4_MARK,
2373};
2374static const unsigned int intc_ex_irq5_pins[] = {
2375 /* IRQ5 */
2376 RCAR_GP_PIN(2, 5),
2377};
2378static const unsigned int intc_ex_irq5_mux[] = {
2379 IRQ5_MARK,
2380};
2381
3e6c7727
GU		 2382/* - MSIOF0 ----------------------------------------------------------------- */
2383static const unsigned int msiof0_clk_pins[] = {
2384 /* SCK */
2385 RCAR_GP_PIN(5, 17),
2386};
2387static const unsigned int msiof0_clk_mux[] = {
2388 MSIOF0_SCK_MARK,
2389};
2390static const unsigned int msiof0_sync_pins[] = {
2391 /* SYNC */
2392 RCAR_GP_PIN(5, 18),
2393};
2394static const unsigned int msiof0_sync_mux[] = {
2395 MSIOF0_SYNC_MARK,
2396};
2397static const unsigned int msiof0_ss1_pins[] = {
2398 /* SS1 */
2399 RCAR_GP_PIN(5, 19),
2400};
2401static const unsigned int msiof0_ss1_mux[] = {
2402 MSIOF0_SS1_MARK,
2403};
2404static const unsigned int msiof0_ss2_pins[] = {
2405 /* SS2 */
2406 RCAR_GP_PIN(5, 21),
2407};
2408static const unsigned int msiof0_ss2_mux[] = {
2409 MSIOF0_SS2_MARK,
2410};
2411static const unsigned int msiof0_txd_pins[] = {
2412 /* TXD */
2413 RCAR_GP_PIN(5, 20),
2414};
2415static const unsigned int msiof0_txd_mux[] = {
2416 MSIOF0_TXD_MARK,
2417};
2418static const unsigned int msiof0_rxd_pins[] = {
2419 /* RXD */
2420 RCAR_GP_PIN(5, 22),
2421};
2422static const unsigned int msiof0_rxd_mux[] = {
2423 MSIOF0_RXD_MARK,
2424};
2425/* - MSIOF1 ----------------------------------------------------------------- */
2426static const unsigned int msiof1_clk_a_pins[] = {
2427 /* SCK */
2428 RCAR_GP_PIN(6, 8),
2429};
2430static const unsigned int msiof1_clk_a_mux[] = {
2431 MSIOF1_SCK_A_MARK,
2432};
2433static const unsigned int msiof1_sync_a_pins[] = {
2434 /* SYNC */
2435 RCAR_GP_PIN(6, 9),
2436};
2437static const unsigned int msiof1_sync_a_mux[] = {
2438 MSIOF1_SYNC_A_MARK,
2439};
2440static const unsigned int msiof1_ss1_a_pins[] = {
2441 /* SS1 */
2442 RCAR_GP_PIN(6, 5),
2443};
2444static const unsigned int msiof1_ss1_a_mux[] = {
2445 MSIOF1_SS1_A_MARK,
2446};
2447static const unsigned int msiof1_ss2_a_pins[] = {
2448 /* SS2 */
2449 RCAR_GP_PIN(6, 6),
2450};
2451static const unsigned int msiof1_ss2_a_mux[] = {
2452 MSIOF1_SS2_A_MARK,
2453};
2454static const unsigned int msiof1_txd_a_pins[] = {
2455 /* TXD */
2456 RCAR_GP_PIN(6, 7),
2457};
2458static const unsigned int msiof1_txd_a_mux[] = {
2459 MSIOF1_TXD_A_MARK,
2460};
2461static const unsigned int msiof1_rxd_a_pins[] = {
2462 /* RXD */
2463 RCAR_GP_PIN(6, 10),
2464};
2465static const unsigned int msiof1_rxd_a_mux[] = {
2466 MSIOF1_RXD_A_MARK,
2467};
2468static const unsigned int msiof1_clk_b_pins[] = {
2469 /* SCK */
2470 RCAR_GP_PIN(5, 9),
2471};
2472static const unsigned int msiof1_clk_b_mux[] = {
2473 MSIOF1_SCK_B_MARK,
2474};
2475static const unsigned int msiof1_sync_b_pins[] = {
2476 /* SYNC */
2477 RCAR_GP_PIN(5, 3),
2478};
2479static const unsigned int msiof1_sync_b_mux[] = {
2480 MSIOF1_SYNC_B_MARK,
2481};
2482static const unsigned int msiof1_ss1_b_pins[] = {
2483 /* SS1 */
2484 RCAR_GP_PIN(5, 4),
2485};
2486static const unsigned int msiof1_ss1_b_mux[] = {
2487 MSIOF1_SS1_B_MARK,
2488};
2489static const unsigned int msiof1_ss2_b_pins[] = {
2490 /* SS2 */
2491 RCAR_GP_PIN(5, 0),
2492};
2493static const unsigned int msiof1_ss2_b_mux[] = {
2494 MSIOF1_SS2_B_MARK,
2495};
2496static const unsigned int msiof1_txd_b_pins[] = {
2497 /* TXD */
2498 RCAR_GP_PIN(5, 8),
2499};
2500static const unsigned int msiof1_txd_b_mux[] = {
2501 MSIOF1_TXD_B_MARK,
2502};
2503static const unsigned int msiof1_rxd_b_pins[] = {
2504 /* RXD */
2505 RCAR_GP_PIN(5, 7),
2506};
2507static const unsigned int msiof1_rxd_b_mux[] = {
2508 MSIOF1_RXD_B_MARK,
2509};
2510static const unsigned int msiof1_clk_c_pins[] = {
2511 /* SCK */
2512 RCAR_GP_PIN(6, 17),
2513};
2514static const unsigned int msiof1_clk_c_mux[] = {
2515 MSIOF1_SCK_C_MARK,
2516};
2517static const unsigned int msiof1_sync_c_pins[] = {
2518 /* SYNC */
2519 RCAR_GP_PIN(6, 18),
2520};
2521static const unsigned int msiof1_sync_c_mux[] = {
2522 MSIOF1_SYNC_C_MARK,
2523};
2524static const unsigned int msiof1_ss1_c_pins[] = {
2525 /* SS1 */
2526 RCAR_GP_PIN(6, 21),
2527};
2528static const unsigned int msiof1_ss1_c_mux[] = {
2529 MSIOF1_SS1_C_MARK,
2530};
2531static const unsigned int msiof1_ss2_c_pins[] = {
2532 /* SS2 */
2533 RCAR_GP_PIN(6, 27),
2534};
2535static const unsigned int msiof1_ss2_c_mux[] = {
2536 MSIOF1_SS2_C_MARK,
2537};
2538static const unsigned int msiof1_txd_c_pins[] = {
2539 /* TXD */
2540 RCAR_GP_PIN(6, 20),
2541};
2542static const unsigned int msiof1_txd_c_mux[] = {
2543 MSIOF1_TXD_C_MARK,
2544};
2545static const unsigned int msiof1_rxd_c_pins[] = {
2546 /* RXD */
2547 RCAR_GP_PIN(6, 19),
2548};
2549static const unsigned int msiof1_rxd_c_mux[] = {
2550 MSIOF1_RXD_C_MARK,
2551};
2552static const unsigned int msiof1_clk_d_pins[] = {
2553 /* SCK */
2554 RCAR_GP_PIN(5, 12),
2555};
2556static const unsigned int msiof1_clk_d_mux[] = {
2557 MSIOF1_SCK_D_MARK,
2558};
2559static const unsigned int msiof1_sync_d_pins[] = {
2560 /* SYNC */
2561 RCAR_GP_PIN(5, 15),
2562};
2563static const unsigned int msiof1_sync_d_mux[] = {
2564 MSIOF1_SYNC_D_MARK,
2565};
2566static const unsigned int msiof1_ss1_d_pins[] = {
2567 /* SS1 */
2568 RCAR_GP_PIN(5, 16),
2569};
2570static const unsigned int msiof1_ss1_d_mux[] = {
2571 MSIOF1_SS1_D_MARK,
2572};
2573static const unsigned int msiof1_ss2_d_pins[] = {
2574 /* SS2 */
2575 RCAR_GP_PIN(5, 21),
2576};
2577static const unsigned int msiof1_ss2_d_mux[] = {
2578 MSIOF1_SS2_D_MARK,
2579};
2580static const unsigned int msiof1_txd_d_pins[] = {
2581 /* TXD */
2582 RCAR_GP_PIN(5, 14),
2583};
2584static const unsigned int msiof1_txd_d_mux[] = {
2585 MSIOF1_TXD_D_MARK,
2586};
2587static const unsigned int msiof1_rxd_d_pins[] = {
2588 /* RXD */
2589 RCAR_GP_PIN(5, 13),
2590};
2591static const unsigned int msiof1_rxd_d_mux[] = {
2592 MSIOF1_RXD_D_MARK,
2593};
2594static const unsigned int msiof1_clk_e_pins[] = {
2595 /* SCK */
2596 RCAR_GP_PIN(3, 0),
2597};
2598static const unsigned int msiof1_clk_e_mux[] = {
2599 MSIOF1_SCK_E_MARK,
2600};
2601static const unsigned int msiof1_sync_e_pins[] = {
2602 /* SYNC */
2603 RCAR_GP_PIN(3, 1),
2604};
2605static const unsigned int msiof1_sync_e_mux[] = {
2606 MSIOF1_SYNC_E_MARK,
2607};
2608static const unsigned int msiof1_ss1_e_pins[] = {
2609 /* SS1 */
2610 RCAR_GP_PIN(3, 4),
2611};
2612static const unsigned int msiof1_ss1_e_mux[] = {
2613 MSIOF1_SS1_E_MARK,
2614};
2615static const unsigned int msiof1_ss2_e_pins[] = {
2616 /* SS2 */
2617 RCAR_GP_PIN(3, 5),
2618};
2619static const unsigned int msiof1_ss2_e_mux[] = {
2620 MSIOF1_SS2_E_MARK,
2621};
2622static const unsigned int msiof1_txd_e_pins[] = {
2623 /* TXD */
2624 RCAR_GP_PIN(3, 3),
2625};
2626static const unsigned int msiof1_txd_e_mux[] = {
2627 MSIOF1_TXD_E_MARK,
2628};
2629static const unsigned int msiof1_rxd_e_pins[] = {
2630 /* RXD */
2631 RCAR_GP_PIN(3, 2),
2632};
2633static const unsigned int msiof1_rxd_e_mux[] = {
2634 MSIOF1_RXD_E_MARK,
2635};
2636static const unsigned int msiof1_clk_f_pins[] = {
2637 /* SCK */
2638 RCAR_GP_PIN(5, 23),
2639};
2640static const unsigned int msiof1_clk_f_mux[] = {
2641 MSIOF1_SCK_F_MARK,
2642};
2643static const unsigned int msiof1_sync_f_pins[] = {
2644 /* SYNC */
2645 RCAR_GP_PIN(5, 24),
2646};
2647static const unsigned int msiof1_sync_f_mux[] = {
2648 MSIOF1_SYNC_F_MARK,
2649};
2650static const unsigned int msiof1_ss1_f_pins[] = {
2651 /* SS1 */
2652 RCAR_GP_PIN(6, 1),
2653};
2654static const unsigned int msiof1_ss1_f_mux[] = {
2655 MSIOF1_SS1_F_MARK,
2656};
2657static const unsigned int msiof1_ss2_f_pins[] = {
2658 /* SS2 */
2659 RCAR_GP_PIN(6, 2),
2660};
2661static const unsigned int msiof1_ss2_f_mux[] = {
2662 MSIOF1_SS2_F_MARK,
2663};
2664static const unsigned int msiof1_txd_f_pins[] = {
2665 /* TXD */
2666 RCAR_GP_PIN(6, 0),
2667};
2668static const unsigned int msiof1_txd_f_mux[] = {
2669 MSIOF1_TXD_F_MARK,
2670};
2671static const unsigned int msiof1_rxd_f_pins[] = {
2672 /* RXD */
2673 RCAR_GP_PIN(5, 25),
2674};
2675static const unsigned int msiof1_rxd_f_mux[] = {
2676 MSIOF1_RXD_F_MARK,
2677};
2678static const unsigned int msiof1_clk_g_pins[] = {
2679 /* SCK */
2680 RCAR_GP_PIN(3, 6),
2681};
2682static const unsigned int msiof1_clk_g_mux[] = {
2683 MSIOF1_SCK_G_MARK,
2684};
2685static const unsigned int msiof1_sync_g_pins[] = {
2686 /* SYNC */
2687 RCAR_GP_PIN(3, 7),
2688};
2689static const unsigned int msiof1_sync_g_mux[] = {
2690 MSIOF1_SYNC_G_MARK,
2691};
2692static const unsigned int msiof1_ss1_g_pins[] = {
2693 /* SS1 */
2694 RCAR_GP_PIN(3, 10),
2695};
2696static const unsigned int msiof1_ss1_g_mux[] = {
2697 MSIOF1_SS1_G_MARK,
2698};
2699static const unsigned int msiof1_ss2_g_pins[] = {
2700 /* SS2 */
2701 RCAR_GP_PIN(3, 11),
2702};
2703static const unsigned int msiof1_ss2_g_mux[] = {
2704 MSIOF1_SS2_G_MARK,
2705};
2706static const unsigned int msiof1_txd_g_pins[] = {
2707 /* TXD */
2708 RCAR_GP_PIN(3, 9),
2709};
2710static const unsigned int msiof1_txd_g_mux[] = {
2711 MSIOF1_TXD_G_MARK,
2712};
2713static const unsigned int msiof1_rxd_g_pins[] = {
2714 /* RXD */
2715 RCAR_GP_PIN(3, 8),
2716};
2717static const unsigned int msiof1_rxd_g_mux[] = {
2718 MSIOF1_RXD_G_MARK,
2719};
2720/* - MSIOF2 ----------------------------------------------------------------- */
2721static const unsigned int msiof2_clk_a_pins[] = {
2722 /* SCK */
2723 RCAR_GP_PIN(1, 9),
2724};
2725static const unsigned int msiof2_clk_a_mux[] = {
2726 MSIOF2_SCK_A_MARK,
2727};
2728static const unsigned int msiof2_sync_a_pins[] = {
2729 /* SYNC */
2730 RCAR_GP_PIN(1, 8),
2731};
2732static const unsigned int msiof2_sync_a_mux[] = {
2733 MSIOF2_SYNC_A_MARK,
2734};
2735static const unsigned int msiof2_ss1_a_pins[] = {
2736 /* SS1 */
2737 RCAR_GP_PIN(1, 6),
2738};
2739static const unsigned int msiof2_ss1_a_mux[] = {
2740 MSIOF2_SS1_A_MARK,
2741};
2742static const unsigned int msiof2_ss2_a_pins[] = {
2743 /* SS2 */
2744 RCAR_GP_PIN(1, 7),
2745};
2746static const unsigned int msiof2_ss2_a_mux[] = {
2747 MSIOF2_SS2_A_MARK,
2748};
2749static const unsigned int msiof2_txd_a_pins[] = {
2750 /* TXD */
2751 RCAR_GP_PIN(1, 11),
2752};
2753static const unsigned int msiof2_txd_a_mux[] = {
2754 MSIOF2_TXD_A_MARK,
2755};
2756static const unsigned int msiof2_rxd_a_pins[] = {
2757 /* RXD */
2758 RCAR_GP_PIN(1, 10),
2759};
2760static const unsigned int msiof2_rxd_a_mux[] = {
2761 MSIOF2_RXD_A_MARK,
2762};
2763static const unsigned int msiof2_clk_b_pins[] = {
2764 /* SCK */
2765 RCAR_GP_PIN(0, 4),
2766};
2767static const unsigned int msiof2_clk_b_mux[] = {
2768 MSIOF2_SCK_B_MARK,
2769};
2770static const unsigned int msiof2_sync_b_pins[] = {
2771 /* SYNC */
2772 RCAR_GP_PIN(0, 5),
2773};
2774static const unsigned int msiof2_sync_b_mux[] = {
2775 MSIOF2_SYNC_B_MARK,
2776};
2777static const unsigned int msiof2_ss1_b_pins[] = {
2778 /* SS1 */
2779 RCAR_GP_PIN(0, 0),
2780};
2781static const unsigned int msiof2_ss1_b_mux[] = {
2782 MSIOF2_SS1_B_MARK,
2783};
2784static const unsigned int msiof2_ss2_b_pins[] = {
2785 /* SS2 */
2786 RCAR_GP_PIN(0, 1),
2787};
2788static const unsigned int msiof2_ss2_b_mux[] = {
2789 MSIOF2_SS2_B_MARK,
2790};
2791static const unsigned int msiof2_txd_b_pins[] = {
2792 /* TXD */
2793 RCAR_GP_PIN(0, 7),
2794};
2795static const unsigned int msiof2_txd_b_mux[] = {
2796 MSIOF2_TXD_B_MARK,
2797};
2798static const unsigned int msiof2_rxd_b_pins[] = {
2799 /* RXD */
2800 RCAR_GP_PIN(0, 6),
2801};
2802static const unsigned int msiof2_rxd_b_mux[] = {
2803 MSIOF2_RXD_B_MARK,
2804};
2805static const unsigned int msiof2_clk_c_pins[] = {
2806 /* SCK */
2807 RCAR_GP_PIN(2, 12),
2808};
2809static const unsigned int msiof2_clk_c_mux[] = {
2810 MSIOF2_SCK_C_MARK,
2811};
2812static const unsigned int msiof2_sync_c_pins[] = {
2813 /* SYNC */
2814 RCAR_GP_PIN(2, 11),
2815};
2816static const unsigned int msiof2_sync_c_mux[] = {
2817 MSIOF2_SYNC_C_MARK,
2818};
2819static const unsigned int msiof2_ss1_c_pins[] = {
2820 /* SS1 */
2821 RCAR_GP_PIN(2, 10),
2822};
2823static const unsigned int msiof2_ss1_c_mux[] = {
2824 MSIOF2_SS1_C_MARK,
2825};
2826static const unsigned int msiof2_ss2_c_pins[] = {
2827 /* SS2 */
2828 RCAR_GP_PIN(2, 9),
2829};
2830static const unsigned int msiof2_ss2_c_mux[] = {
2831 MSIOF2_SS2_C_MARK,
2832};
2833static const unsigned int msiof2_txd_c_pins[] = {
2834 /* TXD */
2835 RCAR_GP_PIN(2, 14),
2836};
2837static const unsigned int msiof2_txd_c_mux[] = {
2838 MSIOF2_TXD_C_MARK,
2839};
2840static const unsigned int msiof2_rxd_c_pins[] = {
2841 /* RXD */
2842 RCAR_GP_PIN(2, 13),
2843};
2844static const unsigned int msiof2_rxd_c_mux[] = {
2845 MSIOF2_RXD_C_MARK,
2846};
2847static const unsigned int msiof2_clk_d_pins[] = {
2848 /* SCK */
2849 RCAR_GP_PIN(0, 8),
2850};
2851static const unsigned int msiof2_clk_d_mux[] = {
2852 MSIOF2_SCK_D_MARK,
2853};
2854static const unsigned int msiof2_sync_d_pins[] = {
2855 /* SYNC */
2856 RCAR_GP_PIN(0, 9),
2857};
2858static const unsigned int msiof2_sync_d_mux[] = {
2859 MSIOF2_SYNC_D_MARK,
2860};
2861static const unsigned int msiof2_ss1_d_pins[] = {
2862 /* SS1 */
2863 RCAR_GP_PIN(0, 12),
2864};
2865static const unsigned int msiof2_ss1_d_mux[] = {
2866 MSIOF2_SS1_D_MARK,
2867};
2868static const unsigned int msiof2_ss2_d_pins[] = {
2869 /* SS2 */
2870 RCAR_GP_PIN(0, 13),
2871};
2872static const unsigned int msiof2_ss2_d_mux[] = {
2873 MSIOF2_SS2_D_MARK,
2874};
2875static const unsigned int msiof2_txd_d_pins[] = {
2876 /* TXD */
2877 RCAR_GP_PIN(0, 11),
2878};
2879static const unsigned int msiof2_txd_d_mux[] = {
2880 MSIOF2_TXD_D_MARK,
2881};
2882static const unsigned int msiof2_rxd_d_pins[] = {
2883 /* RXD */
2884 RCAR_GP_PIN(0, 10),
2885};
2886static const unsigned int msiof2_rxd_d_mux[] = {
2887 MSIOF2_RXD_D_MARK,
2888};
2889/* - MSIOF3 ----------------------------------------------------------------- */
2890static const unsigned int msiof3_clk_a_pins[] = {
2891 /* SCK */
2892 RCAR_GP_PIN(0, 0),
2893};
2894static const unsigned int msiof3_clk_a_mux[] = {
2895 MSIOF3_SCK_A_MARK,
2896};
2897static const unsigned int msiof3_sync_a_pins[] = {
2898 /* SYNC */
2899 RCAR_GP_PIN(0, 1),
2900};
2901static const unsigned int msiof3_sync_a_mux[] = {
2902 MSIOF3_SYNC_A_MARK,
2903};
2904static const unsigned int msiof3_ss1_a_pins[] = {
2905 /* SS1 */
2906 RCAR_GP_PIN(0, 14),
2907};
2908static const unsigned int msiof3_ss1_a_mux[] = {
2909 MSIOF3_SS1_A_MARK,
2910};
2911static const unsigned int msiof3_ss2_a_pins[] = {
2912 /* SS2 */
2913 RCAR_GP_PIN(0, 15),
2914};
2915static const unsigned int msiof3_ss2_a_mux[] = {
2916 MSIOF3_SS2_A_MARK,
2917};
2918static const unsigned int msiof3_txd_a_pins[] = {
2919 /* TXD */
2920 RCAR_GP_PIN(0, 3),
2921};
2922static const unsigned int msiof3_txd_a_mux[] = {
2923 MSIOF3_TXD_A_MARK,
2924};
2925static const unsigned int msiof3_rxd_a_pins[] = {
2926 /* RXD */
2927 RCAR_GP_PIN(0, 2),
2928};
2929static const unsigned int msiof3_rxd_a_mux[] = {
2930 MSIOF3_RXD_A_MARK,
2931};
2932static const unsigned int msiof3_clk_b_pins[] = {
2933 /* SCK */
2934 RCAR_GP_PIN(1, 2),
2935};
2936static const unsigned int msiof3_clk_b_mux[] = {
2937 MSIOF3_SCK_B_MARK,
2938};
2939static const unsigned int msiof3_sync_b_pins[] = {
2940 /* SYNC */
2941 RCAR_GP_PIN(1, 0),
2942};
2943static const unsigned int msiof3_sync_b_mux[] = {
2944 MSIOF3_SYNC_B_MARK,
2945};
2946static const unsigned int msiof3_ss1_b_pins[] = {
2947 /* SS1 */
2948 RCAR_GP_PIN(1, 4),
2949};
2950static const unsigned int msiof3_ss1_b_mux[] = {
2951 MSIOF3_SS1_B_MARK,
2952};
2953static const unsigned int msiof3_ss2_b_pins[] = {
2954 /* SS2 */
2955 RCAR_GP_PIN(1, 5),
2956};
2957static const unsigned int msiof3_ss2_b_mux[] = {
2958 MSIOF3_SS2_B_MARK,
2959};
2960static const unsigned int msiof3_txd_b_pins[] = {
2961 /* TXD */
2962 RCAR_GP_PIN(1, 1),
2963};
2964static const unsigned int msiof3_txd_b_mux[] = {
2965 MSIOF3_TXD_B_MARK,
2966};
2967static const unsigned int msiof3_rxd_b_pins[] = {
2968 /* RXD */
2969 RCAR_GP_PIN(1, 3),
2970};
2971static const unsigned int msiof3_rxd_b_mux[] = {
2972 MSIOF3_RXD_B_MARK,
2973};
2974static const unsigned int msiof3_clk_c_pins[] = {
2975 /* SCK */
2976 RCAR_GP_PIN(1, 12),
2977};
2978static const unsigned int msiof3_clk_c_mux[] = {
2979 MSIOF3_SCK_C_MARK,
2980};
2981static const unsigned int msiof3_sync_c_pins[] = {
2982 /* SYNC */
2983 RCAR_GP_PIN(1, 13),
2984};
2985static const unsigned int msiof3_sync_c_mux[] = {
2986 MSIOF3_SYNC_C_MARK,
2987};
2988static const unsigned int msiof3_txd_c_pins[] = {
2989 /* TXD */
2990 RCAR_GP_PIN(1, 15),
2991};
2992static const unsigned int msiof3_txd_c_mux[] = {
2993 MSIOF3_TXD_C_MARK,
2994};
2995static const unsigned int msiof3_rxd_c_pins[] = {
2996 /* RXD */
2997 RCAR_GP_PIN(1, 14),
2998};
2999static const unsigned int msiof3_rxd_c_mux[] = {
3000 MSIOF3_RXD_C_MARK,
3001};
3002static const unsigned int msiof3_clk_d_pins[] = {
3003 /* SCK */
3004 RCAR_GP_PIN(1, 22),
3005};
3006static const unsigned int msiof3_clk_d_mux[] = {
3007 MSIOF3_SCK_D_MARK,
3008};
3009static const unsigned int msiof3_sync_d_pins[] = {
3010 /* SYNC */
3011 RCAR_GP_PIN(1, 23),
3012};
3013static const unsigned int msiof3_sync_d_mux[] = {
3014 MSIOF3_SYNC_D_MARK,
3015};
3016static const unsigned int msiof3_ss1_d_pins[] = {
3017 /* SS1 */
3018 RCAR_GP_PIN(1, 26),
3019};
3020static const unsigned int msiof3_ss1_d_mux[] = {
3021 MSIOF3_SS1_D_MARK,
3022};
3023static const unsigned int msiof3_txd_d_pins[] = {
3024 /* TXD */
3025 RCAR_GP_PIN(1, 25),
3026};
3027static const unsigned int msiof3_txd_d_mux[] = {
3028 MSIOF3_TXD_D_MARK,
3029};
3030static const unsigned int msiof3_rxd_d_pins[] = {
3031 /* RXD */
3032 RCAR_GP_PIN(1, 24),
3033};
3034static const unsigned int msiof3_rxd_d_mux[] = {
3035 MSIOF3_RXD_D_MARK,
3036};
3037static const unsigned int msiof3_clk_e_pins[] = {
3038 /* SCK */
3039 RCAR_GP_PIN(2, 3),
3040};
3041static const unsigned int msiof3_clk_e_mux[] = {
3042 MSIOF3_SCK_E_MARK,
3043};
3044static const unsigned int msiof3_sync_e_pins[] = {
3045 /* SYNC */
3046 RCAR_GP_PIN(2, 2),
3047};
3048static const unsigned int msiof3_sync_e_mux[] = {
3049 MSIOF3_SYNC_E_MARK,
3050};
3051static const unsigned int msiof3_ss1_e_pins[] = {
3052 /* SS1 */
3053 RCAR_GP_PIN(2, 1),
3054};
3055static const unsigned int msiof3_ss1_e_mux[] = {
3056 MSIOF3_SS1_E_MARK,
3057};
3058static const unsigned int msiof3_ss2_e_pins[] = {
3059 /* SS1 */
3060 RCAR_GP_PIN(2, 0),
3061};
3062static const unsigned int msiof3_ss2_e_mux[] = {
3063 MSIOF3_SS2_E_MARK,
3064};
3065static const unsigned int msiof3_txd_e_pins[] = {
3066 /* TXD */
3067 RCAR_GP_PIN(2, 5),
3068};
3069static const unsigned int msiof3_txd_e_mux[] = {
3070 MSIOF3_TXD_E_MARK,
3071};
3072static const unsigned int msiof3_rxd_e_pins[] = {
3073 /* RXD */
3074 RCAR_GP_PIN(2, 4),
3075};
3076static const unsigned int msiof3_rxd_e_mux[] = {
3077 MSIOF3_RXD_E_MARK,
3078};
3079
c03a133b
LP		 3080/* - PWM0 --------------------------------------------------------------------*/
3081static const unsigned int pwm0_pins[] = {
3082 /* PWM */
3083 RCAR_GP_PIN(2, 6),
3084};
3085static const unsigned int pwm0_mux[] = {
3086 PWM0_MARK,
3087};
3088/* - PWM1 --------------------------------------------------------------------*/
3089static const unsigned int pwm1_a_pins[] = {
3090 /* PWM */
3091 RCAR_GP_PIN(2, 7),
3092};
3093static const unsigned int pwm1_a_mux[] = {
3094 PWM1_A_MARK,
3095};
3096static const unsigned int pwm1_b_pins[] = {
3097 /* PWM */
3098 RCAR_GP_PIN(1, 8),
3099};
3100static const unsigned int pwm1_b_mux[] = {
3101 PWM1_B_MARK,
3102};
3103/* - PWM2 --------------------------------------------------------------------*/
3104static const unsigned int pwm2_a_pins[] = {
3105 /* PWM */
3106 RCAR_GP_PIN(2, 8),
3107};
3108static const unsigned int pwm2_a_mux[] = {
3109 PWM2_A_MARK,
3110};
3111static const unsigned int pwm2_b_pins[] = {
3112 /* PWM */
3113 RCAR_GP_PIN(1, 11),
3114};
3115static const unsigned int pwm2_b_mux[] = {
3116 PWM2_B_MARK,
3117};
3118/* - PWM3 --------------------------------------------------------------------*/
3119static const unsigned int pwm3_a_pins[] = {
3120 /* PWM */
3121 RCAR_GP_PIN(1, 0),
3122};
3123static const unsigned int pwm3_a_mux[] = {
3124 PWM3_A_MARK,
3125};
3126static const unsigned int pwm3_b_pins[] = {
3127 /* PWM */
3128 RCAR_GP_PIN(2, 2),
3129};
3130static const unsigned int pwm3_b_mux[] = {
3131 PWM3_B_MARK,
3132};
3133/* - PWM4 --------------------------------------------------------------------*/
3134static const unsigned int pwm4_a_pins[] = {
3135 /* PWM */
3136 RCAR_GP_PIN(1, 1),
3137};
3138static const unsigned int pwm4_a_mux[] = {
3139 PWM4_A_MARK,
3140};
3141static const unsigned int pwm4_b_pins[] = {
3142 /* PWM */
3143 RCAR_GP_PIN(2, 3),
3144};
3145static const unsigned int pwm4_b_mux[] = {
3146 PWM4_B_MARK,
3147};
3148/* - PWM5 --------------------------------------------------------------------*/
3149static const unsigned int pwm5_a_pins[] = {
3150 /* PWM */
3151 RCAR_GP_PIN(1, 2),
3152};
3153static const unsigned int pwm5_a_mux[] = {
3154 PWM5_A_MARK,
3155};
3156static const unsigned int pwm5_b_pins[] = {
3157 /* PWM */
3158 RCAR_GP_PIN(2, 4),
3159};
3160static const unsigned int pwm5_b_mux[] = {
3161 PWM5_B_MARK,
3162};
3163/* - PWM6 --------------------------------------------------------------------*/
3164static const unsigned int pwm6_a_pins[] = {
3165 /* PWM */
3166 RCAR_GP_PIN(1, 3),
3167};
3168static const unsigned int pwm6_a_mux[] = {
3169 PWM6_A_MARK,
3170};
3171static const unsigned int pwm6_b_pins[] = {
3172 /* PWM */
3173 RCAR_GP_PIN(2, 5),
3174};
3175static const unsigned int pwm6_b_mux[] = {
3176 PWM6_B_MARK,
3177};
3178
e7ad4d3c
GU		 3179/* - SCIF0 ------------------------------------------------------------------ */
3180static const unsigned int scif0_data_pins[] = {
3181 /* RX, TX */
3182 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3183};
3184static const unsigned int scif0_data_mux[] = {
3185 RX0_MARK, TX0_MARK,
3186};
3187static const unsigned int scif0_clk_pins[] = {
3188 /* SCK */
3189 RCAR_GP_PIN(5, 0),
3190};
3191static const unsigned int scif0_clk_mux[] = {
3192 SCK0_MARK,
3193};
3194static const unsigned int scif0_ctrl_pins[] = {
3195 /* RTS, CTS */
3196 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3197};
3198static const unsigned int scif0_ctrl_mux[] = {
3199 RTS0_N_TANS_MARK, CTS0_N_MARK,
3200};
3201/* - SCIF1 ------------------------------------------------------------------ */
3202static const unsigned int scif1_data_a_pins[] = {
3203 /* RX, TX */
3204 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3205};
3206static const unsigned int scif1_data_a_mux[] = {
3207 RX1_A_MARK, TX1_A_MARK,
3208};
3209static const unsigned int scif1_clk_pins[] = {
3210 /* SCK */
3211 RCAR_GP_PIN(6, 21),
3212};
3213static const unsigned int scif1_clk_mux[] = {
3214 SCK1_MARK,
3215};
3216static const unsigned int scif1_ctrl_pins[] = {
3217 /* RTS, CTS */
3218 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3219};
3220static const unsigned int scif1_ctrl_mux[] = {
3221 RTS1_N_TANS_MARK, CTS1_N_MARK,
3222};
3223
3224static const unsigned int scif1_data_b_pins[] = {
3225 /* RX, TX */
3226 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3227};
3228static const unsigned int scif1_data_b_mux[] = {
3229 RX1_B_MARK, TX1_B_MARK,
3230};
3231/* - SCIF2 ------------------------------------------------------------------ */
3232static const unsigned int scif2_data_a_pins[] = {
3233 /* RX, TX */
3234 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3235};
3236static const unsigned int scif2_data_a_mux[] = {
3237 RX2_A_MARK, TX2_A_MARK,
3238};
3239static const unsigned int scif2_clk_pins[] = {
3240 /* SCK */
3241 RCAR_GP_PIN(5, 9),
3242};
3243static const unsigned int scif2_clk_mux[] = {
3244 SCK2_MARK,
3245};
3246static const unsigned int scif2_data_b_pins[] = {
3247 /* RX, TX */
3248 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3249};
3250static const unsigned int scif2_data_b_mux[] = {
3251 RX2_B_MARK, TX2_B_MARK,
3252};
3253/* - SCIF3 ------------------------------------------------------------------ */
3254static const unsigned int scif3_data_a_pins[] = {
3255 /* RX, TX */
3256 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3257};
3258static const unsigned int scif3_data_a_mux[] = {
3259 RX3_A_MARK, TX3_A_MARK,
3260};
3261static const unsigned int scif3_clk_pins[] = {
3262 /* SCK */
3263 RCAR_GP_PIN(1, 22),
3264};
3265static const unsigned int scif3_clk_mux[] = {
3266 SCK3_MARK,
3267};
3268static const unsigned int scif3_ctrl_pins[] = {
3269 /* RTS, CTS */
3270 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3271};
3272static const unsigned int scif3_ctrl_mux[] = {
3273 RTS3_N_TANS_MARK, CTS3_N_MARK,
3274};
3275static const unsigned int scif3_data_b_pins[] = {
3276 /* RX, TX */
3277 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3278};
3279static const unsigned int scif3_data_b_mux[] = {
3280 RX3_B_MARK, TX3_B_MARK,
3281};
3282/* - SCIF4 ------------------------------------------------------------------ */
3283static const unsigned int scif4_data_a_pins[] = {
3284 /* RX, TX */
3285 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3286};
3287static const unsigned int scif4_data_a_mux[] = {
3288 RX4_A_MARK, TX4_A_MARK,
3289};
3290static const unsigned int scif4_clk_a_pins[] = {
3291 /* SCK */
3292 RCAR_GP_PIN(2, 10),
3293};
3294static const unsigned int scif4_clk_a_mux[] = {
3295 SCK4_A_MARK,
3296};
3297static const unsigned int scif4_ctrl_a_pins[] = {
3298 /* RTS, CTS */
3299 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3300};
3301static const unsigned int scif4_ctrl_a_mux[] = {
3302 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3303};
3304static const unsigned int scif4_data_b_pins[] = {
3305 /* RX, TX */
3306 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3307};
3308static const unsigned int scif4_data_b_mux[] = {
3309 RX4_B_MARK, TX4_B_MARK,
3310};
3311static const unsigned int scif4_clk_b_pins[] = {
3312 /* SCK */
3313 RCAR_GP_PIN(1, 5),
3314};
3315static const unsigned int scif4_clk_b_mux[] = {
3316 SCK4_B_MARK,
3317};
3318static const unsigned int scif4_ctrl_b_pins[] = {
3319 /* RTS, CTS */
3320 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3321};
3322static const unsigned int scif4_ctrl_b_mux[] = {
3323 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3324};
3325static const unsigned int scif4_data_c_pins[] = {
3326 /* RX, TX */
3327 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3328};
3329static const unsigned int scif4_data_c_mux[] = {
3330 RX4_C_MARK, TX4_C_MARK,
3331};
3332static const unsigned int scif4_clk_c_pins[] = {
3333 /* SCK */
3334 RCAR_GP_PIN(0, 8),
3335};
3336static const unsigned int scif4_clk_c_mux[] = {
3337 SCK4_C_MARK,
3338};
3339static const unsigned int scif4_ctrl_c_pins[] = {
3340 /* RTS, CTS */
3341 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3342};
3343static const unsigned int scif4_ctrl_c_mux[] = {
3344 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3345};
3346/* - SCIF5 ------------------------------------------------------------------ */
3347static const unsigned int scif5_data_a_pins[] = {
3348 /* RX, TX */
3349 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3350};
3351static const unsigned int scif5_data_a_mux[] = {
3352 RX5_A_MARK, TX5_A_MARK,
3353};
3354static const unsigned int scif5_clk_a_pins[] = {
3355 /* SCK */
3356 RCAR_GP_PIN(6, 21),
3357};
3358static const unsigned int scif5_clk_a_mux[] = {
3359 SCK5_A_MARK,
3360};
3361static const unsigned int scif5_data_b_pins[] = {
3362 /* RX, TX */
3363 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3364};
3365static const unsigned int scif5_data_b_mux[] = {
3366 RX5_B_MARK, TX5_B_MARK,
3367};
3368static const unsigned int scif5_clk_b_pins[] = {
3369 /* SCK */
3370 RCAR_GP_PIN(5, 0),
3371};
3372static const unsigned int scif5_clk_b_mux[] = {
3373 SCK5_B_MARK,
3374};
3375
b4062b46
GU		 3376/* - SCIF Clock ------------------------------------------------------------- */
3377static const unsigned int scif_clk_a_pins[] = {
3378 /* SCIF_CLK */
3379 RCAR_GP_PIN(6, 23),
3380};
3381static const unsigned int scif_clk_a_mux[] = {
3382 SCIF_CLK_A_MARK,
3383};
3384static const unsigned int scif_clk_b_pins[] = {
3385 /* SCIF_CLK */
3386 RCAR_GP_PIN(5, 9),
3387};
3388static const unsigned int scif_clk_b_mux[] = {
3389 SCIF_CLK_B_MARK,
3390};
3391
9ed13958
TK		 3392/* - SDHI0 ------------------------------------------------------------------ */
3393static const unsigned int sdhi0_data1_pins[] = {
3394 /* D0 */
3395 RCAR_GP_PIN(3, 2),
3396};
3397static const unsigned int sdhi0_data1_mux[] = {
3398 SD0_DAT0_MARK,
3399};
3400static const unsigned int sdhi0_data4_pins[] = {
3401 /* D[0:3] */
3402 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3403 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3404};
3405static const unsigned int sdhi0_data4_mux[] = {
3406 SD0_DAT0_MARK, SD0_DAT1_MARK,
3407 SD0_DAT2_MARK, SD0_DAT3_MARK,
3408};
3409static const unsigned int sdhi0_ctrl_pins[] = {
3410 /* CLK, CMD */
3411 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3412};
3413static const unsigned int sdhi0_ctrl_mux[] = {
3414 SD0_CLK_MARK, SD0_CMD_MARK,
3415};
3416static const unsigned int sdhi0_cd_pins[] = {
3417 /* CD */
3418 RCAR_GP_PIN(3, 12),
3419};
3420static const unsigned int sdhi0_cd_mux[] = {
3421 SD0_CD_MARK,
3422};
3423static const unsigned int sdhi0_wp_pins[] = {
3424 /* WP */
3425 RCAR_GP_PIN(3, 13),
3426};
3427static const unsigned int sdhi0_wp_mux[] = {
3428 SD0_WP_MARK,
3429};
3430/* - SDHI1 ------------------------------------------------------------------ */
3431static const unsigned int sdhi1_data1_pins[] = {
3432 /* D0 */
3433 RCAR_GP_PIN(3, 8),
3434};
3435static const unsigned int sdhi1_data1_mux[] = {
3436 SD1_DAT0_MARK,
3437};
3438static const unsigned int sdhi1_data4_pins[] = {
3439 /* D[0:3] */
3440 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3441 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3442};
3443static const unsigned int sdhi1_data4_mux[] = {
3444 SD1_DAT0_MARK, SD1_DAT1_MARK,
3445 SD1_DAT2_MARK, SD1_DAT3_MARK,
3446};
3447static const unsigned int sdhi1_ctrl_pins[] = {
3448 /* CLK, CMD */
3449 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3450};
3451static const unsigned int sdhi1_ctrl_mux[] = {
3452 SD1_CLK_MARK, SD1_CMD_MARK,
3453};
3454static const unsigned int sdhi1_cd_pins[] = {
3455 /* CD */
3456 RCAR_GP_PIN(3, 14),
3457};
3458static const unsigned int sdhi1_cd_mux[] = {
3459 SD1_CD_MARK,
3460};
3461static const unsigned int sdhi1_wp_pins[] = {
3462 /* WP */
3463 RCAR_GP_PIN(3, 15),
3464};
3465static const unsigned int sdhi1_wp_mux[] = {
3466 SD1_WP_MARK,
3467};
3468/* - SDHI2 ------------------------------------------------------------------ */
3469static const unsigned int sdhi2_data1_pins[] = {
3470 /* D0 */
3471 RCAR_GP_PIN(4, 2),
3472};
3473static const unsigned int sdhi2_data1_mux[] = {
3474 SD2_DAT0_MARK,
3475};
3476static const unsigned int sdhi2_data4_pins[] = {
3477 /* D[0:3] */
3478 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3479 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3480};
3481static const unsigned int sdhi2_data4_mux[] = {
3482 SD2_DAT0_MARK, SD2_DAT1_MARK,
3483 SD2_DAT2_MARK, SD2_DAT3_MARK,
3484};
3485static const unsigned int sdhi2_data8_pins[] = {
3486 /* D[0:7] */
3487 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3488 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3489 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3490 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3491};
3492static const unsigned int sdhi2_data8_mux[] = {
3493 SD2_DAT0_MARK, SD2_DAT1_MARK,
3494 SD2_DAT2_MARK, SD2_DAT3_MARK,
3495 SD2_DAT4_MARK, SD2_DAT5_MARK,
3496 SD2_DAT6_MARK, SD2_DAT7_MARK,
3497};
3498static const unsigned int sdhi2_ctrl_pins[] = {
3499 /* CLK, CMD */
3500 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3501};
3502static const unsigned int sdhi2_ctrl_mux[] = {
3503 SD2_CLK_MARK, SD2_CMD_MARK,
3504};
3505static const unsigned int sdhi2_cd_a_pins[] = {
3506 /* CD */
3507 RCAR_GP_PIN(4, 13),
3508};
3509static const unsigned int sdhi2_cd_a_mux[] = {
3510 SD2_CD_A_MARK,
3511};
3512static const unsigned int sdhi2_cd_b_pins[] = {
3513 /* CD */
3514 RCAR_GP_PIN(5, 10),
3515};
3516static const unsigned int sdhi2_cd_b_mux[] = {
3517 SD2_CD_B_MARK,
3518};
3519static const unsigned int sdhi2_wp_a_pins[] = {
3520 /* WP */
3521 RCAR_GP_PIN(4, 14),
3522};
3523static const unsigned int sdhi2_wp_a_mux[] = {
3524 SD2_WP_A_MARK,
3525};
3526static const unsigned int sdhi2_wp_b_pins[] = {
3527 /* WP */
3528 RCAR_GP_PIN(5, 11),
3529};
3530static const unsigned int sdhi2_wp_b_mux[] = {
3531 SD2_WP_B_MARK,
3532};
3533static const unsigned int sdhi2_ds_pins[] = {
3534 /* DS */
3535 RCAR_GP_PIN(4, 6),
3536};
3537static const unsigned int sdhi2_ds_mux[] = {
3538 SD2_DS_MARK,
3539};
3540/* - SDHI3 ------------------------------------------------------------------ */
3541static const unsigned int sdhi3_data1_pins[] = {
3542 /* D0 */
3543 RCAR_GP_PIN(4, 9),
3544};
3545static const unsigned int sdhi3_data1_mux[] = {
3546 SD3_DAT0_MARK,
3547};
3548static const unsigned int sdhi3_data4_pins[] = {
3549 /* D[0:3] */
3550 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3551 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3552};
3553static const unsigned int sdhi3_data4_mux[] = {
3554 SD3_DAT0_MARK, SD3_DAT1_MARK,
3555 SD3_DAT2_MARK, SD3_DAT3_MARK,
3556};
3557static const unsigned int sdhi3_data8_pins[] = {
3558 /* D[0:7] */
3559 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3560 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3561 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3562 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3563};
3564static const unsigned int sdhi3_data8_mux[] = {
3565 SD3_DAT0_MARK, SD3_DAT1_MARK,
3566 SD3_DAT2_MARK, SD3_DAT3_MARK,
3567 SD3_DAT4_MARK, SD3_DAT5_MARK,
3568 SD3_DAT6_MARK, SD3_DAT7_MARK,
3569};
3570static const unsigned int sdhi3_ctrl_pins[] = {
3571 /* CLK, CMD */
3572 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3573};
3574static const unsigned int sdhi3_ctrl_mux[] = {
3575 SD3_CLK_MARK, SD3_CMD_MARK,
3576};
3577static const unsigned int sdhi3_cd_pins[] = {
3578 /* CD */
3579 RCAR_GP_PIN(4, 15),
3580};
3581static const unsigned int sdhi3_cd_mux[] = {
3582 SD3_CD_MARK,
3583};
3584static const unsigned int sdhi3_wp_pins[] = {
3585 /* WP */
3586 RCAR_GP_PIN(4, 16),
3587};
3588static const unsigned int sdhi3_wp_mux[] = {
3589 SD3_WP_MARK,
3590};
3591static const unsigned int sdhi3_ds_pins[] = {
3592 /* DS */
3593 RCAR_GP_PIN(4, 17),
3594};
3595static const unsigned int sdhi3_ds_mux[] = {
3596 SD3_DS_MARK,
3597};
3598
0526234d
KM		 3599/* - SSI -------------------------------------------------------------------- */
3600static const unsigned int ssi0_data_pins[] = {
3601 /* SDATA */
3602 RCAR_GP_PIN(6, 2),
3603};
3604static const unsigned int ssi0_data_mux[] = {
3605 SSI_SDATA0_MARK,
3606};
3607static const unsigned int ssi01239_ctrl_pins[] = {
3608 /* SCK, WS */
3609 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3610};
3611static const unsigned int ssi01239_ctrl_mux[] = {
3612 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3613};
3614static const unsigned int ssi1_data_a_pins[] = {
3615 /* SDATA */
3616 RCAR_GP_PIN(6, 3),
3617};
3618static const unsigned int ssi1_data_a_mux[] = {
3619 SSI_SDATA1_A_MARK,
3620};
3621static const unsigned int ssi1_data_b_pins[] = {
3622 /* SDATA */
3623 RCAR_GP_PIN(5, 12),
3624};
3625static const unsigned int ssi1_data_b_mux[] = {
3626 SSI_SDATA1_B_MARK,
3627};
3628static const unsigned int ssi1_ctrl_a_pins[] = {
3629 /* SCK, WS */
3630 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3631};
3632static const unsigned int ssi1_ctrl_a_mux[] = {
3633 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3634};
3635static const unsigned int ssi1_ctrl_b_pins[] = {
3636 /* SCK, WS */
3637 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3638};
3639static const unsigned int ssi1_ctrl_b_mux[] = {
3640 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3641};
3642static const unsigned int ssi2_data_a_pins[] = {
3643 /* SDATA */
3644 RCAR_GP_PIN(6, 4),
3645};
3646static const unsigned int ssi2_data_a_mux[] = {
3647 SSI_SDATA2_A_MARK,
3648};
3649static const unsigned int ssi2_data_b_pins[] = {
3650 /* SDATA */
3651 RCAR_GP_PIN(5, 13),
3652};
3653static const unsigned int ssi2_data_b_mux[] = {
3654 SSI_SDATA2_B_MARK,
3655};
3656static const unsigned int ssi2_ctrl_a_pins[] = {
3657 /* SCK, WS */
3658 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3659};
3660static const unsigned int ssi2_ctrl_a_mux[] = {
3661 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3662};
3663static const unsigned int ssi2_ctrl_b_pins[] = {
3664 /* SCK, WS */
3665 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3666};
3667static const unsigned int ssi2_ctrl_b_mux[] = {
3668 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3669};
3670static const unsigned int ssi3_data_pins[] = {
3671 /* SDATA */
3672 RCAR_GP_PIN(6, 7),
3673};
3674static const unsigned int ssi3_data_mux[] = {
3675 SSI_SDATA3_MARK,
3676};
3677static const unsigned int ssi349_ctrl_pins[] = {
3678 /* SCK, WS */
3679 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3680};
3681static const unsigned int ssi349_ctrl_mux[] = {
3682 SSI_SCK349_MARK, SSI_WS349_MARK,
3683};
3684static const unsigned int ssi4_data_pins[] = {
3685 /* SDATA */
3686 RCAR_GP_PIN(6, 10),
3687};
3688static const unsigned int ssi4_data_mux[] = {
3689 SSI_SDATA4_MARK,
3690};
3691static const unsigned int ssi4_ctrl_pins[] = {
3692 /* SCK, WS */
3693 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3694};
3695static const unsigned int ssi4_ctrl_mux[] = {
3696 SSI_SCK4_MARK, SSI_WS4_MARK,
3697};
3698static const unsigned int ssi5_data_pins[] = {
3699 /* SDATA */
3700 RCAR_GP_PIN(6, 13),
3701};
3702static const unsigned int ssi5_data_mux[] = {
3703 SSI_SDATA5_MARK,
3704};
3705static const unsigned int ssi5_ctrl_pins[] = {
3706 /* SCK, WS */
3707 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3708};
3709static const unsigned int ssi5_ctrl_mux[] = {
3710 SSI_SCK5_MARK, SSI_WS5_MARK,
3711};
3712static const unsigned int ssi6_data_pins[] = {
3713 /* SDATA */
3714 RCAR_GP_PIN(6, 16),
3715};
3716static const unsigned int ssi6_data_mux[] = {
3717 SSI_SDATA6_MARK,
3718};
3719static const unsigned int ssi6_ctrl_pins[] = {
3720 /* SCK, WS */
3721 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3722};
3723static const unsigned int ssi6_ctrl_mux[] = {
3724 SSI_SCK6_MARK, SSI_WS6_MARK,
3725};
3726static const unsigned int ssi7_data_pins[] = {
3727 /* SDATA */
3728 RCAR_GP_PIN(6, 19),
3729};
3730static const unsigned int ssi7_data_mux[] = {
3731 SSI_SDATA7_MARK,
3732};
3733static const unsigned int ssi78_ctrl_pins[] = {
3734 /* SCK, WS */
3735 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3736};
3737static const unsigned int ssi78_ctrl_mux[] = {
3738 SSI_SCK78_MARK, SSI_WS78_MARK,
3739};
3740static const unsigned int ssi8_data_pins[] = {
3741 /* SDATA */
3742 RCAR_GP_PIN(6, 20),
3743};
3744static const unsigned int ssi8_data_mux[] = {
3745 SSI_SDATA8_MARK,
3746};
3747static const unsigned int ssi9_data_a_pins[] = {
3748 /* SDATA */
3749 RCAR_GP_PIN(6, 21),
3750};
3751static const unsigned int ssi9_data_a_mux[] = {
3752 SSI_SDATA9_A_MARK,
3753};
3754static const unsigned int ssi9_data_b_pins[] = {
3755 /* SDATA */
3756 RCAR_GP_PIN(5, 14),
3757};
3758static const unsigned int ssi9_data_b_mux[] = {
3759 SSI_SDATA9_B_MARK,
3760};
3761static const unsigned int ssi9_ctrl_a_pins[] = {
3762 /* SCK, WS */
3763 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3764};
3765static const unsigned int ssi9_ctrl_a_mux[] = {
3766 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3767};
3768static const unsigned int ssi9_ctrl_b_pins[] = {
3769 /* SCK, WS */
3770 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3771};
3772static const unsigned int ssi9_ctrl_b_mux[] = {
3773 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3774};
3775
933ddbe5
YS		 3776/* - USB0 ------------------------------------------------------------------- */
3777static const unsigned int usb0_pins[] = {
3778 /* PWEN, OVC */
3779 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3780};
3781static const unsigned int usb0_mux[] = {
3782 USB0_PWEN_MARK, USB0_OVC_MARK,
3783};
3784/* - USB1 ------------------------------------------------------------------- */
3785static const unsigned int usb1_pins[] = {
3786 /* PWEN, OVC */
3787 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3788};
3789static const unsigned int usb1_mux[] = {
3790 USB1_PWEN_MARK, USB1_OVC_MARK,
3791};
3792/* - USB2 ------------------------------------------------------------------- */
3793static const unsigned int usb2_pins[] = {
3794 /* PWEN, OVC */
3795 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3796};
3797static const unsigned int usb2_mux[] = {
3798 USB2_PWEN_MARK, USB2_OVC_MARK,
3799};
3800/* - USB2_CH3 --------------------------------------------------------------- */
3801static const unsigned int usb2_ch3_pins[] = {
3802 /* PWEN, OVC */
3803 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3804};
3805static const unsigned int usb2_ch3_mux[] = {
3806 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3807};
3808
5ec8a41a
TK		 3809/* - USB30 ------------------------------------------------------------------ */
3810static const unsigned int usb30_pins[] = {
3811 /* PWEN, OVC */
3812 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3813};
3814static const unsigned int usb30_mux[] = {
3815 USB30_PWEN_MARK, USB30_OVC_MARK,
3816};
3817
b205914c 3818static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 3819 SH_PFC_PIN_GROUP(audio_clk_a_a),
3820 SH_PFC_PIN_GROUP(audio_clk_a_b),
3821 SH_PFC_PIN_GROUP(audio_clk_a_c),
3822 SH_PFC_PIN_GROUP(audio_clk_b_a),
3823 SH_PFC_PIN_GROUP(audio_clk_b_b),
3824 SH_PFC_PIN_GROUP(audio_clk_c_a),
3825 SH_PFC_PIN_GROUP(audio_clk_c_b),
3826 SH_PFC_PIN_GROUP(audio_clkout_a),
3827 SH_PFC_PIN_GROUP(audio_clkout_b),
3828 SH_PFC_PIN_GROUP(audio_clkout_c),
3829 SH_PFC_PIN_GROUP(audio_clkout_d),
3830 SH_PFC_PIN_GROUP(audio_clkout1_a),
3831 SH_PFC_PIN_GROUP(audio_clkout1_b),
3832 SH_PFC_PIN_GROUP(audio_clkout2_a),
3833 SH_PFC_PIN_GROUP(audio_clkout2_b),
3834 SH_PFC_PIN_GROUP(audio_clkout3_a),
3835 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 3836 SH_PFC_PIN_GROUP(avb_link),
3837 SH_PFC_PIN_GROUP(avb_magic),
3838 SH_PFC_PIN_GROUP(avb_phy_int),
3839 SH_PFC_PIN_GROUP(avb_mdc),
3840 SH_PFC_PIN_GROUP(avb_mii),
3841 SH_PFC_PIN_GROUP(avb_avtp_pps),
3842 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3843 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3844 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3845 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
641b0ab8
DB		 3846 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3847 SH_PFC_PIN_GROUP(drif0_data0_a),
3848 SH_PFC_PIN_GROUP(drif0_data1_a),
3849 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3850 SH_PFC_PIN_GROUP(drif0_data0_b),
3851 SH_PFC_PIN_GROUP(drif0_data1_b),
3852 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3853 SH_PFC_PIN_GROUP(drif0_data0_c),
3854 SH_PFC_PIN_GROUP(drif0_data1_c),
3855 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3856 SH_PFC_PIN_GROUP(drif1_data0_a),
3857 SH_PFC_PIN_GROUP(drif1_data1_a),
3858 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3859 SH_PFC_PIN_GROUP(drif1_data0_b),
3860 SH_PFC_PIN_GROUP(drif1_data1_b),
3861 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3862 SH_PFC_PIN_GROUP(drif1_data0_c),
3863 SH_PFC_PIN_GROUP(drif1_data1_c),
3864 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3865 SH_PFC_PIN_GROUP(drif2_data0_a),
3866 SH_PFC_PIN_GROUP(drif2_data1_a),
3867 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3868 SH_PFC_PIN_GROUP(drif2_data0_b),
3869 SH_PFC_PIN_GROUP(drif2_data1_b),
3870 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3871 SH_PFC_PIN_GROUP(drif3_data0_a),
3872 SH_PFC_PIN_GROUP(drif3_data1_a),
3873 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3874 SH_PFC_PIN_GROUP(drif3_data0_b),
3875 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 3876 SH_PFC_PIN_GROUP(du_rgb666),
3877 SH_PFC_PIN_GROUP(du_rgb888),
3878 SH_PFC_PIN_GROUP(du_clk_out_0),
3879 SH_PFC_PIN_GROUP(du_clk_out_1),
3880 SH_PFC_PIN_GROUP(du_sync),
3881 SH_PFC_PIN_GROUP(du_oddf),
3882 SH_PFC_PIN_GROUP(du_cde),
3883 SH_PFC_PIN_GROUP(du_disp),
7a362e34
WS		 3884 SH_PFC_PIN_GROUP(hscif0_data),
3885 SH_PFC_PIN_GROUP(hscif0_clk),
3886 SH_PFC_PIN_GROUP(hscif0_ctrl),
3887 SH_PFC_PIN_GROUP(hscif1_data_a),
3888 SH_PFC_PIN_GROUP(hscif1_clk_a),
3889 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3890 SH_PFC_PIN_GROUP(hscif1_data_b),
3891 SH_PFC_PIN_GROUP(hscif1_clk_b),
3892 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3893 SH_PFC_PIN_GROUP(hscif2_data_a),
3894 SH_PFC_PIN_GROUP(hscif2_clk_a),
3895 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3896 SH_PFC_PIN_GROUP(hscif2_data_b),
3897 SH_PFC_PIN_GROUP(hscif2_clk_b),
3898 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3899 SH_PFC_PIN_GROUP(hscif2_data_c),
3900 SH_PFC_PIN_GROUP(hscif2_clk_c),
3901 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3902 SH_PFC_PIN_GROUP(hscif3_data_a),
3903 SH_PFC_PIN_GROUP(hscif3_clk),
3904 SH_PFC_PIN_GROUP(hscif3_ctrl),
3905 SH_PFC_PIN_GROUP(hscif3_data_b),
3906 SH_PFC_PIN_GROUP(hscif3_data_c),
3907 SH_PFC_PIN_GROUP(hscif3_data_d),
3908 SH_PFC_PIN_GROUP(hscif4_data_a),
3909 SH_PFC_PIN_GROUP(hscif4_clk),
3910 SH_PFC_PIN_GROUP(hscif4_ctrl),
3911 SH_PFC_PIN_GROUP(hscif4_data_b),
f62d4c9e
WS		 3912 SH_PFC_PIN_GROUP(i2c1_a),
3913 SH_PFC_PIN_GROUP(i2c1_b),
3914 SH_PFC_PIN_GROUP(i2c2_a),
3915 SH_PFC_PIN_GROUP(i2c2_b),
3916 SH_PFC_PIN_GROUP(i2c6_a),
3917 SH_PFC_PIN_GROUP(i2c6_b),
3918 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 3919 SH_PFC_PIN_GROUP(intc_ex_irq0),
3920 SH_PFC_PIN_GROUP(intc_ex_irq1),
3921 SH_PFC_PIN_GROUP(intc_ex_irq2),
3922 SH_PFC_PIN_GROUP(intc_ex_irq3),
3923 SH_PFC_PIN_GROUP(intc_ex_irq4),
3924 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 3925 SH_PFC_PIN_GROUP(msiof0_clk),
3926 SH_PFC_PIN_GROUP(msiof0_sync),
3927 SH_PFC_PIN_GROUP(msiof0_ss1),
3928 SH_PFC_PIN_GROUP(msiof0_ss2),
3929 SH_PFC_PIN_GROUP(msiof0_txd),
3930 SH_PFC_PIN_GROUP(msiof0_rxd),
3931 SH_PFC_PIN_GROUP(msiof1_clk_a),
3932 SH_PFC_PIN_GROUP(msiof1_sync_a),
3933 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3934 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3935 SH_PFC_PIN_GROUP(msiof1_txd_a),
3936 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3937 SH_PFC_PIN_GROUP(msiof1_clk_b),
3938 SH_PFC_PIN_GROUP(msiof1_sync_b),
3939 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3940 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3941 SH_PFC_PIN_GROUP(msiof1_txd_b),
3942 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3943 SH_PFC_PIN_GROUP(msiof1_clk_c),
3944 SH_PFC_PIN_GROUP(msiof1_sync_c),
3945 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3946 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3947 SH_PFC_PIN_GROUP(msiof1_txd_c),
3948 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3949 SH_PFC_PIN_GROUP(msiof1_clk_d),
3950 SH_PFC_PIN_GROUP(msiof1_sync_d),
3951 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3952 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3953 SH_PFC_PIN_GROUP(msiof1_txd_d),
3954 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3955 SH_PFC_PIN_GROUP(msiof1_clk_e),
3956 SH_PFC_PIN_GROUP(msiof1_sync_e),
3957 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3958 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3959 SH_PFC_PIN_GROUP(msiof1_txd_e),
3960 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3961 SH_PFC_PIN_GROUP(msiof1_clk_f),
3962 SH_PFC_PIN_GROUP(msiof1_sync_f),
3963 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3964 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3965 SH_PFC_PIN_GROUP(msiof1_txd_f),
3966 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3967 SH_PFC_PIN_GROUP(msiof1_clk_g),
3968 SH_PFC_PIN_GROUP(msiof1_sync_g),
3969 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3970 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3971 SH_PFC_PIN_GROUP(msiof1_txd_g),
3972 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3973 SH_PFC_PIN_GROUP(msiof2_clk_a),
3974 SH_PFC_PIN_GROUP(msiof2_sync_a),
3975 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3976 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3977 SH_PFC_PIN_GROUP(msiof2_txd_a),
3978 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3979 SH_PFC_PIN_GROUP(msiof2_clk_b),
3980 SH_PFC_PIN_GROUP(msiof2_sync_b),
3981 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3982 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3983 SH_PFC_PIN_GROUP(msiof2_txd_b),
3984 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3985 SH_PFC_PIN_GROUP(msiof2_clk_c),
3986 SH_PFC_PIN_GROUP(msiof2_sync_c),
3987 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3988 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3989 SH_PFC_PIN_GROUP(msiof2_txd_c),
3990 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3991 SH_PFC_PIN_GROUP(msiof2_clk_d),
3992 SH_PFC_PIN_GROUP(msiof2_sync_d),
3993 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3994 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3995 SH_PFC_PIN_GROUP(msiof2_txd_d),
3996 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3997 SH_PFC_PIN_GROUP(msiof3_clk_a),
3998 SH_PFC_PIN_GROUP(msiof3_sync_a),
3999 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4000 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4001 SH_PFC_PIN_GROUP(msiof3_txd_a),
4002 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4003 SH_PFC_PIN_GROUP(msiof3_clk_b),
4004 SH_PFC_PIN_GROUP(msiof3_sync_b),
4005 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4006 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4007 SH_PFC_PIN_GROUP(msiof3_txd_b),
4008 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4009 SH_PFC_PIN_GROUP(msiof3_clk_c),
4010 SH_PFC_PIN_GROUP(msiof3_sync_c),
4011 SH_PFC_PIN_GROUP(msiof3_txd_c),
4012 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4013 SH_PFC_PIN_GROUP(msiof3_clk_d),
4014 SH_PFC_PIN_GROUP(msiof3_sync_d),
4015 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4016 SH_PFC_PIN_GROUP(msiof3_txd_d),
4017 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4018 SH_PFC_PIN_GROUP(msiof3_clk_e),
4019 SH_PFC_PIN_GROUP(msiof3_sync_e),
4020 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4021 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4022 SH_PFC_PIN_GROUP(msiof3_txd_e),
4023 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4024 SH_PFC_PIN_GROUP(pwm0),
4025 SH_PFC_PIN_GROUP(pwm1_a),
4026 SH_PFC_PIN_GROUP(pwm1_b),
4027 SH_PFC_PIN_GROUP(pwm2_a),
4028 SH_PFC_PIN_GROUP(pwm2_b),
4029 SH_PFC_PIN_GROUP(pwm3_a),
4030 SH_PFC_PIN_GROUP(pwm3_b),
4031 SH_PFC_PIN_GROUP(pwm4_a),
4032 SH_PFC_PIN_GROUP(pwm4_b),
4033 SH_PFC_PIN_GROUP(pwm5_a),
4034 SH_PFC_PIN_GROUP(pwm5_b),
4035 SH_PFC_PIN_GROUP(pwm6_a),
4036 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 4037 SH_PFC_PIN_GROUP(scif0_data),
4038 SH_PFC_PIN_GROUP(scif0_clk),
4039 SH_PFC_PIN_GROUP(scif0_ctrl),
4040 SH_PFC_PIN_GROUP(scif1_data_a),
4041 SH_PFC_PIN_GROUP(scif1_clk),
4042 SH_PFC_PIN_GROUP(scif1_ctrl),
4043 SH_PFC_PIN_GROUP(scif1_data_b),
4044 SH_PFC_PIN_GROUP(scif2_data_a),
4045 SH_PFC_PIN_GROUP(scif2_clk),
4046 SH_PFC_PIN_GROUP(scif2_data_b),
4047 SH_PFC_PIN_GROUP(scif3_data_a),
4048 SH_PFC_PIN_GROUP(scif3_clk),
4049 SH_PFC_PIN_GROUP(scif3_ctrl),
4050 SH_PFC_PIN_GROUP(scif3_data_b),
4051 SH_PFC_PIN_GROUP(scif4_data_a),
4052 SH_PFC_PIN_GROUP(scif4_clk_a),
4053 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4054 SH_PFC_PIN_GROUP(scif4_data_b),
4055 SH_PFC_PIN_GROUP(scif4_clk_b),
4056 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4057 SH_PFC_PIN_GROUP(scif4_data_c),
4058 SH_PFC_PIN_GROUP(scif4_clk_c),
4059 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4060 SH_PFC_PIN_GROUP(scif5_data_a),
4061 SH_PFC_PIN_GROUP(scif5_clk_a),
4062 SH_PFC_PIN_GROUP(scif5_data_b),
4063 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4064 SH_PFC_PIN_GROUP(scif_clk_a),
4065 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4066 SH_PFC_PIN_GROUP(sdhi0_data1),
4067 SH_PFC_PIN_GROUP(sdhi0_data4),
4068 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4069 SH_PFC_PIN_GROUP(sdhi0_cd),
4070 SH_PFC_PIN_GROUP(sdhi0_wp),
4071 SH_PFC_PIN_GROUP(sdhi1_data1),
4072 SH_PFC_PIN_GROUP(sdhi1_data4),
4073 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4074 SH_PFC_PIN_GROUP(sdhi1_cd),
4075 SH_PFC_PIN_GROUP(sdhi1_wp),
4076 SH_PFC_PIN_GROUP(sdhi2_data1),
4077 SH_PFC_PIN_GROUP(sdhi2_data4),
4078 SH_PFC_PIN_GROUP(sdhi2_data8),
4079 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4080 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4081 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4082 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4083 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4084 SH_PFC_PIN_GROUP(sdhi2_ds),
4085 SH_PFC_PIN_GROUP(sdhi3_data1),
4086 SH_PFC_PIN_GROUP(sdhi3_data4),
4087 SH_PFC_PIN_GROUP(sdhi3_data8),
4088 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4089 SH_PFC_PIN_GROUP(sdhi3_cd),
4090 SH_PFC_PIN_GROUP(sdhi3_wp),
4091 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4092 SH_PFC_PIN_GROUP(ssi0_data),
4093 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4094 SH_PFC_PIN_GROUP(ssi1_data_a),
4095 SH_PFC_PIN_GROUP(ssi1_data_b),
4096 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4097 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4098 SH_PFC_PIN_GROUP(ssi2_data_a),
4099 SH_PFC_PIN_GROUP(ssi2_data_b),
4100 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4101 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4102 SH_PFC_PIN_GROUP(ssi3_data),
4103 SH_PFC_PIN_GROUP(ssi349_ctrl),
4104 SH_PFC_PIN_GROUP(ssi4_data),
4105 SH_PFC_PIN_GROUP(ssi4_ctrl),
4106 SH_PFC_PIN_GROUP(ssi5_data),
4107 SH_PFC_PIN_GROUP(ssi5_ctrl),
4108 SH_PFC_PIN_GROUP(ssi6_data),
4109 SH_PFC_PIN_GROUP(ssi6_ctrl),
4110 SH_PFC_PIN_GROUP(ssi7_data),
4111 SH_PFC_PIN_GROUP(ssi78_ctrl),
4112 SH_PFC_PIN_GROUP(ssi8_data),
4113 SH_PFC_PIN_GROUP(ssi9_data_a),
4114 SH_PFC_PIN_GROUP(ssi9_data_b),
4115 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4116 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
933ddbe5
YS		 4117 SH_PFC_PIN_GROUP(usb0),
4118 SH_PFC_PIN_GROUP(usb1),
4119 SH_PFC_PIN_GROUP(usb2),
4120 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4121 SH_PFC_PIN_GROUP(usb30),
e7ad4d3c
GU		 4122};
4123
55bfea9f
KM		 4124static const char * const audio_clk_groups[] = {
4125 "audio_clk_a_a",
4126 "audio_clk_a_b",
4127 "audio_clk_a_c",
4128 "audio_clk_b_a",
4129 "audio_clk_b_b",
4130 "audio_clk_c_a",
4131 "audio_clk_c_b",
4132 "audio_clkout_a",
4133 "audio_clkout_b",
4134 "audio_clkout_c",
4135 "audio_clkout_d",
4136 "audio_clkout1_a",
4137 "audio_clkout1_b",
4138 "audio_clkout2_a",
4139 "audio_clkout2_b",
4140 "audio_clkout3_a",
4141 "audio_clkout3_b",
4142};
4143
30c078de
GU		 4144static const char * const avb_groups[] = {
4145 "avb_link",
4146 "avb_magic",
4147 "avb_phy_int",
4148 "avb_mdc",
4149 "avb_mii",
4150 "avb_avtp_pps",
4151 "avb_avtp_match_a",
4152 "avb_avtp_capture_a",
4153 "avb_avtp_match_b",
4154 "avb_avtp_capture_b",
4155};
4156
641b0ab8
DB		 4157static const char * const drif0_groups[] = {
4158 "drif0_ctrl_a",
4159 "drif0_data0_a",
4160 "drif0_data1_a",
4161 "drif0_ctrl_b",
4162 "drif0_data0_b",
4163 "drif0_data1_b",
4164 "drif0_ctrl_c",
4165 "drif0_data0_c",
4166 "drif0_data1_c",
4167};
4168
4169static const char * const drif1_groups[] = {
4170 "drif1_ctrl_a",
4171 "drif1_data0_a",
4172 "drif1_data1_a",
4173 "drif1_ctrl_b",
4174 "drif1_data0_b",
4175 "drif1_data1_b",
4176 "drif1_ctrl_c",
4177 "drif1_data0_c",
4178 "drif1_data1_c",
4179};
4180
4181static const char * const drif2_groups[] = {
4182 "drif2_ctrl_a",
4183 "drif2_data0_a",
4184 "drif2_data1_a",
4185 "drif2_ctrl_b",
4186 "drif2_data0_b",
4187 "drif2_data1_b",
4188};
4189
4190static const char * const drif3_groups[] = {
4191 "drif3_ctrl_a",
4192 "drif3_data0_a",
4193 "drif3_data1_a",
4194 "drif3_ctrl_b",
4195 "drif3_data0_b",
4196 "drif3_data1_b",
4197};
4198
a20a6585
LP		 4199static const char * const du_groups[] = {
4200 "du_rgb666",
4201 "du_rgb888",
4202 "du_clk_out_0",
4203 "du_clk_out_1",
4204 "du_sync",
4205 "du_oddf",
4206 "du_cde",
4207 "du_disp",
4208};
4209
7a362e34
WS		 4210static const char * const hscif0_groups[] = {
4211 "hscif0_data",
4212 "hscif0_clk",
4213 "hscif0_ctrl",
4214};
4215
4216static const char * const hscif1_groups[] = {
4217 "hscif1_data_a",
4218 "hscif1_clk_a",
4219 "hscif1_ctrl_a",
4220 "hscif1_data_b",
4221 "hscif1_clk_b",
4222 "hscif1_ctrl_b",
4223};
4224
4225static const char * const hscif2_groups[] = {
4226 "hscif2_data_a",
4227 "hscif2_clk_a",
4228 "hscif2_ctrl_a",
4229 "hscif2_data_b",
4230 "hscif2_clk_b",
4231 "hscif2_ctrl_b",
4232 "hscif2_data_c",
4233 "hscif2_clk_c",
4234 "hscif2_ctrl_c",
4235};
4236
4237static const char * const hscif3_groups[] = {
4238 "hscif3_data_a",
4239 "hscif3_clk",
4240 "hscif3_ctrl",
4241 "hscif3_data_b",
4242 "hscif3_data_c",
4243 "hscif3_data_d",
4244};
4245
4246static const char * const hscif4_groups[] = {
4247 "hscif4_data_a",
4248 "hscif4_clk",
4249 "hscif4_ctrl",
4250 "hscif4_data_b",
4251};
4252
f62d4c9e
WS		 4253static const char * const i2c1_groups[] = {
4254 "i2c1_a",
4255 "i2c1_b",
4256};
4257
4258static const char * const i2c2_groups[] = {
4259 "i2c2_a",
4260 "i2c2_b",
4261};
4262
4263static const char * const i2c6_groups[] = {
4264 "i2c6_a",
4265 "i2c6_b",
4266 "i2c6_c",
4267};
4268
8480e6ca
GU		 4269static const char * const intc_ex_groups[] = {
4270 "intc_ex_irq0",
4271 "intc_ex_irq1",
4272 "intc_ex_irq2",
4273 "intc_ex_irq3",
4274 "intc_ex_irq4",
4275 "intc_ex_irq5",
4276};
4277
3e6c7727
GU		 4278static const char * const msiof0_groups[] = {
4279 "msiof0_clk",
4280 "msiof0_sync",
4281 "msiof0_ss1",
4282 "msiof0_ss2",
4283 "msiof0_txd",
4284 "msiof0_rxd",
4285};
4286
4287static const char * const msiof1_groups[] = {
4288 "msiof1_clk_a",
4289 "msiof1_sync_a",
4290 "msiof1_ss1_a",
4291 "msiof1_ss2_a",
4292 "msiof1_txd_a",
4293 "msiof1_rxd_a",
4294 "msiof1_clk_b",
4295 "msiof1_sync_b",
4296 "msiof1_ss1_b",
4297 "msiof1_ss2_b",
4298 "msiof1_txd_b",
4299 "msiof1_rxd_b",
4300 "msiof1_clk_c",
4301 "msiof1_sync_c",
4302 "msiof1_ss1_c",
4303 "msiof1_ss2_c",
4304 "msiof1_txd_c",
4305 "msiof1_rxd_c",
4306 "msiof1_clk_d",
4307 "msiof1_sync_d",
4308 "msiof1_ss1_d",
4309 "msiof1_ss2_d",
4310 "msiof1_txd_d",
4311 "msiof1_rxd_d",
4312 "msiof1_clk_e",
4313 "msiof1_sync_e",
4314 "msiof1_ss1_e",
4315 "msiof1_ss2_e",
4316 "msiof1_txd_e",
4317 "msiof1_rxd_e",
4318 "msiof1_clk_f",
4319 "msiof1_sync_f",
4320 "msiof1_ss1_f",
4321 "msiof1_ss2_f",
4322 "msiof1_txd_f",
4323 "msiof1_rxd_f",
4324 "msiof1_clk_g",
4325 "msiof1_sync_g",
4326 "msiof1_ss1_g",
4327 "msiof1_ss2_g",
4328 "msiof1_txd_g",
4329 "msiof1_rxd_g",
4330};
4331
4332static const char * const msiof2_groups[] = {
4333 "msiof2_clk_a",
4334 "msiof2_sync_a",
4335 "msiof2_ss1_a",
4336 "msiof2_ss2_a",
4337 "msiof2_txd_a",
4338 "msiof2_rxd_a",
4339 "msiof2_clk_b",
4340 "msiof2_sync_b",
4341 "msiof2_ss1_b",
4342 "msiof2_ss2_b",
4343 "msiof2_txd_b",
4344 "msiof2_rxd_b",
4345 "msiof2_clk_c",
4346 "msiof2_sync_c",
4347 "msiof2_ss1_c",
4348 "msiof2_ss2_c",
4349 "msiof2_txd_c",
4350 "msiof2_rxd_c",
4351 "msiof2_clk_d",
4352 "msiof2_sync_d",
4353 "msiof2_ss1_d",
4354 "msiof2_ss2_d",
4355 "msiof2_txd_d",
4356 "msiof2_rxd_d",
4357};
4358
4359static const char * const msiof3_groups[] = {
4360 "msiof3_clk_a",
4361 "msiof3_sync_a",
4362 "msiof3_ss1_a",
4363 "msiof3_ss2_a",
4364 "msiof3_txd_a",
4365 "msiof3_rxd_a",
4366 "msiof3_clk_b",
4367 "msiof3_sync_b",
4368 "msiof3_ss1_b",
4369 "msiof3_ss2_b",
4370 "msiof3_txd_b",
4371 "msiof3_rxd_b",
4372 "msiof3_clk_c",
4373 "msiof3_sync_c",
4374 "msiof3_txd_c",
4375 "msiof3_rxd_c",
4376 "msiof3_clk_d",
4377 "msiof3_sync_d",
4378 "msiof3_ss1_d",
4379 "msiof3_txd_d",
4380 "msiof3_rxd_d",
4381 "msiof3_clk_e",
4382 "msiof3_sync_e",
4383 "msiof3_ss1_e",
4384 "msiof3_ss2_e",
4385 "msiof3_txd_e",
4386 "msiof3_rxd_e",
4387};
4388
c03a133b
LP		 4389static const char * const pwm0_groups[] = {
4390 "pwm0",
4391};
4392
4393static const char * const pwm1_groups[] = {
4394 "pwm1_a",
4395 "pwm1_b",
4396};
4397
4398static const char * const pwm2_groups[] = {
4399 "pwm2_a",
4400 "pwm2_b",
4401};
4402
4403static const char * const pwm3_groups[] = {
4404 "pwm3_a",
4405 "pwm3_b",
4406};
4407
4408static const char * const pwm4_groups[] = {
4409 "pwm4_a",
4410 "pwm4_b",
4411};
4412
4413static const char * const pwm5_groups[] = {
4414 "pwm5_a",
4415 "pwm5_b",
4416};
4417
4418static const char * const pwm6_groups[] = {
4419 "pwm6_a",
4420 "pwm6_b",
4421};
4422
e7ad4d3c
GU		 4423static const char * const scif0_groups[] = {
4424 "scif0_data",
4425 "scif0_clk",
4426 "scif0_ctrl",
4427};
4428
4429static const char * const scif1_groups[] = {
4430 "scif1_data_a",
4431 "scif1_clk",
4432 "scif1_ctrl",
4433 "scif1_data_b",
4434};
4435
4436static const char * const scif2_groups[] = {
4437 "scif2_data_a",
4438 "scif2_clk",
4439 "scif2_data_b",
4440};
4441
4442static const char * const scif3_groups[] = {
4443 "scif3_data_a",
4444 "scif3_clk",
4445 "scif3_ctrl",
4446 "scif3_data_b",
4447};
4448
4449static const char * const scif4_groups[] = {
4450 "scif4_data_a",
4451 "scif4_clk_a",
4452 "scif4_ctrl_a",
4453 "scif4_data_b",
4454 "scif4_clk_b",
4455 "scif4_ctrl_b",
4456 "scif4_data_c",
4457 "scif4_clk_c",
4458 "scif4_ctrl_c",
4459};
4460
4461static const char * const scif5_groups[] = {
4462 "scif5_data_a",
4463 "scif5_clk_a",
4464 "scif5_data_b",
4465 "scif5_clk_b",
76250a6c
TK		 4466};
4467
d14a39ed
GU		 4468static const char * const scif_clk_groups[] = {
4469 "scif_clk_a",
4470 "scif_clk_b",
4471};
4472
9ed13958
TK		 4473static const char * const sdhi0_groups[] = {
4474 "sdhi0_data1",
4475 "sdhi0_data4",
4476 "sdhi0_ctrl",
4477 "sdhi0_cd",
4478 "sdhi0_wp",
4479};
4480
4481static const char * const sdhi1_groups[] = {
4482 "sdhi1_data1",
4483 "sdhi1_data4",
4484 "sdhi1_ctrl",
4485 "sdhi1_cd",
4486 "sdhi1_wp",
4487};
4488
4489static const char * const sdhi2_groups[] = {
4490 "sdhi2_data1",
4491 "sdhi2_data4",
4492 "sdhi2_data8",
4493 "sdhi2_ctrl",
4494 "sdhi2_cd_a",
4495 "sdhi2_wp_a",
4496 "sdhi2_cd_b",
4497 "sdhi2_wp_b",
4498 "sdhi2_ds",
4499};
4500
4501static const char * const sdhi3_groups[] = {
4502 "sdhi3_data1",
4503 "sdhi3_data4",
4504 "sdhi3_data8",
4505 "sdhi3_ctrl",
4506 "sdhi3_cd",
4507 "sdhi3_wp",
4508 "sdhi3_ds",
4509};
4510
0526234d
KM		 4511static const char * const ssi_groups[] = {
4512 "ssi0_data",
4513 "ssi01239_ctrl",
4514 "ssi1_data_a",
4515 "ssi1_data_b",
4516 "ssi1_ctrl_a",
4517 "ssi1_ctrl_b",
4518 "ssi2_data_a",
4519 "ssi2_data_b",
4520 "ssi2_ctrl_a",
4521 "ssi2_ctrl_b",
4522 "ssi3_data",
4523 "ssi349_ctrl",
4524 "ssi4_data",
4525 "ssi4_ctrl",
4526 "ssi5_data",
4527 "ssi5_ctrl",
4528 "ssi6_data",
4529 "ssi6_ctrl",
4530 "ssi7_data",
4531 "ssi78_ctrl",
4532 "ssi8_data",
4533 "ssi9_data_a",
4534 "ssi9_data_b",
4535 "ssi9_ctrl_a",
4536 "ssi9_ctrl_b",
4537};
4538
933ddbe5
YS		 4539static const char * const usb0_groups[] = {
4540 "usb0",
4541};
4542
4543static const char * const usb1_groups[] = {
4544 "usb1",
4545};
4546
4547static const char * const usb2_groups[] = {
4548 "usb2",
4549};
4550
4551static const char * const usb2_ch3_groups[] = {
4552 "usb2_ch3",
4553};
4554
5ec8a41a
TK		 4555static const char * const usb30_groups[] = {
4556 "usb30",
4557};
4558
0b0ffc96 4559static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 4560 SH_PFC_FUNCTION(audio_clk),
30c078de 4561 SH_PFC_FUNCTION(avb),
641b0ab8
DB		 4562 SH_PFC_FUNCTION(drif0),
4563 SH_PFC_FUNCTION(drif1),
4564 SH_PFC_FUNCTION(drif2),
4565 SH_PFC_FUNCTION(drif3),
a20a6585 4566 SH_PFC_FUNCTION(du),
7a362e34
WS		 4567 SH_PFC_FUNCTION(hscif0),
4568 SH_PFC_FUNCTION(hscif1),
4569 SH_PFC_FUNCTION(hscif2),
4570 SH_PFC_FUNCTION(hscif3),
4571 SH_PFC_FUNCTION(hscif4),
f62d4c9e
WS		 4572 SH_PFC_FUNCTION(i2c1),
4573 SH_PFC_FUNCTION(i2c2),
4574 SH_PFC_FUNCTION(i2c6),
8480e6ca 4575 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 4576 SH_PFC_FUNCTION(msiof0),
4577 SH_PFC_FUNCTION(msiof1),
4578 SH_PFC_FUNCTION(msiof2),
4579 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 4580 SH_PFC_FUNCTION(pwm0),
4581 SH_PFC_FUNCTION(pwm1),
4582 SH_PFC_FUNCTION(pwm2),
4583 SH_PFC_FUNCTION(pwm3),
4584 SH_PFC_FUNCTION(pwm4),
4585 SH_PFC_FUNCTION(pwm5),
4586 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 4587 SH_PFC_FUNCTION(scif0),
4588 SH_PFC_FUNCTION(scif1),
4589 SH_PFC_FUNCTION(scif2),
4590 SH_PFC_FUNCTION(scif3),
4591 SH_PFC_FUNCTION(scif4),
4592 SH_PFC_FUNCTION(scif5),
d14a39ed 4593 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 4594 SH_PFC_FUNCTION(sdhi0),
4595 SH_PFC_FUNCTION(sdhi1),
4596 SH_PFC_FUNCTION(sdhi2),
4597 SH_PFC_FUNCTION(sdhi3),
0526234d 4598 SH_PFC_FUNCTION(ssi),
933ddbe5
YS		 4599 SH_PFC_FUNCTION(usb0),
4600 SH_PFC_FUNCTION(usb1),
4601 SH_PFC_FUNCTION(usb2),
4602 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 4603 SH_PFC_FUNCTION(usb30),
0b0ffc96
TK		 4604};
4605
4606static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4607#define F_(x, y) FN_##y
4608#define FM(x) FN_##x
4609 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4610 0, 0,
4611 0, 0,
4612 0, 0,
4613 0, 0,
4614 0, 0,
4615 0, 0,
4616 0, 0,
4617 0, 0,
4618 0, 0,
4619 0, 0,
4620 0, 0,
4621 0, 0,
4622 0, 0,
4623 0, 0,
4624 0, 0,
4625 0, 0,
4626 GP_0_15_FN, GPSR0_15,
4627 GP_0_14_FN, GPSR0_14,
4628 GP_0_13_FN, GPSR0_13,
4629 GP_0_12_FN, GPSR0_12,
4630 GP_0_11_FN, GPSR0_11,
4631 GP_0_10_FN, GPSR0_10,
4632 GP_0_9_FN, GPSR0_9,
4633 GP_0_8_FN, GPSR0_8,
4634 GP_0_7_FN, GPSR0_7,
4635 GP_0_6_FN, GPSR0_6,
4636 GP_0_5_FN, GPSR0_5,
4637 GP_0_4_FN, GPSR0_4,
4638 GP_0_3_FN, GPSR0_3,
4639 GP_0_2_FN, GPSR0_2,
4640 GP_0_1_FN, GPSR0_1,
4641 GP_0_0_FN, GPSR0_0, }
4642 },
4643 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4644 0, 0,
4645 0, 0,
4646 0, 0,
4647 0, 0,
4648 GP_1_27_FN, GPSR1_27,
4649 GP_1_26_FN, GPSR1_26,
4650 GP_1_25_FN, GPSR1_25,
4651 GP_1_24_FN, GPSR1_24,
4652 GP_1_23_FN, GPSR1_23,
4653 GP_1_22_FN, GPSR1_22,
4654 GP_1_21_FN, GPSR1_21,
4655 GP_1_20_FN, GPSR1_20,
4656 GP_1_19_FN, GPSR1_19,
4657 GP_1_18_FN, GPSR1_18,
4658 GP_1_17_FN, GPSR1_17,
4659 GP_1_16_FN, GPSR1_16,
4660 GP_1_15_FN, GPSR1_15,
4661 GP_1_14_FN, GPSR1_14,
4662 GP_1_13_FN, GPSR1_13,
4663 GP_1_12_FN, GPSR1_12,
4664 GP_1_11_FN, GPSR1_11,
4665 GP_1_10_FN, GPSR1_10,
4666 GP_1_9_FN, GPSR1_9,
4667 GP_1_8_FN, GPSR1_8,
4668 GP_1_7_FN, GPSR1_7,
4669 GP_1_6_FN, GPSR1_6,
4670 GP_1_5_FN, GPSR1_5,
4671 GP_1_4_FN, GPSR1_4,
4672 GP_1_3_FN, GPSR1_3,
4673 GP_1_2_FN, GPSR1_2,
4674 GP_1_1_FN, GPSR1_1,
4675 GP_1_0_FN, GPSR1_0, }
4676 },
4677 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4678 0, 0,
4679 0, 0,
4680 0, 0,
4681 0, 0,
4682 0, 0,
4683 0, 0,
4684 0, 0,
4685 0, 0,
4686 0, 0,
4687 0, 0,
4688 0, 0,
4689 0, 0,
4690 0, 0,
4691 0, 0,
4692 0, 0,
4693 0, 0,
4694 0, 0,
4695 GP_2_14_FN, GPSR2_14,
4696 GP_2_13_FN, GPSR2_13,
4697 GP_2_12_FN, GPSR2_12,
4698 GP_2_11_FN, GPSR2_11,
4699 GP_2_10_FN, GPSR2_10,
4700 GP_2_9_FN, GPSR2_9,
4701 GP_2_8_FN, GPSR2_8,
4702 GP_2_7_FN, GPSR2_7,
4703 GP_2_6_FN, GPSR2_6,
4704 GP_2_5_FN, GPSR2_5,
4705 GP_2_4_FN, GPSR2_4,
4706 GP_2_3_FN, GPSR2_3,
4707 GP_2_2_FN, GPSR2_2,
4708 GP_2_1_FN, GPSR2_1,
4709 GP_2_0_FN, GPSR2_0, }
4710 },
4711 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4712 0, 0,
4713 0, 0,
4714 0, 0,
4715 0, 0,
4716 0, 0,
4717 0, 0,
4718 0, 0,
4719 0, 0,
4720 0, 0,
4721 0, 0,
4722 0, 0,
4723 0, 0,
4724 0, 0,
4725 0, 0,
4726 0, 0,
4727 0, 0,
4728 GP_3_15_FN, GPSR3_15,
4729 GP_3_14_FN, GPSR3_14,
4730 GP_3_13_FN, GPSR3_13,
4731 GP_3_12_FN, GPSR3_12,
4732 GP_3_11_FN, GPSR3_11,
4733 GP_3_10_FN, GPSR3_10,
4734 GP_3_9_FN, GPSR3_9,
4735 GP_3_8_FN, GPSR3_8,
4736 GP_3_7_FN, GPSR3_7,
4737 GP_3_6_FN, GPSR3_6,
4738 GP_3_5_FN, GPSR3_5,
4739 GP_3_4_FN, GPSR3_4,
4740 GP_3_3_FN, GPSR3_3,
4741 GP_3_2_FN, GPSR3_2,
4742 GP_3_1_FN, GPSR3_1,
4743 GP_3_0_FN, GPSR3_0, }
4744 },
4745 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4746 0, 0,
4747 0, 0,
4748 0, 0,
4749 0, 0,
4750 0, 0,
4751 0, 0,
4752 0, 0,
4753 0, 0,
4754 0, 0,
4755 0, 0,
4756 0, 0,
4757 0, 0,
4758 0, 0,
4759 0, 0,
4760 GP_4_17_FN, GPSR4_17,
4761 GP_4_16_FN, GPSR4_16,
4762 GP_4_15_FN, GPSR4_15,
4763 GP_4_14_FN, GPSR4_14,
4764 GP_4_13_FN, GPSR4_13,
4765 GP_4_12_FN, GPSR4_12,
4766 GP_4_11_FN, GPSR4_11,
4767 GP_4_10_FN, GPSR4_10,
4768 GP_4_9_FN, GPSR4_9,
4769 GP_4_8_FN, GPSR4_8,
4770 GP_4_7_FN, GPSR4_7,
4771 GP_4_6_FN, GPSR4_6,
4772 GP_4_5_FN, GPSR4_5,
4773 GP_4_4_FN, GPSR4_4,
4774 GP_4_3_FN, GPSR4_3,
4775 GP_4_2_FN, GPSR4_2,
4776 GP_4_1_FN, GPSR4_1,
4777 GP_4_0_FN, GPSR4_0, }
4778 },
4779 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4780 0, 0,
4781 0, 0,
4782 0, 0,
4783 0, 0,
4784 0, 0,
4785 0, 0,
4786 GP_5_25_FN, GPSR5_25,
4787 GP_5_24_FN, GPSR5_24,
4788 GP_5_23_FN, GPSR5_23,
4789 GP_5_22_FN, GPSR5_22,
4790 GP_5_21_FN, GPSR5_21,
4791 GP_5_20_FN, GPSR5_20,
4792 GP_5_19_FN, GPSR5_19,
4793 GP_5_18_FN, GPSR5_18,
4794 GP_5_17_FN, GPSR5_17,
4795 GP_5_16_FN, GPSR5_16,
4796 GP_5_15_FN, GPSR5_15,
4797 GP_5_14_FN, GPSR5_14,
4798 GP_5_13_FN, GPSR5_13,
4799 GP_5_12_FN, GPSR5_12,
4800 GP_5_11_FN, GPSR5_11,
4801 GP_5_10_FN, GPSR5_10,
4802 GP_5_9_FN, GPSR5_9,
4803 GP_5_8_FN, GPSR5_8,
4804 GP_5_7_FN, GPSR5_7,
4805 GP_5_6_FN, GPSR5_6,
4806 GP_5_5_FN, GPSR5_5,
4807 GP_5_4_FN, GPSR5_4,
4808 GP_5_3_FN, GPSR5_3,
4809 GP_5_2_FN, GPSR5_2,
4810 GP_5_1_FN, GPSR5_1,
4811 GP_5_0_FN, GPSR5_0, }
4812 },
4813 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4814 GP_6_31_FN, GPSR6_31,
4815 GP_6_30_FN, GPSR6_30,
4816 GP_6_29_FN, GPSR6_29,
4817 GP_6_28_FN, GPSR6_28,
4818 GP_6_27_FN, GPSR6_27,
4819 GP_6_26_FN, GPSR6_26,
4820 GP_6_25_FN, GPSR6_25,
4821 GP_6_24_FN, GPSR6_24,
4822 GP_6_23_FN, GPSR6_23,
4823 GP_6_22_FN, GPSR6_22,
4824 GP_6_21_FN, GPSR6_21,
4825 GP_6_20_FN, GPSR6_20,
4826 GP_6_19_FN, GPSR6_19,
4827 GP_6_18_FN, GPSR6_18,
4828 GP_6_17_FN, GPSR6_17,
4829 GP_6_16_FN, GPSR6_16,
4830 GP_6_15_FN, GPSR6_15,
4831 GP_6_14_FN, GPSR6_14,
4832 GP_6_13_FN, GPSR6_13,
4833 GP_6_12_FN, GPSR6_12,
4834 GP_6_11_FN, GPSR6_11,
4835 GP_6_10_FN, GPSR6_10,
4836 GP_6_9_FN, GPSR6_9,
4837 GP_6_8_FN, GPSR6_8,
4838 GP_6_7_FN, GPSR6_7,
4839 GP_6_6_FN, GPSR6_6,
4840 GP_6_5_FN, GPSR6_5,
4841 GP_6_4_FN, GPSR6_4,
4842 GP_6_3_FN, GPSR6_3,
4843 GP_6_2_FN, GPSR6_2,
4844 GP_6_1_FN, GPSR6_1,
4845 GP_6_0_FN, GPSR6_0, }
4846 },
4847 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4848 0, 0,
4849 0, 0,
4850 0, 0,
4851 0, 0,
4852 0, 0,
4853 0, 0,
4854 0, 0,
4855 0, 0,
4856 0, 0,
4857 0, 0,
4858 0, 0,
4859 0, 0,
4860 0, 0,
4861 0, 0,
4862 0, 0,
4863 0, 0,
4864 0, 0,
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 0, 0,
4872 0, 0,
4873 0, 0,
4874 0, 0,
4875 0, 0,
4876 GP_7_3_FN, GPSR7_3,
4877 GP_7_2_FN, GPSR7_2,
4878 GP_7_1_FN, GPSR7_1,
4879 GP_7_0_FN, GPSR7_0, }
4880 },
4881#undef F_
4882#undef FM
4883
4884#define F_(x, y) x,
4885#define FM(x) FN_##x,
4886 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4887 IP0_31_28
4888 IP0_27_24
4889 IP0_23_20
4890 IP0_19_16
4891 IP0_15_12
4892 IP0_11_8
4893 IP0_7_4
4894 IP0_3_0 }
4895 },
4896 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4897 IP1_31_28
4898 IP1_27_24
4899 IP1_23_20
4900 IP1_19_16
4901 IP1_15_12
4902 IP1_11_8
4903 IP1_7_4
4904 IP1_3_0 }
4905 },
4906 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4907 IP2_31_28
4908 IP2_27_24
4909 IP2_23_20
4910 IP2_19_16
4911 IP2_15_12
4912 IP2_11_8
4913 IP2_7_4
4914 IP2_3_0 }
4915 },
4916 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4917 IP3_31_28
4918 IP3_27_24
4919 IP3_23_20
4920 IP3_19_16
4921 IP3_15_12
4922 IP3_11_8
4923 IP3_7_4
4924 IP3_3_0 }
4925 },
4926 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4927 IP4_31_28
4928 IP4_27_24
4929 IP4_23_20
4930 IP4_19_16
4931 IP4_15_12
4932 IP4_11_8
4933 IP4_7_4
4934 IP4_3_0 }
4935 },
4936 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4937 IP5_31_28
4938 IP5_27_24
4939 IP5_23_20
4940 IP5_19_16
4941 IP5_15_12
4942 IP5_11_8
4943 IP5_7_4
4944 IP5_3_0 }
4945 },
4946 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4947 IP6_31_28
4948 IP6_27_24
4949 IP6_23_20
4950 IP6_19_16
4951 IP6_15_12
4952 IP6_11_8
4953 IP6_7_4
4954 IP6_3_0 }
4955 },
4956 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4957 IP7_31_28
4958 IP7_27_24
4959 IP7_23_20
4960 IP7_19_16
30cd1c46 4961 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 4962 IP7_11_8
4963 IP7_7_4
4964 IP7_3_0 }
4965 },
4966 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4967 IP8_31_28
4968 IP8_27_24
4969 IP8_23_20
4970 IP8_19_16
4971 IP8_15_12
4972 IP8_11_8
4973 IP8_7_4
4974 IP8_3_0 }
4975 },
4976 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4977 IP9_31_28
4978 IP9_27_24
4979 IP9_23_20
4980 IP9_19_16
4981 IP9_15_12
4982 IP9_11_8
4983 IP9_7_4
4984 IP9_3_0 }
4985 },
4986 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4987 IP10_31_28
4988 IP10_27_24
4989 IP10_23_20
4990 IP10_19_16
4991 IP10_15_12
4992 IP10_11_8
4993 IP10_7_4
4994 IP10_3_0 }
4995 },
4996 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4997 IP11_31_28
4998 IP11_27_24
4999 IP11_23_20
5000 IP11_19_16
5001 IP11_15_12
5002 IP11_11_8
5003 IP11_7_4
5004 IP11_3_0 }
5005 },
5006 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5007 IP12_31_28
5008 IP12_27_24
5009 IP12_23_20
5010 IP12_19_16
5011 IP12_15_12
5012 IP12_11_8
5013 IP12_7_4
5014 IP12_3_0 }
5015 },
5016 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5017 IP13_31_28
5018 IP13_27_24
5019 IP13_23_20
5020 IP13_19_16
5021 IP13_15_12
5022 IP13_11_8
5023 IP13_7_4
5024 IP13_3_0 }
5025 },
5026 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5027 IP14_31_28
5028 IP14_27_24
5029 IP14_23_20
5030 IP14_19_16
5031 IP14_15_12
5032 IP14_11_8
5033 IP14_7_4
5034 IP14_3_0 }
5035 },
5036 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5037 IP15_31_28
5038 IP15_27_24
5039 IP15_23_20
5040 IP15_19_16
5041 IP15_15_12
5042 IP15_11_8
5043 IP15_7_4
5044 IP15_3_0 }
5045 },
5046 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5047 IP16_31_28
5048 IP16_27_24
5049 IP16_23_20
5050 IP16_19_16
5051 IP16_15_12
5052 IP16_11_8
5053 IP16_7_4
5054 IP16_3_0 }
5055 },
5056 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 5057 IP17_31_28
5058 IP17_27_24
5059 IP17_23_20
5060 IP17_19_16
5061 IP17_15_12
5062 IP17_11_8
0b0ffc96
TK		 5063 IP17_7_4
5064 IP17_3_0 }
5065 },
b205914c
GU		 5066 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5067 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5068 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5069 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5070 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5071 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5072 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5073 IP18_7_4
5074 IP18_3_0 }
5075 },
0b0ffc96
TK		 5076#undef F_
5077#undef FM
5078
5079#define F_(x, y) x,
5080#define FM(x) FN_##x,
5081 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 5082 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5083 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5084 MOD_SEL0_31_30_29
0b0ffc96
TK		 5085 MOD_SEL0_28_27
5086 MOD_SEL0_26_25_24
5087 MOD_SEL0_23
5088 MOD_SEL0_22
b205914c
GU		 5089 MOD_SEL0_21
5090 MOD_SEL0_20
0b0ffc96 5091 MOD_SEL0_19
b205914c
GU		 5092 MOD_SEL0_18_17
5093 MOD_SEL0_16
5094 0, 0, /* RESERVED 15 */
5095 MOD_SEL0_14_13
0b0ffc96
TK		 5096 MOD_SEL0_12
5097 MOD_SEL0_11
5098 MOD_SEL0_10
b205914c 5099 MOD_SEL0_9_8
0b0ffc96 5100 MOD_SEL0_7_6
b205914c
GU		 5101 MOD_SEL0_5
5102 MOD_SEL0_4_3
5103 /* RESERVED 2, 1, 0 */
5104 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 5105 },
5106 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5107 2, 3, 1, 2, 3, 1, 1, 2, 1,
5108 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5109 MOD_SEL1_31_30
5110 MOD_SEL1_29_28_27
5111 MOD_SEL1_26
5112 MOD_SEL1_25_24
5113 MOD_SEL1_23_22_21
5114 MOD_SEL1_20
5115 MOD_SEL1_19
5116 MOD_SEL1_18_17
5117 MOD_SEL1_16
5118 MOD_SEL1_15_14
5119 MOD_SEL1_13
5120 MOD_SEL1_12
5121 MOD_SEL1_11
5122 MOD_SEL1_10
5123 MOD_SEL1_9
5124 0, 0, 0, 0, /* RESERVED 8, 7 */
5125 MOD_SEL1_6
5126 MOD_SEL1_5
5127 MOD_SEL1_4
5128 MOD_SEL1_3
5129 MOD_SEL1_2
5130 MOD_SEL1_1
5131 MOD_SEL1_0 }
5132 },
5133 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 5134 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5135 4, 4, 4, 3, 1) {
0b0ffc96
TK		 5136 MOD_SEL2_31
5137 MOD_SEL2_30
5138 MOD_SEL2_29
b205914c
GU		 5139 MOD_SEL2_28_27
5140 MOD_SEL2_26
5141 MOD_SEL2_25_24_23
3c612d2c
TK		 5142 /* RESERVED 22 */
5143 0, 0,
b205914c
GU		 5144 MOD_SEL2_21
5145 MOD_SEL2_20
5146 MOD_SEL2_19
5147 MOD_SEL2_18
5148 MOD_SEL2_17
5149 /* RESERVED 16 */
0b0ffc96 5150 0, 0,
0b0ffc96
TK		 5151 /* RESERVED 15, 14, 13, 12 */
5152 0, 0, 0, 0, 0, 0, 0, 0,
5153 0, 0, 0, 0, 0, 0, 0, 0,
5154 /* RESERVED 11, 10, 9, 8 */
5155 0, 0, 0, 0, 0, 0, 0, 0,
5156 0, 0, 0, 0, 0, 0, 0, 0,
5157 /* RESERVED 7, 6, 5, 4 */
5158 0, 0, 0, 0, 0, 0, 0, 0,
5159 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5160 /* RESERVED 3, 2, 1 */
5161 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5162 MOD_SEL2_0 }
5163 },
5164 { },
5165};
5166
92e6d9a2 5167static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5168 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5169 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5170 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5171 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5172 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5173 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5174 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5175 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5176 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5177 } },
5178 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5179 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5180 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5181 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5182 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5183 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5184 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5185 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5186 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5187 } },
5188 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5189 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5190 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5191 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5192 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5193 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5194 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5195 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5196 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5197 } },
92e6d9a2 5198 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5199 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5200 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5201 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5202 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5203 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5204 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5205 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5206 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5207 } },
5208 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5209 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5210 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5211 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5212 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5213 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5214 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5215 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5216 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5217 } },
5218 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5219 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5220 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5221 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5222 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5223 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5224 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5225 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5226 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5227 } },
5228 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5229 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5230 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5231 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5232 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5233 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5234 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5235 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5236 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5237 } },
5238 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5239 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5240 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5241 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5242 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5243 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5244 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5245 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5246 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5247 } },
5248 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
ea9c7405 5249 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5250 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5251 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5252 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5253 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5254 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5255 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5256 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5257 } },
5258 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5259 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5260 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5261 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5262 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5263 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5264 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5265 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5266 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5267 } },
5268 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5269 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5270 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5271 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5272 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5273 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5274 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5275 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5276 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5277 } },
5278 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5279 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5280 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5281 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5282 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5283 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5284 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5285 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5286 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5287 } },
5288 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5289 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5290 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5291 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5292 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5293 } },
5294 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5295 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5296 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5297 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5298 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5299 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5300 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5301 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5302 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5303 } },
5304 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5305 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5306 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5307 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5308 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5309 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5310 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5311 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5312 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5313 } },
5314 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5315 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5316 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5317 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5318 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5319 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5320 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5321 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5322 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5323 } },
5324 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5325 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5326 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5327 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5328 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5329 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5330 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5331 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5332 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5333 } },
5334 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5335 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5336 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5337 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5338 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5339 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5340 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5341 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5342 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5343 } },
5344 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5345 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5346 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5347 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5348 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5349 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5350 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5351 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5352 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5353 } },
5354 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5355 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5356 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5357 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5358 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5359 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5360 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5361 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5362 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5363 } },
5364 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5365 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5366 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5367 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5368 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5369 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5370 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5371 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5372 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5373 } },
5374 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5375 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5376 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5377 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5378 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5379 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5380 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5381 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5382 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5383 } },
5384 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5385 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5386 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5387 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5388 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5389 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5390 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5391 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5392 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5393 } },
5394 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5395 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5396 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5397 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5398 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5399 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5400 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5401 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5402 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5403 } },
5404 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5405 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5406 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5407 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5408 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5409 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5410 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5411 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5412 } },
5413 { },
5414};
5415
e2aad846
GU		 5416enum ioctrl_regs {
5417 POCCTRL,
5418};
5419
5420static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5421 [POCCTRL] = { 0xe6060380, },
5422 { /* sentinel */ },
5423};
5424
e9eace32
WS		 5425static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5426{
5427 int bit = -EINVAL;
5428
e2aad846 5429 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
e9eace32
WS		 5430
5431 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5432 bit = pin & 0x1f;
5433
5434 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5435 bit = (pin & 0x1f) + 12;
5436
5437 return bit;
5438}
5439
6f4b74f3
GU		 5440static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5441 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5442 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5443 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5444 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5445 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5446 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5447 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5448 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5449 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5450 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5451 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5452 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5453 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5454 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5455 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5456 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5457 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5458 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5459 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5460 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5461 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5462 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5463 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5464 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5465 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5466 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5467 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5468 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5469 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5470 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5471 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5472 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5473 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5474 } },
5475 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5476 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5477 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5478 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5479 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5480 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5481 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5482 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5483 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5484 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5485 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5486 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5487 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5488 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5489 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5490 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5491 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5492 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5493 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5494 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5495 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5496 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5497 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5498 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5499 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5500 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5501 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5502 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5503 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5504 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5505 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5506 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5507 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5508 } },
5509 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5510 [ 0] = PIN_NUMBER('F', 1), /* CLKOUT */
5511 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5512 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5513 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5514 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5515 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5516 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5517 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5518 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5519 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5520 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5521 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5522 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5523 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5524 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5525 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5526 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5527 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5528 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5529 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5530 [20] = RCAR_GP_PIN(0, 10), /* D10 */
5531 [21] = RCAR_GP_PIN(0, 11), /* D11 */
5532 [22] = RCAR_GP_PIN(0, 12), /* D12 */
5533 [23] = RCAR_GP_PIN(0, 13), /* D13 */
5534 [24] = RCAR_GP_PIN(0, 14), /* D14 */
5535 [25] = RCAR_GP_PIN(0, 15), /* D15 */
5536 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
5537 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
5538 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
5539 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
5540 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
5541 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
5542 } },
5543 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
5544 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
5545 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
5546 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
5547 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
5548 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
5549 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
5550 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
5551 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
5552 [ 8] = PIN_NONE,
5553 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
5554 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
5555 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
5556 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
5557 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
5558 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
5559 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
5560 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
5561 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
5562 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
5563 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
5564 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
5565 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
5566 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
5567 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
5568 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
5569 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
5570 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
5571 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
5572 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
5573 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
5574 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
5575 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
5576 } },
5577 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
5578 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
5579 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
5580 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
5581 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
5582 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
5583 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
5584 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
5585 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
5586 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
5587 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
5588 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
5589 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
5590 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
5591 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
5592 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
5593 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
5594 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N_TANS */
5595 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
5596 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
5597 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
5598 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N_TANS */
5599 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
5600 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
5601 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
5602 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
5603 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
5604 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
5605 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
5606 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
5607 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
5608 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
5609 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
5610 } },
5611 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
5612 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
5613 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
5614 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
5615 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
5616 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
5617 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
5618 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
5619 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
5620 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
5621 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
5622 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
5623 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
5624 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
5625 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
5626 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
5627 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
5628 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
5629 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
5630 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
5631 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
5632 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
5633 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
5634 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
5635 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
5636 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
5637 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
5638 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
5639 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
5640 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
5641 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
5642 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
5643 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
5644 } },
5645 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
5646 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
5647 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
5648 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
5649 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
5650 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
5651 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
5652 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
5653 [ 7] = PIN_NONE,
5654 [ 8] = PIN_NONE,
5655 [ 9] = PIN_NONE,
5656 [10] = PIN_NONE,
5657 [11] = PIN_NONE,
5658 [12] = PIN_NONE,
5659 [13] = PIN_NONE,
5660 [14] = PIN_NONE,
5661 [15] = PIN_NONE,
5662 [16] = PIN_NONE,
5663 [17] = PIN_NONE,
5664 [18] = PIN_NONE,
5665 [19] = PIN_NONE,
5666 [20] = PIN_NONE,
5667 [21] = PIN_NONE,
5668 [22] = PIN_NONE,
5669 [23] = PIN_NONE,
5670 [24] = PIN_NONE,
5671 [25] = PIN_NONE,
5672 [26] = PIN_NONE,
5673 [27] = PIN_NONE,
5674 [28] = PIN_NONE,
5675 [29] = PIN_NONE,
5676 [30] = PIN_NONE,
5677 [31] = PIN_NONE,
5678 } },
5679 { /* sentinel */ },
56065524
UH		 5680};
5681
5682static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5683 unsigned int pin)
5684{
6f4b74f3
GU		 5685 const struct pinmux_bias_reg *reg;
5686 unsigned int bit;
56065524 5687
6f4b74f3
GU		 5688 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5689 if (!reg)
56065524
UH		 5690 return PIN_CONFIG_BIAS_DISABLE;
5691
6f4b74f3 5692 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
56065524 5693 return PIN_CONFIG_BIAS_DISABLE;
6f4b74f3 5694 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
42831cf9
NS		 5695 return PIN_CONFIG_BIAS_PULL_UP;
5696 else
5697 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 5698}
5699
5700static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5701 unsigned int bias)
5702{
6f4b74f3 5703 const struct pinmux_bias_reg *reg;
56065524 5704 u32 enable, updown;
6f4b74f3 5705 unsigned int bit;
56065524 5706
6f4b74f3
GU		 5707 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
5708 if (!reg)
56065524
UH		 5709 return;
5710
6f4b74f3 5711 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
56065524 5712 if (bias != PIN_CONFIG_BIAS_DISABLE)
6f4b74f3 5713 enable |= BIT(bit);
56065524 5714
6f4b74f3 5715 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
56065524 5716 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6f4b74f3 5717 updown |= BIT(bit);
56065524 5718
6f4b74f3
GU		 5719 sh_pfc_write(pfc, reg->pud, updown);
5720 sh_pfc_write(pfc, reg->puen, enable);
56065524
UH		 5721}
5722
b205914c
GU		 5723static const struct soc_device_attribute r8a7795es1[] = {
5724 { .soc_id = "r8a7795", .revision = "ES1.*" },
5725 { /* sentinel */ }
5726};
5727
5728static int r8a7795_pinmux_init(struct sh_pfc *pfc)
5729{
5730 if (soc_device_match(r8a7795es1))
5731 pfc->info = &r8a7795es1_pinmux_info;
5732
5733 return 0;
5734}
5735
e9eace32 5736static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 5737 .init = r8a7795_pinmux_init,
e9eace32 5738 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 5739 .get_bias = r8a7795_pinmux_get_bias,
5740 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 5741};
5742
0b0ffc96 5743const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 5744 .name = "r8a77951_pfc",
e9eace32 5745 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 5746 .unlock_reg = 0xe6060000, /* PMMR */
5747
5748 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5749
5750 .pins = pinmux_pins,
5751 .nr_pins = ARRAY_SIZE(pinmux_pins),
5752 .groups = pinmux_groups,
5753 .nr_groups = ARRAY_SIZE(pinmux_groups),
5754 .functions = pinmux_functions,
5755 .nr_functions = ARRAY_SIZE(pinmux_functions),
5756
5757 .cfg_regs = pinmux_config_regs,
92e6d9a2 5758 .drive_regs = pinmux_drive_regs,
6f4b74f3 5759 .bias_regs = pinmux_bias_regs,
e2aad846 5760 .ioctrl_regs = pinmux_ioctrl_regs,
0b0ffc96 5761
b8b47d67
GU		 5762 .pinmux_data = pinmux_data,
5763 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 5764};
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