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pinctrl: sh-pfc: r8a7795: Rename SSI_{WS,SCK}0129 to SSI_{WS,SCK}01239
[mirror_ubuntu-zesty-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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TK		 1/*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
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TK		 12
13#include "core.h"
14#include "sh_pfc.h"
15
0b0ffc96 16#define CPU_ALL_PORT(fn, sfx) \
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GU		 17 PORT_GP_16(0, fn, sfx), \
18 PORT_GP_28(1, fn, sfx), \
19 PORT_GP_15(2, fn, sfx), \
20 PORT_GP_16(3, fn, sfx), \
21 PORT_GP_18(4, fn, sfx), \
22 PORT_GP_26(5, fn, sfx), \
0b0ffc96 23 PORT_GP_32(6, fn, sfx), \
b8856085 24 PORT_GP_4(7, fn, sfx)
0b0ffc96
TK		 25/*
26 * F_() : just information
27 * FM() : macro for FN_xxx / xxx_MARK
28 */
29
30/* GPSR0 */
31#define GPSR0_15 F_(D15, IP7_11_8)
32#define GPSR0_14 F_(D14, IP7_7_4)
33#define GPSR0_13 F_(D13, IP7_3_0)
34#define GPSR0_12 F_(D12, IP6_31_28)
35#define GPSR0_11 F_(D11, IP6_27_24)
36#define GPSR0_10 F_(D10, IP6_23_20)
37#define GPSR0_9 F_(D9, IP6_19_16)
38#define GPSR0_8 F_(D8, IP6_15_12)
39#define GPSR0_7 F_(D7, IP6_11_8)
40#define GPSR0_6 F_(D6, IP6_7_4)
41#define GPSR0_5 F_(D5, IP6_3_0)
42#define GPSR0_4 F_(D4, IP5_31_28)
43#define GPSR0_3 F_(D3, IP5_27_24)
44#define GPSR0_2 F_(D2, IP5_23_20)
45#define GPSR0_1 F_(D1, IP5_19_16)
46#define GPSR0_0 F_(D0, IP5_15_12)
47
48/* GPSR1 */
49#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
50#define GPSR1_26 F_(WE1_N, IP5_7_4)
51#define GPSR1_25 F_(WE0_N, IP5_3_0)
52#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
53#define GPSR1_23 F_(RD_N, IP4_27_24)
54#define GPSR1_22 F_(BS_N, IP4_23_20)
55#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
56#define GPSR1_20 F_(CS0_N, IP4_15_12)
57#define GPSR1_19 F_(A19, IP4_11_8)
58#define GPSR1_18 F_(A18, IP4_7_4)
59#define GPSR1_17 F_(A17, IP4_3_0)
60#define GPSR1_16 F_(A16, IP3_31_28)
61#define GPSR1_15 F_(A15, IP3_27_24)
62#define GPSR1_14 F_(A14, IP3_23_20)
63#define GPSR1_13 F_(A13, IP3_19_16)
64#define GPSR1_12 F_(A12, IP3_15_12)
65#define GPSR1_11 F_(A11, IP3_11_8)
66#define GPSR1_10 F_(A10, IP3_7_4)
67#define GPSR1_9 F_(A9, IP3_3_0)
68#define GPSR1_8 F_(A8, IP2_31_28)
69#define GPSR1_7 F_(A7, IP2_27_24)
70#define GPSR1_6 F_(A6, IP2_23_20)
71#define GPSR1_5 F_(A5, IP2_19_16)
72#define GPSR1_4 F_(A4, IP2_15_12)
73#define GPSR1_3 F_(A3, IP2_11_8)
74#define GPSR1_2 F_(A2, IP2_7_4)
75#define GPSR1_1 F_(A1, IP2_3_0)
76#define GPSR1_0 F_(A0, IP1_31_28)
77
78/* GPSR2 */
79#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
80#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
81#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
82#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
83#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
84#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
85#define GPSR2_8 F_(PWM2_A, IP1_27_24)
86#define GPSR2_7 F_(PWM1_A, IP1_23_20)
87#define GPSR2_6 F_(PWM0, IP1_19_16)
88#define GPSR2_5 F_(IRQ5, IP1_15_12)
89#define GPSR2_4 F_(IRQ4, IP1_11_8)
90#define GPSR2_3 F_(IRQ3, IP1_7_4)
91#define GPSR2_2 F_(IRQ2, IP1_3_0)
92#define GPSR2_1 F_(IRQ1, IP0_31_28)
93#define GPSR2_0 F_(IRQ0, IP0_27_24)
94
95/* GPSR3 */
96#define GPSR3_15 F_(SD1_WP, IP10_23_20)
97#define GPSR3_14 F_(SD1_CD, IP10_19_16)
98#define GPSR3_13 F_(SD0_WP, IP10_15_12)
99#define GPSR3_12 F_(SD0_CD, IP10_11_8)
100#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
101#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
102#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
103#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
104#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
105#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
106#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
107#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
108#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
109#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
110#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
111#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
112
113/* GPSR4 */
114#define GPSR4_17 FM(SD3_DS)
115#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
116#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
117#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
118#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
119#define GPSR4_12 FM(SD3_DAT3)
120#define GPSR4_11 FM(SD3_DAT2)
121#define GPSR4_10 FM(SD3_DAT1)
122#define GPSR4_9 FM(SD3_DAT0)
123#define GPSR4_8 FM(SD3_CMD)
124#define GPSR4_7 FM(SD3_CLK)
125#define GPSR4_6 F_(SD2_DS, IP9_23_20)
126#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
127#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
128#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
129#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
130#define GPSR4_1 FM(SD2_CMD)
131#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
132
133/* GPSR5 */
134#define GPSR5_25 F_(MLB_DAT, IP13_19_16)
135#define GPSR5_24 F_(MLB_SIG, IP13_15_12)
136#define GPSR5_23 F_(MLB_CLK, IP13_11_8)
137#define GPSR5_22 FM(MSIOF0_RXD)
138#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
139#define GPSR5_20 FM(MSIOF0_TXD)
140#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
141#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
142#define GPSR5_17 FM(MSIOF0_SCK)
143#define GPSR5_16 F_(HRTS0_N, IP12_27_24)
144#define GPSR5_15 F_(HCTS0_N, IP12_23_20)
145#define GPSR5_14 F_(HTX0, IP12_19_16)
146#define GPSR5_13 F_(HRX0, IP12_15_12)
147#define GPSR5_12 F_(HSCK0, IP12_11_8)
148#define GPSR5_11 F_(RX2_A, IP12_7_4)
149#define GPSR5_10 F_(TX2_A, IP12_3_0)
150#define GPSR5_9 F_(SCK2, IP11_31_28)
151#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
152#define GPSR5_7 F_(CTS1_N, IP11_23_20)
153#define GPSR5_6 F_(TX1_A, IP11_19_16)
154#define GPSR5_5 F_(RX1_A, IP11_15_12)
155#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
156#define GPSR5_3 F_(CTS0_N, IP11_7_4)
157#define GPSR5_2 F_(TX0, IP11_3_0)
158#define GPSR5_1 F_(RX0, IP10_31_28)
159#define GPSR5_0 F_(SCK0, IP10_27_24)
160
161/* GPSR6 */
162#define GPSR6_31 F_(USB31_OVC, IP17_7_4)
163#define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
164#define GPSR6_29 F_(USB30_OVC, IP16_31_28)
165#define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
166#define GPSR6_27 F_(USB1_OVC, IP16_23_20)
167#define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
168#define GPSR6_25 F_(USB0_OVC, IP16_15_12)
169#define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
170#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
171#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
172#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
173#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
174#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
175#define GPSR6_18 F_(SSI_WS78, IP15_19_16)
176#define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
177#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
178#define GPSR6_15 F_(SSI_WS6, IP15_7_4)
179#define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
180#define GPSR6_13 FM(SSI_SDATA5)
181#define GPSR6_12 FM(SSI_WS5)
182#define GPSR6_11 FM(SSI_SCK5)
183#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
184#define GPSR6_9 F_(SSI_WS4, IP14_27_24)
185#define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
186#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
187#define GPSR6_6 F_(SSI_WS34, IP14_15_12)
188#define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
189#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
190#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
191#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
00edf542
GU		 192#define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
193#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
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TK		 194
195/* GPSR7 */
196#define GPSR7_3 FM(HDMI1_CEC)
197#define GPSR7_2 FM(HDMI0_CEC)
198#define GPSR7_1 FM(AVS2)
199#define GPSR7_0 FM(AVS1)
200
201
202/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
203#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222
223/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
224#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266
267/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
268#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
00edf542
GU		 318#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 320#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347
348#define PINMUX_GPSR \
349\
350 GPSR6_31 \
351 GPSR6_30 \
352 GPSR6_29 \
353 GPSR6_28 \
354 GPSR1_27 GPSR6_27 \
355 GPSR1_26 GPSR6_26 \
356 GPSR1_25 GPSR5_25 GPSR6_25 \
357 GPSR1_24 GPSR5_24 GPSR6_24 \
358 GPSR1_23 GPSR5_23 GPSR6_23 \
359 GPSR1_22 GPSR5_22 GPSR6_22 \
360 GPSR1_21 GPSR5_21 GPSR6_21 \
361 GPSR1_20 GPSR5_20 GPSR6_20 \
362 GPSR1_19 GPSR5_19 GPSR6_19 \
363 GPSR1_18 GPSR5_18 GPSR6_18 \
364 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
365 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
366GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
367GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
368GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
369GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
370GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
371GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
372GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
373GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
374GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
375GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
376GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
377GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
378GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
379GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
380GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
381GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
382
383#define PINMUX_IPSR \
384\
385FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
386FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
387FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
388FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
389FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
390FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
391FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
392FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
393\
394FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
395FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
396FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
397FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
398FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
399FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
400FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
401FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
402\
403FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
404FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
405FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
406FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
407FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
408FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
409FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
410FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
411\
412FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
413FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
414FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
415FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
416FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
417FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
418FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
419FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
420\
421FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
422FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
423FM(IP16_11_8) IP16_11_8 \
424FM(IP16_15_12) IP16_15_12 \
425FM(IP16_19_16) IP16_19_16 \
426FM(IP16_23_20) IP16_23_20 \
427FM(IP16_27_24) IP16_27_24 \
428FM(IP16_31_28) IP16_31_28
429
430/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
431#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
432#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
433#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
434#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
435#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
436#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
437#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
438#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
439#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
440#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
441#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
442#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
443#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
444#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
445#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
446#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
447#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
448#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
449#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
450#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
451#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
452
453/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
454#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
455#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
456#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
457#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
458#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
459#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
460#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
461#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
462#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
463#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
464#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
465#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
466#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
fd1aa743 467#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
0b0ffc96
TK		 468#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
469#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
470#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
471#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
472#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
473#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
474#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
475#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
476
477/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
478#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
479#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
480#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
481#define MOD_SEL2_2_1 FM(SEL_VSP_0) FM(SEL_VSP_1) FM(SEL_VSP_2) FM(SEL_VSP_3)
482#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
483
484#define PINMUX_MOD_SELS\
485\
486 MOD_SEL1_31_30 MOD_SEL2_31 \
487MOD_SEL0_30_29 MOD_SEL2_30 \
488 MOD_SEL1_29_28_27 MOD_SEL2_29 \
489MOD_SEL0_28_27 \
490\
491MOD_SEL0_26_25_24 MOD_SEL1_26 \
492 MOD_SEL1_25_24 \
493\
494MOD_SEL0_23 MOD_SEL1_23_22_21 \
495MOD_SEL0_22 \
496MOD_SEL0_21_20 \
497 MOD_SEL1_20 \
498MOD_SEL0_19 MOD_SEL1_19 \
499MOD_SEL0_18 MOD_SEL1_18_17 \
500MOD_SEL0_17 \
501MOD_SEL0_16_15 MOD_SEL1_16 \
502 MOD_SEL1_15_14 \
503MOD_SEL0_14 \
504MOD_SEL0_13 MOD_SEL1_13 \
505MOD_SEL0_12 MOD_SEL1_12 \
506MOD_SEL0_11 MOD_SEL1_11 \
507MOD_SEL0_10 MOD_SEL1_10 \
508MOD_SEL0_9 MOD_SEL1_9 \
509MOD_SEL0_8 \
510MOD_SEL0_7_6 \
511 MOD_SEL1_6 \
512MOD_SEL0_5_4 MOD_SEL1_5 \
513 MOD_SEL1_4 \
514MOD_SEL0_3 MOD_SEL1_3 \
515MOD_SEL0_2_1 MOD_SEL1_2 MOD_SEL2_2_1 \
516 MOD_SEL1_1 \
517 MOD_SEL1_0 MOD_SEL2_0
518
519
520enum {
521 PINMUX_RESERVED = 0,
522
523 PINMUX_DATA_BEGIN,
524 GP_ALL(DATA),
525 PINMUX_DATA_END,
526
527#define F_(x, y)
528#define FM(x) FN_##x,
529 PINMUX_FUNCTION_BEGIN,
530 GP_ALL(FN),
531 PINMUX_GPSR
532 PINMUX_IPSR
533 PINMUX_MOD_SELS
534 PINMUX_FUNCTION_END,
535#undef F_
536#undef FM
537
538#define F_(x, y)
539#define FM(x) x##_MARK,
540 PINMUX_MARK_BEGIN,
541 PINMUX_GPSR
542 PINMUX_IPSR
543 PINMUX_MOD_SELS
544 PINMUX_MARK_END,
545#undef F_
546#undef FM
547};
548
549static const u16 pinmux_data[] = {
550 PINMUX_DATA_GP_ALL(),
551
8d4df573
GU		 552 PINMUX_SINGLE(AVS1),
553 PINMUX_SINGLE(AVS2),
554 PINMUX_SINGLE(HDMI0_CEC),
555 PINMUX_SINGLE(HDMI1_CEC),
556 PINMUX_SINGLE(MSIOF0_RXD),
557 PINMUX_SINGLE(MSIOF0_SCK),
558 PINMUX_SINGLE(MSIOF0_TXD),
559 PINMUX_SINGLE(SD2_CMD),
560 PINMUX_SINGLE(SD3_CLK),
561 PINMUX_SINGLE(SD3_CMD),
562 PINMUX_SINGLE(SD3_DAT0),
563 PINMUX_SINGLE(SD3_DAT1),
564 PINMUX_SINGLE(SD3_DAT2),
565 PINMUX_SINGLE(SD3_DAT3),
566 PINMUX_SINGLE(SD3_DS),
567 PINMUX_SINGLE(SSI_SCK5),
568 PINMUX_SINGLE(SSI_SDATA5),
569 PINMUX_SINGLE(SSI_WS5),
570
0b0ffc96 571 /* IPSR0 */
e01678e3 572 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 573 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
574
e01678e3 575 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 576 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
577 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
578
e01678e3 579 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 580 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
581 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
582
e01678e3 583 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 584 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
585 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
586
587 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
588 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
589 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
590
591 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
592 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
593 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
594
e01678e3
GU		 595 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
596 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
597 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 598 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
599 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
600 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
601
e01678e3
GU		 602 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
603 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
604 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 605 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
606 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
607 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
608
609 /* IPSR1 */
e01678e3
GU		 610 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
611 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
612 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 613 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
614 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
615
e01678e3
GU		 616 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
617 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
618 PINMUX_IPSR_GPSR(IP1_7_4, A25),
619 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 620 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
621 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
622
e01678e3
GU		 623 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
624 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
625 PINMUX_IPSR_GPSR(IP1_11_8, A24),
626 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 627 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
628 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
629
e01678e3
GU		 630 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
631 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
632 PINMUX_IPSR_GPSR(IP1_15_12, A23),
633 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 634 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
635 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
638 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
639 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
642
643 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 644 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 645 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
646 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
648
649 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 650 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 651 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
652 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
653
e01678e3
GU		 654 PINMUX_IPSR_GPSR(IP1_31_28, A0),
655 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 656 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 657 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
658 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 659 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
660
661 /* IPSR2 */
e01678e3
GU		 662 PINMUX_IPSR_GPSR(IP2_3_0, A1),
663 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 664 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 665 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
666 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 667 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
668
e01678e3
GU		 669 PINMUX_IPSR_GPSR(IP2_7_4, A2),
670 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 671 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 672 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
673 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 674 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
675
e01678e3
GU		 676 PINMUX_IPSR_GPSR(IP2_11_8, A3),
677 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 678 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 679 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
680 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 681 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
682
e01678e3
GU		 683 PINMUX_IPSR_GPSR(IP2_15_12, A4),
684 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 685 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 686 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
687 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
688 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 689
e01678e3
GU		 690 PINMUX_IPSR_GPSR(IP2_19_16, A5),
691 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 692 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
693 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 694 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
695 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
696 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 697
e01678e3
GU		 698 PINMUX_IPSR_GPSR(IP2_23_20, A6),
699 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 700 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
701 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 702 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
703 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
704 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 705
e01678e3
GU		 706 PINMUX_IPSR_GPSR(IP2_27_24, A7),
707 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 708 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
709 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 710 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
711 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
712 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 713
e01678e3 714 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 715 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
716 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
717 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
718 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
719 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
720 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
721
722 /* IPSR3 */
e01678e3 723 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 724 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
725 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 726 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 727
e01678e3 728 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 729 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
730 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 731 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 732
e01678e3 733 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 734 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
735 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 737 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
738 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 739 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
740 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
741 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
742
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP3_15_12, A12),
744 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 745 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
746 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 747 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
748 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 749
e01678e3
GU		 750 PINMUX_IPSR_GPSR(IP3_19_16, A13),
751 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 752 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
753 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 754 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
755 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 756
e01678e3
GU		 757 PINMUX_IPSR_GPSR(IP3_23_20, A14),
758 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 759 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 760 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
761 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
762 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 763
e01678e3
GU		 764 PINMUX_IPSR_GPSR(IP3_27_24, A15),
765 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 766 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 767 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
768 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
769 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 770
e01678e3
GU		 771 PINMUX_IPSR_GPSR(IP3_31_28, A16),
772 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
773 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
774 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 775
776 /* IPSR4 */
e01678e3
GU		 777 PINMUX_IPSR_GPSR(IP4_3_0, A17),
778 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
779 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
780 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
781
782 PINMUX_IPSR_GPSR(IP4_7_4, A18),
783 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
784 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
785 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
786
787 PINMUX_IPSR_GPSR(IP4_11_8, A19),
788 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
789 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
790 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
791
792 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
793 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
794
795 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
796 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 797 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
798
e01678e3
GU		 799 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
800 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 801 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 802 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
803 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
804 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
805 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 806 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
807
e01678e3 808 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 809 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
810 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
811 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
812 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
813 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
814
e01678e3 815 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 816 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
817 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
818 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
819 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
820 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
821
822 /* IPSR5 */
e01678e3 823 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 824 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 825 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
826 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 827 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 828 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 829 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
830
e01678e3 831 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 832 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 833 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
834 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 835 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 836 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
837 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 838 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
839
840 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 841 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
842 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
843 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 844
e01678e3 845 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 846 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
847 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 848 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
849 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 850
e01678e3 851 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 852 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
853 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 854 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
855 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 856
e01678e3 857 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 858 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 859 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
860 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 861
e01678e3 862 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 863 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 864 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
865 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 866
e01678e3 867 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 868 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 869 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
870 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 871
872 /* IPSR6 */
e01678e3 873 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 874 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 875 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
876 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 877
e01678e3 878 PINMUX_IPSR_GPSR(IP6_7_4, D6),
0b0ffc96 879 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
e01678e3
GU		 880 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
881 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
0b0ffc96 882
e01678e3 883 PINMUX_IPSR_GPSR(IP6_11_8, D7),
0b0ffc96 884 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
e01678e3
GU		 885 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
886 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
0b0ffc96 887
e01678e3
GU		 888 PINMUX_IPSR_GPSR(IP6_15_12, D8),
889 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
0b0ffc96
TK		 890 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
891 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
892 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
e01678e3 893 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
0b0ffc96 894
e01678e3
GU		 895 PINMUX_IPSR_GPSR(IP6_19_16, D9),
896 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
0b0ffc96
TK		 897 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
898 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
e01678e3 899 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
0b0ffc96 900
e01678e3
GU		 901 PINMUX_IPSR_GPSR(IP6_23_20, D10),
902 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
0b0ffc96
TK		 903 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
904 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
905 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
906 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
e01678e3 907 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
0b0ffc96 908
e01678e3
GU		 909 PINMUX_IPSR_GPSR(IP6_27_24, D11),
910 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
0b0ffc96
TK		 911 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
912 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
913 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
914 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
e01678e3 915 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
0b0ffc96 916
e01678e3
GU		 917 PINMUX_IPSR_GPSR(IP6_31_28, D12),
918 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
0b0ffc96
TK		 919 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
920 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
921 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
e01678e3 922 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
0b0ffc96
TK		 923
924 /* IPSR7 */
e01678e3
GU		 925 PINMUX_IPSR_GPSR(IP7_3_0, D13),
926 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
0b0ffc96
TK		 927 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
928 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
929 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
e01678e3 930 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
0b0ffc96 931
e01678e3
GU		 932 PINMUX_IPSR_GPSR(IP7_7_4, D14),
933 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
0b0ffc96
TK		 934 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
935 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
936 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
e01678e3 937 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
0b0ffc96
TK		 938 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
939
e01678e3
GU		 940 PINMUX_IPSR_GPSR(IP7_11_8, D15),
941 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
0b0ffc96
TK		 942 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
943 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
944 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
e01678e3 945 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
0b0ffc96
TK		 946 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
947
e01678e3 948 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
0b0ffc96 949
e01678e3 950 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
0b0ffc96
TK		 951 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
952 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
953
e01678e3 954 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
0b0ffc96
TK		 955 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
956 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
957
e01678e3 958 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
0b0ffc96
TK		 959 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
960 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
961 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
962
e01678e3 963 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
0b0ffc96
TK		 964 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
965 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
966 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
967
968 /* IPSR8 */
e01678e3 969 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
0b0ffc96
TK		 970 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
971 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
972 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
973
e01678e3 974 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
0b0ffc96
TK		 975 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
976 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
977 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
978
e01678e3 979 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
0b0ffc96
TK		 980 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
981 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
982
e01678e3 983 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
0b0ffc96
TK		 984 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
985 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
986 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
987
e01678e3
GU		 988 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
989 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
0b0ffc96
TK		 990 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
991 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
992 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
993
e01678e3
GU		 994 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
995 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
0b0ffc96
TK		 996 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
997 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
998 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
999
e01678e3
GU		 1000 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1001 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
0b0ffc96
TK		 1002 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1003 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1004 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1005
e01678e3
GU		 1006 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1007 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
0b0ffc96
TK		 1008 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1009 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1010 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1011
1012 /* IPSR9 */
e01678e3 1013 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
0b0ffc96 1014
e01678e3 1015 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
0b0ffc96 1016
e01678e3 1017 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
0b0ffc96 1018
e01678e3 1019 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
0b0ffc96 1020
e01678e3 1021 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
0b0ffc96 1022
e01678e3 1023 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
fd1aa743 1024 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
0b0ffc96 1025
e01678e3 1026 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
0b0ffc96
TK		 1027 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1028
e01678e3 1029 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
0b0ffc96
TK		 1030 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1031
1032 /* IPSR10 */
e01678e3
GU		 1033 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1034 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
0b0ffc96 1035
e01678e3
GU		 1036 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1037 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
0b0ffc96 1038
e01678e3 1039 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
0b0ffc96
TK		 1040 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1041 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1042
e01678e3 1043 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
0b0ffc96
TK		 1044 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1045
e01678e3 1046 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
0b0ffc96
TK		 1047 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1048
e01678e3 1049 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
0b0ffc96
TK		 1050 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1051
e01678e3 1052 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
0b0ffc96
TK		 1053 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1054 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1055 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1056 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1057 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1058 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1059 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
e01678e3 1060 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
0b0ffc96 1061
e01678e3 1062 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
0b0ffc96
TK		 1063 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1064 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1065 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1066 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1067
1068 /* IPSR11 */
e01678e3 1069 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
0b0ffc96
TK		 1070 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1071 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1072 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1073 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1074
e01678e3 1075 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
0b0ffc96
TK		 1076 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1077 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1078 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1079 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1080 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1081 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
e01678e3 1082 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
0b0ffc96 1083
e01678e3 1084 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
0b0ffc96
TK		 1085 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1086 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1087 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1088 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1089 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1090 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
e01678e3 1091 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
0b0ffc96
TK		 1092
1093 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1094 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1095 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1096 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1097 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1098
1099 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1100 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1101 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1102 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1103 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1104
e01678e3 1105 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
0b0ffc96
TK		 1106 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1107 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1108 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1109 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1110 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
e01678e3 1111 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
0b0ffc96 1112
e01678e3 1113 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
0b0ffc96
TK		 1114 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1115 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1116 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1117 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1118 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
e01678e3 1119 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
0b0ffc96 1120
e01678e3 1121 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
0b0ffc96
TK		 1122 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1123 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1124 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1125 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1126 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
e01678e3 1127 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
0b0ffc96
TK		 1128
1129 /* IPSR12 */
1130 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1131 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1132 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1133 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1134 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1135 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1136
1137 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1138 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1139 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1140 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1141 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1142 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1143
e01678e3 1144 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
0b0ffc96
TK		 1145 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1146 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1147 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1148 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1149 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1150 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1151
e01678e3 1152 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
0b0ffc96
TK		 1153 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1154 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1155 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1156 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1157 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1158
e01678e3 1159 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
0b0ffc96
TK		 1160 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1161 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1162 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1163 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1164 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1165
e01678e3 1166 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
0b0ffc96
TK		 1167 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1168 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1169 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1170 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1171 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1172 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1173 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1174
e01678e3 1175 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
0b0ffc96
TK		 1176 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1177 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1178 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1179 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1180 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1181 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1182
e01678e3 1183 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
0b0ffc96
TK		 1184 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1185
1186 /* IPSR13 */
e01678e3
GU		 1187 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1188 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
0b0ffc96
TK		 1189 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1190 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1191 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1192 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1193 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1194
e01678e3
GU		 1195 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1196 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
0b0ffc96
TK		 1197 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1198 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1199 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1200 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1201 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1202 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1203
e01678e3 1204 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
0b0ffc96
TK		 1205 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1206 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1207
e01678e3 1208 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
0b0ffc96
TK		 1209 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1210 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1211 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1212
e01678e3 1213 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
0b0ffc96
TK		 1214 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1215 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1216
00edf542 1217 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
0b0ffc96
TK		 1218 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1219
00edf542 1220 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
0b0ffc96
TK		 1221 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1222
e01678e3 1223 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
0b0ffc96
TK		 1224 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1225
1226 /* IPSR14 */
1227 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1228
1229 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1230 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1231
e01678e3 1232 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
0b0ffc96
TK		 1233 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1234 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1235
e01678e3 1236 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
0b0ffc96
TK		 1237 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1238 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1239 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1240
e01678e3 1241 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
0b0ffc96
TK		 1242 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1243 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1244 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1245 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1246 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1247 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1248
e01678e3 1249 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
0b0ffc96
TK		 1250 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1251 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1252 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1253 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1254 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1255 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1256
e01678e3 1257 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
0b0ffc96
TK		 1258 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1259 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1260 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1261 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1262 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1263 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1264
e01678e3 1265 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
0b0ffc96
TK		 1266 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1267 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1268 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1269 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1270 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1271 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1272
1273 /* IPSR15 */
e01678e3
GU		 1274 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1275 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
0b0ffc96
TK		 1276 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1277
e01678e3
GU		 1278 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1279 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
0b0ffc96
TK		 1280 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1281
e01678e3 1282 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
0b0ffc96 1283 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
fd1aa743 1284 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
0b0ffc96 1285
e01678e3 1286 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
0b0ffc96
TK		 1287 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1288 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1289 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1290 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1291 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1292 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1293
e01678e3 1294 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
0b0ffc96
TK		 1295 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1296 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1297 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1298 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1299 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1300 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1301
e01678e3 1302 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
0b0ffc96
TK		 1303 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1304 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1305 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1306 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1307 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1308 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1309 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1310
e01678e3 1311 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
0b0ffc96
TK		 1312 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1313 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1314 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1315 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1316 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1317 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1318
1319 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1320 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1321 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1322 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1323 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
e01678e3 1324 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
0b0ffc96 1325 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
e01678e3 1326 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
0b0ffc96
TK		 1327
1328 /* IPSR16 */
1329 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
e01678e3 1330 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
0b0ffc96
TK		 1331
1332 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1333 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1334 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1335 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1336 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1337
e01678e3 1338 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
0b0ffc96
TK		 1339 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1340 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1341 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1342 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1343 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1344
e01678e3 1345 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
0b0ffc96
TK		 1346 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1347 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1348 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1349 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1350
e01678e3 1351 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
0b0ffc96
TK		 1352 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1353 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1354 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1355 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1356 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1357 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1358 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1359
e01678e3 1360 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
0b0ffc96
TK		 1361 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1362 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1363 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1364 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1365 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1366 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1367 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1368
e01678e3 1369 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
0b0ffc96
TK		 1370 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1371 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1372 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1373 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1374 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1375 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1376 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
e01678e3 1377 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
0b0ffc96 1378
e01678e3 1379 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
0b0ffc96
TK		 1380 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1381 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1382 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1383 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1384 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1385 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1386 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
e01678e3 1387 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
0b0ffc96
TK		 1388
1389 /* IPSR17 */
e01678e3 1390 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
0b0ffc96
TK		 1391 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1392 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1393 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1394 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1395 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
e01678e3 1396 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
0b0ffc96 1397
e01678e3 1398 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
0b0ffc96
TK		 1399 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1400 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1401 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1402 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1403 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
e01678e3 1404 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
0b0ffc96
TK		 1405
1406 /* I2C */
1407 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1408 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1409 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1410};
1411
1412static const struct sh_pfc_pin pinmux_pins[] = {
1413 PINMUX_GPIO_GP_ALL(),
1414};
1415
c33a7fe3
KM		 1416/* - AUDIO CLOCK ------------------------------------------------------------ */
1417static const unsigned int audio_clk_a_a_pins[] = {
1418 /* CLK A */
1419 RCAR_GP_PIN(6, 22),
1420};
1421static const unsigned int audio_clk_a_a_mux[] = {
1422 AUDIO_CLKA_A_MARK,
1423};
1424static const unsigned int audio_clk_a_b_pins[] = {
1425 /* CLK A */
1426 RCAR_GP_PIN(5, 4),
1427};
1428static const unsigned int audio_clk_a_b_mux[] = {
1429 AUDIO_CLKA_B_MARK,
1430};
1431static const unsigned int audio_clk_a_c_pins[] = {
1432 /* CLK A */
1433 RCAR_GP_PIN(5, 19),
1434};
1435static const unsigned int audio_clk_a_c_mux[] = {
1436 AUDIO_CLKA_C_MARK,
1437};
1438static const unsigned int audio_clk_b_a_pins[] = {
1439 /* CLK B */
1440 RCAR_GP_PIN(5, 12),
1441};
1442static const unsigned int audio_clk_b_a_mux[] = {
1443 AUDIO_CLKB_A_MARK,
1444};
1445static const unsigned int audio_clk_b_b_pins[] = {
1446 /* CLK B */
1447 RCAR_GP_PIN(6, 23),
1448};
1449static const unsigned int audio_clk_b_b_mux[] = {
1450 AUDIO_CLKB_B_MARK,
1451};
1452static const unsigned int audio_clk_c_a_pins[] = {
1453 /* CLK C */
1454 RCAR_GP_PIN(5, 21),
1455};
1456static const unsigned int audio_clk_c_a_mux[] = {
1457 AUDIO_CLKC_A_MARK,
1458};
1459static const unsigned int audio_clk_c_b_pins[] = {
1460 /* CLK C */
1461 RCAR_GP_PIN(5, 0),
1462};
1463static const unsigned int audio_clk_c_b_mux[] = {
1464 AUDIO_CLKC_B_MARK,
1465};
1466static const unsigned int audio_clkout_a_pins[] = {
1467 /* CLKOUT */
1468 RCAR_GP_PIN(5, 18),
1469};
1470static const unsigned int audio_clkout_a_mux[] = {
1471 AUDIO_CLKOUT_A_MARK,
1472};
1473static const unsigned int audio_clkout_b_pins[] = {
1474 /* CLKOUT */
1475 RCAR_GP_PIN(6, 28),
1476};
1477static const unsigned int audio_clkout_b_mux[] = {
1478 AUDIO_CLKOUT_B_MARK,
1479};
1480static const unsigned int audio_clkout_c_pins[] = {
1481 /* CLKOUT */
1482 RCAR_GP_PIN(5, 3),
1483};
1484static const unsigned int audio_clkout_c_mux[] = {
1485 AUDIO_CLKOUT_C_MARK,
1486};
1487static const unsigned int audio_clkout_d_pins[] = {
1488 /* CLKOUT */
1489 RCAR_GP_PIN(5, 21),
1490};
1491static const unsigned int audio_clkout_d_mux[] = {
1492 AUDIO_CLKOUT_D_MARK,
1493};
1494static const unsigned int audio_clkout1_a_pins[] = {
1495 /* CLKOUT1 */
1496 RCAR_GP_PIN(5, 15),
1497};
1498static const unsigned int audio_clkout1_a_mux[] = {
1499 AUDIO_CLKOUT1_A_MARK,
1500};
1501static const unsigned int audio_clkout1_b_pins[] = {
1502 /* CLKOUT1 */
1503 RCAR_GP_PIN(6, 29),
1504};
1505static const unsigned int audio_clkout1_b_mux[] = {
1506 AUDIO_CLKOUT1_B_MARK,
1507};
1508static const unsigned int audio_clkout2_a_pins[] = {
1509 /* CLKOUT2 */
1510 RCAR_GP_PIN(5, 16),
1511};
1512static const unsigned int audio_clkout2_a_mux[] = {
1513 AUDIO_CLKOUT2_A_MARK,
1514};
1515static const unsigned int audio_clkout2_b_pins[] = {
1516 /* CLKOUT2 */
1517 RCAR_GP_PIN(6, 30),
1518};
1519static const unsigned int audio_clkout2_b_mux[] = {
1520 AUDIO_CLKOUT2_B_MARK,
1521};
1522
1523static const unsigned int audio_clkout3_a_pins[] = {
1524 /* CLKOUT3 */
1525 RCAR_GP_PIN(5, 19),
1526};
1527static const unsigned int audio_clkout3_a_mux[] = {
1528 AUDIO_CLKOUT3_A_MARK,
1529};
1530static const unsigned int audio_clkout3_b_pins[] = {
1531 /* CLKOUT3 */
1532 RCAR_GP_PIN(6, 31),
1533};
1534static const unsigned int audio_clkout3_b_mux[] = {
1535 AUDIO_CLKOUT3_B_MARK,
1536};
1537
819fd4bf
TK		 1538/* - EtherAVB --------------------------------------------------------------- */
1539static const unsigned int avb_link_pins[] = {
1540 /* AVB_LINK */
1541 RCAR_GP_PIN(2, 12),
1542};
1543static const unsigned int avb_link_mux[] = {
1544 AVB_LINK_MARK,
1545};
1546static const unsigned int avb_magic_pins[] = {
1547 /* AVB_MAGIC_ */
1548 RCAR_GP_PIN(2, 10),
1549};
1550static const unsigned int avb_magic_mux[] = {
1551 AVB_MAGIC_MARK,
1552};
1553static const unsigned int avb_phy_int_pins[] = {
1554 /* AVB_PHY_INT */
1555 RCAR_GP_PIN(2, 11),
1556};
1557static const unsigned int avb_phy_int_mux[] = {
1558 AVB_PHY_INT_MARK,
1559};
1560static const unsigned int avb_mdc_pins[] = {
1561 /* AVB_MDC */
1562 RCAR_GP_PIN(2, 9),
1563};
1564static const unsigned int avb_mdc_mux[] = {
1565 AVB_MDC_MARK,
1566};
1567static const unsigned int avb_avtp_pps_pins[] = {
1568 /* AVB_AVTP_PPS */
1569 RCAR_GP_PIN(2, 6),
1570};
1571static const unsigned int avb_avtp_pps_mux[] = {
1572 AVB_AVTP_PPS_MARK,
1573};
1574static const unsigned int avb_avtp_match_a_pins[] = {
1575 /* AVB_AVTP_MATCH_A */
1576 RCAR_GP_PIN(2, 13),
1577};
1578static const unsigned int avb_avtp_match_a_mux[] = {
1579 AVB_AVTP_MATCH_A_MARK,
1580};
1581static const unsigned int avb_avtp_capture_a_pins[] = {
1582 /* AVB_AVTP_CAPTURE_A */
1583 RCAR_GP_PIN(2, 14),
1584};
1585static const unsigned int avb_avtp_capture_a_mux[] = {
1586 AVB_AVTP_CAPTURE_A_MARK,
1587};
1588static const unsigned int avb_avtp_match_b_pins[] = {
1589 /* AVB_AVTP_MATCH_B */
1590 RCAR_GP_PIN(1, 8),
1591};
1592static const unsigned int avb_avtp_match_b_mux[] = {
1593 AVB_AVTP_MATCH_B_MARK,
1594};
1595static const unsigned int avb_avtp_capture_b_pins[] = {
1596 /* AVB_AVTP_CAPTURE_B */
1597 RCAR_GP_PIN(1, 11),
1598};
1599static const unsigned int avb_avtp_capture_b_mux[] = {
1600 AVB_AVTP_CAPTURE_B_MARK,
1601};
1602
a56069c4
GU		 1603/* - HSCIF0 ----------------------------------------------------------------- */
1604static const unsigned int hscif0_data_pins[] = {
1605 /* RX, TX */
1606 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1607};
1608static const unsigned int hscif0_data_mux[] = {
1609 HRX0_MARK, HTX0_MARK,
1610};
1611static const unsigned int hscif0_clk_pins[] = {
1612 /* SCK */
1613 RCAR_GP_PIN(5, 12),
1614};
1615static const unsigned int hscif0_clk_mux[] = {
1616 HSCK0_MARK,
1617};
1618static const unsigned int hscif0_ctrl_pins[] = {
1619 /* RTS, CTS */
1620 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1621};
1622static const unsigned int hscif0_ctrl_mux[] = {
1623 HRTS0_N_MARK, HCTS0_N_MARK,
1624};
1625/* - HSCIF1 ----------------------------------------------------------------- */
1626static const unsigned int hscif1_data_a_pins[] = {
1627 /* RX, TX */
1628 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1629};
1630static const unsigned int hscif1_data_a_mux[] = {
1631 HRX1_A_MARK, HTX1_A_MARK,
1632};
1633static const unsigned int hscif1_clk_a_pins[] = {
1634 /* SCK */
1635 RCAR_GP_PIN(6, 21),
1636};
1637static const unsigned int hscif1_clk_a_mux[] = {
1638 HSCK1_A_MARK,
1639};
1640static const unsigned int hscif1_ctrl_a_pins[] = {
1641 /* RTS, CTS */
1642 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1643};
1644static const unsigned int hscif1_ctrl_a_mux[] = {
1645 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1646};
1647
1648static const unsigned int hscif1_data_b_pins[] = {
1649 /* RX, TX */
1650 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1651};
1652static const unsigned int hscif1_data_b_mux[] = {
1653 HRX1_B_MARK, HTX1_B_MARK,
1654};
1655static const unsigned int hscif1_clk_b_pins[] = {
1656 /* SCK */
1657 RCAR_GP_PIN(5, 0),
1658};
1659static const unsigned int hscif1_clk_b_mux[] = {
1660 HSCK1_B_MARK,
1661};
1662static const unsigned int hscif1_ctrl_b_pins[] = {
1663 /* RTS, CTS */
1664 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1665};
1666static const unsigned int hscif1_ctrl_b_mux[] = {
1667 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1668};
1669/* - HSCIF2 ----------------------------------------------------------------- */
1670static const unsigned int hscif2_data_a_pins[] = {
1671 /* RX, TX */
1672 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1673};
1674static const unsigned int hscif2_data_a_mux[] = {
1675 HRX2_A_MARK, HTX2_A_MARK,
1676};
1677static const unsigned int hscif2_clk_a_pins[] = {
1678 /* SCK */
1679 RCAR_GP_PIN(6, 10),
1680};
1681static const unsigned int hscif2_clk_a_mux[] = {
1682 HSCK2_A_MARK,
1683};
1684static const unsigned int hscif2_ctrl_a_pins[] = {
1685 /* RTS, CTS */
1686 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1687};
1688static const unsigned int hscif2_ctrl_a_mux[] = {
1689 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1690};
1691
1692static const unsigned int hscif2_data_b_pins[] = {
1693 /* RX, TX */
1694 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1695};
1696static const unsigned int hscif2_data_b_mux[] = {
1697 HRX2_B_MARK, HTX2_B_MARK,
1698};
1699static const unsigned int hscif2_clk_b_pins[] = {
1700 /* SCK */
1701 RCAR_GP_PIN(6, 21),
1702};
1703static const unsigned int hscif2_clk_b_mux[] = {
1704 HSCK1_B_MARK,
1705};
1706static const unsigned int hscif2_ctrl_b_pins[] = {
1707 /* RTS, CTS */
1708 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1709};
1710static const unsigned int hscif2_ctrl_b_mux[] = {
1711 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1712};
1713/* - HSCIF3 ----------------------------------------------------------------- */
1714static const unsigned int hscif3_data_a_pins[] = {
1715 /* RX, TX */
1716 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1717};
1718static const unsigned int hscif3_data_a_mux[] = {
1719 HRX3_A_MARK, HTX3_A_MARK,
1720};
1721static const unsigned int hscif3_clk_pins[] = {
1722 /* SCK */
1723 RCAR_GP_PIN(1, 22),
1724};
1725static const unsigned int hscif3_clk_mux[] = {
1726 HSCK3_MARK,
1727};
1728static const unsigned int hscif3_ctrl_pins[] = {
1729 /* RTS, CTS */
1730 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1731};
1732static const unsigned int hscif3_ctrl_mux[] = {
1733 HRTS3_N_MARK, HCTS3_N_MARK,
1734};
1735
1736static const unsigned int hscif3_data_b_pins[] = {
1737 /* RX, TX */
1738 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1739};
1740static const unsigned int hscif3_data_b_mux[] = {
1741 HRX3_B_MARK, HTX3_B_MARK,
1742};
1743static const unsigned int hscif3_data_c_pins[] = {
1744 /* RX, TX */
1745 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1746};
1747static const unsigned int hscif3_data_c_mux[] = {
1748 HRX3_C_MARK, HTX3_C_MARK,
1749};
1750static const unsigned int hscif3_data_d_pins[] = {
1751 /* RX, TX */
1752 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1753};
1754static const unsigned int hscif3_data_d_mux[] = {
1755 HRX3_D_MARK, HTX3_D_MARK,
1756};
1757/* - HSCIF4 ----------------------------------------------------------------- */
1758static const unsigned int hscif4_data_a_pins[] = {
1759 /* RX, TX */
1760 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
1761};
1762static const unsigned int hscif4_data_a_mux[] = {
1763 HRX4_A_MARK, HTX4_A_MARK,
1764};
1765static const unsigned int hscif4_clk_pins[] = {
1766 /* SCK */
1767 RCAR_GP_PIN(1, 11),
1768};
1769static const unsigned int hscif4_clk_mux[] = {
1770 HSCK4_MARK,
1771};
1772static const unsigned int hscif4_ctrl_pins[] = {
1773 /* RTS, CTS */
1774 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1775};
1776static const unsigned int hscif4_ctrl_mux[] = {
1777 HRTS4_N_MARK, HCTS3_N_MARK,
1778};
1779
1780static const unsigned int hscif4_data_b_pins[] = {
1781 /* RX, TX */
1782 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1783};
1784static const unsigned int hscif4_data_b_mux[] = {
1785 HRX4_B_MARK, HTX4_B_MARK,
1786};
1787
2544ef72
KM		 1788/* - I2C -------------------------------------------------------------------- */
1789static const unsigned int i2c1_a_pins[] = {
1790 /* SDA, SCL */
1791 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1792};
1793static const unsigned int i2c1_a_mux[] = {
1794 SDA1_A_MARK, SCL1_A_MARK,
1795};
1796static const unsigned int i2c1_b_pins[] = {
1797 /* SDA, SCL */
1798 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1799};
1800static const unsigned int i2c1_b_mux[] = {
1801 SDA1_B_MARK, SCL1_B_MARK,
1802};
1803static const unsigned int i2c2_a_pins[] = {
1804 /* SDA, SCL */
1805 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1806};
1807static const unsigned int i2c2_a_mux[] = {
1808 SDA2_A_MARK, SCL2_A_MARK,
1809};
1810static const unsigned int i2c2_b_pins[] = {
1811 /* SDA, SCL */
1812 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1813};
1814static const unsigned int i2c2_b_mux[] = {
1815 SDA2_B_MARK, SCL2_B_MARK,
1816};
1817static const unsigned int i2c6_a_pins[] = {
1818 /* SDA, SCL */
1819 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1820};
1821static const unsigned int i2c6_a_mux[] = {
1822 SDA6_A_MARK, SCL6_A_MARK,
1823};
1824static const unsigned int i2c6_b_pins[] = {
1825 /* SDA, SCL */
1826 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1827};
1828static const unsigned int i2c6_b_mux[] = {
1829 SDA6_B_MARK, SCL6_B_MARK,
1830};
1831static const unsigned int i2c6_c_pins[] = {
1832 /* SDA, SCL */
1833 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1834};
1835static const unsigned int i2c6_c_mux[] = {
1836 SDA6_C_MARK, SCL6_C_MARK,
1837};
1838
e7419b81
GU		 1839/* - MSIOF0 ----------------------------------------------------------------- */
1840static const unsigned int msiof0_clk_pins[] = {
1841 /* SCK */
1842 RCAR_GP_PIN(5, 17),
1843};
1844static const unsigned int msiof0_clk_mux[] = {
1845 MSIOF0_SCK_MARK,
1846};
1847static const unsigned int msiof0_sync_pins[] = {
1848 /* SYNC */
1849 RCAR_GP_PIN(5, 18),
1850};
1851static const unsigned int msiof0_sync_mux[] = {
1852 MSIOF0_SYNC_MARK,
1853};
1854static const unsigned int msiof0_ss1_pins[] = {
1855 /* SS1 */
1856 RCAR_GP_PIN(5, 19),
1857};
1858static const unsigned int msiof0_ss1_mux[] = {
1859 MSIOF0_SS1_MARK,
1860};
1861static const unsigned int msiof0_ss2_pins[] = {
1862 /* SS2 */
1863 RCAR_GP_PIN(5, 21),
1864};
1865static const unsigned int msiof0_ss2_mux[] = {
1866 MSIOF0_SS2_MARK,
1867};
1868static const unsigned int msiof0_txd_pins[] = {
1869 /* TXD */
1870 RCAR_GP_PIN(5, 20),
1871};
1872static const unsigned int msiof0_txd_mux[] = {
1873 MSIOF0_TXD_MARK,
1874};
1875static const unsigned int msiof0_rxd_pins[] = {
1876 /* RXD */
1877 RCAR_GP_PIN(5, 22),
1878};
1879static const unsigned int msiof0_rxd_mux[] = {
1880 MSIOF0_RXD_MARK,
1881};
1882/* - MSIOF1 ----------------------------------------------------------------- */
1883static const unsigned int msiof1_clk_a_pins[] = {
1884 /* SCK */
1885 RCAR_GP_PIN(6, 8),
1886};
1887static const unsigned int msiof1_clk_a_mux[] = {
1888 MSIOF1_SCK_A_MARK,
1889};
1890static const unsigned int msiof1_sync_a_pins[] = {
1891 /* SYNC */
1892 RCAR_GP_PIN(6, 9),
1893};
1894static const unsigned int msiof1_sync_a_mux[] = {
1895 MSIOF1_SYNC_A_MARK,
1896};
1897static const unsigned int msiof1_ss1_a_pins[] = {
1898 /* SS1 */
1899 RCAR_GP_PIN(6, 5),
1900};
1901static const unsigned int msiof1_ss1_a_mux[] = {
1902 MSIOF1_SS1_A_MARK,
1903};
1904static const unsigned int msiof1_ss2_a_pins[] = {
1905 /* SS2 */
1906 RCAR_GP_PIN(6, 6),
1907};
1908static const unsigned int msiof1_ss2_a_mux[] = {
1909 MSIOF1_SS2_A_MARK,
1910};
1911static const unsigned int msiof1_txd_a_pins[] = {
1912 /* TXD */
1913 RCAR_GP_PIN(6, 7),
1914};
1915static const unsigned int msiof1_txd_a_mux[] = {
1916 MSIOF1_TXD_A_MARK,
1917};
1918static const unsigned int msiof1_rxd_a_pins[] = {
1919 /* RXD */
1920 RCAR_GP_PIN(6, 10),
1921};
1922static const unsigned int msiof1_rxd_a_mux[] = {
1923 MSIOF1_RXD_A_MARK,
1924};
1925static const unsigned int msiof1_clk_b_pins[] = {
1926 /* SCK */
1927 RCAR_GP_PIN(5, 9),
1928};
1929static const unsigned int msiof1_clk_b_mux[] = {
1930 MSIOF1_SCK_B_MARK,
1931};
1932static const unsigned int msiof1_sync_b_pins[] = {
1933 /* SYNC */
1934 RCAR_GP_PIN(5, 3),
1935};
1936static const unsigned int msiof1_sync_b_mux[] = {
1937 MSIOF1_SYNC_B_MARK,
1938};
1939static const unsigned int msiof1_ss1_b_pins[] = {
1940 /* SS1 */
1941 RCAR_GP_PIN(5, 4),
1942};
1943static const unsigned int msiof1_ss1_b_mux[] = {
1944 MSIOF1_SS1_B_MARK,
1945};
1946static const unsigned int msiof1_ss2_b_pins[] = {
1947 /* SS2 */
1948 RCAR_GP_PIN(5, 0),
1949};
1950static const unsigned int msiof1_ss2_b_mux[] = {
1951 MSIOF1_SS2_B_MARK,
1952};
1953static const unsigned int msiof1_txd_b_pins[] = {
1954 /* TXD */
1955 RCAR_GP_PIN(5, 8),
1956};
1957static const unsigned int msiof1_txd_b_mux[] = {
1958 MSIOF1_TXD_B_MARK,
1959};
1960static const unsigned int msiof1_rxd_b_pins[] = {
1961 /* RXD */
1962 RCAR_GP_PIN(5, 7),
1963};
1964static const unsigned int msiof1_rxd_b_mux[] = {
1965 MSIOF1_RXD_B_MARK,
1966};
1967static const unsigned int msiof1_clk_c_pins[] = {
1968 /* SCK */
1969 RCAR_GP_PIN(6, 17),
1970};
1971static const unsigned int msiof1_clk_c_mux[] = {
1972 MSIOF1_SCK_C_MARK,
1973};
1974static const unsigned int msiof1_sync_c_pins[] = {
1975 /* SYNC */
1976 RCAR_GP_PIN(6, 18),
1977};
1978static const unsigned int msiof1_sync_c_mux[] = {
1979 MSIOF1_SYNC_C_MARK,
1980};
1981static const unsigned int msiof1_ss1_c_pins[] = {
1982 /* SS1 */
1983 RCAR_GP_PIN(6, 21),
1984};
1985static const unsigned int msiof1_ss1_c_mux[] = {
1986 MSIOF1_SS1_C_MARK,
1987};
1988static const unsigned int msiof1_ss2_c_pins[] = {
1989 /* SS2 */
1990 RCAR_GP_PIN(6, 27),
1991};
1992static const unsigned int msiof1_ss2_c_mux[] = {
1993 MSIOF1_SS2_C_MARK,
1994};
1995static const unsigned int msiof1_txd_c_pins[] = {
1996 /* TXD */
1997 RCAR_GP_PIN(6, 20),
1998};
1999static const unsigned int msiof1_txd_c_mux[] = {
2000 MSIOF1_TXD_C_MARK,
2001};
2002static const unsigned int msiof1_rxd_c_pins[] = {
2003 /* RXD */
2004 RCAR_GP_PIN(6, 19),
2005};
2006static const unsigned int msiof1_rxd_c_mux[] = {
2007 MSIOF1_RXD_C_MARK,
2008};
2009static const unsigned int msiof1_clk_d_pins[] = {
2010 /* SCK */
2011 RCAR_GP_PIN(5, 12),
2012};
2013static const unsigned int msiof1_clk_d_mux[] = {
2014 MSIOF1_SCK_D_MARK,
2015};
2016static const unsigned int msiof1_sync_d_pins[] = {
2017 /* SYNC */
2018 RCAR_GP_PIN(5, 15),
2019};
2020static const unsigned int msiof1_sync_d_mux[] = {
2021 MSIOF1_SYNC_D_MARK,
2022};
2023static const unsigned int msiof1_ss1_d_pins[] = {
2024 /* SS1 */
2025 RCAR_GP_PIN(5, 16),
2026};
2027static const unsigned int msiof1_ss1_d_mux[] = {
2028 MSIOF1_SS1_D_MARK,
2029};
2030static const unsigned int msiof1_ss2_d_pins[] = {
2031 /* SS2 */
2032 RCAR_GP_PIN(5, 21),
2033};
2034static const unsigned int msiof1_ss2_d_mux[] = {
2035 MSIOF1_SS2_D_MARK,
2036};
2037static const unsigned int msiof1_txd_d_pins[] = {
2038 /* TXD */
2039 RCAR_GP_PIN(5, 14),
2040};
2041static const unsigned int msiof1_txd_d_mux[] = {
2042 MSIOF1_TXD_D_MARK,
2043};
2044static const unsigned int msiof1_rxd_d_pins[] = {
2045 /* RXD */
2046 RCAR_GP_PIN(5, 13),
2047};
2048static const unsigned int msiof1_rxd_d_mux[] = {
2049 MSIOF1_RXD_D_MARK,
2050};
2051static const unsigned int msiof1_clk_e_pins[] = {
2052 /* SCK */
2053 RCAR_GP_PIN(3, 0),
2054};
2055static const unsigned int msiof1_clk_e_mux[] = {
2056 MSIOF1_SCK_E_MARK,
2057};
2058static const unsigned int msiof1_sync_e_pins[] = {
2059 /* SYNC */
2060 RCAR_GP_PIN(3, 1),
2061};
2062static const unsigned int msiof1_sync_e_mux[] = {
2063 MSIOF1_SYNC_E_MARK,
2064};
2065static const unsigned int msiof1_ss1_e_pins[] = {
2066 /* SS1 */
2067 RCAR_GP_PIN(3, 4),
2068};
2069static const unsigned int msiof1_ss1_e_mux[] = {
2070 MSIOF1_SS1_E_MARK,
2071};
2072static const unsigned int msiof1_ss2_e_pins[] = {
2073 /* SS2 */
2074 RCAR_GP_PIN(3, 5),
2075};
2076static const unsigned int msiof1_ss2_e_mux[] = {
2077 MSIOF1_SS2_E_MARK,
2078};
2079static const unsigned int msiof1_txd_e_pins[] = {
2080 /* TXD */
2081 RCAR_GP_PIN(3, 3),
2082};
2083static const unsigned int msiof1_txd_e_mux[] = {
2084 MSIOF1_TXD_E_MARK,
2085};
2086static const unsigned int msiof1_rxd_e_pins[] = {
2087 /* RXD */
2088 RCAR_GP_PIN(3, 2),
2089};
2090static const unsigned int msiof1_rxd_e_mux[] = {
2091 MSIOF1_RXD_E_MARK,
2092};
2093static const unsigned int msiof1_clk_f_pins[] = {
2094 /* SCK */
2095 RCAR_GP_PIN(5, 23),
2096};
2097static const unsigned int msiof1_clk_f_mux[] = {
2098 MSIOF1_SCK_F_MARK,
2099};
2100static const unsigned int msiof1_sync_f_pins[] = {
2101 /* SYNC */
2102 RCAR_GP_PIN(5, 24),
2103};
2104static const unsigned int msiof1_sync_f_mux[] = {
2105 MSIOF1_SYNC_F_MARK,
2106};
2107static const unsigned int msiof1_ss1_f_pins[] = {
2108 /* SS1 */
2109 RCAR_GP_PIN(6, 1),
2110};
2111static const unsigned int msiof1_ss1_f_mux[] = {
2112 MSIOF1_SS1_F_MARK,
2113};
2114static const unsigned int msiof1_ss2_f_pins[] = {
2115 /* SS2 */
2116 RCAR_GP_PIN(6, 2),
2117};
2118static const unsigned int msiof1_ss2_f_mux[] = {
2119 MSIOF1_SS2_F_MARK,
2120};
2121static const unsigned int msiof1_txd_f_pins[] = {
2122 /* TXD */
2123 RCAR_GP_PIN(6, 0),
2124};
2125static const unsigned int msiof1_txd_f_mux[] = {
2126 MSIOF1_TXD_F_MARK,
2127};
2128static const unsigned int msiof1_rxd_f_pins[] = {
2129 /* RXD */
2130 RCAR_GP_PIN(5, 25),
2131};
2132static const unsigned int msiof1_rxd_f_mux[] = {
2133 MSIOF1_RXD_F_MARK,
2134};
2135static const unsigned int msiof1_clk_g_pins[] = {
2136 /* SCK */
2137 RCAR_GP_PIN(3, 6),
2138};
2139static const unsigned int msiof1_clk_g_mux[] = {
2140 MSIOF1_SCK_G_MARK,
2141};
2142static const unsigned int msiof1_sync_g_pins[] = {
2143 /* SYNC */
2144 RCAR_GP_PIN(3, 7),
2145};
2146static const unsigned int msiof1_sync_g_mux[] = {
2147 MSIOF1_SYNC_G_MARK,
2148};
2149static const unsigned int msiof1_ss1_g_pins[] = {
2150 /* SS1 */
2151 RCAR_GP_PIN(3, 10),
2152};
2153static const unsigned int msiof1_ss1_g_mux[] = {
2154 MSIOF1_SS1_G_MARK,
2155};
2156static const unsigned int msiof1_ss2_g_pins[] = {
2157 /* SS2 */
2158 RCAR_GP_PIN(3, 11),
2159};
2160static const unsigned int msiof1_ss2_g_mux[] = {
2161 MSIOF1_SS2_G_MARK,
2162};
2163static const unsigned int msiof1_txd_g_pins[] = {
2164 /* TXD */
2165 RCAR_GP_PIN(3, 9),
2166};
2167static const unsigned int msiof1_txd_g_mux[] = {
2168 MSIOF1_TXD_G_MARK,
2169};
2170static const unsigned int msiof1_rxd_g_pins[] = {
2171 /* RXD */
2172 RCAR_GP_PIN(3, 8),
2173};
2174static const unsigned int msiof1_rxd_g_mux[] = {
2175 MSIOF1_RXD_G_MARK,
2176};
2177/* - MSIOF2 ----------------------------------------------------------------- */
2178static const unsigned int msiof2_clk_a_pins[] = {
2179 /* SCK */
2180 RCAR_GP_PIN(1, 9),
2181};
2182static const unsigned int msiof2_clk_a_mux[] = {
2183 MSIOF2_SCK_A_MARK,
2184};
2185static const unsigned int msiof2_sync_a_pins[] = {
2186 /* SYNC */
2187 RCAR_GP_PIN(1, 8),
2188};
2189static const unsigned int msiof2_sync_a_mux[] = {
2190 MSIOF2_SYNC_A_MARK,
2191};
2192static const unsigned int msiof2_ss1_a_pins[] = {
2193 /* SS1 */
2194 RCAR_GP_PIN(1, 6),
2195};
2196static const unsigned int msiof2_ss1_a_mux[] = {
2197 MSIOF2_SS1_A_MARK,
2198};
2199static const unsigned int msiof2_ss2_a_pins[] = {
2200 /* SS2 */
2201 RCAR_GP_PIN(1, 7),
2202};
2203static const unsigned int msiof2_ss2_a_mux[] = {
2204 MSIOF2_SS2_A_MARK,
2205};
2206static const unsigned int msiof2_txd_a_pins[] = {
2207 /* TXD */
2208 RCAR_GP_PIN(1, 11),
2209};
2210static const unsigned int msiof2_txd_a_mux[] = {
2211 MSIOF2_TXD_A_MARK,
2212};
2213static const unsigned int msiof2_rxd_a_pins[] = {
2214 /* RXD */
2215 RCAR_GP_PIN(1, 10),
2216};
2217static const unsigned int msiof2_rxd_a_mux[] = {
2218 MSIOF2_RXD_A_MARK,
2219};
2220static const unsigned int msiof2_clk_b_pins[] = {
2221 /* SCK */
2222 RCAR_GP_PIN(0, 4),
2223};
2224static const unsigned int msiof2_clk_b_mux[] = {
2225 MSIOF2_SCK_B_MARK,
2226};
2227static const unsigned int msiof2_sync_b_pins[] = {
2228 /* SYNC */
2229 RCAR_GP_PIN(0, 5),
2230};
2231static const unsigned int msiof2_sync_b_mux[] = {
2232 MSIOF2_SYNC_B_MARK,
2233};
2234static const unsigned int msiof2_ss1_b_pins[] = {
2235 /* SS1 */
2236 RCAR_GP_PIN(0, 0),
2237};
2238static const unsigned int msiof2_ss1_b_mux[] = {
2239 MSIOF2_SS1_B_MARK,
2240};
2241static const unsigned int msiof2_ss2_b_pins[] = {
2242 /* SS2 */
2243 RCAR_GP_PIN(0, 1),
2244};
2245static const unsigned int msiof2_ss2_b_mux[] = {
2246 MSIOF2_SS2_B_MARK,
2247};
2248static const unsigned int msiof2_txd_b_pins[] = {
2249 /* TXD */
2250 RCAR_GP_PIN(0, 7),
2251};
2252static const unsigned int msiof2_txd_b_mux[] = {
2253 MSIOF2_TXD_B_MARK,
2254};
2255static const unsigned int msiof2_rxd_b_pins[] = {
2256 /* RXD */
2257 RCAR_GP_PIN(0, 6),
2258};
2259static const unsigned int msiof2_rxd_b_mux[] = {
2260 MSIOF2_RXD_B_MARK,
2261};
2262static const unsigned int msiof2_clk_c_pins[] = {
2263 /* SCK */
2264 RCAR_GP_PIN(2, 12),
2265};
2266static const unsigned int msiof2_clk_c_mux[] = {
2267 MSIOF2_SCK_C_MARK,
2268};
2269static const unsigned int msiof2_sync_c_pins[] = {
2270 /* SYNC */
2271 RCAR_GP_PIN(2, 11),
2272};
2273static const unsigned int msiof2_sync_c_mux[] = {
2274 MSIOF2_SYNC_C_MARK,
2275};
2276static const unsigned int msiof2_ss1_c_pins[] = {
2277 /* SS1 */
2278 RCAR_GP_PIN(2, 10),
2279};
2280static const unsigned int msiof2_ss1_c_mux[] = {
2281 MSIOF2_SS1_C_MARK,
2282};
2283static const unsigned int msiof2_ss2_c_pins[] = {
2284 /* SS2 */
2285 RCAR_GP_PIN(2, 9),
2286};
2287static const unsigned int msiof2_ss2_c_mux[] = {
2288 MSIOF2_SS2_C_MARK,
2289};
2290static const unsigned int msiof2_txd_c_pins[] = {
2291 /* TXD */
2292 RCAR_GP_PIN(2, 14),
2293};
2294static const unsigned int msiof2_txd_c_mux[] = {
2295 MSIOF2_TXD_C_MARK,
2296};
2297static const unsigned int msiof2_rxd_c_pins[] = {
2298 /* RXD */
2299 RCAR_GP_PIN(2, 13),
2300};
2301static const unsigned int msiof2_rxd_c_mux[] = {
2302 MSIOF2_RXD_C_MARK,
2303};
2304static const unsigned int msiof2_clk_d_pins[] = {
2305 /* SCK */
2306 RCAR_GP_PIN(0, 8),
2307};
2308static const unsigned int msiof2_clk_d_mux[] = {
2309 MSIOF2_SCK_D_MARK,
2310};
2311static const unsigned int msiof2_sync_d_pins[] = {
2312 /* SYNC */
2313 RCAR_GP_PIN(0, 9),
2314};
2315static const unsigned int msiof2_sync_d_mux[] = {
2316 MSIOF2_SYNC_D_MARK,
2317};
2318static const unsigned int msiof2_ss1_d_pins[] = {
2319 /* SS1 */
2320 RCAR_GP_PIN(0, 12),
2321};
2322static const unsigned int msiof2_ss1_d_mux[] = {
2323 MSIOF2_SS1_D_MARK,
2324};
2325static const unsigned int msiof2_ss2_d_pins[] = {
2326 /* SS2 */
2327 RCAR_GP_PIN(0, 13),
2328};
2329static const unsigned int msiof2_ss2_d_mux[] = {
2330 MSIOF2_SS2_D_MARK,
2331};
2332static const unsigned int msiof2_txd_d_pins[] = {
2333 /* TXD */
2334 RCAR_GP_PIN(0, 11),
2335};
2336static const unsigned int msiof2_txd_d_mux[] = {
2337 MSIOF2_TXD_D_MARK,
2338};
2339static const unsigned int msiof2_rxd_d_pins[] = {
2340 /* RXD */
2341 RCAR_GP_PIN(0, 10),
2342};
2343static const unsigned int msiof2_rxd_d_mux[] = {
2344 MSIOF2_RXD_D_MARK,
2345};
2346/* - MSIOF3 ----------------------------------------------------------------- */
2347static const unsigned int msiof3_clk_a_pins[] = {
2348 /* SCK */
2349 RCAR_GP_PIN(0, 0),
2350};
2351static const unsigned int msiof3_clk_a_mux[] = {
2352 MSIOF3_SCK_A_MARK,
2353};
2354static const unsigned int msiof3_sync_a_pins[] = {
2355 /* SYNC */
2356 RCAR_GP_PIN(0, 1),
2357};
2358static const unsigned int msiof3_sync_a_mux[] = {
2359 MSIOF3_SYNC_A_MARK,
2360};
2361static const unsigned int msiof3_ss1_a_pins[] = {
2362 /* SS1 */
2363 RCAR_GP_PIN(0, 14),
2364};
2365static const unsigned int msiof3_ss1_a_mux[] = {
2366 MSIOF3_SS1_A_MARK,
2367};
2368static const unsigned int msiof3_ss2_a_pins[] = {
2369 /* SS2 */
2370 RCAR_GP_PIN(0, 15),
2371};
2372static const unsigned int msiof3_ss2_a_mux[] = {
2373 MSIOF3_SS2_A_MARK,
2374};
2375static const unsigned int msiof3_txd_a_pins[] = {
2376 /* TXD */
2377 RCAR_GP_PIN(0, 3),
2378};
2379static const unsigned int msiof3_txd_a_mux[] = {
2380 MSIOF3_TXD_A_MARK,
2381};
2382static const unsigned int msiof3_rxd_a_pins[] = {
2383 /* RXD */
2384 RCAR_GP_PIN(0, 2),
2385};
2386static const unsigned int msiof3_rxd_a_mux[] = {
2387 MSIOF3_RXD_A_MARK,
2388};
2389static const unsigned int msiof3_clk_b_pins[] = {
2390 /* SCK */
2391 RCAR_GP_PIN(1, 2),
2392};
2393static const unsigned int msiof3_clk_b_mux[] = {
2394 MSIOF3_SCK_B_MARK,
2395};
2396static const unsigned int msiof3_sync_b_pins[] = {
2397 /* SYNC */
2398 RCAR_GP_PIN(1, 0),
2399};
2400static const unsigned int msiof3_sync_b_mux[] = {
2401 MSIOF3_SYNC_B_MARK,
2402};
2403static const unsigned int msiof3_ss1_b_pins[] = {
2404 /* SS1 */
2405 RCAR_GP_PIN(1, 4),
2406};
2407static const unsigned int msiof3_ss1_b_mux[] = {
2408 MSIOF3_SS1_B_MARK,
2409};
2410static const unsigned int msiof3_ss2_b_pins[] = {
2411 /* SS2 */
2412 RCAR_GP_PIN(1, 5),
2413};
2414static const unsigned int msiof3_ss2_b_mux[] = {
2415 MSIOF3_SS2_B_MARK,
2416};
2417static const unsigned int msiof3_txd_b_pins[] = {
2418 /* TXD */
2419 RCAR_GP_PIN(1, 1),
2420};
2421static const unsigned int msiof3_txd_b_mux[] = {
2422 MSIOF3_TXD_B_MARK,
2423};
2424static const unsigned int msiof3_rxd_b_pins[] = {
2425 /* RXD */
2426 RCAR_GP_PIN(1, 3),
2427};
2428static const unsigned int msiof3_rxd_b_mux[] = {
2429 MSIOF3_RXD_B_MARK,
2430};
2431static const unsigned int msiof3_clk_c_pins[] = {
2432 /* SCK */
2433 RCAR_GP_PIN(1, 12),
2434};
2435static const unsigned int msiof3_clk_c_mux[] = {
2436 MSIOF3_SCK_C_MARK,
2437};
2438static const unsigned int msiof3_sync_c_pins[] = {
2439 /* SYNC */
2440 RCAR_GP_PIN(1, 13),
2441};
2442static const unsigned int msiof3_sync_c_mux[] = {
2443 MSIOF3_SYNC_C_MARK,
2444};
2445static const unsigned int msiof3_txd_c_pins[] = {
2446 /* TXD */
2447 RCAR_GP_PIN(1, 15),
2448};
2449static const unsigned int msiof3_txd_c_mux[] = {
2450 MSIOF3_TXD_C_MARK,
2451};
2452static const unsigned int msiof3_rxd_c_pins[] = {
2453 /* RXD */
2454 RCAR_GP_PIN(1, 14),
2455};
2456static const unsigned int msiof3_rxd_c_mux[] = {
2457 MSIOF3_RXD_C_MARK,
2458};
2459static const unsigned int msiof3_clk_d_pins[] = {
2460 /* SCK */
2461 RCAR_GP_PIN(1, 22),
2462};
2463static const unsigned int msiof3_clk_d_mux[] = {
2464 MSIOF3_SCK_D_MARK,
2465};
2466static const unsigned int msiof3_sync_d_pins[] = {
2467 /* SYNC */
2468 RCAR_GP_PIN(1, 23),
2469};
2470static const unsigned int msiof3_sync_d_mux[] = {
2471 MSIOF3_SYNC_D_MARK,
2472};
2473static const unsigned int msiof3_ss1_d_pins[] = {
2474 /* SS1 */
2475 RCAR_GP_PIN(1, 26),
2476};
2477static const unsigned int msiof3_ss1_d_mux[] = {
2478 MSIOF3_SS1_D_MARK,
2479};
2480static const unsigned int msiof3_txd_d_pins[] = {
2481 /* TXD */
2482 RCAR_GP_PIN(1, 25),
2483};
2484static const unsigned int msiof3_txd_d_mux[] = {
2485 MSIOF3_TXD_D_MARK,
2486};
2487static const unsigned int msiof3_rxd_d_pins[] = {
2488 /* RXD */
2489 RCAR_GP_PIN(1, 24),
2490};
2491static const unsigned int msiof3_rxd_d_mux[] = {
2492 MSIOF3_RXD_D_MARK,
2493};
2494
34dc4e16
TK		 2495/* - SATA --------------------------------------------------------------------*/
2496static const unsigned int sata0_devslp_a_pins[] = {
2497 /* DEVSLP */
2498 RCAR_GP_PIN(6, 16),
2499};
2500static const unsigned int sata0_devslp_a_mux[] = {
2501 SATA_DEVSLP_A_MARK,
2502};
2503static const unsigned int sata0_devslp_b_pins[] = {
2504 /* DEVSLP */
2505 RCAR_GP_PIN(4, 6),
2506};
2507static const unsigned int sata0_devslp_b_mux[] = {
2508 SATA_DEVSLP_B_MARK,
2509};
2510
ff8459a5
GU		 2511/* - SCIF0 ------------------------------------------------------------------ */
2512static const unsigned int scif0_data_pins[] = {
2513 /* RX, TX */
2514 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2515};
2516static const unsigned int scif0_data_mux[] = {
2517 RX0_MARK, TX0_MARK,
2518};
2519static const unsigned int scif0_clk_pins[] = {
2520 /* SCK */
2521 RCAR_GP_PIN(5, 0),
2522};
2523static const unsigned int scif0_clk_mux[] = {
2524 SCK0_MARK,
2525};
2526static const unsigned int scif0_ctrl_pins[] = {
2527 /* RTS, CTS */
2528 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2529};
2530static const unsigned int scif0_ctrl_mux[] = {
2531 RTS0_N_TANS_MARK, CTS0_N_MARK,
2532};
2533/* - SCIF1 ------------------------------------------------------------------ */
2534static const unsigned int scif1_data_a_pins[] = {
2535 /* RX, TX */
2536 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2537};
2538static const unsigned int scif1_data_a_mux[] = {
2539 RX1_A_MARK, TX1_A_MARK,
2540};
2541static const unsigned int scif1_clk_pins[] = {
2542 /* SCK */
2543 RCAR_GP_PIN(6, 21),
2544};
2545static const unsigned int scif1_clk_mux[] = {
2546 SCK1_MARK,
2547};
2548static const unsigned int scif1_ctrl_pins[] = {
2549 /* RTS, CTS */
2550 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2551};
2552static const unsigned int scif1_ctrl_mux[] = {
2553 RTS1_N_TANS_MARK, CTS1_N_MARK,
2554};
2555
2556static const unsigned int scif1_data_b_pins[] = {
2557 /* RX, TX */
2558 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2559};
2560static const unsigned int scif1_data_b_mux[] = {
2561 RX1_B_MARK, TX1_B_MARK,
2562};
2563/* - SCIF2 ------------------------------------------------------------------ */
2564static const unsigned int scif2_data_a_pins[] = {
2565 /* RX, TX */
2566 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2567};
2568static const unsigned int scif2_data_a_mux[] = {
2569 RX2_A_MARK, TX2_A_MARK,
2570};
2571static const unsigned int scif2_clk_pins[] = {
2572 /* SCK */
2573 RCAR_GP_PIN(5, 9),
2574};
2575static const unsigned int scif2_clk_mux[] = {
2576 SCK2_MARK,
2577};
2578static const unsigned int scif2_data_b_pins[] = {
2579 /* RX, TX */
2580 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2581};
2582static const unsigned int scif2_data_b_mux[] = {
2583 RX2_B_MARK, TX2_B_MARK,
2584};
2585/* - SCIF3 ------------------------------------------------------------------ */
2586static const unsigned int scif3_data_a_pins[] = {
2587 /* RX, TX */
2588 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2589};
2590static const unsigned int scif3_data_a_mux[] = {
2591 RX3_A_MARK, TX3_A_MARK,
2592};
2593static const unsigned int scif3_clk_pins[] = {
2594 /* SCK */
2595 RCAR_GP_PIN(1, 22),
2596};
2597static const unsigned int scif3_clk_mux[] = {
2598 SCK3_MARK,
2599};
2600static const unsigned int scif3_ctrl_pins[] = {
2601 /* RTS, CTS */
2602 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2603};
2604static const unsigned int scif3_ctrl_mux[] = {
2605 RTS3_N_TANS_MARK, CTS3_N_MARK,
2606};
2607static const unsigned int scif3_data_b_pins[] = {
2608 /* RX, TX */
2609 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2610};
2611static const unsigned int scif3_data_b_mux[] = {
2612 RX3_B_MARK, TX3_B_MARK,
2613};
2614/* - SCIF4 ------------------------------------------------------------------ */
2615static const unsigned int scif4_data_a_pins[] = {
2616 /* RX, TX */
2617 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2618};
2619static const unsigned int scif4_data_a_mux[] = {
2620 RX4_A_MARK, TX4_A_MARK,
2621};
2622static const unsigned int scif4_clk_a_pins[] = {
2623 /* SCK */
2624 RCAR_GP_PIN(2, 10),
2625};
2626static const unsigned int scif4_clk_a_mux[] = {
2627 SCK4_A_MARK,
2628};
2629static const unsigned int scif4_ctrl_a_pins[] = {
2630 /* RTS, CTS */
2631 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2632};
2633static const unsigned int scif4_ctrl_a_mux[] = {
2634 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2635};
2636static const unsigned int scif4_data_b_pins[] = {
2637 /* RX, TX */
2638 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2639};
2640static const unsigned int scif4_data_b_mux[] = {
2641 RX4_B_MARK, TX4_B_MARK,
2642};
2643static const unsigned int scif4_clk_b_pins[] = {
2644 /* SCK */
2645 RCAR_GP_PIN(1, 5),
2646};
2647static const unsigned int scif4_clk_b_mux[] = {
2648 SCK4_B_MARK,
2649};
2650static const unsigned int scif4_ctrl_b_pins[] = {
2651 /* RTS, CTS */
2652 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2653};
2654static const unsigned int scif4_ctrl_b_mux[] = {
2655 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2656};
2657static const unsigned int scif4_data_c_pins[] = {
2658 /* RX, TX */
2659 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2660};
2661static const unsigned int scif4_data_c_mux[] = {
2662 RX4_C_MARK, TX4_C_MARK,
2663};
2664static const unsigned int scif4_clk_c_pins[] = {
2665 /* SCK */
2666 RCAR_GP_PIN(0, 8),
2667};
2668static const unsigned int scif4_clk_c_mux[] = {
2669 SCK4_C_MARK,
2670};
2671static const unsigned int scif4_ctrl_c_pins[] = {
2672 /* RTS, CTS */
2673 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2674};
2675static const unsigned int scif4_ctrl_c_mux[] = {
2676 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2677};
2678/* - SCIF5 ------------------------------------------------------------------ */
2679static const unsigned int scif5_data_pins[] = {
2680 /* RX, TX */
2681 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2682};
2683static const unsigned int scif5_data_mux[] = {
2684 RX5_MARK, TX5_MARK,
2685};
2686static const unsigned int scif5_clk_pins[] = {
2687 /* SCK */
2688 RCAR_GP_PIN(6, 21),
2689};
2690static const unsigned int scif5_clk_mux[] = {
2691 SCK5_MARK,
2692};
20cacae1
TK		 2693/* - SDHI0 ------------------------------------------------------------------ */
2694static const unsigned int sdhi0_data1_pins[] = {
2695 /* D0 */
2696 RCAR_GP_PIN(3, 2),
2697};
2698static const unsigned int sdhi0_data1_mux[] = {
2699 SD0_DAT0_MARK,
2700};
2701static const unsigned int sdhi0_data4_pins[] = {
2702 /* D[0:3] */
2703 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2704 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2705};
2706static const unsigned int sdhi0_data4_mux[] = {
2707 SD0_DAT0_MARK, SD0_DAT1_MARK,
2708 SD0_DAT2_MARK, SD0_DAT3_MARK,
2709};
2710static const unsigned int sdhi0_ctrl_pins[] = {
2711 /* CLK, CMD */
2712 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2713};
2714static const unsigned int sdhi0_ctrl_mux[] = {
2715 SD0_CLK_MARK, SD0_CMD_MARK,
2716};
2717static const unsigned int sdhi0_cd_pins[] = {
2718 /* CD */
2719 RCAR_GP_PIN(3, 12),
2720};
2721static const unsigned int sdhi0_cd_mux[] = {
2722 SD0_CD_MARK,
2723};
2724static const unsigned int sdhi0_wp_pins[] = {
2725 /* WP */
2726 RCAR_GP_PIN(3, 13),
2727};
2728static const unsigned int sdhi0_wp_mux[] = {
2729 SD0_WP_MARK,
2730};
2731/* - SDHI1 ------------------------------------------------------------------ */
2732static const unsigned int sdhi1_data1_pins[] = {
2733 /* D0 */
2734 RCAR_GP_PIN(3, 8),
2735};
2736static const unsigned int sdhi1_data1_mux[] = {
2737 SD1_DAT0_MARK,
2738};
2739static const unsigned int sdhi1_data4_pins[] = {
2740 /* D[0:3] */
2741 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2742 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2743};
2744static const unsigned int sdhi1_data4_mux[] = {
2745 SD1_DAT0_MARK, SD1_DAT1_MARK,
2746 SD1_DAT2_MARK, SD1_DAT3_MARK,
2747};
2748static const unsigned int sdhi1_ctrl_pins[] = {
2749 /* CLK, CMD */
2750 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2751};
2752static const unsigned int sdhi1_ctrl_mux[] = {
2753 SD1_CLK_MARK, SD1_CMD_MARK,
2754};
2755static const unsigned int sdhi1_cd_pins[] = {
2756 /* CD */
2757 RCAR_GP_PIN(3, 14),
2758};
2759static const unsigned int sdhi1_cd_mux[] = {
2760 SD1_CD_MARK,
2761};
2762static const unsigned int sdhi1_wp_pins[] = {
2763 /* WP */
2764 RCAR_GP_PIN(3, 15),
2765};
2766static const unsigned int sdhi1_wp_mux[] = {
2767 SD1_WP_MARK,
2768};
2769/* - SDHI2 ------------------------------------------------------------------ */
2770static const unsigned int sdhi2_data1_pins[] = {
2771 /* D0 */
2772 RCAR_GP_PIN(4, 2),
2773};
2774static const unsigned int sdhi2_data1_mux[] = {
2775 SD2_DAT0_MARK,
2776};
2777static const unsigned int sdhi2_data4_pins[] = {
2778 /* D[0:3] */
2779 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2780 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2781};
2782static const unsigned int sdhi2_data4_mux[] = {
2783 SD2_DAT0_MARK, SD2_DAT1_MARK,
2784 SD2_DAT2_MARK, SD2_DAT3_MARK,
2785};
2786static const unsigned int sdhi2_data8_pins[] = {
2787 /* D[0:7] */
2788 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2789 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2790 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2791 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2792};
2793static const unsigned int sdhi2_data8_mux[] = {
2794 SD2_DAT0_MARK, SD2_DAT1_MARK,
2795 SD2_DAT2_MARK, SD2_DAT3_MARK,
2796 SD2_DAT4_MARK, SD2_DAT5_MARK,
2797 SD2_DAT6_MARK, SD2_DAT7_MARK,
2798};
2799static const unsigned int sdhi2_ctrl_pins[] = {
2800 /* CLK, CMD */
2801 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2802};
2803static const unsigned int sdhi2_ctrl_mux[] = {
2804 SD2_CLK_MARK, SD2_CMD_MARK,
2805};
2806static const unsigned int sdhi2_cd_a_pins[] = {
2807 /* CD */
2808 RCAR_GP_PIN(4, 13),
2809};
2810static const unsigned int sdhi2_cd_a_mux[] = {
2811 SD2_CD_A_MARK,
2812};
2813static const unsigned int sdhi2_cd_b_pins[] = {
2814 /* CD */
2815 RCAR_GP_PIN(5, 10),
2816};
2817static const unsigned int sdhi2_cd_b_mux[] = {
2818 SD2_CD_B_MARK,
2819};
2820static const unsigned int sdhi2_wp_a_pins[] = {
2821 /* WP */
2822 RCAR_GP_PIN(4, 14),
2823};
2824static const unsigned int sdhi2_wp_a_mux[] = {
2825 SD2_WP_A_MARK,
2826};
2827static const unsigned int sdhi2_wp_b_pins[] = {
2828 /* WP */
2829 RCAR_GP_PIN(5, 11),
2830};
2831static const unsigned int sdhi2_wp_b_mux[] = {
2832 SD2_WP_B_MARK,
2833};
2834static const unsigned int sdhi2_ds_pins[] = {
2835 /* DS */
2836 RCAR_GP_PIN(4, 6),
2837};
2838static const unsigned int sdhi2_ds_mux[] = {
2839 SD2_DS_MARK,
2840};
2841/* - SDHI3 ------------------------------------------------------------------ */
2842static const unsigned int sdhi3_data1_pins[] = {
2843 /* D0 */
2844 RCAR_GP_PIN(4, 9),
2845};
2846static const unsigned int sdhi3_data1_mux[] = {
2847 SD3_DAT0_MARK,
2848};
2849static const unsigned int sdhi3_data4_pins[] = {
2850 /* D[0:3] */
2851 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2852 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2853};
2854static const unsigned int sdhi3_data4_mux[] = {
2855 SD3_DAT0_MARK, SD3_DAT1_MARK,
2856 SD3_DAT2_MARK, SD3_DAT3_MARK,
2857};
2858static const unsigned int sdhi3_data8_pins[] = {
2859 /* D[0:7] */
2860 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2861 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2862 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2863 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2864};
2865static const unsigned int sdhi3_data8_mux[] = {
2866 SD3_DAT0_MARK, SD3_DAT1_MARK,
2867 SD3_DAT2_MARK, SD3_DAT3_MARK,
2868 SD3_DAT4_MARK, SD3_DAT5_MARK,
2869 SD3_DAT6_MARK, SD3_DAT7_MARK,
2870};
2871static const unsigned int sdhi3_ctrl_pins[] = {
2872 /* CLK, CMD */
2873 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2874};
2875static const unsigned int sdhi3_ctrl_mux[] = {
2876 SD3_CLK_MARK, SD3_CMD_MARK,
2877};
2878static const unsigned int sdhi3_cd_pins[] = {
2879 /* CD */
2880 RCAR_GP_PIN(4, 15),
2881};
2882static const unsigned int sdhi3_cd_mux[] = {
2883 SD3_CD_MARK,
2884};
2885static const unsigned int sdhi3_wp_pins[] = {
2886 /* WP */
2887 RCAR_GP_PIN(4, 16),
2888};
2889static const unsigned int sdhi3_wp_mux[] = {
2890 SD3_WP_MARK,
2891};
2892static const unsigned int sdhi3_ds_pins[] = {
2893 /* DS */
2894 RCAR_GP_PIN(4, 17),
2895};
2896static const unsigned int sdhi3_ds_mux[] = {
2897 SD3_DS_MARK,
2898};
ff8459a5 2899
f27200f9
GU		 2900/* - SCIF Clock ------------------------------------------------------------- */
2901static const unsigned int scif_clk_a_pins[] = {
2902 /* SCIF_CLK */
2903 RCAR_GP_PIN(6, 23),
2904};
2905static const unsigned int scif_clk_a_mux[] = {
2906 SCIF_CLK_A_MARK,
2907};
2908static const unsigned int scif_clk_b_pins[] = {
2909 /* SCIF_CLK */
2910 RCAR_GP_PIN(5, 9),
2911};
2912static const unsigned int scif_clk_b_mux[] = {
2913 SCIF_CLK_B_MARK,
2914};
2915
9b132ba3
KM		 2916/* - SSI -------------------------------------------------------------------- */
2917static const unsigned int ssi0_data_pins[] = {
2918 /* SDATA */
2919 RCAR_GP_PIN(6, 2),
2920};
2921static const unsigned int ssi0_data_mux[] = {
2922 SSI_SDATA0_MARK,
2923};
2924static const unsigned int ssi01239_ctrl_pins[] = {
2925 /* SCK, WS */
2926 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2927};
2928static const unsigned int ssi01239_ctrl_mux[] = {
00edf542 2929 SSI_SCK01239_MARK, SSI_WS01239_MARK,
9b132ba3
KM		 2930};
2931static const unsigned int ssi1_data_a_pins[] = {
2932 /* SDATA */
2933 RCAR_GP_PIN(6, 3),
2934};
2935static const unsigned int ssi1_data_a_mux[] = {
2936 SSI_SDATA1_A_MARK,
2937};
2938static const unsigned int ssi1_data_b_pins[] = {
2939 /* SDATA */
2940 RCAR_GP_PIN(5, 12),
2941};
2942static const unsigned int ssi1_data_b_mux[] = {
2943 SSI_SDATA1_B_MARK,
2944};
2945static const unsigned int ssi1_ctrl_a_pins[] = {
2946 /* SCK, WS */
2947 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2948};
2949static const unsigned int ssi1_ctrl_a_mux[] = {
2950 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
2951};
2952static const unsigned int ssi1_ctrl_b_pins[] = {
2953 /* SCK, WS */
2954 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
2955};
2956static const unsigned int ssi1_ctrl_b_mux[] = {
2957 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
2958};
2959static const unsigned int ssi2_data_a_pins[] = {
2960 /* SDATA */
2961 RCAR_GP_PIN(6, 4),
2962};
2963static const unsigned int ssi2_data_a_mux[] = {
2964 SSI_SDATA2_A_MARK,
2965};
2966static const unsigned int ssi2_data_b_pins[] = {
2967 /* SDATA */
2968 RCAR_GP_PIN(5, 13),
2969};
2970static const unsigned int ssi2_data_b_mux[] = {
2971 SSI_SDATA2_B_MARK,
2972};
2973static const unsigned int ssi2_ctrl_a_pins[] = {
2974 /* SCK, WS */
2975 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2976};
2977static const unsigned int ssi2_ctrl_a_mux[] = {
2978 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
2979};
2980static const unsigned int ssi2_ctrl_b_pins[] = {
2981 /* SCK, WS */
2982 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2983};
2984static const unsigned int ssi2_ctrl_b_mux[] = {
2985 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
2986};
2987static const unsigned int ssi3_data_pins[] = {
2988 /* SDATA */
2989 RCAR_GP_PIN(6, 7),
2990};
2991static const unsigned int ssi3_data_mux[] = {
2992 SSI_SDATA3_MARK,
2993};
2994static const unsigned int ssi34_ctrl_pins[] = {
2995 /* SCK, WS */
2996 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
2997};
2998static const unsigned int ssi34_ctrl_mux[] = {
2999 SSI_SCK34_MARK, SSI_WS34_MARK,
3000};
3001static const unsigned int ssi4_data_pins[] = {
3002 /* SDATA */
3003 RCAR_GP_PIN(6, 10),
3004};
3005static const unsigned int ssi4_data_mux[] = {
3006 SSI_SDATA4_MARK,
3007};
3008static const unsigned int ssi4_ctrl_pins[] = {
3009 /* SCK, WS */
3010 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3011};
3012static const unsigned int ssi4_ctrl_mux[] = {
3013 SSI_SCK4_MARK, SSI_WS4_MARK,
3014};
3015static const unsigned int ssi5_data_pins[] = {
3016 /* SDATA */
3017 RCAR_GP_PIN(6, 13),
3018};
3019static const unsigned int ssi5_data_mux[] = {
3020 SSI_SDATA5_MARK,
3021};
3022static const unsigned int ssi5_ctrl_pins[] = {
3023 /* SCK, WS */
3024 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3025};
3026static const unsigned int ssi5_ctrl_mux[] = {
3027 SSI_SCK5_MARK, SSI_WS5_MARK,
3028};
3029static const unsigned int ssi6_data_pins[] = {
3030 /* SDATA */
3031 RCAR_GP_PIN(6, 16),
3032};
3033static const unsigned int ssi6_data_mux[] = {
3034 SSI_SDATA6_MARK,
3035};
3036static const unsigned int ssi6_ctrl_pins[] = {
3037 /* SCK, WS */
3038 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3039};
3040static const unsigned int ssi6_ctrl_mux[] = {
3041 SSI_SCK6_MARK, SSI_WS6_MARK,
3042};
3043static const unsigned int ssi7_data_pins[] = {
3044 /* SDATA */
3045 RCAR_GP_PIN(6, 19),
3046};
3047static const unsigned int ssi7_data_mux[] = {
3048 SSI_SDATA7_MARK,
3049};
3050static const unsigned int ssi78_ctrl_pins[] = {
3051 /* SCK, WS */
3052 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3053};
3054static const unsigned int ssi78_ctrl_mux[] = {
3055 SSI_SCK78_MARK, SSI_WS78_MARK,
3056};
3057static const unsigned int ssi8_data_pins[] = {
3058 /* SDATA */
3059 RCAR_GP_PIN(6, 20),
3060};
3061static const unsigned int ssi8_data_mux[] = {
3062 SSI_SDATA8_MARK,
3063};
3064static const unsigned int ssi9_data_a_pins[] = {
3065 /* SDATA */
3066 RCAR_GP_PIN(6, 21),
3067};
3068static const unsigned int ssi9_data_a_mux[] = {
3069 SSI_SDATA9_A_MARK,
3070};
3071static const unsigned int ssi9_data_b_pins[] = {
3072 /* SDATA */
3073 RCAR_GP_PIN(5, 14),
3074};
3075static const unsigned int ssi9_data_b_mux[] = {
3076 SSI_SDATA9_B_MARK,
3077};
3078static const unsigned int ssi9_ctrl_a_pins[] = {
3079 /* SCK, WS */
3080 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3081};
3082static const unsigned int ssi9_ctrl_a_mux[] = {
3083 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3084};
3085static const unsigned int ssi9_ctrl_b_pins[] = {
3086 /* SCK, WS */
3087 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3088};
3089static const unsigned int ssi9_ctrl_b_mux[] = {
3090 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3091};
3092
0b0ffc96 3093static const struct sh_pfc_pin_group pinmux_groups[] = {
c33a7fe3
KM		 3094 SH_PFC_PIN_GROUP(audio_clk_a_a),
3095 SH_PFC_PIN_GROUP(audio_clk_a_b),
3096 SH_PFC_PIN_GROUP(audio_clk_a_c),
3097 SH_PFC_PIN_GROUP(audio_clk_b_a),
3098 SH_PFC_PIN_GROUP(audio_clk_b_b),
3099 SH_PFC_PIN_GROUP(audio_clk_c_a),
3100 SH_PFC_PIN_GROUP(audio_clk_c_b),
3101 SH_PFC_PIN_GROUP(audio_clkout_a),
3102 SH_PFC_PIN_GROUP(audio_clkout_b),
3103 SH_PFC_PIN_GROUP(audio_clkout_c),
3104 SH_PFC_PIN_GROUP(audio_clkout_d),
3105 SH_PFC_PIN_GROUP(audio_clkout1_a),
3106 SH_PFC_PIN_GROUP(audio_clkout1_b),
3107 SH_PFC_PIN_GROUP(audio_clkout2_a),
3108 SH_PFC_PIN_GROUP(audio_clkout2_b),
3109 SH_PFC_PIN_GROUP(audio_clkout3_a),
3110 SH_PFC_PIN_GROUP(audio_clkout3_b),
819fd4bf
TK		 3111 SH_PFC_PIN_GROUP(avb_link),
3112 SH_PFC_PIN_GROUP(avb_magic),
3113 SH_PFC_PIN_GROUP(avb_phy_int),
3114 SH_PFC_PIN_GROUP(avb_mdc),
3115 SH_PFC_PIN_GROUP(avb_avtp_pps),
3116 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3117 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3118 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3119 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a56069c4
GU		 3120 SH_PFC_PIN_GROUP(hscif0_data),
3121 SH_PFC_PIN_GROUP(hscif0_clk),
3122 SH_PFC_PIN_GROUP(hscif0_ctrl),
3123 SH_PFC_PIN_GROUP(hscif1_data_a),
3124 SH_PFC_PIN_GROUP(hscif1_clk_a),
3125 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3126 SH_PFC_PIN_GROUP(hscif1_data_b),
3127 SH_PFC_PIN_GROUP(hscif1_clk_b),
3128 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3129 SH_PFC_PIN_GROUP(hscif2_data_a),
3130 SH_PFC_PIN_GROUP(hscif2_clk_a),
3131 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3132 SH_PFC_PIN_GROUP(hscif2_data_b),
3133 SH_PFC_PIN_GROUP(hscif2_clk_b),
3134 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3135 SH_PFC_PIN_GROUP(hscif3_data_a),
3136 SH_PFC_PIN_GROUP(hscif3_clk),
3137 SH_PFC_PIN_GROUP(hscif3_ctrl),
3138 SH_PFC_PIN_GROUP(hscif3_data_b),
3139 SH_PFC_PIN_GROUP(hscif3_data_c),
3140 SH_PFC_PIN_GROUP(hscif3_data_d),
3141 SH_PFC_PIN_GROUP(hscif4_data_a),
3142 SH_PFC_PIN_GROUP(hscif4_clk),
3143 SH_PFC_PIN_GROUP(hscif4_ctrl),
3144 SH_PFC_PIN_GROUP(hscif4_data_b),
2544ef72
KM		 3145 SH_PFC_PIN_GROUP(i2c1_a),
3146 SH_PFC_PIN_GROUP(i2c1_b),
3147 SH_PFC_PIN_GROUP(i2c2_a),
3148 SH_PFC_PIN_GROUP(i2c2_b),
3149 SH_PFC_PIN_GROUP(i2c6_a),
3150 SH_PFC_PIN_GROUP(i2c6_b),
3151 SH_PFC_PIN_GROUP(i2c6_c),
e7419b81
GU		 3152 SH_PFC_PIN_GROUP(msiof0_clk),
3153 SH_PFC_PIN_GROUP(msiof0_sync),
3154 SH_PFC_PIN_GROUP(msiof0_ss1),
3155 SH_PFC_PIN_GROUP(msiof0_ss2),
3156 SH_PFC_PIN_GROUP(msiof0_txd),
3157 SH_PFC_PIN_GROUP(msiof0_rxd),
3158 SH_PFC_PIN_GROUP(msiof1_clk_a),
3159 SH_PFC_PIN_GROUP(msiof1_sync_a),
3160 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3161 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3162 SH_PFC_PIN_GROUP(msiof1_txd_a),
3163 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3164 SH_PFC_PIN_GROUP(msiof1_clk_b),
3165 SH_PFC_PIN_GROUP(msiof1_sync_b),
3166 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3167 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3168 SH_PFC_PIN_GROUP(msiof1_txd_b),
3169 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3170 SH_PFC_PIN_GROUP(msiof1_clk_c),
3171 SH_PFC_PIN_GROUP(msiof1_sync_c),
3172 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3173 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3174 SH_PFC_PIN_GROUP(msiof1_txd_c),
3175 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3176 SH_PFC_PIN_GROUP(msiof1_clk_d),
3177 SH_PFC_PIN_GROUP(msiof1_sync_d),
3178 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3179 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3180 SH_PFC_PIN_GROUP(msiof1_txd_d),
3181 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3182 SH_PFC_PIN_GROUP(msiof1_clk_e),
3183 SH_PFC_PIN_GROUP(msiof1_sync_e),
3184 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3185 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3186 SH_PFC_PIN_GROUP(msiof1_txd_e),
3187 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3188 SH_PFC_PIN_GROUP(msiof1_clk_f),
3189 SH_PFC_PIN_GROUP(msiof1_sync_f),
3190 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3191 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3192 SH_PFC_PIN_GROUP(msiof1_txd_f),
3193 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3194 SH_PFC_PIN_GROUP(msiof1_clk_g),
3195 SH_PFC_PIN_GROUP(msiof1_sync_g),
3196 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3197 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3198 SH_PFC_PIN_GROUP(msiof1_txd_g),
3199 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3200 SH_PFC_PIN_GROUP(msiof2_clk_a),
3201 SH_PFC_PIN_GROUP(msiof2_sync_a),
3202 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3203 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3204 SH_PFC_PIN_GROUP(msiof2_txd_a),
3205 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3206 SH_PFC_PIN_GROUP(msiof2_clk_b),
3207 SH_PFC_PIN_GROUP(msiof2_sync_b),
3208 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3209 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3210 SH_PFC_PIN_GROUP(msiof2_txd_b),
3211 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3212 SH_PFC_PIN_GROUP(msiof2_clk_c),
3213 SH_PFC_PIN_GROUP(msiof2_sync_c),
3214 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3215 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3216 SH_PFC_PIN_GROUP(msiof2_txd_c),
3217 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3218 SH_PFC_PIN_GROUP(msiof2_clk_d),
3219 SH_PFC_PIN_GROUP(msiof2_sync_d),
3220 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3221 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3222 SH_PFC_PIN_GROUP(msiof2_txd_d),
3223 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3224 SH_PFC_PIN_GROUP(msiof3_clk_a),
3225 SH_PFC_PIN_GROUP(msiof3_sync_a),
3226 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3227 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3228 SH_PFC_PIN_GROUP(msiof3_txd_a),
3229 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3230 SH_PFC_PIN_GROUP(msiof3_clk_b),
3231 SH_PFC_PIN_GROUP(msiof3_sync_b),
3232 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3233 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3234 SH_PFC_PIN_GROUP(msiof3_txd_b),
3235 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3236 SH_PFC_PIN_GROUP(msiof3_clk_c),
3237 SH_PFC_PIN_GROUP(msiof3_sync_c),
3238 SH_PFC_PIN_GROUP(msiof3_txd_c),
3239 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3240 SH_PFC_PIN_GROUP(msiof3_clk_d),
3241 SH_PFC_PIN_GROUP(msiof3_sync_d),
3242 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3243 SH_PFC_PIN_GROUP(msiof3_txd_d),
3244 SH_PFC_PIN_GROUP(msiof3_rxd_d),
34dc4e16
TK		 3245 SH_PFC_PIN_GROUP(sata0_devslp_a),
3246 SH_PFC_PIN_GROUP(sata0_devslp_b),
ff8459a5
GU		 3247 SH_PFC_PIN_GROUP(scif0_data),
3248 SH_PFC_PIN_GROUP(scif0_clk),
3249 SH_PFC_PIN_GROUP(scif0_ctrl),
3250 SH_PFC_PIN_GROUP(scif1_data_a),
3251 SH_PFC_PIN_GROUP(scif1_clk),
3252 SH_PFC_PIN_GROUP(scif1_ctrl),
3253 SH_PFC_PIN_GROUP(scif1_data_b),
3254 SH_PFC_PIN_GROUP(scif2_data_a),
3255 SH_PFC_PIN_GROUP(scif2_clk),
3256 SH_PFC_PIN_GROUP(scif2_data_b),
3257 SH_PFC_PIN_GROUP(scif3_data_a),
3258 SH_PFC_PIN_GROUP(scif3_clk),
3259 SH_PFC_PIN_GROUP(scif3_ctrl),
3260 SH_PFC_PIN_GROUP(scif3_data_b),
3261 SH_PFC_PIN_GROUP(scif4_data_a),
3262 SH_PFC_PIN_GROUP(scif4_clk_a),
3263 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3264 SH_PFC_PIN_GROUP(scif4_data_b),
3265 SH_PFC_PIN_GROUP(scif4_clk_b),
3266 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3267 SH_PFC_PIN_GROUP(scif4_data_c),
3268 SH_PFC_PIN_GROUP(scif4_clk_c),
3269 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3270 SH_PFC_PIN_GROUP(scif5_data),
3271 SH_PFC_PIN_GROUP(scif5_clk),
f27200f9
GU		 3272 SH_PFC_PIN_GROUP(scif_clk_a),
3273 SH_PFC_PIN_GROUP(scif_clk_b),
20cacae1
TK		 3274 SH_PFC_PIN_GROUP(sdhi0_data1),
3275 SH_PFC_PIN_GROUP(sdhi0_data4),
3276 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3277 SH_PFC_PIN_GROUP(sdhi0_cd),
3278 SH_PFC_PIN_GROUP(sdhi0_wp),
3279 SH_PFC_PIN_GROUP(sdhi1_data1),
3280 SH_PFC_PIN_GROUP(sdhi1_data4),
3281 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3282 SH_PFC_PIN_GROUP(sdhi1_cd),
3283 SH_PFC_PIN_GROUP(sdhi1_wp),
3284 SH_PFC_PIN_GROUP(sdhi2_data1),
3285 SH_PFC_PIN_GROUP(sdhi2_data4),
3286 SH_PFC_PIN_GROUP(sdhi2_data8),
3287 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3288 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3289 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3290 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3291 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3292 SH_PFC_PIN_GROUP(sdhi2_ds),
3293 SH_PFC_PIN_GROUP(sdhi3_data1),
3294 SH_PFC_PIN_GROUP(sdhi3_data4),
3295 SH_PFC_PIN_GROUP(sdhi3_data8),
3296 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3297 SH_PFC_PIN_GROUP(sdhi3_cd),
3298 SH_PFC_PIN_GROUP(sdhi3_wp),
3299 SH_PFC_PIN_GROUP(sdhi3_ds),
9b132ba3
KM		 3300 SH_PFC_PIN_GROUP(ssi0_data),
3301 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3302 SH_PFC_PIN_GROUP(ssi1_data_a),
3303 SH_PFC_PIN_GROUP(ssi1_data_b),
3304 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3305 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3306 SH_PFC_PIN_GROUP(ssi2_data_a),
3307 SH_PFC_PIN_GROUP(ssi2_data_b),
3308 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3309 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3310 SH_PFC_PIN_GROUP(ssi3_data),
3311 SH_PFC_PIN_GROUP(ssi34_ctrl),
3312 SH_PFC_PIN_GROUP(ssi4_data),
3313 SH_PFC_PIN_GROUP(ssi4_ctrl),
3314 SH_PFC_PIN_GROUP(ssi5_data),
3315 SH_PFC_PIN_GROUP(ssi5_ctrl),
3316 SH_PFC_PIN_GROUP(ssi6_data),
3317 SH_PFC_PIN_GROUP(ssi6_ctrl),
3318 SH_PFC_PIN_GROUP(ssi7_data),
3319 SH_PFC_PIN_GROUP(ssi78_ctrl),
3320 SH_PFC_PIN_GROUP(ssi8_data),
3321 SH_PFC_PIN_GROUP(ssi9_data_a),
3322 SH_PFC_PIN_GROUP(ssi9_data_b),
3323 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3324 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
ff8459a5
GU		 3325};
3326
c33a7fe3
KM		 3327static const char * const audio_clk_groups[] = {
3328 "audio_clk_a_a",
3329 "audio_clk_a_b",
3330 "audio_clk_a_c",
3331 "audio_clk_b_a",
3332 "audio_clk_b_b",
3333 "audio_clk_c_a",
3334 "audio_clk_c_b",
3335 "audio_clkout_a",
3336 "audio_clkout_b",
3337 "audio_clkout_c",
3338 "audio_clkout_d",
3339 "audio_clkout1_a",
3340 "audio_clkout1_b",
3341 "audio_clkout2_a",
3342 "audio_clkout2_b",
3343 "audio_clkout3_a",
3344 "audio_clkout3_b",
3345};
3346
819fd4bf
TK		 3347static const char * const avb_groups[] = {
3348 "avb_link",
3349 "avb_magic",
3350 "avb_phy_int",
3351 "avb_mdc",
3352 "avb_avtp_pps",
3353 "avb_avtp_match_a",
3354 "avb_avtp_capture_a",
3355 "avb_avtp_match_b",
3356 "avb_avtp_capture_b",
3357};
3358
a56069c4
GU		 3359static const char * const hscif0_groups[] = {
3360 "hscif0_data",
3361 "hscif0_clk",
3362 "hscif0_ctrl",
3363};
3364
3365static const char * const hscif1_groups[] = {
3366 "hscif1_data_a",
3367 "hscif1_clk_a",
3368 "hscif1_ctrl_a",
3369 "hscif1_data_b",
3370 "hscif1_clk_b",
3371 "hscif1_ctrl_b",
3372};
3373
3374static const char * const hscif2_groups[] = {
3375 "hscif2_data_a",
3376 "hscif2_clk_a",
3377 "hscif2_ctrl_a",
3378 "hscif2_data_b",
3379 "hscif2_clk_b",
3380 "hscif2_ctrl_b",
3381};
3382
3383static const char * const hscif3_groups[] = {
3384 "hscif3_data_a",
3385 "hscif3_clk",
3386 "hscif3_ctrl",
3387 "hscif3_data_b",
3388 "hscif3_data_c",
3389 "hscif3_data_d",
3390};
3391
3392static const char * const hscif4_groups[] = {
3393 "hscif4_data_a",
3394 "hscif4_clk",
3395 "hscif4_ctrl",
3396 "hscif4_data_b",
3397};
3398
2544ef72
KM		 3399static const char * const i2c1_groups[] = {
3400 "i2c1_a",
3401 "i2c1_b",
3402};
3403
3404static const char * const i2c2_groups[] = {
3405 "i2c2_a",
3406 "i2c2_b",
3407};
3408
3409static const char * const i2c6_groups[] = {
3410 "i2c6_a",
3411 "i2c6_b",
3412 "i2c6_c",
3413};
3414
e7419b81
GU		 3415static const char * const msiof0_groups[] = {
3416 "msiof0_clk",
3417 "msiof0_sync",
3418 "msiof0_ss1",
3419 "msiof0_ss2",
3420 "msiof0_txd",
3421 "msiof0_rxd",
3422};
3423
3424static const char * const msiof1_groups[] = {
3425 "msiof1_clk_a",
3426 "msiof1_sync_a",
3427 "msiof1_ss1_a",
3428 "msiof1_ss2_a",
3429 "msiof1_txd_a",
3430 "msiof1_rxd_a",
3431 "msiof1_clk_b",
3432 "msiof1_sync_b",
3433 "msiof1_ss1_b",
3434 "msiof1_ss2_b",
3435 "msiof1_txd_b",
3436 "msiof1_rxd_b",
3437 "msiof1_clk_c",
3438 "msiof1_sync_c",
3439 "msiof1_ss1_c",
3440 "msiof1_ss2_c",
3441 "msiof1_txd_c",
3442 "msiof1_rxd_c",
3443 "msiof1_clk_d",
3444 "msiof1_sync_d",
3445 "msiof1_ss1_d",
3446 "msiof1_ss2_d",
3447 "msiof1_txd_d",
3448 "msiof1_rxd_d",
3449 "msiof1_clk_e",
3450 "msiof1_sync_e",
3451 "msiof1_ss1_e",
3452 "msiof1_ss2_e",
3453 "msiof1_txd_e",
3454 "msiof1_rxd_e",
3455 "msiof1_clk_f",
3456 "msiof1_sync_f",
3457 "msiof1_ss1_f",
3458 "msiof1_ss2_f",
3459 "msiof1_txd_f",
3460 "msiof1_rxd_f",
3461 "msiof1_clk_g",
3462 "msiof1_sync_g",
3463 "msiof1_ss1_g",
3464 "msiof1_ss2_g",
3465 "msiof1_txd_g",
3466 "msiof1_rxd_g",
3467};
3468
3469static const char * const msiof2_groups[] = {
3470 "msiof2_clk_a",
3471 "msiof2_sync_a",
3472 "msiof2_ss1_a",
3473 "msiof2_ss2_a",
3474 "msiof2_txd_a",
3475 "msiof2_rxd_a",
3476 "msiof2_clk_b",
3477 "msiof2_sync_b",
3478 "msiof2_ss1_b",
3479 "msiof2_ss2_b",
3480 "msiof2_txd_b",
3481 "msiof2_rxd_b",
3482 "msiof2_clk_c",
3483 "msiof2_sync_c",
3484 "msiof2_ss1_c",
3485 "msiof2_ss2_c",
3486 "msiof2_txd_c",
3487 "msiof2_rxd_c",
3488 "msiof2_clk_d",
3489 "msiof2_sync_d",
3490 "msiof2_ss1_d",
3491 "msiof2_ss2_d",
3492 "msiof2_txd_d",
3493 "msiof2_rxd_d",
3494};
3495
3496static const char * const msiof3_groups[] = {
3497 "msiof3_clk_a",
3498 "msiof3_sync_a",
3499 "msiof3_ss1_a",
3500 "msiof3_ss2_a",
3501 "msiof3_txd_a",
3502 "msiof3_rxd_a",
3503 "msiof3_clk_b",
3504 "msiof3_sync_b",
3505 "msiof3_ss1_b",
3506 "msiof3_ss2_b",
3507 "msiof3_txd_b",
3508 "msiof3_rxd_b",
3509 "msiof3_clk_c",
3510 "msiof3_sync_c",
3511 "msiof3_txd_c",
3512 "msiof3_rxd_c",
3513 "msiof3_clk_d",
3514 "msiof3_sync_d",
3515 "msiof3_ss1_d",
3516 "msiof3_txd_d",
3517 "msiof3_rxd_d",
3518};
3519
34dc4e16
TK		 3520static const char * const sata0_groups[] = {
3521 "sata0_devslp_a",
3522 "sata0_devslp_b",
3523};
3524
ff8459a5
GU		 3525static const char * const scif0_groups[] = {
3526 "scif0_data",
3527 "scif0_clk",
3528 "scif0_ctrl",
3529};
3530
3531static const char * const scif1_groups[] = {
3532 "scif1_data_a",
3533 "scif1_clk",
3534 "scif1_ctrl",
3535 "scif1_data_b",
3536};
3537
3538static const char * const scif2_groups[] = {
3539 "scif2_data_a",
3540 "scif2_clk",
3541 "scif2_data_b",
3542};
3543
3544static const char * const scif3_groups[] = {
3545 "scif3_data_a",
3546 "scif3_clk",
3547 "scif3_ctrl",
3548 "scif3_data_b",
3549};
3550
3551static const char * const scif4_groups[] = {
3552 "scif4_data_a",
3553 "scif4_clk_a",
3554 "scif4_ctrl_a",
3555 "scif4_data_b",
3556 "scif4_clk_b",
3557 "scif4_ctrl_b",
3558 "scif4_data_c",
3559 "scif4_clk_c",
3560 "scif4_ctrl_c",
3561};
3562
3563static const char * const scif5_groups[] = {
3564 "scif5_data",
3565 "scif5_clk",
0b0ffc96
TK		 3566};
3567
f27200f9
GU		 3568static const char * const scif_clk_groups[] = {
3569 "scif_clk_a",
3570 "scif_clk_b",
3571};
3572
20cacae1
TK		 3573static const char * const sdhi0_groups[] = {
3574 "sdhi0_data1",
3575 "sdhi0_data4",
3576 "sdhi0_ctrl",
3577 "sdhi0_cd",
3578 "sdhi0_wp",
3579};
3580
3581static const char * const sdhi1_groups[] = {
3582 "sdhi1_data1",
3583 "sdhi1_data4",
3584 "sdhi1_ctrl",
3585 "sdhi1_cd",
3586 "sdhi1_wp",
3587};
3588
3589static const char * const sdhi2_groups[] = {
3590 "sdhi2_data1",
3591 "sdhi2_data4",
3592 "sdhi2_data8",
3593 "sdhi2_ctrl",
3594 "sdhi2_cd_a",
3595 "sdhi2_wp_a",
3596 "sdhi2_cd_b",
3597 "sdhi2_wp_b",
3598 "sdhi2_ds",
3599};
3600
3601static const char * const sdhi3_groups[] = {
3602 "sdhi3_data1",
3603 "sdhi3_data4",
3604 "sdhi3_data8",
3605 "sdhi3_ctrl",
3606 "sdhi3_cd",
3607 "sdhi3_wp",
3608 "sdhi3_ds",
3609};
3610
9b132ba3
KM		 3611static const char * const ssi_groups[] = {
3612 "ssi0_data",
3613 "ssi01239_ctrl",
3614 "ssi1_data_a",
3615 "ssi1_data_b",
3616 "ssi1_ctrl_a",
3617 "ssi1_ctrl_b",
3618 "ssi2_data_a",
3619 "ssi2_data_b",
3620 "ssi2_ctrl_a",
3621 "ssi2_ctrl_b",
3622 "ssi3_data",
3623 "ssi34_ctrl",
3624 "ssi4_data",
3625 "ssi4_ctrl",
3626 "ssi5_data",
3627 "ssi5_ctrl",
3628 "ssi6_data",
3629 "ssi6_ctrl",
3630 "ssi7_data",
3631 "ssi78_ctrl",
3632 "ssi8_data",
3633 "ssi9_data_a",
3634 "ssi9_data_b",
3635 "ssi9_ctrl_a",
3636 "ssi9_ctrl_b",
3637};
3638
0b0ffc96 3639static const struct sh_pfc_function pinmux_functions[] = {
c33a7fe3 3640 SH_PFC_FUNCTION(audio_clk),
819fd4bf 3641 SH_PFC_FUNCTION(avb),
a56069c4
GU		 3642 SH_PFC_FUNCTION(hscif0),
3643 SH_PFC_FUNCTION(hscif1),
3644 SH_PFC_FUNCTION(hscif2),
3645 SH_PFC_FUNCTION(hscif3),
3646 SH_PFC_FUNCTION(hscif4),
2544ef72
KM		 3647 SH_PFC_FUNCTION(i2c1),
3648 SH_PFC_FUNCTION(i2c2),
3649 SH_PFC_FUNCTION(i2c6),
e7419b81
GU		 3650 SH_PFC_FUNCTION(msiof0),
3651 SH_PFC_FUNCTION(msiof1),
3652 SH_PFC_FUNCTION(msiof2),
3653 SH_PFC_FUNCTION(msiof3),
34dc4e16 3654 SH_PFC_FUNCTION(sata0),
ff8459a5
GU		 3655 SH_PFC_FUNCTION(scif0),
3656 SH_PFC_FUNCTION(scif1),
3657 SH_PFC_FUNCTION(scif2),
3658 SH_PFC_FUNCTION(scif3),
3659 SH_PFC_FUNCTION(scif4),
3660 SH_PFC_FUNCTION(scif5),
f27200f9 3661 SH_PFC_FUNCTION(scif_clk),
20cacae1
TK		 3662 SH_PFC_FUNCTION(sdhi0),
3663 SH_PFC_FUNCTION(sdhi1),
3664 SH_PFC_FUNCTION(sdhi2),
3665 SH_PFC_FUNCTION(sdhi3),
9b132ba3 3666 SH_PFC_FUNCTION(ssi),
0b0ffc96
TK		 3667};
3668
3669static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3670#define F_(x, y) FN_##y
3671#define FM(x) FN_##x
3672 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
3673 0, 0,
3674 0, 0,
3675 0, 0,
3676 0, 0,
3677 0, 0,
3678 0, 0,
3679 0, 0,
3680 0, 0,
3681 0, 0,
3682 0, 0,
3683 0, 0,
3684 0, 0,
3685 0, 0,
3686 0, 0,
3687 0, 0,
3688 0, 0,
3689 GP_0_15_FN, GPSR0_15,
3690 GP_0_14_FN, GPSR0_14,
3691 GP_0_13_FN, GPSR0_13,
3692 GP_0_12_FN, GPSR0_12,
3693 GP_0_11_FN, GPSR0_11,
3694 GP_0_10_FN, GPSR0_10,
3695 GP_0_9_FN, GPSR0_9,
3696 GP_0_8_FN, GPSR0_8,
3697 GP_0_7_FN, GPSR0_7,
3698 GP_0_6_FN, GPSR0_6,
3699 GP_0_5_FN, GPSR0_5,
3700 GP_0_4_FN, GPSR0_4,
3701 GP_0_3_FN, GPSR0_3,
3702 GP_0_2_FN, GPSR0_2,
3703 GP_0_1_FN, GPSR0_1,
3704 GP_0_0_FN, GPSR0_0, }
3705 },
3706 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
3707 0, 0,
3708 0, 0,
3709 0, 0,
3710 0, 0,
3711 GP_1_27_FN, GPSR1_27,
3712 GP_1_26_FN, GPSR1_26,
3713 GP_1_25_FN, GPSR1_25,
3714 GP_1_24_FN, GPSR1_24,
3715 GP_1_23_FN, GPSR1_23,
3716 GP_1_22_FN, GPSR1_22,
3717 GP_1_21_FN, GPSR1_21,
3718 GP_1_20_FN, GPSR1_20,
3719 GP_1_19_FN, GPSR1_19,
3720 GP_1_18_FN, GPSR1_18,
3721 GP_1_17_FN, GPSR1_17,
3722 GP_1_16_FN, GPSR1_16,
3723 GP_1_15_FN, GPSR1_15,
3724 GP_1_14_FN, GPSR1_14,
3725 GP_1_13_FN, GPSR1_13,
3726 GP_1_12_FN, GPSR1_12,
3727 GP_1_11_FN, GPSR1_11,
3728 GP_1_10_FN, GPSR1_10,
3729 GP_1_9_FN, GPSR1_9,
3730 GP_1_8_FN, GPSR1_8,
3731 GP_1_7_FN, GPSR1_7,
3732 GP_1_6_FN, GPSR1_6,
3733 GP_1_5_FN, GPSR1_5,
3734 GP_1_4_FN, GPSR1_4,
3735 GP_1_3_FN, GPSR1_3,
3736 GP_1_2_FN, GPSR1_2,
3737 GP_1_1_FN, GPSR1_1,
3738 GP_1_0_FN, GPSR1_0, }
3739 },
3740 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
3741 0, 0,
3742 0, 0,
3743 0, 0,
3744 0, 0,
3745 0, 0,
3746 0, 0,
3747 0, 0,
3748 0, 0,
3749 0, 0,
3750 0, 0,
3751 0, 0,
3752 0, 0,
3753 0, 0,
3754 0, 0,
3755 0, 0,
3756 0, 0,
3757 0, 0,
3758 GP_2_14_FN, GPSR2_14,
3759 GP_2_13_FN, GPSR2_13,
3760 GP_2_12_FN, GPSR2_12,
3761 GP_2_11_FN, GPSR2_11,
3762 GP_2_10_FN, GPSR2_10,
3763 GP_2_9_FN, GPSR2_9,
3764 GP_2_8_FN, GPSR2_8,
3765 GP_2_7_FN, GPSR2_7,
3766 GP_2_6_FN, GPSR2_6,
3767 GP_2_5_FN, GPSR2_5,
3768 GP_2_4_FN, GPSR2_4,
3769 GP_2_3_FN, GPSR2_3,
3770 GP_2_2_FN, GPSR2_2,
3771 GP_2_1_FN, GPSR2_1,
3772 GP_2_0_FN, GPSR2_0, }
3773 },
3774 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
3775 0, 0,
3776 0, 0,
3777 0, 0,
3778 0, 0,
3779 0, 0,
3780 0, 0,
3781 0, 0,
3782 0, 0,
3783 0, 0,
3784 0, 0,
3785 0, 0,
3786 0, 0,
3787 0, 0,
3788 0, 0,
3789 0, 0,
3790 0, 0,
3791 GP_3_15_FN, GPSR3_15,
3792 GP_3_14_FN, GPSR3_14,
3793 GP_3_13_FN, GPSR3_13,
3794 GP_3_12_FN, GPSR3_12,
3795 GP_3_11_FN, GPSR3_11,
3796 GP_3_10_FN, GPSR3_10,
3797 GP_3_9_FN, GPSR3_9,
3798 GP_3_8_FN, GPSR3_8,
3799 GP_3_7_FN, GPSR3_7,
3800 GP_3_6_FN, GPSR3_6,
3801 GP_3_5_FN, GPSR3_5,
3802 GP_3_4_FN, GPSR3_4,
3803 GP_3_3_FN, GPSR3_3,
3804 GP_3_2_FN, GPSR3_2,
3805 GP_3_1_FN, GPSR3_1,
3806 GP_3_0_FN, GPSR3_0, }
3807 },
3808 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
3809 0, 0,
3810 0, 0,
3811 0, 0,
3812 0, 0,
3813 0, 0,
3814 0, 0,
3815 0, 0,
3816 0, 0,
3817 0, 0,
3818 0, 0,
3819 0, 0,
3820 0, 0,
3821 0, 0,
3822 0, 0,
3823 GP_4_17_FN, GPSR4_17,
3824 GP_4_16_FN, GPSR4_16,
3825 GP_4_15_FN, GPSR4_15,
3826 GP_4_14_FN, GPSR4_14,
3827 GP_4_13_FN, GPSR4_13,
3828 GP_4_12_FN, GPSR4_12,
3829 GP_4_11_FN, GPSR4_11,
3830 GP_4_10_FN, GPSR4_10,
3831 GP_4_9_FN, GPSR4_9,
3832 GP_4_8_FN, GPSR4_8,
3833 GP_4_7_FN, GPSR4_7,
3834 GP_4_6_FN, GPSR4_6,
3835 GP_4_5_FN, GPSR4_5,
3836 GP_4_4_FN, GPSR4_4,
3837 GP_4_3_FN, GPSR4_3,
3838 GP_4_2_FN, GPSR4_2,
3839 GP_4_1_FN, GPSR4_1,
3840 GP_4_0_FN, GPSR4_0, }
3841 },
3842 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
3843 0, 0,
3844 0, 0,
3845 0, 0,
3846 0, 0,
3847 0, 0,
3848 0, 0,
3849 GP_5_25_FN, GPSR5_25,
3850 GP_5_24_FN, GPSR5_24,
3851 GP_5_23_FN, GPSR5_23,
3852 GP_5_22_FN, GPSR5_22,
3853 GP_5_21_FN, GPSR5_21,
3854 GP_5_20_FN, GPSR5_20,
3855 GP_5_19_FN, GPSR5_19,
3856 GP_5_18_FN, GPSR5_18,
3857 GP_5_17_FN, GPSR5_17,
3858 GP_5_16_FN, GPSR5_16,
3859 GP_5_15_FN, GPSR5_15,
3860 GP_5_14_FN, GPSR5_14,
3861 GP_5_13_FN, GPSR5_13,
3862 GP_5_12_FN, GPSR5_12,
3863 GP_5_11_FN, GPSR5_11,
3864 GP_5_10_FN, GPSR5_10,
3865 GP_5_9_FN, GPSR5_9,
3866 GP_5_8_FN, GPSR5_8,
3867 GP_5_7_FN, GPSR5_7,
3868 GP_5_6_FN, GPSR5_6,
3869 GP_5_5_FN, GPSR5_5,
3870 GP_5_4_FN, GPSR5_4,
3871 GP_5_3_FN, GPSR5_3,
3872 GP_5_2_FN, GPSR5_2,
3873 GP_5_1_FN, GPSR5_1,
3874 GP_5_0_FN, GPSR5_0, }
3875 },
3876 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
3877 GP_6_31_FN, GPSR6_31,
3878 GP_6_30_FN, GPSR6_30,
3879 GP_6_29_FN, GPSR6_29,
3880 GP_6_28_FN, GPSR6_28,
3881 GP_6_27_FN, GPSR6_27,
3882 GP_6_26_FN, GPSR6_26,
3883 GP_6_25_FN, GPSR6_25,
3884 GP_6_24_FN, GPSR6_24,
3885 GP_6_23_FN, GPSR6_23,
3886 GP_6_22_FN, GPSR6_22,
3887 GP_6_21_FN, GPSR6_21,
3888 GP_6_20_FN, GPSR6_20,
3889 GP_6_19_FN, GPSR6_19,
3890 GP_6_18_FN, GPSR6_18,
3891 GP_6_17_FN, GPSR6_17,
3892 GP_6_16_FN, GPSR6_16,
3893 GP_6_15_FN, GPSR6_15,
3894 GP_6_14_FN, GPSR6_14,
3895 GP_6_13_FN, GPSR6_13,
3896 GP_6_12_FN, GPSR6_12,
3897 GP_6_11_FN, GPSR6_11,
3898 GP_6_10_FN, GPSR6_10,
3899 GP_6_9_FN, GPSR6_9,
3900 GP_6_8_FN, GPSR6_8,
3901 GP_6_7_FN, GPSR6_7,
3902 GP_6_6_FN, GPSR6_6,
3903 GP_6_5_FN, GPSR6_5,
3904 GP_6_4_FN, GPSR6_4,
3905 GP_6_3_FN, GPSR6_3,
3906 GP_6_2_FN, GPSR6_2,
3907 GP_6_1_FN, GPSR6_1,
3908 GP_6_0_FN, GPSR6_0, }
3909 },
3910 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
3911 0, 0,
3912 0, 0,
3913 0, 0,
3914 0, 0,
3915 0, 0,
3916 0, 0,
3917 0, 0,
3918 0, 0,
3919 0, 0,
3920 0, 0,
3921 0, 0,
3922 0, 0,
3923 0, 0,
3924 0, 0,
3925 0, 0,
3926 0, 0,
3927 0, 0,
3928 0, 0,
3929 0, 0,
3930 0, 0,
3931 0, 0,
3932 0, 0,
3933 0, 0,
3934 0, 0,
3935 0, 0,
3936 0, 0,
3937 0, 0,
3938 0, 0,
3939 GP_7_3_FN, GPSR7_3,
3940 GP_7_2_FN, GPSR7_2,
3941 GP_7_1_FN, GPSR7_1,
3942 GP_7_0_FN, GPSR7_0, }
3943 },
3944#undef F_
3945#undef FM
3946
3947#define F_(x, y) x,
3948#define FM(x) FN_##x,
3949 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
3950 IP0_31_28
3951 IP0_27_24
3952 IP0_23_20
3953 IP0_19_16
3954 IP0_15_12
3955 IP0_11_8
3956 IP0_7_4
3957 IP0_3_0 }
3958 },
3959 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
3960 IP1_31_28
3961 IP1_27_24
3962 IP1_23_20
3963 IP1_19_16
3964 IP1_15_12
3965 IP1_11_8
3966 IP1_7_4
3967 IP1_3_0 }
3968 },
3969 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
3970 IP2_31_28
3971 IP2_27_24
3972 IP2_23_20
3973 IP2_19_16
3974 IP2_15_12
3975 IP2_11_8
3976 IP2_7_4
3977 IP2_3_0 }
3978 },
3979 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
3980 IP3_31_28
3981 IP3_27_24
3982 IP3_23_20
3983 IP3_19_16
3984 IP3_15_12
3985 IP3_11_8
3986 IP3_7_4
3987 IP3_3_0 }
3988 },
3989 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
3990 IP4_31_28
3991 IP4_27_24
3992 IP4_23_20
3993 IP4_19_16
3994 IP4_15_12
3995 IP4_11_8
3996 IP4_7_4
3997 IP4_3_0 }
3998 },
3999 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4000 IP5_31_28
4001 IP5_27_24
4002 IP5_23_20
4003 IP5_19_16
4004 IP5_15_12
4005 IP5_11_8
4006 IP5_7_4
4007 IP5_3_0 }
4008 },
4009 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4010 IP6_31_28
4011 IP6_27_24
4012 IP6_23_20
4013 IP6_19_16
4014 IP6_15_12
4015 IP6_11_8
4016 IP6_7_4
4017 IP6_3_0 }
4018 },
4019 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4020 IP7_31_28
4021 IP7_27_24
4022 IP7_23_20
4023 IP7_19_16
4024 IP7_15_12
4025 IP7_11_8
4026 IP7_7_4
4027 IP7_3_0 }
4028 },
4029 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4030 IP8_31_28
4031 IP8_27_24
4032 IP8_23_20
4033 IP8_19_16
4034 IP8_15_12
4035 IP8_11_8
4036 IP8_7_4
4037 IP8_3_0 }
4038 },
4039 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4040 IP9_31_28
4041 IP9_27_24
4042 IP9_23_20
4043 IP9_19_16
4044 IP9_15_12
4045 IP9_11_8
4046 IP9_7_4
4047 IP9_3_0 }
4048 },
4049 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4050 IP10_31_28
4051 IP10_27_24
4052 IP10_23_20
4053 IP10_19_16
4054 IP10_15_12
4055 IP10_11_8
4056 IP10_7_4
4057 IP10_3_0 }
4058 },
4059 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4060 IP11_31_28
4061 IP11_27_24
4062 IP11_23_20
4063 IP11_19_16
4064 IP11_15_12
4065 IP11_11_8
4066 IP11_7_4
4067 IP11_3_0 }
4068 },
4069 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4070 IP12_31_28
4071 IP12_27_24
4072 IP12_23_20
4073 IP12_19_16
4074 IP12_15_12
4075 IP12_11_8
4076 IP12_7_4
4077 IP12_3_0 }
4078 },
4079 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4080 IP13_31_28
4081 IP13_27_24
4082 IP13_23_20
4083 IP13_19_16
4084 IP13_15_12
4085 IP13_11_8
4086 IP13_7_4
4087 IP13_3_0 }
4088 },
4089 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4090 IP14_31_28
4091 IP14_27_24
4092 IP14_23_20
4093 IP14_19_16
4094 IP14_15_12
4095 IP14_11_8
4096 IP14_7_4
4097 IP14_3_0 }
4098 },
4099 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4100 IP15_31_28
4101 IP15_27_24
4102 IP15_23_20
4103 IP15_19_16
4104 IP15_15_12
4105 IP15_11_8
4106 IP15_7_4
4107 IP15_3_0 }
4108 },
4109 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4110 IP16_31_28
4111 IP16_27_24
4112 IP16_23_20
4113 IP16_19_16
4114 IP16_15_12
4115 IP16_11_8
4116 IP16_7_4
4117 IP16_3_0 }
4118 },
4119 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4120 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4121 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4122 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4123 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4124 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4125 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4126 IP17_7_4
4127 IP17_3_0 }
4128 },
4129#undef F_
4130#undef FM
4131
4132#define F_(x, y) x,
4133#define FM(x) FN_##x,
4134 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4135 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4136 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4137 0, 0, /* RESERVED 31 */
4138 MOD_SEL0_30_29
4139 MOD_SEL0_28_27
4140 MOD_SEL0_26_25_24
4141 MOD_SEL0_23
4142 MOD_SEL0_22
4143 MOD_SEL0_21_20
4144 MOD_SEL0_19
4145 MOD_SEL0_18
4146 MOD_SEL0_17
4147 MOD_SEL0_16_15
4148 MOD_SEL0_14
4149 MOD_SEL0_13
4150 MOD_SEL0_12
4151 MOD_SEL0_11
4152 MOD_SEL0_10
4153 MOD_SEL0_9
4154 MOD_SEL0_8
4155 MOD_SEL0_7_6
4156 MOD_SEL0_5_4
4157 MOD_SEL0_3
4158 MOD_SEL0_2_1
4159 0, 0, /* RESERVED 0 */ }
4160 },
4161 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4162 2, 3, 1, 2, 3, 1, 1, 2, 1,
4163 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4164 MOD_SEL1_31_30
4165 MOD_SEL1_29_28_27
4166 MOD_SEL1_26
4167 MOD_SEL1_25_24
4168 MOD_SEL1_23_22_21
4169 MOD_SEL1_20
4170 MOD_SEL1_19
4171 MOD_SEL1_18_17
4172 MOD_SEL1_16
4173 MOD_SEL1_15_14
4174 MOD_SEL1_13
4175 MOD_SEL1_12
4176 MOD_SEL1_11
4177 MOD_SEL1_10
4178 MOD_SEL1_9
4179 0, 0, 0, 0, /* RESERVED 8, 7 */
4180 MOD_SEL1_6
4181 MOD_SEL1_5
4182 MOD_SEL1_4
4183 MOD_SEL1_3
4184 MOD_SEL1_2
4185 MOD_SEL1_1
4186 MOD_SEL1_0 }
4187 },
4188 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4189 1, 1, 1, 1, 4, 4, 4,
4190 4, 4, 4, 1, 2, 1) {
4191 MOD_SEL2_31
4192 MOD_SEL2_30
4193 MOD_SEL2_29
4194 /* RESERVED 28 */
4195 0, 0,
4196 /* RESERVED 27, 26, 25, 24 */
4197 0, 0, 0, 0, 0, 0, 0, 0,
4198 0, 0, 0, 0, 0, 0, 0, 0,
4199 /* RESERVED 23, 22, 21, 20 */
4200 0, 0, 0, 0, 0, 0, 0, 0,
4201 0, 0, 0, 0, 0, 0, 0, 0,
4202 /* RESERVED 19, 18, 17, 16 */
4203 0, 0, 0, 0, 0, 0, 0, 0,
4204 0, 0, 0, 0, 0, 0, 0, 0,
4205 /* RESERVED 15, 14, 13, 12 */
4206 0, 0, 0, 0, 0, 0, 0, 0,
4207 0, 0, 0, 0, 0, 0, 0, 0,
4208 /* RESERVED 11, 10, 9, 8 */
4209 0, 0, 0, 0, 0, 0, 0, 0,
4210 0, 0, 0, 0, 0, 0, 0, 0,
4211 /* RESERVED 7, 6, 5, 4 */
4212 0, 0, 0, 0, 0, 0, 0, 0,
4213 0, 0, 0, 0, 0, 0, 0, 0,
4214 /* RESERVED 3 */
4215 0, 0,
4216 MOD_SEL2_2_1
4217 MOD_SEL2_0 }
4218 },
4219 { },
4220};
4221
4222const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4223 .name = "r8a77950_pfc",
4224 .unlock_reg = 0xe6060000, /* PMMR */
4225
4226 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4227
4228 .pins = pinmux_pins,
4229 .nr_pins = ARRAY_SIZE(pinmux_pins),
4230 .groups = pinmux_groups,
4231 .nr_groups = ARRAY_SIZE(pinmux_groups),
4232 .functions = pinmux_functions,
4233 .nr_functions = ARRAY_SIZE(pinmux_functions),
4234
4235 .cfg_regs = pinmux_config_regs,
4236
b8b47d67
GU		 4237 .pinmux_data = pinmux_data,
4238 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 4239};
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