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Merge branches 'for-5.1/upstream-fixes', 'for-5.2/core', 'for-5.2/ish', 'for-5.2...
[mirror_ubuntu-kernels.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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63b6d7e7 1// SPDX-License-Identifier: GPL-2.0
0b0ffc96 2/*
b205914c 3 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 4 *
740a4a3a 5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
0b0ffc96
TK		 6 */
7
8#include <linux/kernel.h>
b205914c 9#include <linux/sys_soc.h>
0b0ffc96
TK		 10
11#include "core.h"
12#include "sh_pfc.h"
13
56065524
UH		 14#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
15 SH_PFC_PIN_CFG_PULL_UP | \
16 SH_PFC_PIN_CFG_PULL_DOWN)
17
0b0ffc96 18#define CPU_ALL_PORT(fn, sfx) \
56065524 19 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
82d2de5a 20 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
56065524
UH		 21 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
22 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
23 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
28 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 31/*
32 * F_() : just information
33 * FM() : macro for FN_xxx / xxx_MARK
34 */
35
36/* GPSR0 */
37#define GPSR0_15 F_(D15, IP7_11_8)
38#define GPSR0_14 F_(D14, IP7_7_4)
39#define GPSR0_13 F_(D13, IP7_3_0)
40#define GPSR0_12 F_(D12, IP6_31_28)
41#define GPSR0_11 F_(D11, IP6_27_24)
42#define GPSR0_10 F_(D10, IP6_23_20)
43#define GPSR0_9 F_(D9, IP6_19_16)
44#define GPSR0_8 F_(D8, IP6_15_12)
45#define GPSR0_7 F_(D7, IP6_11_8)
46#define GPSR0_6 F_(D6, IP6_7_4)
47#define GPSR0_5 F_(D5, IP6_3_0)
48#define GPSR0_4 F_(D4, IP5_31_28)
49#define GPSR0_3 F_(D3, IP5_27_24)
50#define GPSR0_2 F_(D2, IP5_23_20)
51#define GPSR0_1 F_(D1, IP5_19_16)
52#define GPSR0_0 F_(D0, IP5_15_12)
53
54/* GPSR1 */
82d2de5a 55#define GPSR1_28 FM(CLKOUT)
0b0ffc96
TK		 56#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
57#define GPSR1_26 F_(WE1_N, IP5_7_4)
58#define GPSR1_25 F_(WE0_N, IP5_3_0)
59#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
60#define GPSR1_23 F_(RD_N, IP4_27_24)
61#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 62#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 63#define GPSR1_20 F_(CS0_N, IP4_15_12)
64#define GPSR1_19 F_(A19, IP4_11_8)
65#define GPSR1_18 F_(A18, IP4_7_4)
66#define GPSR1_17 F_(A17, IP4_3_0)
67#define GPSR1_16 F_(A16, IP3_31_28)
68#define GPSR1_15 F_(A15, IP3_27_24)
69#define GPSR1_14 F_(A14, IP3_23_20)
70#define GPSR1_13 F_(A13, IP3_19_16)
71#define GPSR1_12 F_(A12, IP3_15_12)
72#define GPSR1_11 F_(A11, IP3_11_8)
73#define GPSR1_10 F_(A10, IP3_7_4)
74#define GPSR1_9 F_(A9, IP3_3_0)
75#define GPSR1_8 F_(A8, IP2_31_28)
76#define GPSR1_7 F_(A7, IP2_27_24)
77#define GPSR1_6 F_(A6, IP2_23_20)
78#define GPSR1_5 F_(A5, IP2_19_16)
79#define GPSR1_4 F_(A4, IP2_15_12)
80#define GPSR1_3 F_(A3, IP2_11_8)
81#define GPSR1_2 F_(A2, IP2_7_4)
82#define GPSR1_1 F_(A1, IP2_3_0)
83#define GPSR1_0 F_(A0, IP1_31_28)
84
85/* GPSR2 */
86#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
87#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
88#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
89#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
90#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
91#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
92#define GPSR2_8 F_(PWM2_A, IP1_27_24)
93#define GPSR2_7 F_(PWM1_A, IP1_23_20)
94#define GPSR2_6 F_(PWM0, IP1_19_16)
95#define GPSR2_5 F_(IRQ5, IP1_15_12)
96#define GPSR2_4 F_(IRQ4, IP1_11_8)
97#define GPSR2_3 F_(IRQ3, IP1_7_4)
98#define GPSR2_2 F_(IRQ2, IP1_3_0)
99#define GPSR2_1 F_(IRQ1, IP0_31_28)
100#define GPSR2_0 F_(IRQ0, IP0_27_24)
101
102/* GPSR3 */
b205914c
GU		 103#define GPSR3_15 F_(SD1_WP, IP11_23_20)
104#define GPSR3_14 F_(SD1_CD, IP11_19_16)
105#define GPSR3_13 F_(SD0_WP, IP11_15_12)
106#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 107#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
108#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
109#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
110#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
111#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
112#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
113#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
114#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
115#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
116#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
117#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
118#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
119
120/* GPSR4 */
b205914c
GU		 121#define GPSR4_17 F_(SD3_DS, IP11_7_4)
122#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
123#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
124#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
125#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
126#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
127#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
128#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
129#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
130#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
131#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
132#define GPSR4_6 F_(SD2_DS, IP9_27_24)
133#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
134#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
135#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
136#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
137#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 138#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
139
140/* GPSR5 */
b205914c
GU		 141#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
142#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
143#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 144#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 145#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 146#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 147#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
148#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 149#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 150#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
151#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
152#define GPSR5_14 F_(HTX0, IP13_19_16)
153#define GPSR5_13 F_(HRX0, IP13_15_12)
154#define GPSR5_12 F_(HSCK0, IP13_11_8)
155#define GPSR5_11 F_(RX2_A, IP13_7_4)
156#define GPSR5_10 F_(TX2_A, IP13_3_0)
157#define GPSR5_9 F_(SCK2, IP12_31_28)
8714a9c1 158#define GPSR5_8 F_(RTS1_N, IP12_27_24)
b205914c
GU		 159#define GPSR5_7 F_(CTS1_N, IP12_23_20)
160#define GPSR5_6 F_(TX1_A, IP12_19_16)
161#define GPSR5_5 F_(RX1_A, IP12_15_12)
8714a9c1 162#define GPSR5_4 F_(RTS0_N, IP12_11_8)
b205914c
GU		 163#define GPSR5_3 F_(CTS0_N, IP12_7_4)
164#define GPSR5_2 F_(TX0, IP12_3_0)
165#define GPSR5_1 F_(RX0, IP11_31_28)
166#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 167
168/* GPSR6 */
f9d13080
YS		 169#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
170#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 171#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
172#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
173#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
174#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
175#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
176#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
177#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
178#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
179#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
180#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
181#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
182#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
183#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
184#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
185#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
186#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 187#define GPSR6_13 FM(SSI_SDATA5)
188#define GPSR6_12 FM(SSI_WS5)
189#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 190#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
191#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
192#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
193#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 194#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
195#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 196#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
197#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
198#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
199#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
200#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 201
202/* GPSR7 */
203#define GPSR7_3 FM(HDMI1_CEC)
204#define GPSR7_2 FM(HDMI0_CEC)
205#define GPSR7_1 FM(AVS2)
206#define GPSR7_0 FM(AVS1)
207
208
209/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
210#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 214#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 215#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 216#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 218#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
7716c51b
TK		 219#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 225#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229
230/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
231#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 237#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 238#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 248#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 249#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 253#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 254#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 266#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 267#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 271#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272
273/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
274#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 280#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 285#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 303#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 304
305/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 306#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 313#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 314#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
8714a9c1 317#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 318#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
327#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334
335/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
336#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 339#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 341#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
356#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
357#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
358#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
359#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
360#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 361#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
362#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 363
364#define PINMUX_GPSR \
365\
366 GPSR6_31 \
367 GPSR6_30 \
368 GPSR6_29 \
82d2de5a 369 GPSR1_28 GPSR6_28 \
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TK		 370 GPSR1_27 GPSR6_27 \
371 GPSR1_26 GPSR6_26 \
372 GPSR1_25 GPSR5_25 GPSR6_25 \
373 GPSR1_24 GPSR5_24 GPSR6_24 \
374 GPSR1_23 GPSR5_23 GPSR6_23 \
375 GPSR1_22 GPSR5_22 GPSR6_22 \
376 GPSR1_21 GPSR5_21 GPSR6_21 \
377 GPSR1_20 GPSR5_20 GPSR6_20 \
378 GPSR1_19 GPSR5_19 GPSR6_19 \
379 GPSR1_18 GPSR5_18 GPSR6_18 \
380 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
381 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
382GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
383GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
384GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
385GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
386GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
387GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
388GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
389GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
390GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
391GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
392GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
393GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
394GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
395GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
396GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
397GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
398
399#define PINMUX_IPSR \
400\
401FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
402FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
403FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
404FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
405FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
406FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
407FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
408FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
409\
410FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
411FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
412FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 413FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 414FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
415FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
416FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
417FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
418\
419FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
420FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
421FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
422FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
423FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
424FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
425FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
426FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
427\
428FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
429FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
430FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
431FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
432FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
433FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
434FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
435FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
436\
b205914c
GU		 437FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
438FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
439FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
440FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
441FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
442FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
443FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
444FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 445
446/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 447#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 448#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
449#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
450#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
451#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 452#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
453#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
454#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
455#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
456#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
457#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
458#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
459#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
460#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
461#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
462#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
463#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
464#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 465
466/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
467#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
468#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 469#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 470#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
471#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
740a4a3a 472#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
0b0ffc96
TK		 473#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
474#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
475#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
476#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
477#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
478#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
479#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 480#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 481#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
482#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
483#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
484#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
485#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
486#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
487#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
488#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
489
490/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
491#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
492#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
493#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 494#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
495#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
496#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 497#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
498#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
499#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
500#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
501#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 502#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
503
b205914c 504#define PINMUX_MOD_SELS \
0b0ffc96 505\
b205914c
GU		 506MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
507 MOD_SEL2_30 \
0b0ffc96 508 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 509MOD_SEL0_28_27 MOD_SEL2_28_27 \
510MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
511 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 512MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 513MOD_SEL0_22 \
b205914c
GU		 514MOD_SEL0_21 MOD_SEL2_21 \
515MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
516MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
517MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
518 MOD_SEL2_17 \
519MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 520 MOD_SEL1_15_14 \
b205914c
GU		 521MOD_SEL0_14_13 \
522 MOD_SEL1_13 \
0b0ffc96
TK		 523MOD_SEL0_12 MOD_SEL1_12 \
524MOD_SEL0_11 MOD_SEL1_11 \
525MOD_SEL0_10 MOD_SEL1_10 \
b205914c 526MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 527MOD_SEL0_7_6 \
528 MOD_SEL1_6 \
b205914c
GU		 529MOD_SEL0_5 MOD_SEL1_5 \
530MOD_SEL0_4_3 MOD_SEL1_4 \
531 MOD_SEL1_3 \
532 MOD_SEL1_2 \
0b0ffc96
TK		 533 MOD_SEL1_1 \
534 MOD_SEL1_0 MOD_SEL2_0
535
ea9c7405
NS		 536/*
537 * These pins are not able to be muxed but have other properties
538 * that can be set, such as drive-strength or pull-up/pull-down enable.
539 */
540#define PINMUX_STATIC \
541 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
542 FM(QSPI0_IO2) FM(QSPI0_IO3) \
543 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
544 FM(QSPI1_IO2) FM(QSPI1_IO3) \
545 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
546 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
547 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
548 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
82d2de5a 549 FM(PRESETOUT) \
ea9c7405 550 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 551 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96 552
100431b6
TK		 553#define PINMUX_PHYS \
554 FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
555
0b0ffc96
TK		 556enum {
557 PINMUX_RESERVED = 0,
558
559 PINMUX_DATA_BEGIN,
560 GP_ALL(DATA),
561 PINMUX_DATA_END,
562
563#define F_(x, y)
564#define FM(x) FN_##x,
565 PINMUX_FUNCTION_BEGIN,
566 GP_ALL(FN),
567 PINMUX_GPSR
568 PINMUX_IPSR
569 PINMUX_MOD_SELS
570 PINMUX_FUNCTION_END,
571#undef F_
572#undef FM
573
574#define F_(x, y)
575#define FM(x) x##_MARK,
576 PINMUX_MARK_BEGIN,
577 PINMUX_GPSR
578 PINMUX_IPSR
579 PINMUX_MOD_SELS
ea9c7405 580 PINMUX_STATIC
100431b6 581 PINMUX_PHYS
0b0ffc96
TK		 582 PINMUX_MARK_END,
583#undef F_
584#undef FM
585};
586
587static const u16 pinmux_data[] = {
588 PINMUX_DATA_GP_ALL(),
589
8d4df573
GU		 590 PINMUX_SINGLE(AVS1),
591 PINMUX_SINGLE(AVS2),
82d2de5a 592 PINMUX_SINGLE(CLKOUT),
8d4df573
GU		 593 PINMUX_SINGLE(HDMI0_CEC),
594 PINMUX_SINGLE(HDMI1_CEC),
595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
0b0ffc96 602 /* IPSR0 */
e01678e3 603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
e01678e3 606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
e01678e3 610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
e01678e3 614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
100431b6
TK		 618 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
619 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
620 PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, FSCLKST2_N_A, I2C_SEL_5_0),
622 PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
0b0ffc96 623
100431b6
TK		 624 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
625 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
626 PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
627 PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
0b0ffc96 628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 644
645 /* IPSR1 */
e01678e3
GU		 646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 652
e01678e3
GU		 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
e01678e3 655 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 656 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 658 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 659
e01678e3
GU		 660 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
661 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
e01678e3 662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 666
e01678e3
GU		 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
e01678e3 669 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 670 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 672 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
673 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 674
e01678e3
GU		 675 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
676 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
0b0ffc96
TK		 677 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
678 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
679
100431b6
TK		 680 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
681 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
682 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
683 PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
684 PINMUX_IPSR_PHYS(IP0_23_20, SCL3, I2C_SEL_3_1),
0b0ffc96 685
100431b6
TK		 686 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
687 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
688 PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
689 PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
0b0ffc96 690
e01678e3
GU		 691 PINMUX_IPSR_GPSR(IP1_31_28, A0),
692 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 693 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 694 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
695 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 696 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
697
698 /* IPSR2 */
e01678e3
GU		 699 PINMUX_IPSR_GPSR(IP2_3_0, A1),
700 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 701 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 702 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
703 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 704 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
705
e01678e3
GU		 706 PINMUX_IPSR_GPSR(IP2_7_4, A2),
707 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 708 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 709 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
710 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 711 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
712
e01678e3
GU		 713 PINMUX_IPSR_GPSR(IP2_11_8, A3),
714 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 715 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 716 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
717 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 718 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
719
e01678e3
GU		 720 PINMUX_IPSR_GPSR(IP2_15_12, A4),
721 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 722 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 723 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
724 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
725 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 726
e01678e3
GU		 727 PINMUX_IPSR_GPSR(IP2_19_16, A5),
728 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 729 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
730 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 731 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
732 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
733 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 734
e01678e3
GU		 735 PINMUX_IPSR_GPSR(IP2_23_20, A6),
736 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 737 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
738 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 739 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
740 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
741 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 742
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP2_27_24, A7),
744 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 745 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
746 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 747 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
748 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
749 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 750
e01678e3 751 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 752 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
753 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
754 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
758
759 /* IPSR3 */
e01678e3 760 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 761 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
762 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 763 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 764
e01678e3 765 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96 766 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
8714a9c1 767 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
e01678e3 768 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 769
e01678e3 770 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 771 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
772 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
773 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 774 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
775 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 776 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
778 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
779
e01678e3
GU		 780 PINMUX_IPSR_GPSR(IP3_15_12, A12),
781 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 782 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
783 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 784 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
785 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 786
e01678e3
GU		 787 PINMUX_IPSR_GPSR(IP3_19_16, A13),
788 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 789 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
790 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 791 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
792 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 793
e01678e3
GU		 794 PINMUX_IPSR_GPSR(IP3_23_20, A14),
795 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 796 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 797 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
798 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
799 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 800
e01678e3
GU		 801 PINMUX_IPSR_GPSR(IP3_27_24, A15),
802 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 803 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 804 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
805 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
806 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 807
e01678e3
GU		 808 PINMUX_IPSR_GPSR(IP3_31_28, A16),
809 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
810 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
811 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 812
813 /* IPSR4 */
e01678e3
GU		 814 PINMUX_IPSR_GPSR(IP4_3_0, A17),
815 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
816 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
817 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
818
819 PINMUX_IPSR_GPSR(IP4_7_4, A18),
820 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
821 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
822 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
823
824 PINMUX_IPSR_GPSR(IP4_11_8, A19),
825 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
826 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
827 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
828
829 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
830 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
831
fc8fd9be 832 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 833 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 834 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
835
e01678e3
GU		 836 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
837 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 838 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 839 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
840 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
841 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
842 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 843 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
844
e01678e3 845 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 846 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
847 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
848 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
849 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
851
e01678e3 852 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 853 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
854 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
855 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
856 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
858
859 /* IPSR5 */
e01678e3 860 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 861 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 862 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
863 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 864 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 865 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 866 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
867
e01678e3 868 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 869 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
8714a9c1 870 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
e01678e3 871 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 872 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 873 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
874 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 875 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
876
877 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 878 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
879 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
880 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 881
e01678e3 882 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 883 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
884 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 885 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
886 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 887
e01678e3 888 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 889 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
890 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 891 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
892 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 893
e01678e3 894 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 895 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 896 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
897 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 898
e01678e3 899 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 900 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 901 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
902 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 903
e01678e3 904 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 905 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 906 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
907 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 908
909 /* IPSR6 */
e01678e3 910 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 911 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 912 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
913 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 914
b205914c
GU		 915 PINMUX_IPSR_GPSR(IP6_7_4, D6),
916 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
917 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
918 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 919
b205914c
GU		 920 PINMUX_IPSR_GPSR(IP6_11_8, D7),
921 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
922 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
923 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 924
b205914c
GU		 925 PINMUX_IPSR_GPSR(IP6_15_12, D8),
926 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
927 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
928 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
929 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
930 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 931
b205914c
GU		 932 PINMUX_IPSR_GPSR(IP6_19_16, D9),
933 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
934 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
935 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
936 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 937
b205914c
GU		 938 PINMUX_IPSR_GPSR(IP6_23_20, D10),
939 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
940 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
941 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
942 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
943 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
944 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 945
b205914c
GU		 946 PINMUX_IPSR_GPSR(IP6_27_24, D11),
947 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
948 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
949 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
950 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
8714a9c1 951 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
b205914c 952 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 953
b205914c
GU		 954 PINMUX_IPSR_GPSR(IP6_31_28, D12),
955 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
956 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
957 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
958 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
959 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 960
b205914c
GU		 961 /* IPSR7 */
962 PINMUX_IPSR_GPSR(IP7_3_0, D13),
963 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
964 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
965 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
966 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
967 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 968
b205914c
GU		 969 PINMUX_IPSR_GPSR(IP7_7_4, D14),
970 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
971 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
972 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
973 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
974 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
975 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 976
b205914c
GU		 977 PINMUX_IPSR_GPSR(IP7_11_8, D15),
978 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
979 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
980 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
981 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
982 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
983 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 984
b205914c
GU		 985 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
986 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
987 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 988
b205914c
GU		 989 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
990 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
991 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 992
b205914c
GU		 993 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
994 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
995 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
996 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 997
b205914c
GU		 998 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
999 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1000 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1002
b205914c
GU		 1003 /* IPSR8 */
1004 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1005 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1008
b205914c
GU		 1009 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1010 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1011 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1012 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1013
b205914c
GU		 1014 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1015 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1016 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1017
b205914c
GU		 1018 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1019 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1020 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1021 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1022 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1023
b205914c
GU		 1024 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1025 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1026 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1027 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1028 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1029 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1030
b205914c
GU		 1031 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1032 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1033 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1034 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1035 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1036 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1037
b205914c
GU		 1038 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1039 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1040 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1041 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1042 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1043 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1044
b205914c
GU		 1045 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1046 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1047 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1048 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1049 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1050 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1051
b205914c
GU		 1052 /* IPSR9 */
1053 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1054 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1055
b205914c
GU		 1056 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1057 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1058
b205914c
GU		 1059 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1060 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1061
b205914c
GU		 1062 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1063 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1064
b205914c
GU		 1065 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1066 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1067
b205914c
GU		 1068 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1069 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1070
b205914c
GU		 1071 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1072 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1073 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1074
b205914c
GU		 1075 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1076 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1077
b205914c
GU		 1078 /* IPSR10 */
1079 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1080 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1081
b205914c
GU		 1082 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1083 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1084
b205914c
GU		 1085 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1086 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1087
b205914c
GU		 1088 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1089 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1090
b205914c
GU		 1091 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1092 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1093
b205914c
GU		 1094 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1095 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1096 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1097
b205914c
GU		 1098 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1099 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1100 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1101
b205914c
GU		 1102 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1103 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1104 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1105
b205914c
GU		 1106 /* IPSR11 */
1107 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1108 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1109 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1110
1111 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1112 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1113
1114 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1115 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1116 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1117
1118 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1119 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1120
100431b6
TK		 1121 PINMUX_IPSR_MSEL(IP11_19_16, SD1_CD, I2C_SEL_0_0),
1122 PINMUX_IPSR_PHYS_MSEL(IP11_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1123 PINMUX_IPSR_PHYS(IP11_19_16, SCL0, I2C_SEL_0_1),
b205914c 1124
100431b6
TK		 1125 PINMUX_IPSR_MSEL(IP11_23_20, SD1_WP, I2C_SEL_0_0),
1126 PINMUX_IPSR_PHYS_MSEL(IP11_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
1127 PINMUX_IPSR_PHYS(IP11_23_20, SDA0, I2C_SEL_0_1),
b205914c
GU		 1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1145
b205914c
GU		 1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
8714a9c1 1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
b205914c
GU		 1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
8714a9c1 1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
b205914c
GU		 1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1206
b205914c
GU		 1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
740a4a3a 1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
b205914c
GU		 1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
740a4a3a 1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
b205914c
GU		 1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
740a4a3a 1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
b205914c
GU		 1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
740a4a3a 1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
b205914c
GU		 1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
740a4a3a 1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
b205914c
GU		 1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1266
b205914c
GU		 1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c 1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
740a4a3a 1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
b205914c
GU		 1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
740a4a3a 1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
b205914c
GU		 1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1307
b205914c 1308 /* IPSR15 */
740a4a3a 1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
b205914c 1310
740a4a3a
TK		 1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
b205914c 1313
68e63892 1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1354
b205914c
GU		 1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
740a4a3a 1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
b205914c
GU		 1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
740a4a3a 1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
b205914c
GU		 1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1409
b205914c
GU		 1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
740a4a3a 1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
b205914c
GU		 1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
740a4a3a 1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
b205914c
GU		 1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
740a4a3a 1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
b205914c 1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
740a4a3a 1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
b205914c
GU		 1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
f9d13080 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
740a4a3a 1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
b205914c
GU		 1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
f9d13080 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
740a4a3a 1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
b205914c
GU		 1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1497
b205914c
GU		 1498/*
1499 * Static pins can not be muxed between different functions but
db701f4b 1500 * still need mark entries in the pinmux list. Add each static
b205914c 1501 * pin to the list without an associated function. The sh-pfc
db701f4b
GU		 1502 * core will do the right thing and skip trying to mux the pin
1503 * while still applying configuration to it.
b205914c
GU		 1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
9b132ba3
KM		 1508};
1509
b205914c 1510/*
ecd54509 1511 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
b205914c
GU		 1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
6f4b74f3 1517#define PIN_NONE U16_MAX
b205914c
GU		 1518
1519static const struct sh_pfc_pin pinmux_pins[] = {
1520 PINMUX_GPIO_GP_ALL(),
76250a6c 1521
b205914c
GU		 1522 /*
1523 * Pins not associated with a GPIO port.
1524 *
1525 * The pin positions are different between different r8a7795
1526 * packages, all that is needed for the pfc driver is a unique
1527 * number for each pin. To this end use the pin layout from
1528 * R-Car H3SiP to calculate a unique number for each pin.
1529 */
1530 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
b205914c
GU		 1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1573};
1574
55bfea9f
KM		 1575/* - AUDIO CLOCK ------------------------------------------------------------ */
1576static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681static const unsigned int audio_clkout3_a_pins[] = {
1682 /* CLKOUT3 */
1683 RCAR_GP_PIN(5, 19),
1684};
1685static const unsigned int audio_clkout3_a_mux[] = {
1686 AUDIO_CLKOUT3_A_MARK,
1687};
1688static const unsigned int audio_clkout3_b_pins[] = {
1689 /* CLKOUT3 */
1690 RCAR_GP_PIN(6, 31),
1691};
1692static const unsigned int audio_clkout3_b_mux[] = {
1693 AUDIO_CLKOUT3_B_MARK,
1694};
1695
30c078de
GU		 1696/* - EtherAVB --------------------------------------------------------------- */
1697static const unsigned int avb_link_pins[] = {
1698 /* AVB_LINK */
1699 RCAR_GP_PIN(2, 12),
1700};
1701static const unsigned int avb_link_mux[] = {
1702 AVB_LINK_MARK,
1703};
1704static const unsigned int avb_magic_pins[] = {
1705 /* AVB_MAGIC_ */
1706 RCAR_GP_PIN(2, 10),
1707};
1708static const unsigned int avb_magic_mux[] = {
1709 AVB_MAGIC_MARK,
1710};
1711static const unsigned int avb_phy_int_pins[] = {
1712 /* AVB_PHY_INT */
1713 RCAR_GP_PIN(2, 11),
1714};
1715static const unsigned int avb_phy_int_mux[] = {
1716 AVB_PHY_INT_MARK,
1717};
cbe0dd9a 1718static const unsigned int avb_mdio_pins[] = {
30c078de
GU		 1719 /* AVB_MDC, AVB_MDIO */
1720 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1721};
cbe0dd9a 1722static const unsigned int avb_mdio_mux[] = {
30c078de
GU		 1723 AVB_MDC_MARK, AVB_MDIO_MARK,
1724};
1725static const unsigned int avb_mii_pins[] = {
1726 /*
1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1728 * AVB_TD1, AVB_TD2, AVB_TD3,
1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1730 * AVB_RD1, AVB_RD2, AVB_RD3,
1731 * AVB_TXCREFCLK
1732 */
1733 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1734 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1735 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1736 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1737 PIN_NUMBER('A', 12),
1738
1739};
1740static const unsigned int avb_mii_mux[] = {
1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1745 AVB_TXCREFCLK_MARK,
1746};
1747static const unsigned int avb_avtp_pps_pins[] = {
1748 /* AVB_AVTP_PPS */
1749 RCAR_GP_PIN(2, 6),
1750};
1751static const unsigned int avb_avtp_pps_mux[] = {
1752 AVB_AVTP_PPS_MARK,
1753};
1754static const unsigned int avb_avtp_match_a_pins[] = {
1755 /* AVB_AVTP_MATCH_A */
1756 RCAR_GP_PIN(2, 13),
1757};
1758static const unsigned int avb_avtp_match_a_mux[] = {
1759 AVB_AVTP_MATCH_A_MARK,
1760};
1761static const unsigned int avb_avtp_capture_a_pins[] = {
1762 /* AVB_AVTP_CAPTURE_A */
1763 RCAR_GP_PIN(2, 14),
1764};
1765static const unsigned int avb_avtp_capture_a_mux[] = {
1766 AVB_AVTP_CAPTURE_A_MARK,
1767};
1768static const unsigned int avb_avtp_match_b_pins[] = {
1769 /* AVB_AVTP_MATCH_B */
1770 RCAR_GP_PIN(1, 8),
1771};
1772static const unsigned int avb_avtp_match_b_mux[] = {
1773 AVB_AVTP_MATCH_B_MARK,
1774};
1775static const unsigned int avb_avtp_capture_b_pins[] = {
1776 /* AVB_AVTP_CAPTURE_B */
1777 RCAR_GP_PIN(1, 11),
1778};
1779static const unsigned int avb_avtp_capture_b_mux[] = {
1780 AVB_AVTP_CAPTURE_B_MARK,
1781};
1782
a678abfe
RS		 1783/* - CAN ------------------------------------------------------------------ */
1784static const unsigned int can0_data_a_pins[] = {
1785 /* TX, RX */
1786 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1787};
1788static const unsigned int can0_data_a_mux[] = {
1789 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1790};
1791static const unsigned int can0_data_b_pins[] = {
1792 /* TX, RX */
1793 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1794};
1795static const unsigned int can0_data_b_mux[] = {
1796 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1797};
1798static const unsigned int can1_data_pins[] = {
1799 /* TX, RX */
1800 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1801};
1802static const unsigned int can1_data_mux[] = {
1803 CAN1_TX_MARK, CAN1_RX_MARK,
1804};
1805
1806/* - CAN Clock -------------------------------------------------------------- */
1807static const unsigned int can_clk_pins[] = {
1808 /* CLK */
1809 RCAR_GP_PIN(1, 25),
1810};
1811static const unsigned int can_clk_mux[] = {
1812 CAN_CLK_MARK,
1813};
1814
0e1c7a94
RS		 1815/* - CAN FD --------------------------------------------------------------- */
1816static const unsigned int canfd0_data_a_pins[] = {
1817 /* TX, RX */
1818 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1819};
1820static const unsigned int canfd0_data_a_mux[] = {
1821 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1822};
1823static const unsigned int canfd0_data_b_pins[] = {
1824 /* TX, RX */
1825 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1826};
1827static const unsigned int canfd0_data_b_mux[] = {
1828 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1829};
1830static const unsigned int canfd1_data_pins[] = {
1831 /* TX, RX */
1832 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1833};
1834static const unsigned int canfd1_data_mux[] = {
1835 CANFD1_TX_MARK, CANFD1_RX_MARK,
1836};
1837
641b0ab8
DB		 1838/* - DRIF0 --------------------------------------------------------------- */
1839static const unsigned int drif0_ctrl_a_pins[] = {
1840 /* CLK, SYNC */
1841 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1842};
1843static const unsigned int drif0_ctrl_a_mux[] = {
1844 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1845};
1846static const unsigned int drif0_data0_a_pins[] = {
1847 /* D0 */
1848 RCAR_GP_PIN(6, 10),
1849};
1850static const unsigned int drif0_data0_a_mux[] = {
1851 RIF0_D0_A_MARK,
1852};
1853static const unsigned int drif0_data1_a_pins[] = {
1854 /* D1 */
1855 RCAR_GP_PIN(6, 7),
1856};
1857static const unsigned int drif0_data1_a_mux[] = {
1858 RIF0_D1_A_MARK,
1859};
1860static const unsigned int drif0_ctrl_b_pins[] = {
1861 /* CLK, SYNC */
1862 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1863};
1864static const unsigned int drif0_ctrl_b_mux[] = {
1865 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1866};
1867static const unsigned int drif0_data0_b_pins[] = {
1868 /* D0 */
1869 RCAR_GP_PIN(5, 1),
1870};
1871static const unsigned int drif0_data0_b_mux[] = {
1872 RIF0_D0_B_MARK,
1873};
1874static const unsigned int drif0_data1_b_pins[] = {
1875 /* D1 */
1876 RCAR_GP_PIN(5, 2),
1877};
1878static const unsigned int drif0_data1_b_mux[] = {
1879 RIF0_D1_B_MARK,
1880};
1881static const unsigned int drif0_ctrl_c_pins[] = {
1882 /* CLK, SYNC */
1883 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1884};
1885static const unsigned int drif0_ctrl_c_mux[] = {
1886 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1887};
1888static const unsigned int drif0_data0_c_pins[] = {
1889 /* D0 */
1890 RCAR_GP_PIN(5, 13),
1891};
1892static const unsigned int drif0_data0_c_mux[] = {
1893 RIF0_D0_C_MARK,
1894};
1895static const unsigned int drif0_data1_c_pins[] = {
1896 /* D1 */
1897 RCAR_GP_PIN(5, 14),
1898};
1899static const unsigned int drif0_data1_c_mux[] = {
1900 RIF0_D1_C_MARK,
1901};
1902/* - DRIF1 --------------------------------------------------------------- */
1903static const unsigned int drif1_ctrl_a_pins[] = {
1904 /* CLK, SYNC */
1905 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1906};
1907static const unsigned int drif1_ctrl_a_mux[] = {
1908 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1909};
1910static const unsigned int drif1_data0_a_pins[] = {
1911 /* D0 */
1912 RCAR_GP_PIN(6, 19),
1913};
1914static const unsigned int drif1_data0_a_mux[] = {
1915 RIF1_D0_A_MARK,
1916};
1917static const unsigned int drif1_data1_a_pins[] = {
1918 /* D1 */
1919 RCAR_GP_PIN(6, 20),
1920};
1921static const unsigned int drif1_data1_a_mux[] = {
1922 RIF1_D1_A_MARK,
1923};
1924static const unsigned int drif1_ctrl_b_pins[] = {
1925 /* CLK, SYNC */
1926 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1927};
1928static const unsigned int drif1_ctrl_b_mux[] = {
1929 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1930};
1931static const unsigned int drif1_data0_b_pins[] = {
1932 /* D0 */
1933 RCAR_GP_PIN(5, 7),
1934};
1935static const unsigned int drif1_data0_b_mux[] = {
1936 RIF1_D0_B_MARK,
1937};
1938static const unsigned int drif1_data1_b_pins[] = {
1939 /* D1 */
1940 RCAR_GP_PIN(5, 8),
1941};
1942static const unsigned int drif1_data1_b_mux[] = {
1943 RIF1_D1_B_MARK,
1944};
1945static const unsigned int drif1_ctrl_c_pins[] = {
1946 /* CLK, SYNC */
1947 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1948};
1949static const unsigned int drif1_ctrl_c_mux[] = {
1950 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1951};
1952static const unsigned int drif1_data0_c_pins[] = {
1953 /* D0 */
1954 RCAR_GP_PIN(5, 6),
1955};
1956static const unsigned int drif1_data0_c_mux[] = {
1957 RIF1_D0_C_MARK,
1958};
1959static const unsigned int drif1_data1_c_pins[] = {
1960 /* D1 */
1961 RCAR_GP_PIN(5, 10),
1962};
1963static const unsigned int drif1_data1_c_mux[] = {
1964 RIF1_D1_C_MARK,
1965};
1966/* - DRIF2 --------------------------------------------------------------- */
1967static const unsigned int drif2_ctrl_a_pins[] = {
1968 /* CLK, SYNC */
1969 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1970};
1971static const unsigned int drif2_ctrl_a_mux[] = {
1972 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1973};
1974static const unsigned int drif2_data0_a_pins[] = {
1975 /* D0 */
1976 RCAR_GP_PIN(6, 7),
1977};
1978static const unsigned int drif2_data0_a_mux[] = {
1979 RIF2_D0_A_MARK,
1980};
1981static const unsigned int drif2_data1_a_pins[] = {
1982 /* D1 */
1983 RCAR_GP_PIN(6, 10),
1984};
1985static const unsigned int drif2_data1_a_mux[] = {
1986 RIF2_D1_A_MARK,
1987};
1988static const unsigned int drif2_ctrl_b_pins[] = {
1989 /* CLK, SYNC */
1990 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1991};
1992static const unsigned int drif2_ctrl_b_mux[] = {
1993 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1994};
1995static const unsigned int drif2_data0_b_pins[] = {
1996 /* D0 */
1997 RCAR_GP_PIN(6, 30),
1998};
1999static const unsigned int drif2_data0_b_mux[] = {
2000 RIF2_D0_B_MARK,
2001};
2002static const unsigned int drif2_data1_b_pins[] = {
2003 /* D1 */
2004 RCAR_GP_PIN(6, 31),
2005};
2006static const unsigned int drif2_data1_b_mux[] = {
2007 RIF2_D1_B_MARK,
2008};
2009/* - DRIF3 --------------------------------------------------------------- */
2010static const unsigned int drif3_ctrl_a_pins[] = {
2011 /* CLK, SYNC */
2012 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2013};
2014static const unsigned int drif3_ctrl_a_mux[] = {
2015 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2016};
2017static const unsigned int drif3_data0_a_pins[] = {
2018 /* D0 */
2019 RCAR_GP_PIN(6, 19),
2020};
2021static const unsigned int drif3_data0_a_mux[] = {
2022 RIF3_D0_A_MARK,
2023};
2024static const unsigned int drif3_data1_a_pins[] = {
2025 /* D1 */
2026 RCAR_GP_PIN(6, 20),
2027};
2028static const unsigned int drif3_data1_a_mux[] = {
2029 RIF3_D1_A_MARK,
2030};
2031static const unsigned int drif3_ctrl_b_pins[] = {
2032 /* CLK, SYNC */
2033 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2034};
2035static const unsigned int drif3_ctrl_b_mux[] = {
2036 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2037};
2038static const unsigned int drif3_data0_b_pins[] = {
2039 /* D0 */
2040 RCAR_GP_PIN(6, 28),
2041};
2042static const unsigned int drif3_data0_b_mux[] = {
2043 RIF3_D0_B_MARK,
2044};
2045static const unsigned int drif3_data1_b_pins[] = {
2046 /* D1 */
2047 RCAR_GP_PIN(6, 29),
2048};
2049static const unsigned int drif3_data1_b_mux[] = {
2050 RIF3_D1_B_MARK,
2051};
2052
a20a6585
LP		 2053/* - DU --------------------------------------------------------------------- */
2054static const unsigned int du_rgb666_pins[] = {
2055 /* R[7:2], G[7:2], B[7:2] */
2056 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2057 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2058 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2059 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2060 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2061 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2062};
2063static const unsigned int du_rgb666_mux[] = {
2064 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2065 DU_DR3_MARK, DU_DR2_MARK,
2066 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2067 DU_DG3_MARK, DU_DG2_MARK,
2068 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2069 DU_DB3_MARK, DU_DB2_MARK,
2070};
2071static const unsigned int du_rgb888_pins[] = {
2072 /* R[7:0], G[7:0], B[7:0] */
2073 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2074 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2075 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2076 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2077 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2078 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2079 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2080 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2081 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2082};
2083static const unsigned int du_rgb888_mux[] = {
2084 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2085 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2086 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2087 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2088 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2089 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2090};
2091static const unsigned int du_clk_out_0_pins[] = {
2092 /* CLKOUT */
2093 RCAR_GP_PIN(1, 27),
2094};
2095static const unsigned int du_clk_out_0_mux[] = {
2096 DU_DOTCLKOUT0_MARK
2097};
2098static const unsigned int du_clk_out_1_pins[] = {
2099 /* CLKOUT */
2100 RCAR_GP_PIN(2, 3),
2101};
2102static const unsigned int du_clk_out_1_mux[] = {
2103 DU_DOTCLKOUT1_MARK
2104};
2105static const unsigned int du_sync_pins[] = {
2106 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2107 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2108};
2109static const unsigned int du_sync_mux[] = {
2110 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2111};
2112static const unsigned int du_oddf_pins[] = {
2113 /* EXDISP/EXODDF/EXCDE */
2114 RCAR_GP_PIN(2, 2),
2115};
2116static const unsigned int du_oddf_mux[] = {
2117 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2118};
2119static const unsigned int du_cde_pins[] = {
2120 /* CDE */
2121 RCAR_GP_PIN(2, 0),
2122};
2123static const unsigned int du_cde_mux[] = {
2124 DU_CDE_MARK,
2125};
2126static const unsigned int du_disp_pins[] = {
2127 /* DISP */
2128 RCAR_GP_PIN(2, 1),
2129};
2130static const unsigned int du_disp_mux[] = {
2131 DU_DISP_MARK,
2132};
2133
5722110e
TK		 2134/* - HDMI ------------------------------------------------------------------- */
2135static const unsigned int hdmi0_cec_pins[] = {
2136 /* HDMI0_CEC */
2137 RCAR_GP_PIN(7, 2),
2138};
2139static const unsigned int hdmi0_cec_mux[] = {
2140 HDMI0_CEC_MARK,
2141};
2142static const unsigned int hdmi1_cec_pins[] = {
2143 /* HDMI1_CEC */
2144 RCAR_GP_PIN(7, 3),
2145};
2146static const unsigned int hdmi1_cec_mux[] = {
2147 HDMI1_CEC_MARK,
2148};
2149
7a362e34
WS		 2150/* - HSCIF0 ----------------------------------------------------------------- */
2151static const unsigned int hscif0_data_pins[] = {
2152 /* RX, TX */
2153 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2154};
2155static const unsigned int hscif0_data_mux[] = {
2156 HRX0_MARK, HTX0_MARK,
2157};
2158static const unsigned int hscif0_clk_pins[] = {
2159 /* SCK */
2160 RCAR_GP_PIN(5, 12),
2161};
2162static const unsigned int hscif0_clk_mux[] = {
2163 HSCK0_MARK,
2164};
2165static const unsigned int hscif0_ctrl_pins[] = {
2166 /* RTS, CTS */
2167 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2168};
2169static const unsigned int hscif0_ctrl_mux[] = {
2170 HRTS0_N_MARK, HCTS0_N_MARK,
2171};
2172/* - HSCIF1 ----------------------------------------------------------------- */
2173static const unsigned int hscif1_data_a_pins[] = {
2174 /* RX, TX */
2175 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2176};
2177static const unsigned int hscif1_data_a_mux[] = {
2178 HRX1_A_MARK, HTX1_A_MARK,
2179};
2180static const unsigned int hscif1_clk_a_pins[] = {
2181 /* SCK */
2182 RCAR_GP_PIN(6, 21),
2183};
2184static const unsigned int hscif1_clk_a_mux[] = {
2185 HSCK1_A_MARK,
2186};
2187static const unsigned int hscif1_ctrl_a_pins[] = {
2188 /* RTS, CTS */
2189 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2190};
2191static const unsigned int hscif1_ctrl_a_mux[] = {
2192 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2193};
2194
2195static const unsigned int hscif1_data_b_pins[] = {
2196 /* RX, TX */
2197 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2198};
2199static const unsigned int hscif1_data_b_mux[] = {
2200 HRX1_B_MARK, HTX1_B_MARK,
2201};
2202static const unsigned int hscif1_clk_b_pins[] = {
2203 /* SCK */
2204 RCAR_GP_PIN(5, 0),
2205};
2206static const unsigned int hscif1_clk_b_mux[] = {
2207 HSCK1_B_MARK,
2208};
2209static const unsigned int hscif1_ctrl_b_pins[] = {
2210 /* RTS, CTS */
2211 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2212};
2213static const unsigned int hscif1_ctrl_b_mux[] = {
2214 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2215};
2216/* - HSCIF2 ----------------------------------------------------------------- */
2217static const unsigned int hscif2_data_a_pins[] = {
2218 /* RX, TX */
2219 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2220};
2221static const unsigned int hscif2_data_a_mux[] = {
2222 HRX2_A_MARK, HTX2_A_MARK,
2223};
2224static const unsigned int hscif2_clk_a_pins[] = {
2225 /* SCK */
2226 RCAR_GP_PIN(6, 10),
2227};
2228static const unsigned int hscif2_clk_a_mux[] = {
2229 HSCK2_A_MARK,
2230};
2231static const unsigned int hscif2_ctrl_a_pins[] = {
2232 /* RTS, CTS */
2233 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2234};
2235static const unsigned int hscif2_ctrl_a_mux[] = {
2236 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2237};
2238
2239static const unsigned int hscif2_data_b_pins[] = {
2240 /* RX, TX */
2241 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2242};
2243static const unsigned int hscif2_data_b_mux[] = {
2244 HRX2_B_MARK, HTX2_B_MARK,
2245};
2246static const unsigned int hscif2_clk_b_pins[] = {
2247 /* SCK */
2248 RCAR_GP_PIN(6, 21),
2249};
2250static const unsigned int hscif2_clk_b_mux[] = {
2251 HSCK2_B_MARK,
2252};
2253static const unsigned int hscif2_ctrl_b_pins[] = {
2254 /* RTS, CTS */
2255 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2256};
2257static const unsigned int hscif2_ctrl_b_mux[] = {
2258 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2259};
2260
2261static const unsigned int hscif2_data_c_pins[] = {
2262 /* RX, TX */
2263 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2264};
2265static const unsigned int hscif2_data_c_mux[] = {
2266 HRX2_C_MARK, HTX2_C_MARK,
2267};
2268static const unsigned int hscif2_clk_c_pins[] = {
2269 /* SCK */
2270 RCAR_GP_PIN(6, 24),
2271};
2272static const unsigned int hscif2_clk_c_mux[] = {
2273 HSCK2_C_MARK,
2274};
2275static const unsigned int hscif2_ctrl_c_pins[] = {
2276 /* RTS, CTS */
2277 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2278};
2279static const unsigned int hscif2_ctrl_c_mux[] = {
2280 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2281};
2282/* - HSCIF3 ----------------------------------------------------------------- */
2283static const unsigned int hscif3_data_a_pins[] = {
2284 /* RX, TX */
2285 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2286};
2287static const unsigned int hscif3_data_a_mux[] = {
2288 HRX3_A_MARK, HTX3_A_MARK,
2289};
2290static const unsigned int hscif3_clk_pins[] = {
2291 /* SCK */
2292 RCAR_GP_PIN(1, 22),
2293};
2294static const unsigned int hscif3_clk_mux[] = {
2295 HSCK3_MARK,
2296};
2297static const unsigned int hscif3_ctrl_pins[] = {
2298 /* RTS, CTS */
2299 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2300};
2301static const unsigned int hscif3_ctrl_mux[] = {
2302 HRTS3_N_MARK, HCTS3_N_MARK,
2303};
2304
2305static const unsigned int hscif3_data_b_pins[] = {
2306 /* RX, TX */
2307 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2308};
2309static const unsigned int hscif3_data_b_mux[] = {
2310 HRX3_B_MARK, HTX3_B_MARK,
2311};
2312static const unsigned int hscif3_data_c_pins[] = {
2313 /* RX, TX */
2314 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2315};
2316static const unsigned int hscif3_data_c_mux[] = {
2317 HRX3_C_MARK, HTX3_C_MARK,
2318};
2319static const unsigned int hscif3_data_d_pins[] = {
2320 /* RX, TX */
2321 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2322};
2323static const unsigned int hscif3_data_d_mux[] = {
2324 HRX3_D_MARK, HTX3_D_MARK,
2325};
2326/* - HSCIF4 ----------------------------------------------------------------- */
2327static const unsigned int hscif4_data_a_pins[] = {
2328 /* RX, TX */
2329 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2330};
2331static const unsigned int hscif4_data_a_mux[] = {
2332 HRX4_A_MARK, HTX4_A_MARK,
2333};
2334static const unsigned int hscif4_clk_pins[] = {
2335 /* SCK */
2336 RCAR_GP_PIN(1, 11),
2337};
2338static const unsigned int hscif4_clk_mux[] = {
2339 HSCK4_MARK,
2340};
2341static const unsigned int hscif4_ctrl_pins[] = {
2342 /* RTS, CTS */
2343 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2344};
2345static const unsigned int hscif4_ctrl_mux[] = {
2346 HRTS4_N_MARK, HCTS4_N_MARK,
2347};
2348
2349static const unsigned int hscif4_data_b_pins[] = {
2350 /* RX, TX */
2351 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2352};
2353static const unsigned int hscif4_data_b_mux[] = {
2354 HRX4_B_MARK, HTX4_B_MARK,
2355};
2356
f62d4c9e 2357/* - I2C -------------------------------------------------------------------- */
100431b6
TK		 2358static const unsigned int i2c0_pins[] = {
2359 /* SCL, SDA */
2360 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2361};
2362
2363static const unsigned int i2c0_mux[] = {
2364 SCL0_MARK, SDA0_MARK,
2365};
2366
f62d4c9e
WS		 2367static const unsigned int i2c1_a_pins[] = {
2368 /* SDA, SCL */
2369 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2370};
2371static const unsigned int i2c1_a_mux[] = {
2372 SDA1_A_MARK, SCL1_A_MARK,
2373};
2374static const unsigned int i2c1_b_pins[] = {
2375 /* SDA, SCL */
2376 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2377};
2378static const unsigned int i2c1_b_mux[] = {
2379 SDA1_B_MARK, SCL1_B_MARK,
2380};
2381static const unsigned int i2c2_a_pins[] = {
2382 /* SDA, SCL */
2383 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2384};
2385static const unsigned int i2c2_a_mux[] = {
2386 SDA2_A_MARK, SCL2_A_MARK,
2387};
2388static const unsigned int i2c2_b_pins[] = {
2389 /* SDA, SCL */
2390 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2391};
2392static const unsigned int i2c2_b_mux[] = {
2393 SDA2_B_MARK, SCL2_B_MARK,
2394};
100431b6
TK		 2395
2396static const unsigned int i2c3_pins[] = {
2397 /* SCL, SDA */
2398 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2399};
2400
2401static const unsigned int i2c3_mux[] = {
2402 SCL3_MARK, SDA3_MARK,
2403};
2404
2405static const unsigned int i2c5_pins[] = {
2406 /* SCL, SDA */
2407 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
2408};
2409
2410static const unsigned int i2c5_mux[] = {
2411 SCL5_MARK, SDA5_MARK,
2412};
2413
f62d4c9e
WS		 2414static const unsigned int i2c6_a_pins[] = {
2415 /* SDA, SCL */
2416 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2417};
2418static const unsigned int i2c6_a_mux[] = {
2419 SDA6_A_MARK, SCL6_A_MARK,
2420};
2421static const unsigned int i2c6_b_pins[] = {
2422 /* SDA, SCL */
2423 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2424};
2425static const unsigned int i2c6_b_mux[] = {
2426 SDA6_B_MARK, SCL6_B_MARK,
2427};
2428static const unsigned int i2c6_c_pins[] = {
2429 /* SDA, SCL */
2430 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2431};
2432static const unsigned int i2c6_c_mux[] = {
2433 SDA6_C_MARK, SCL6_C_MARK,
2434};
2435
8480e6ca
GU		 2436/* - INTC-EX ---------------------------------------------------------------- */
2437static const unsigned int intc_ex_irq0_pins[] = {
2438 /* IRQ0 */
2439 RCAR_GP_PIN(2, 0),
2440};
2441static const unsigned int intc_ex_irq0_mux[] = {
2442 IRQ0_MARK,
2443};
2444static const unsigned int intc_ex_irq1_pins[] = {
2445 /* IRQ1 */
2446 RCAR_GP_PIN(2, 1),
2447};
2448static const unsigned int intc_ex_irq1_mux[] = {
2449 IRQ1_MARK,
2450};
2451static const unsigned int intc_ex_irq2_pins[] = {
2452 /* IRQ2 */
2453 RCAR_GP_PIN(2, 2),
2454};
2455static const unsigned int intc_ex_irq2_mux[] = {
2456 IRQ2_MARK,
2457};
2458static const unsigned int intc_ex_irq3_pins[] = {
2459 /* IRQ3 */
2460 RCAR_GP_PIN(2, 3),
2461};
2462static const unsigned int intc_ex_irq3_mux[] = {
2463 IRQ3_MARK,
2464};
2465static const unsigned int intc_ex_irq4_pins[] = {
2466 /* IRQ4 */
2467 RCAR_GP_PIN(2, 4),
2468};
2469static const unsigned int intc_ex_irq4_mux[] = {
2470 IRQ4_MARK,
2471};
2472static const unsigned int intc_ex_irq5_pins[] = {
2473 /* IRQ5 */
2474 RCAR_GP_PIN(2, 5),
2475};
2476static const unsigned int intc_ex_irq5_mux[] = {
2477 IRQ5_MARK,
2478};
2479
3e6c7727
GU		 2480/* - MSIOF0 ----------------------------------------------------------------- */
2481static const unsigned int msiof0_clk_pins[] = {
2482 /* SCK */
2483 RCAR_GP_PIN(5, 17),
2484};
2485static const unsigned int msiof0_clk_mux[] = {
2486 MSIOF0_SCK_MARK,
2487};
2488static const unsigned int msiof0_sync_pins[] = {
2489 /* SYNC */
2490 RCAR_GP_PIN(5, 18),
2491};
2492static const unsigned int msiof0_sync_mux[] = {
2493 MSIOF0_SYNC_MARK,
2494};
2495static const unsigned int msiof0_ss1_pins[] = {
2496 /* SS1 */
2497 RCAR_GP_PIN(5, 19),
2498};
2499static const unsigned int msiof0_ss1_mux[] = {
2500 MSIOF0_SS1_MARK,
2501};
2502static const unsigned int msiof0_ss2_pins[] = {
2503 /* SS2 */
2504 RCAR_GP_PIN(5, 21),
2505};
2506static const unsigned int msiof0_ss2_mux[] = {
2507 MSIOF0_SS2_MARK,
2508};
2509static const unsigned int msiof0_txd_pins[] = {
2510 /* TXD */
2511 RCAR_GP_PIN(5, 20),
2512};
2513static const unsigned int msiof0_txd_mux[] = {
2514 MSIOF0_TXD_MARK,
2515};
2516static const unsigned int msiof0_rxd_pins[] = {
2517 /* RXD */
2518 RCAR_GP_PIN(5, 22),
2519};
2520static const unsigned int msiof0_rxd_mux[] = {
2521 MSIOF0_RXD_MARK,
2522};
2523/* - MSIOF1 ----------------------------------------------------------------- */
2524static const unsigned int msiof1_clk_a_pins[] = {
2525 /* SCK */
2526 RCAR_GP_PIN(6, 8),
2527};
2528static const unsigned int msiof1_clk_a_mux[] = {
2529 MSIOF1_SCK_A_MARK,
2530};
2531static const unsigned int msiof1_sync_a_pins[] = {
2532 /* SYNC */
2533 RCAR_GP_PIN(6, 9),
2534};
2535static const unsigned int msiof1_sync_a_mux[] = {
2536 MSIOF1_SYNC_A_MARK,
2537};
2538static const unsigned int msiof1_ss1_a_pins[] = {
2539 /* SS1 */
2540 RCAR_GP_PIN(6, 5),
2541};
2542static const unsigned int msiof1_ss1_a_mux[] = {
2543 MSIOF1_SS1_A_MARK,
2544};
2545static const unsigned int msiof1_ss2_a_pins[] = {
2546 /* SS2 */
2547 RCAR_GP_PIN(6, 6),
2548};
2549static const unsigned int msiof1_ss2_a_mux[] = {
2550 MSIOF1_SS2_A_MARK,
2551};
2552static const unsigned int msiof1_txd_a_pins[] = {
2553 /* TXD */
2554 RCAR_GP_PIN(6, 7),
2555};
2556static const unsigned int msiof1_txd_a_mux[] = {
2557 MSIOF1_TXD_A_MARK,
2558};
2559static const unsigned int msiof1_rxd_a_pins[] = {
2560 /* RXD */
2561 RCAR_GP_PIN(6, 10),
2562};
2563static const unsigned int msiof1_rxd_a_mux[] = {
2564 MSIOF1_RXD_A_MARK,
2565};
2566static const unsigned int msiof1_clk_b_pins[] = {
2567 /* SCK */
2568 RCAR_GP_PIN(5, 9),
2569};
2570static const unsigned int msiof1_clk_b_mux[] = {
2571 MSIOF1_SCK_B_MARK,
2572};
2573static const unsigned int msiof1_sync_b_pins[] = {
2574 /* SYNC */
2575 RCAR_GP_PIN(5, 3),
2576};
2577static const unsigned int msiof1_sync_b_mux[] = {
2578 MSIOF1_SYNC_B_MARK,
2579};
2580static const unsigned int msiof1_ss1_b_pins[] = {
2581 /* SS1 */
2582 RCAR_GP_PIN(5, 4),
2583};
2584static const unsigned int msiof1_ss1_b_mux[] = {
2585 MSIOF1_SS1_B_MARK,
2586};
2587static const unsigned int msiof1_ss2_b_pins[] = {
2588 /* SS2 */
2589 RCAR_GP_PIN(5, 0),
2590};
2591static const unsigned int msiof1_ss2_b_mux[] = {
2592 MSIOF1_SS2_B_MARK,
2593};
2594static const unsigned int msiof1_txd_b_pins[] = {
2595 /* TXD */
2596 RCAR_GP_PIN(5, 8),
2597};
2598static const unsigned int msiof1_txd_b_mux[] = {
2599 MSIOF1_TXD_B_MARK,
2600};
2601static const unsigned int msiof1_rxd_b_pins[] = {
2602 /* RXD */
2603 RCAR_GP_PIN(5, 7),
2604};
2605static const unsigned int msiof1_rxd_b_mux[] = {
2606 MSIOF1_RXD_B_MARK,
2607};
2608static const unsigned int msiof1_clk_c_pins[] = {
2609 /* SCK */
2610 RCAR_GP_PIN(6, 17),
2611};
2612static const unsigned int msiof1_clk_c_mux[] = {
2613 MSIOF1_SCK_C_MARK,
2614};
2615static const unsigned int msiof1_sync_c_pins[] = {
2616 /* SYNC */
2617 RCAR_GP_PIN(6, 18),
2618};
2619static const unsigned int msiof1_sync_c_mux[] = {
2620 MSIOF1_SYNC_C_MARK,
2621};
2622static const unsigned int msiof1_ss1_c_pins[] = {
2623 /* SS1 */
2624 RCAR_GP_PIN(6, 21),
2625};
2626static const unsigned int msiof1_ss1_c_mux[] = {
2627 MSIOF1_SS1_C_MARK,
2628};
2629static const unsigned int msiof1_ss2_c_pins[] = {
2630 /* SS2 */
2631 RCAR_GP_PIN(6, 27),
2632};
2633static const unsigned int msiof1_ss2_c_mux[] = {
2634 MSIOF1_SS2_C_MARK,
2635};
2636static const unsigned int msiof1_txd_c_pins[] = {
2637 /* TXD */
2638 RCAR_GP_PIN(6, 20),
2639};
2640static const unsigned int msiof1_txd_c_mux[] = {
2641 MSIOF1_TXD_C_MARK,
2642};
2643static const unsigned int msiof1_rxd_c_pins[] = {
2644 /* RXD */
2645 RCAR_GP_PIN(6, 19),
2646};
2647static const unsigned int msiof1_rxd_c_mux[] = {
2648 MSIOF1_RXD_C_MARK,
2649};
2650static const unsigned int msiof1_clk_d_pins[] = {
2651 /* SCK */
2652 RCAR_GP_PIN(5, 12),
2653};
2654static const unsigned int msiof1_clk_d_mux[] = {
2655 MSIOF1_SCK_D_MARK,
2656};
2657static const unsigned int msiof1_sync_d_pins[] = {
2658 /* SYNC */
2659 RCAR_GP_PIN(5, 15),
2660};
2661static const unsigned int msiof1_sync_d_mux[] = {
2662 MSIOF1_SYNC_D_MARK,
2663};
2664static const unsigned int msiof1_ss1_d_pins[] = {
2665 /* SS1 */
2666 RCAR_GP_PIN(5, 16),
2667};
2668static const unsigned int msiof1_ss1_d_mux[] = {
2669 MSIOF1_SS1_D_MARK,
2670};
2671static const unsigned int msiof1_ss2_d_pins[] = {
2672 /* SS2 */
2673 RCAR_GP_PIN(5, 21),
2674};
2675static const unsigned int msiof1_ss2_d_mux[] = {
2676 MSIOF1_SS2_D_MARK,
2677};
2678static const unsigned int msiof1_txd_d_pins[] = {
2679 /* TXD */
2680 RCAR_GP_PIN(5, 14),
2681};
2682static const unsigned int msiof1_txd_d_mux[] = {
2683 MSIOF1_TXD_D_MARK,
2684};
2685static const unsigned int msiof1_rxd_d_pins[] = {
2686 /* RXD */
2687 RCAR_GP_PIN(5, 13),
2688};
2689static const unsigned int msiof1_rxd_d_mux[] = {
2690 MSIOF1_RXD_D_MARK,
2691};
2692static const unsigned int msiof1_clk_e_pins[] = {
2693 /* SCK */
2694 RCAR_GP_PIN(3, 0),
2695};
2696static const unsigned int msiof1_clk_e_mux[] = {
2697 MSIOF1_SCK_E_MARK,
2698};
2699static const unsigned int msiof1_sync_e_pins[] = {
2700 /* SYNC */
2701 RCAR_GP_PIN(3, 1),
2702};
2703static const unsigned int msiof1_sync_e_mux[] = {
2704 MSIOF1_SYNC_E_MARK,
2705};
2706static const unsigned int msiof1_ss1_e_pins[] = {
2707 /* SS1 */
2708 RCAR_GP_PIN(3, 4),
2709};
2710static const unsigned int msiof1_ss1_e_mux[] = {
2711 MSIOF1_SS1_E_MARK,
2712};
2713static const unsigned int msiof1_ss2_e_pins[] = {
2714 /* SS2 */
2715 RCAR_GP_PIN(3, 5),
2716};
2717static const unsigned int msiof1_ss2_e_mux[] = {
2718 MSIOF1_SS2_E_MARK,
2719};
2720static const unsigned int msiof1_txd_e_pins[] = {
2721 /* TXD */
2722 RCAR_GP_PIN(3, 3),
2723};
2724static const unsigned int msiof1_txd_e_mux[] = {
2725 MSIOF1_TXD_E_MARK,
2726};
2727static const unsigned int msiof1_rxd_e_pins[] = {
2728 /* RXD */
2729 RCAR_GP_PIN(3, 2),
2730};
2731static const unsigned int msiof1_rxd_e_mux[] = {
2732 MSIOF1_RXD_E_MARK,
2733};
2734static const unsigned int msiof1_clk_f_pins[] = {
2735 /* SCK */
2736 RCAR_GP_PIN(5, 23),
2737};
2738static const unsigned int msiof1_clk_f_mux[] = {
2739 MSIOF1_SCK_F_MARK,
2740};
2741static const unsigned int msiof1_sync_f_pins[] = {
2742 /* SYNC */
2743 RCAR_GP_PIN(5, 24),
2744};
2745static const unsigned int msiof1_sync_f_mux[] = {
2746 MSIOF1_SYNC_F_MARK,
2747};
2748static const unsigned int msiof1_ss1_f_pins[] = {
2749 /* SS1 */
2750 RCAR_GP_PIN(6, 1),
2751};
2752static const unsigned int msiof1_ss1_f_mux[] = {
2753 MSIOF1_SS1_F_MARK,
2754};
2755static const unsigned int msiof1_ss2_f_pins[] = {
2756 /* SS2 */
2757 RCAR_GP_PIN(6, 2),
2758};
2759static const unsigned int msiof1_ss2_f_mux[] = {
2760 MSIOF1_SS2_F_MARK,
2761};
2762static const unsigned int msiof1_txd_f_pins[] = {
2763 /* TXD */
2764 RCAR_GP_PIN(6, 0),
2765};
2766static const unsigned int msiof1_txd_f_mux[] = {
2767 MSIOF1_TXD_F_MARK,
2768};
2769static const unsigned int msiof1_rxd_f_pins[] = {
2770 /* RXD */
2771 RCAR_GP_PIN(5, 25),
2772};
2773static const unsigned int msiof1_rxd_f_mux[] = {
2774 MSIOF1_RXD_F_MARK,
2775};
2776static const unsigned int msiof1_clk_g_pins[] = {
2777 /* SCK */
2778 RCAR_GP_PIN(3, 6),
2779};
2780static const unsigned int msiof1_clk_g_mux[] = {
2781 MSIOF1_SCK_G_MARK,
2782};
2783static const unsigned int msiof1_sync_g_pins[] = {
2784 /* SYNC */
2785 RCAR_GP_PIN(3, 7),
2786};
2787static const unsigned int msiof1_sync_g_mux[] = {
2788 MSIOF1_SYNC_G_MARK,
2789};
2790static const unsigned int msiof1_ss1_g_pins[] = {
2791 /* SS1 */
2792 RCAR_GP_PIN(3, 10),
2793};
2794static const unsigned int msiof1_ss1_g_mux[] = {
2795 MSIOF1_SS1_G_MARK,
2796};
2797static const unsigned int msiof1_ss2_g_pins[] = {
2798 /* SS2 */
2799 RCAR_GP_PIN(3, 11),
2800};
2801static const unsigned int msiof1_ss2_g_mux[] = {
2802 MSIOF1_SS2_G_MARK,
2803};
2804static const unsigned int msiof1_txd_g_pins[] = {
2805 /* TXD */
2806 RCAR_GP_PIN(3, 9),
2807};
2808static const unsigned int msiof1_txd_g_mux[] = {
2809 MSIOF1_TXD_G_MARK,
2810};
2811static const unsigned int msiof1_rxd_g_pins[] = {
2812 /* RXD */
2813 RCAR_GP_PIN(3, 8),
2814};
2815static const unsigned int msiof1_rxd_g_mux[] = {
2816 MSIOF1_RXD_G_MARK,
2817};
2818/* - MSIOF2 ----------------------------------------------------------------- */
2819static const unsigned int msiof2_clk_a_pins[] = {
2820 /* SCK */
2821 RCAR_GP_PIN(1, 9),
2822};
2823static const unsigned int msiof2_clk_a_mux[] = {
2824 MSIOF2_SCK_A_MARK,
2825};
2826static const unsigned int msiof2_sync_a_pins[] = {
2827 /* SYNC */
2828 RCAR_GP_PIN(1, 8),
2829};
2830static const unsigned int msiof2_sync_a_mux[] = {
2831 MSIOF2_SYNC_A_MARK,
2832};
2833static const unsigned int msiof2_ss1_a_pins[] = {
2834 /* SS1 */
2835 RCAR_GP_PIN(1, 6),
2836};
2837static const unsigned int msiof2_ss1_a_mux[] = {
2838 MSIOF2_SS1_A_MARK,
2839};
2840static const unsigned int msiof2_ss2_a_pins[] = {
2841 /* SS2 */
2842 RCAR_GP_PIN(1, 7),
2843};
2844static const unsigned int msiof2_ss2_a_mux[] = {
2845 MSIOF2_SS2_A_MARK,
2846};
2847static const unsigned int msiof2_txd_a_pins[] = {
2848 /* TXD */
2849 RCAR_GP_PIN(1, 11),
2850};
2851static const unsigned int msiof2_txd_a_mux[] = {
2852 MSIOF2_TXD_A_MARK,
2853};
2854static const unsigned int msiof2_rxd_a_pins[] = {
2855 /* RXD */
2856 RCAR_GP_PIN(1, 10),
2857};
2858static const unsigned int msiof2_rxd_a_mux[] = {
2859 MSIOF2_RXD_A_MARK,
2860};
2861static const unsigned int msiof2_clk_b_pins[] = {
2862 /* SCK */
2863 RCAR_GP_PIN(0, 4),
2864};
2865static const unsigned int msiof2_clk_b_mux[] = {
2866 MSIOF2_SCK_B_MARK,
2867};
2868static const unsigned int msiof2_sync_b_pins[] = {
2869 /* SYNC */
2870 RCAR_GP_PIN(0, 5),
2871};
2872static const unsigned int msiof2_sync_b_mux[] = {
2873 MSIOF2_SYNC_B_MARK,
2874};
2875static const unsigned int msiof2_ss1_b_pins[] = {
2876 /* SS1 */
2877 RCAR_GP_PIN(0, 0),
2878};
2879static const unsigned int msiof2_ss1_b_mux[] = {
2880 MSIOF2_SS1_B_MARK,
2881};
2882static const unsigned int msiof2_ss2_b_pins[] = {
2883 /* SS2 */
2884 RCAR_GP_PIN(0, 1),
2885};
2886static const unsigned int msiof2_ss2_b_mux[] = {
2887 MSIOF2_SS2_B_MARK,
2888};
2889static const unsigned int msiof2_txd_b_pins[] = {
2890 /* TXD */
2891 RCAR_GP_PIN(0, 7),
2892};
2893static const unsigned int msiof2_txd_b_mux[] = {
2894 MSIOF2_TXD_B_MARK,
2895};
2896static const unsigned int msiof2_rxd_b_pins[] = {
2897 /* RXD */
2898 RCAR_GP_PIN(0, 6),
2899};
2900static const unsigned int msiof2_rxd_b_mux[] = {
2901 MSIOF2_RXD_B_MARK,
2902};
2903static const unsigned int msiof2_clk_c_pins[] = {
2904 /* SCK */
2905 RCAR_GP_PIN(2, 12),
2906};
2907static const unsigned int msiof2_clk_c_mux[] = {
2908 MSIOF2_SCK_C_MARK,
2909};
2910static const unsigned int msiof2_sync_c_pins[] = {
2911 /* SYNC */
2912 RCAR_GP_PIN(2, 11),
2913};
2914static const unsigned int msiof2_sync_c_mux[] = {
2915 MSIOF2_SYNC_C_MARK,
2916};
2917static const unsigned int msiof2_ss1_c_pins[] = {
2918 /* SS1 */
2919 RCAR_GP_PIN(2, 10),
2920};
2921static const unsigned int msiof2_ss1_c_mux[] = {
2922 MSIOF2_SS1_C_MARK,
2923};
2924static const unsigned int msiof2_ss2_c_pins[] = {
2925 /* SS2 */
2926 RCAR_GP_PIN(2, 9),
2927};
2928static const unsigned int msiof2_ss2_c_mux[] = {
2929 MSIOF2_SS2_C_MARK,
2930};
2931static const unsigned int msiof2_txd_c_pins[] = {
2932 /* TXD */
2933 RCAR_GP_PIN(2, 14),
2934};
2935static const unsigned int msiof2_txd_c_mux[] = {
2936 MSIOF2_TXD_C_MARK,
2937};
2938static const unsigned int msiof2_rxd_c_pins[] = {
2939 /* RXD */
2940 RCAR_GP_PIN(2, 13),
2941};
2942static const unsigned int msiof2_rxd_c_mux[] = {
2943 MSIOF2_RXD_C_MARK,
2944};
2945static const unsigned int msiof2_clk_d_pins[] = {
2946 /* SCK */
2947 RCAR_GP_PIN(0, 8),
2948};
2949static const unsigned int msiof2_clk_d_mux[] = {
2950 MSIOF2_SCK_D_MARK,
2951};
2952static const unsigned int msiof2_sync_d_pins[] = {
2953 /* SYNC */
2954 RCAR_GP_PIN(0, 9),
2955};
2956static const unsigned int msiof2_sync_d_mux[] = {
2957 MSIOF2_SYNC_D_MARK,
2958};
2959static const unsigned int msiof2_ss1_d_pins[] = {
2960 /* SS1 */
2961 RCAR_GP_PIN(0, 12),
2962};
2963static const unsigned int msiof2_ss1_d_mux[] = {
2964 MSIOF2_SS1_D_MARK,
2965};
2966static const unsigned int msiof2_ss2_d_pins[] = {
2967 /* SS2 */
2968 RCAR_GP_PIN(0, 13),
2969};
2970static const unsigned int msiof2_ss2_d_mux[] = {
2971 MSIOF2_SS2_D_MARK,
2972};
2973static const unsigned int msiof2_txd_d_pins[] = {
2974 /* TXD */
2975 RCAR_GP_PIN(0, 11),
2976};
2977static const unsigned int msiof2_txd_d_mux[] = {
2978 MSIOF2_TXD_D_MARK,
2979};
2980static const unsigned int msiof2_rxd_d_pins[] = {
2981 /* RXD */
2982 RCAR_GP_PIN(0, 10),
2983};
2984static const unsigned int msiof2_rxd_d_mux[] = {
2985 MSIOF2_RXD_D_MARK,
2986};
2987/* - MSIOF3 ----------------------------------------------------------------- */
2988static const unsigned int msiof3_clk_a_pins[] = {
2989 /* SCK */
2990 RCAR_GP_PIN(0, 0),
2991};
2992static const unsigned int msiof3_clk_a_mux[] = {
2993 MSIOF3_SCK_A_MARK,
2994};
2995static const unsigned int msiof3_sync_a_pins[] = {
2996 /* SYNC */
2997 RCAR_GP_PIN(0, 1),
2998};
2999static const unsigned int msiof3_sync_a_mux[] = {
3000 MSIOF3_SYNC_A_MARK,
3001};
3002static const unsigned int msiof3_ss1_a_pins[] = {
3003 /* SS1 */
3004 RCAR_GP_PIN(0, 14),
3005};
3006static const unsigned int msiof3_ss1_a_mux[] = {
3007 MSIOF3_SS1_A_MARK,
3008};
3009static const unsigned int msiof3_ss2_a_pins[] = {
3010 /* SS2 */
3011 RCAR_GP_PIN(0, 15),
3012};
3013static const unsigned int msiof3_ss2_a_mux[] = {
3014 MSIOF3_SS2_A_MARK,
3015};
3016static const unsigned int msiof3_txd_a_pins[] = {
3017 /* TXD */
3018 RCAR_GP_PIN(0, 3),
3019};
3020static const unsigned int msiof3_txd_a_mux[] = {
3021 MSIOF3_TXD_A_MARK,
3022};
3023static const unsigned int msiof3_rxd_a_pins[] = {
3024 /* RXD */
3025 RCAR_GP_PIN(0, 2),
3026};
3027static const unsigned int msiof3_rxd_a_mux[] = {
3028 MSIOF3_RXD_A_MARK,
3029};
3030static const unsigned int msiof3_clk_b_pins[] = {
3031 /* SCK */
3032 RCAR_GP_PIN(1, 2),
3033};
3034static const unsigned int msiof3_clk_b_mux[] = {
3035 MSIOF3_SCK_B_MARK,
3036};
3037static const unsigned int msiof3_sync_b_pins[] = {
3038 /* SYNC */
3039 RCAR_GP_PIN(1, 0),
3040};
3041static const unsigned int msiof3_sync_b_mux[] = {
3042 MSIOF3_SYNC_B_MARK,
3043};
3044static const unsigned int msiof3_ss1_b_pins[] = {
3045 /* SS1 */
3046 RCAR_GP_PIN(1, 4),
3047};
3048static const unsigned int msiof3_ss1_b_mux[] = {
3049 MSIOF3_SS1_B_MARK,
3050};
3051static const unsigned int msiof3_ss2_b_pins[] = {
3052 /* SS2 */
3053 RCAR_GP_PIN(1, 5),
3054};
3055static const unsigned int msiof3_ss2_b_mux[] = {
3056 MSIOF3_SS2_B_MARK,
3057};
3058static const unsigned int msiof3_txd_b_pins[] = {
3059 /* TXD */
3060 RCAR_GP_PIN(1, 1),
3061};
3062static const unsigned int msiof3_txd_b_mux[] = {
3063 MSIOF3_TXD_B_MARK,
3064};
3065static const unsigned int msiof3_rxd_b_pins[] = {
3066 /* RXD */
3067 RCAR_GP_PIN(1, 3),
3068};
3069static const unsigned int msiof3_rxd_b_mux[] = {
3070 MSIOF3_RXD_B_MARK,
3071};
3072static const unsigned int msiof3_clk_c_pins[] = {
3073 /* SCK */
3074 RCAR_GP_PIN(1, 12),
3075};
3076static const unsigned int msiof3_clk_c_mux[] = {
3077 MSIOF3_SCK_C_MARK,
3078};
3079static const unsigned int msiof3_sync_c_pins[] = {
3080 /* SYNC */
3081 RCAR_GP_PIN(1, 13),
3082};
3083static const unsigned int msiof3_sync_c_mux[] = {
3084 MSIOF3_SYNC_C_MARK,
3085};
3086static const unsigned int msiof3_txd_c_pins[] = {
3087 /* TXD */
3088 RCAR_GP_PIN(1, 15),
3089};
3090static const unsigned int msiof3_txd_c_mux[] = {
3091 MSIOF3_TXD_C_MARK,
3092};
3093static const unsigned int msiof3_rxd_c_pins[] = {
3094 /* RXD */
3095 RCAR_GP_PIN(1, 14),
3096};
3097static const unsigned int msiof3_rxd_c_mux[] = {
3098 MSIOF3_RXD_C_MARK,
3099};
3100static const unsigned int msiof3_clk_d_pins[] = {
3101 /* SCK */
3102 RCAR_GP_PIN(1, 22),
3103};
3104static const unsigned int msiof3_clk_d_mux[] = {
3105 MSIOF3_SCK_D_MARK,
3106};
3107static const unsigned int msiof3_sync_d_pins[] = {
3108 /* SYNC */
3109 RCAR_GP_PIN(1, 23),
3110};
3111static const unsigned int msiof3_sync_d_mux[] = {
3112 MSIOF3_SYNC_D_MARK,
3113};
3114static const unsigned int msiof3_ss1_d_pins[] = {
3115 /* SS1 */
3116 RCAR_GP_PIN(1, 26),
3117};
3118static const unsigned int msiof3_ss1_d_mux[] = {
3119 MSIOF3_SS1_D_MARK,
3120};
3121static const unsigned int msiof3_txd_d_pins[] = {
3122 /* TXD */
3123 RCAR_GP_PIN(1, 25),
3124};
3125static const unsigned int msiof3_txd_d_mux[] = {
3126 MSIOF3_TXD_D_MARK,
3127};
3128static const unsigned int msiof3_rxd_d_pins[] = {
3129 /* RXD */
3130 RCAR_GP_PIN(1, 24),
3131};
3132static const unsigned int msiof3_rxd_d_mux[] = {
3133 MSIOF3_RXD_D_MARK,
3134};
3135static const unsigned int msiof3_clk_e_pins[] = {
3136 /* SCK */
3137 RCAR_GP_PIN(2, 3),
3138};
3139static const unsigned int msiof3_clk_e_mux[] = {
3140 MSIOF3_SCK_E_MARK,
3141};
3142static const unsigned int msiof3_sync_e_pins[] = {
3143 /* SYNC */
3144 RCAR_GP_PIN(2, 2),
3145};
3146static const unsigned int msiof3_sync_e_mux[] = {
3147 MSIOF3_SYNC_E_MARK,
3148};
3149static const unsigned int msiof3_ss1_e_pins[] = {
3150 /* SS1 */
3151 RCAR_GP_PIN(2, 1),
3152};
3153static const unsigned int msiof3_ss1_e_mux[] = {
3154 MSIOF3_SS1_E_MARK,
3155};
3156static const unsigned int msiof3_ss2_e_pins[] = {
37880512 3157 /* SS2 */
3e6c7727
GU		 3158 RCAR_GP_PIN(2, 0),
3159};
3160static const unsigned int msiof3_ss2_e_mux[] = {
3161 MSIOF3_SS2_E_MARK,
3162};
3163static const unsigned int msiof3_txd_e_pins[] = {
3164 /* TXD */
3165 RCAR_GP_PIN(2, 5),
3166};
3167static const unsigned int msiof3_txd_e_mux[] = {
3168 MSIOF3_TXD_E_MARK,
3169};
3170static const unsigned int msiof3_rxd_e_pins[] = {
3171 /* RXD */
3172 RCAR_GP_PIN(2, 4),
3173};
3174static const unsigned int msiof3_rxd_e_mux[] = {
3175 MSIOF3_RXD_E_MARK,
3176};
3177
c03a133b
LP		 3178/* - PWM0 --------------------------------------------------------------------*/
3179static const unsigned int pwm0_pins[] = {
3180 /* PWM */
3181 RCAR_GP_PIN(2, 6),
3182};
3183static const unsigned int pwm0_mux[] = {
3184 PWM0_MARK,
3185};
3186/* - PWM1 --------------------------------------------------------------------*/
3187static const unsigned int pwm1_a_pins[] = {
3188 /* PWM */
3189 RCAR_GP_PIN(2, 7),
3190};
3191static const unsigned int pwm1_a_mux[] = {
3192 PWM1_A_MARK,
3193};
3194static const unsigned int pwm1_b_pins[] = {
3195 /* PWM */
3196 RCAR_GP_PIN(1, 8),
3197};
3198static const unsigned int pwm1_b_mux[] = {
3199 PWM1_B_MARK,
3200};
3201/* - PWM2 --------------------------------------------------------------------*/
3202static const unsigned int pwm2_a_pins[] = {
3203 /* PWM */
3204 RCAR_GP_PIN(2, 8),
3205};
3206static const unsigned int pwm2_a_mux[] = {
3207 PWM2_A_MARK,
3208};
3209static const unsigned int pwm2_b_pins[] = {
3210 /* PWM */
3211 RCAR_GP_PIN(1, 11),
3212};
3213static const unsigned int pwm2_b_mux[] = {
3214 PWM2_B_MARK,
3215};
3216/* - PWM3 --------------------------------------------------------------------*/
3217static const unsigned int pwm3_a_pins[] = {
3218 /* PWM */
3219 RCAR_GP_PIN(1, 0),
3220};
3221static const unsigned int pwm3_a_mux[] = {
3222 PWM3_A_MARK,
3223};
3224static const unsigned int pwm3_b_pins[] = {
3225 /* PWM */
3226 RCAR_GP_PIN(2, 2),
3227};
3228static const unsigned int pwm3_b_mux[] = {
3229 PWM3_B_MARK,
3230};
3231/* - PWM4 --------------------------------------------------------------------*/
3232static const unsigned int pwm4_a_pins[] = {
3233 /* PWM */
3234 RCAR_GP_PIN(1, 1),
3235};
3236static const unsigned int pwm4_a_mux[] = {
3237 PWM4_A_MARK,
3238};
3239static const unsigned int pwm4_b_pins[] = {
3240 /* PWM */
3241 RCAR_GP_PIN(2, 3),
3242};
3243static const unsigned int pwm4_b_mux[] = {
3244 PWM4_B_MARK,
3245};
3246/* - PWM5 --------------------------------------------------------------------*/
3247static const unsigned int pwm5_a_pins[] = {
3248 /* PWM */
3249 RCAR_GP_PIN(1, 2),
3250};
3251static const unsigned int pwm5_a_mux[] = {
3252 PWM5_A_MARK,
3253};
3254static const unsigned int pwm5_b_pins[] = {
3255 /* PWM */
3256 RCAR_GP_PIN(2, 4),
3257};
3258static const unsigned int pwm5_b_mux[] = {
3259 PWM5_B_MARK,
3260};
3261/* - PWM6 --------------------------------------------------------------------*/
3262static const unsigned int pwm6_a_pins[] = {
3263 /* PWM */
3264 RCAR_GP_PIN(1, 3),
3265};
3266static const unsigned int pwm6_a_mux[] = {
3267 PWM6_A_MARK,
3268};
3269static const unsigned int pwm6_b_pins[] = {
3270 /* PWM */
3271 RCAR_GP_PIN(2, 5),
3272};
3273static const unsigned int pwm6_b_mux[] = {
3274 PWM6_B_MARK,
3275};
3276
297e5b2b
WS		 3277/* - SATA --------------------------------------------------------------------*/
3278static const unsigned int sata0_devslp_a_pins[] = {
3279 /* DEVSLP */
3280 RCAR_GP_PIN(6, 16),
3281};
3282static const unsigned int sata0_devslp_a_mux[] = {
3283 SATA_DEVSLP_A_MARK,
3284};
3285static const unsigned int sata0_devslp_b_pins[] = {
3286 /* DEVSLP */
3287 RCAR_GP_PIN(4, 6),
3288};
3289static const unsigned int sata0_devslp_b_mux[] = {
3290 SATA_DEVSLP_B_MARK,
3291};
3292
e7ad4d3c
GU		 3293/* - SCIF0 ------------------------------------------------------------------ */
3294static const unsigned int scif0_data_pins[] = {
3295 /* RX, TX */
3296 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3297};
3298static const unsigned int scif0_data_mux[] = {
3299 RX0_MARK, TX0_MARK,
3300};
3301static const unsigned int scif0_clk_pins[] = {
3302 /* SCK */
3303 RCAR_GP_PIN(5, 0),
3304};
3305static const unsigned int scif0_clk_mux[] = {
3306 SCK0_MARK,
3307};
3308static const unsigned int scif0_ctrl_pins[] = {
3309 /* RTS, CTS */
3310 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3311};
3312static const unsigned int scif0_ctrl_mux[] = {
8714a9c1 3313 RTS0_N_MARK, CTS0_N_MARK,
e7ad4d3c
GU		 3314};
3315/* - SCIF1 ------------------------------------------------------------------ */
3316static const unsigned int scif1_data_a_pins[] = {
3317 /* RX, TX */
3318 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3319};
3320static const unsigned int scif1_data_a_mux[] = {
3321 RX1_A_MARK, TX1_A_MARK,
3322};
3323static const unsigned int scif1_clk_pins[] = {
3324 /* SCK */
3325 RCAR_GP_PIN(6, 21),
3326};
3327static const unsigned int scif1_clk_mux[] = {
3328 SCK1_MARK,
3329};
3330static const unsigned int scif1_ctrl_pins[] = {
3331 /* RTS, CTS */
3332 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3333};
3334static const unsigned int scif1_ctrl_mux[] = {
8714a9c1 3335 RTS1_N_MARK, CTS1_N_MARK,
e7ad4d3c
GU		 3336};
3337
3338static const unsigned int scif1_data_b_pins[] = {
3339 /* RX, TX */
3340 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3341};
3342static const unsigned int scif1_data_b_mux[] = {
3343 RX1_B_MARK, TX1_B_MARK,
3344};
3345/* - SCIF2 ------------------------------------------------------------------ */
3346static const unsigned int scif2_data_a_pins[] = {
3347 /* RX, TX */
3348 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3349};
3350static const unsigned int scif2_data_a_mux[] = {
3351 RX2_A_MARK, TX2_A_MARK,
3352};
3353static const unsigned int scif2_clk_pins[] = {
3354 /* SCK */
3355 RCAR_GP_PIN(5, 9),
3356};
3357static const unsigned int scif2_clk_mux[] = {
3358 SCK2_MARK,
3359};
3360static const unsigned int scif2_data_b_pins[] = {
3361 /* RX, TX */
3362 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3363};
3364static const unsigned int scif2_data_b_mux[] = {
3365 RX2_B_MARK, TX2_B_MARK,
3366};
3367/* - SCIF3 ------------------------------------------------------------------ */
3368static const unsigned int scif3_data_a_pins[] = {
3369 /* RX, TX */
3370 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3371};
3372static const unsigned int scif3_data_a_mux[] = {
3373 RX3_A_MARK, TX3_A_MARK,
3374};
3375static const unsigned int scif3_clk_pins[] = {
3376 /* SCK */
3377 RCAR_GP_PIN(1, 22),
3378};
3379static const unsigned int scif3_clk_mux[] = {
3380 SCK3_MARK,
3381};
3382static const unsigned int scif3_ctrl_pins[] = {
3383 /* RTS, CTS */
3384 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3385};
3386static const unsigned int scif3_ctrl_mux[] = {
8714a9c1 3387 RTS3_N_MARK, CTS3_N_MARK,
e7ad4d3c
GU		 3388};
3389static const unsigned int scif3_data_b_pins[] = {
3390 /* RX, TX */
3391 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3392};
3393static const unsigned int scif3_data_b_mux[] = {
3394 RX3_B_MARK, TX3_B_MARK,
3395};
3396/* - SCIF4 ------------------------------------------------------------------ */
3397static const unsigned int scif4_data_a_pins[] = {
3398 /* RX, TX */
3399 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3400};
3401static const unsigned int scif4_data_a_mux[] = {
3402 RX4_A_MARK, TX4_A_MARK,
3403};
3404static const unsigned int scif4_clk_a_pins[] = {
3405 /* SCK */
3406 RCAR_GP_PIN(2, 10),
3407};
3408static const unsigned int scif4_clk_a_mux[] = {
3409 SCK4_A_MARK,
3410};
3411static const unsigned int scif4_ctrl_a_pins[] = {
3412 /* RTS, CTS */
3413 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3414};
3415static const unsigned int scif4_ctrl_a_mux[] = {
8714a9c1 3416 RTS4_N_A_MARK, CTS4_N_A_MARK,
e7ad4d3c
GU		 3417};
3418static const unsigned int scif4_data_b_pins[] = {
3419 /* RX, TX */
3420 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3421};
3422static const unsigned int scif4_data_b_mux[] = {
3423 RX4_B_MARK, TX4_B_MARK,
3424};
3425static const unsigned int scif4_clk_b_pins[] = {
3426 /* SCK */
3427 RCAR_GP_PIN(1, 5),
3428};
3429static const unsigned int scif4_clk_b_mux[] = {
3430 SCK4_B_MARK,
3431};
3432static const unsigned int scif4_ctrl_b_pins[] = {
3433 /* RTS, CTS */
3434 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3435};
3436static const unsigned int scif4_ctrl_b_mux[] = {
8714a9c1 3437 RTS4_N_B_MARK, CTS4_N_B_MARK,
e7ad4d3c
GU		 3438};
3439static const unsigned int scif4_data_c_pins[] = {
3440 /* RX, TX */
3441 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3442};
3443static const unsigned int scif4_data_c_mux[] = {
3444 RX4_C_MARK, TX4_C_MARK,
3445};
3446static const unsigned int scif4_clk_c_pins[] = {
3447 /* SCK */
3448 RCAR_GP_PIN(0, 8),
3449};
3450static const unsigned int scif4_clk_c_mux[] = {
3451 SCK4_C_MARK,
3452};
3453static const unsigned int scif4_ctrl_c_pins[] = {
3454 /* RTS, CTS */
3455 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3456};
3457static const unsigned int scif4_ctrl_c_mux[] = {
8714a9c1 3458 RTS4_N_C_MARK, CTS4_N_C_MARK,
e7ad4d3c
GU		 3459};
3460/* - SCIF5 ------------------------------------------------------------------ */
3461static const unsigned int scif5_data_a_pins[] = {
3462 /* RX, TX */
3463 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3464};
3465static const unsigned int scif5_data_a_mux[] = {
3466 RX5_A_MARK, TX5_A_MARK,
3467};
3468static const unsigned int scif5_clk_a_pins[] = {
3469 /* SCK */
3470 RCAR_GP_PIN(6, 21),
3471};
3472static const unsigned int scif5_clk_a_mux[] = {
3473 SCK5_A_MARK,
3474};
3475static const unsigned int scif5_data_b_pins[] = {
3476 /* RX, TX */
3477 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3478};
3479static const unsigned int scif5_data_b_mux[] = {
3480 RX5_B_MARK, TX5_B_MARK,
3481};
3482static const unsigned int scif5_clk_b_pins[] = {
3483 /* SCK */
3484 RCAR_GP_PIN(5, 0),
3485};
3486static const unsigned int scif5_clk_b_mux[] = {
3487 SCK5_B_MARK,
3488};
3489
b4062b46
GU		 3490/* - SCIF Clock ------------------------------------------------------------- */
3491static const unsigned int scif_clk_a_pins[] = {
3492 /* SCIF_CLK */
3493 RCAR_GP_PIN(6, 23),
3494};
3495static const unsigned int scif_clk_a_mux[] = {
3496 SCIF_CLK_A_MARK,
3497};
3498static const unsigned int scif_clk_b_pins[] = {
3499 /* SCIF_CLK */
3500 RCAR_GP_PIN(5, 9),
3501};
3502static const unsigned int scif_clk_b_mux[] = {
3503 SCIF_CLK_B_MARK,
3504};
3505
9ed13958
TK		 3506/* - SDHI0 ------------------------------------------------------------------ */
3507static const unsigned int sdhi0_data1_pins[] = {
3508 /* D0 */
3509 RCAR_GP_PIN(3, 2),
3510};
3511static const unsigned int sdhi0_data1_mux[] = {
3512 SD0_DAT0_MARK,
3513};
3514static const unsigned int sdhi0_data4_pins[] = {
3515 /* D[0:3] */
3516 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3517 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3518};
3519static const unsigned int sdhi0_data4_mux[] = {
3520 SD0_DAT0_MARK, SD0_DAT1_MARK,
3521 SD0_DAT2_MARK, SD0_DAT3_MARK,
3522};
3523static const unsigned int sdhi0_ctrl_pins[] = {
3524 /* CLK, CMD */
3525 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3526};
3527static const unsigned int sdhi0_ctrl_mux[] = {
3528 SD0_CLK_MARK, SD0_CMD_MARK,
3529};
3530static const unsigned int sdhi0_cd_pins[] = {
3531 /* CD */
3532 RCAR_GP_PIN(3, 12),
3533};
3534static const unsigned int sdhi0_cd_mux[] = {
3535 SD0_CD_MARK,
3536};
3537static const unsigned int sdhi0_wp_pins[] = {
3538 /* WP */
3539 RCAR_GP_PIN(3, 13),
3540};
3541static const unsigned int sdhi0_wp_mux[] = {
3542 SD0_WP_MARK,
3543};
3544/* - SDHI1 ------------------------------------------------------------------ */
3545static const unsigned int sdhi1_data1_pins[] = {
3546 /* D0 */
3547 RCAR_GP_PIN(3, 8),
3548};
3549static const unsigned int sdhi1_data1_mux[] = {
3550 SD1_DAT0_MARK,
3551};
3552static const unsigned int sdhi1_data4_pins[] = {
3553 /* D[0:3] */
3554 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3555 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3556};
3557static const unsigned int sdhi1_data4_mux[] = {
3558 SD1_DAT0_MARK, SD1_DAT1_MARK,
3559 SD1_DAT2_MARK, SD1_DAT3_MARK,
3560};
3561static const unsigned int sdhi1_ctrl_pins[] = {
3562 /* CLK, CMD */
3563 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3564};
3565static const unsigned int sdhi1_ctrl_mux[] = {
3566 SD1_CLK_MARK, SD1_CMD_MARK,
3567};
3568static const unsigned int sdhi1_cd_pins[] = {
3569 /* CD */
3570 RCAR_GP_PIN(3, 14),
3571};
3572static const unsigned int sdhi1_cd_mux[] = {
3573 SD1_CD_MARK,
3574};
3575static const unsigned int sdhi1_wp_pins[] = {
3576 /* WP */
3577 RCAR_GP_PIN(3, 15),
3578};
3579static const unsigned int sdhi1_wp_mux[] = {
3580 SD1_WP_MARK,
3581};
3582/* - SDHI2 ------------------------------------------------------------------ */
3583static const unsigned int sdhi2_data1_pins[] = {
3584 /* D0 */
3585 RCAR_GP_PIN(4, 2),
3586};
3587static const unsigned int sdhi2_data1_mux[] = {
3588 SD2_DAT0_MARK,
3589};
3590static const unsigned int sdhi2_data4_pins[] = {
3591 /* D[0:3] */
3592 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3593 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3594};
3595static const unsigned int sdhi2_data4_mux[] = {
3596 SD2_DAT0_MARK, SD2_DAT1_MARK,
3597 SD2_DAT2_MARK, SD2_DAT3_MARK,
3598};
3599static const unsigned int sdhi2_data8_pins[] = {
3600 /* D[0:7] */
3601 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3602 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3603 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3604 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3605};
3606static const unsigned int sdhi2_data8_mux[] = {
3607 SD2_DAT0_MARK, SD2_DAT1_MARK,
3608 SD2_DAT2_MARK, SD2_DAT3_MARK,
3609 SD2_DAT4_MARK, SD2_DAT5_MARK,
3610 SD2_DAT6_MARK, SD2_DAT7_MARK,
3611};
3612static const unsigned int sdhi2_ctrl_pins[] = {
3613 /* CLK, CMD */
3614 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3615};
3616static const unsigned int sdhi2_ctrl_mux[] = {
3617 SD2_CLK_MARK, SD2_CMD_MARK,
3618};
3619static const unsigned int sdhi2_cd_a_pins[] = {
3620 /* CD */
3621 RCAR_GP_PIN(4, 13),
3622};
3623static const unsigned int sdhi2_cd_a_mux[] = {
3624 SD2_CD_A_MARK,
3625};
3626static const unsigned int sdhi2_cd_b_pins[] = {
3627 /* CD */
3628 RCAR_GP_PIN(5, 10),
3629};
3630static const unsigned int sdhi2_cd_b_mux[] = {
3631 SD2_CD_B_MARK,
3632};
3633static const unsigned int sdhi2_wp_a_pins[] = {
3634 /* WP */
3635 RCAR_GP_PIN(4, 14),
3636};
3637static const unsigned int sdhi2_wp_a_mux[] = {
3638 SD2_WP_A_MARK,
3639};
3640static const unsigned int sdhi2_wp_b_pins[] = {
3641 /* WP */
3642 RCAR_GP_PIN(5, 11),
3643};
3644static const unsigned int sdhi2_wp_b_mux[] = {
3645 SD2_WP_B_MARK,
3646};
3647static const unsigned int sdhi2_ds_pins[] = {
3648 /* DS */
3649 RCAR_GP_PIN(4, 6),
3650};
3651static const unsigned int sdhi2_ds_mux[] = {
3652 SD2_DS_MARK,
3653};
3654/* - SDHI3 ------------------------------------------------------------------ */
3655static const unsigned int sdhi3_data1_pins[] = {
3656 /* D0 */
3657 RCAR_GP_PIN(4, 9),
3658};
3659static const unsigned int sdhi3_data1_mux[] = {
3660 SD3_DAT0_MARK,
3661};
3662static const unsigned int sdhi3_data4_pins[] = {
3663 /* D[0:3] */
3664 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3665 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3666};
3667static const unsigned int sdhi3_data4_mux[] = {
3668 SD3_DAT0_MARK, SD3_DAT1_MARK,
3669 SD3_DAT2_MARK, SD3_DAT3_MARK,
3670};
3671static const unsigned int sdhi3_data8_pins[] = {
3672 /* D[0:7] */
3673 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3674 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3675 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3676 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3677};
3678static const unsigned int sdhi3_data8_mux[] = {
3679 SD3_DAT0_MARK, SD3_DAT1_MARK,
3680 SD3_DAT2_MARK, SD3_DAT3_MARK,
3681 SD3_DAT4_MARK, SD3_DAT5_MARK,
3682 SD3_DAT6_MARK, SD3_DAT7_MARK,
3683};
3684static const unsigned int sdhi3_ctrl_pins[] = {
3685 /* CLK, CMD */
3686 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3687};
3688static const unsigned int sdhi3_ctrl_mux[] = {
3689 SD3_CLK_MARK, SD3_CMD_MARK,
3690};
3691static const unsigned int sdhi3_cd_pins[] = {
3692 /* CD */
3693 RCAR_GP_PIN(4, 15),
3694};
3695static const unsigned int sdhi3_cd_mux[] = {
3696 SD3_CD_MARK,
3697};
3698static const unsigned int sdhi3_wp_pins[] = {
3699 /* WP */
3700 RCAR_GP_PIN(4, 16),
3701};
3702static const unsigned int sdhi3_wp_mux[] = {
3703 SD3_WP_MARK,
3704};
3705static const unsigned int sdhi3_ds_pins[] = {
3706 /* DS */
3707 RCAR_GP_PIN(4, 17),
3708};
3709static const unsigned int sdhi3_ds_mux[] = {
3710 SD3_DS_MARK,
3711};
3712
0526234d
KM		 3713/* - SSI -------------------------------------------------------------------- */
3714static const unsigned int ssi0_data_pins[] = {
3715 /* SDATA */
3716 RCAR_GP_PIN(6, 2),
3717};
3718static const unsigned int ssi0_data_mux[] = {
3719 SSI_SDATA0_MARK,
3720};
3721static const unsigned int ssi01239_ctrl_pins[] = {
3722 /* SCK, WS */
3723 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3724};
3725static const unsigned int ssi01239_ctrl_mux[] = {
3726 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3727};
3728static const unsigned int ssi1_data_a_pins[] = {
3729 /* SDATA */
3730 RCAR_GP_PIN(6, 3),
3731};
3732static const unsigned int ssi1_data_a_mux[] = {
3733 SSI_SDATA1_A_MARK,
3734};
3735static const unsigned int ssi1_data_b_pins[] = {
3736 /* SDATA */
3737 RCAR_GP_PIN(5, 12),
3738};
3739static const unsigned int ssi1_data_b_mux[] = {
3740 SSI_SDATA1_B_MARK,
3741};
3742static const unsigned int ssi1_ctrl_a_pins[] = {
3743 /* SCK, WS */
3744 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3745};
3746static const unsigned int ssi1_ctrl_a_mux[] = {
3747 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3748};
3749static const unsigned int ssi1_ctrl_b_pins[] = {
3750 /* SCK, WS */
3751 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3752};
3753static const unsigned int ssi1_ctrl_b_mux[] = {
3754 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3755};
3756static const unsigned int ssi2_data_a_pins[] = {
3757 /* SDATA */
3758 RCAR_GP_PIN(6, 4),
3759};
3760static const unsigned int ssi2_data_a_mux[] = {
3761 SSI_SDATA2_A_MARK,
3762};
3763static const unsigned int ssi2_data_b_pins[] = {
3764 /* SDATA */
3765 RCAR_GP_PIN(5, 13),
3766};
3767static const unsigned int ssi2_data_b_mux[] = {
3768 SSI_SDATA2_B_MARK,
3769};
3770static const unsigned int ssi2_ctrl_a_pins[] = {
3771 /* SCK, WS */
3772 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3773};
3774static const unsigned int ssi2_ctrl_a_mux[] = {
3775 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3776};
3777static const unsigned int ssi2_ctrl_b_pins[] = {
3778 /* SCK, WS */
3779 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3780};
3781static const unsigned int ssi2_ctrl_b_mux[] = {
3782 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3783};
3784static const unsigned int ssi3_data_pins[] = {
3785 /* SDATA */
3786 RCAR_GP_PIN(6, 7),
3787};
3788static const unsigned int ssi3_data_mux[] = {
3789 SSI_SDATA3_MARK,
3790};
3791static const unsigned int ssi349_ctrl_pins[] = {
3792 /* SCK, WS */
3793 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3794};
3795static const unsigned int ssi349_ctrl_mux[] = {
3796 SSI_SCK349_MARK, SSI_WS349_MARK,
3797};
3798static const unsigned int ssi4_data_pins[] = {
3799 /* SDATA */
3800 RCAR_GP_PIN(6, 10),
3801};
3802static const unsigned int ssi4_data_mux[] = {
3803 SSI_SDATA4_MARK,
3804};
3805static const unsigned int ssi4_ctrl_pins[] = {
3806 /* SCK, WS */
3807 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3808};
3809static const unsigned int ssi4_ctrl_mux[] = {
3810 SSI_SCK4_MARK, SSI_WS4_MARK,
3811};
3812static const unsigned int ssi5_data_pins[] = {
3813 /* SDATA */
3814 RCAR_GP_PIN(6, 13),
3815};
3816static const unsigned int ssi5_data_mux[] = {
3817 SSI_SDATA5_MARK,
3818};
3819static const unsigned int ssi5_ctrl_pins[] = {
3820 /* SCK, WS */
3821 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3822};
3823static const unsigned int ssi5_ctrl_mux[] = {
3824 SSI_SCK5_MARK, SSI_WS5_MARK,
3825};
3826static const unsigned int ssi6_data_pins[] = {
3827 /* SDATA */
3828 RCAR_GP_PIN(6, 16),
3829};
3830static const unsigned int ssi6_data_mux[] = {
3831 SSI_SDATA6_MARK,
3832};
3833static const unsigned int ssi6_ctrl_pins[] = {
3834 /* SCK, WS */
3835 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3836};
3837static const unsigned int ssi6_ctrl_mux[] = {
3838 SSI_SCK6_MARK, SSI_WS6_MARK,
3839};
3840static const unsigned int ssi7_data_pins[] = {
3841 /* SDATA */
3842 RCAR_GP_PIN(6, 19),
3843};
3844static const unsigned int ssi7_data_mux[] = {
3845 SSI_SDATA7_MARK,
3846};
3847static const unsigned int ssi78_ctrl_pins[] = {
3848 /* SCK, WS */
3849 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3850};
3851static const unsigned int ssi78_ctrl_mux[] = {
3852 SSI_SCK78_MARK, SSI_WS78_MARK,
3853};
3854static const unsigned int ssi8_data_pins[] = {
3855 /* SDATA */
3856 RCAR_GP_PIN(6, 20),
3857};
3858static const unsigned int ssi8_data_mux[] = {
3859 SSI_SDATA8_MARK,
3860};
3861static const unsigned int ssi9_data_a_pins[] = {
3862 /* SDATA */
3863 RCAR_GP_PIN(6, 21),
3864};
3865static const unsigned int ssi9_data_a_mux[] = {
3866 SSI_SDATA9_A_MARK,
3867};
3868static const unsigned int ssi9_data_b_pins[] = {
3869 /* SDATA */
3870 RCAR_GP_PIN(5, 14),
3871};
3872static const unsigned int ssi9_data_b_mux[] = {
3873 SSI_SDATA9_B_MARK,
3874};
3875static const unsigned int ssi9_ctrl_a_pins[] = {
3876 /* SCK, WS */
3877 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3878};
3879static const unsigned int ssi9_ctrl_a_mux[] = {
3880 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3881};
3882static const unsigned int ssi9_ctrl_b_pins[] = {
3883 /* SCK, WS */
3884 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3885};
3886static const unsigned int ssi9_ctrl_b_mux[] = {
3887 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3888};
3889
edcc14c8
TK		 3890/* - TMU -------------------------------------------------------------------- */
3891static const unsigned int tmu_tclk1_a_pins[] = {
3892 /* TCLK */
3893 RCAR_GP_PIN(6, 23),
3894};
3895static const unsigned int tmu_tclk1_a_mux[] = {
3896 TCLK1_A_MARK,
3897};
3898static const unsigned int tmu_tclk1_b_pins[] = {
3899 /* TCLK */
3900 RCAR_GP_PIN(5, 19),
3901};
3902static const unsigned int tmu_tclk1_b_mux[] = {
3903 TCLK1_B_MARK,
3904};
3905static const unsigned int tmu_tclk2_a_pins[] = {
3906 /* TCLK */
3907 RCAR_GP_PIN(6, 19),
3908};
3909static const unsigned int tmu_tclk2_a_mux[] = {
3910 TCLK2_A_MARK,
3911};
3912static const unsigned int tmu_tclk2_b_pins[] = {
3913 /* TCLK */
3914 RCAR_GP_PIN(6, 28),
3915};
3916static const unsigned int tmu_tclk2_b_mux[] = {
3917 TCLK2_B_MARK,
3918};
3919
933ddbe5
YS		 3920/* - USB0 ------------------------------------------------------------------- */
3921static const unsigned int usb0_pins[] = {
3922 /* PWEN, OVC */
3923 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3924};
3925static const unsigned int usb0_mux[] = {
3926 USB0_PWEN_MARK, USB0_OVC_MARK,
3927};
3928/* - USB1 ------------------------------------------------------------------- */
3929static const unsigned int usb1_pins[] = {
3930 /* PWEN, OVC */
3931 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3932};
3933static const unsigned int usb1_mux[] = {
3934 USB1_PWEN_MARK, USB1_OVC_MARK,
3935};
3936/* - USB2 ------------------------------------------------------------------- */
3937static const unsigned int usb2_pins[] = {
3938 /* PWEN, OVC */
3939 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3940};
3941static const unsigned int usb2_mux[] = {
3942 USB2_PWEN_MARK, USB2_OVC_MARK,
3943};
3944/* - USB2_CH3 --------------------------------------------------------------- */
3945static const unsigned int usb2_ch3_pins[] = {
3946 /* PWEN, OVC */
3947 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3948};
3949static const unsigned int usb2_ch3_mux[] = {
3950 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3951};
3952
5ec8a41a
TK		 3953/* - USB30 ------------------------------------------------------------------ */
3954static const unsigned int usb30_pins[] = {
3955 /* PWEN, OVC */
3956 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3957};
3958static const unsigned int usb30_mux[] = {
3959 USB30_PWEN_MARK, USB30_OVC_MARK,
3960};
3961
6b4de408 3962/* - VIN4 ------------------------------------------------------------------- */
6b4de408 3963static const unsigned int vin4_data18_a_pins[] = {
6b4de408
UH		 3964 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3965 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3966 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
6b4de408
UH		 3967 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3968 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3969 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
b538dc5b
UH		 3970 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3971 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3972 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
6b4de408
UH		 3973};
3974static const unsigned int vin4_data18_a_mux[] = {
6b4de408
UH		 3975 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3976 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3977 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
6b4de408
UH		 3978 VI4_DATA10_MARK, VI4_DATA11_MARK,
3979 VI4_DATA12_MARK, VI4_DATA13_MARK,
3980 VI4_DATA14_MARK, VI4_DATA15_MARK,
b538dc5b
UH		 3981 VI4_DATA18_MARK, VI4_DATA19_MARK,
3982 VI4_DATA20_MARK, VI4_DATA21_MARK,
3983 VI4_DATA22_MARK, VI4_DATA23_MARK,
6b4de408
UH		 3984};
3985static const unsigned int vin4_data18_b_pins[] = {
6b4de408
UH		 3986 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3987 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3988 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
6b4de408
UH		 3989 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3990 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3991 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
b538dc5b
UH		 3992 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3993 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3994 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
6b4de408
UH		 3995};
3996static const unsigned int vin4_data18_b_mux[] = {
6b4de408
UH		 3997 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3998 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3999 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
6b4de408
UH		 4000 VI4_DATA10_MARK, VI4_DATA11_MARK,
4001 VI4_DATA12_MARK, VI4_DATA13_MARK,
4002 VI4_DATA14_MARK, VI4_DATA15_MARK,
b538dc5b
UH		 4003 VI4_DATA18_MARK, VI4_DATA19_MARK,
4004 VI4_DATA20_MARK, VI4_DATA21_MARK,
4005 VI4_DATA22_MARK, VI4_DATA23_MARK,
6b4de408 4006};
9942a5b5
UH		 4007static const union vin_data vin4_data_a_pins = {
4008 .data24 = {
4009 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
4010 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
4011 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
4012 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
4013 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4014 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4015 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4016 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4017 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4018 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4019 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4020 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4021 },
4022};
4023static const union vin_data vin4_data_a_mux = {
4024 .data24 = {
4025 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
4026 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
4027 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
4028 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
4029 VI4_DATA8_MARK, VI4_DATA9_MARK,
4030 VI4_DATA10_MARK, VI4_DATA11_MARK,
4031 VI4_DATA12_MARK, VI4_DATA13_MARK,
4032 VI4_DATA14_MARK, VI4_DATA15_MARK,
4033 VI4_DATA16_MARK, VI4_DATA17_MARK,
4034 VI4_DATA18_MARK, VI4_DATA19_MARK,
4035 VI4_DATA20_MARK, VI4_DATA21_MARK,
4036 VI4_DATA22_MARK, VI4_DATA23_MARK,
4037 },
4038};
4039static const union vin_data vin4_data_b_pins = {
4040 .data24 = {
4041 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4042 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4043 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4044 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4045 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4046 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4047 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4048 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4049 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4050 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4051 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4052 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4053 },
4054};
4055static const union vin_data vin4_data_b_mux = {
4056 .data24 = {
4057 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4058 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4059 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4060 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4061 VI4_DATA8_MARK, VI4_DATA9_MARK,
4062 VI4_DATA10_MARK, VI4_DATA11_MARK,
4063 VI4_DATA12_MARK, VI4_DATA13_MARK,
4064 VI4_DATA14_MARK, VI4_DATA15_MARK,
4065 VI4_DATA16_MARK, VI4_DATA17_MARK,
4066 VI4_DATA18_MARK, VI4_DATA19_MARK,
4067 VI4_DATA20_MARK, VI4_DATA21_MARK,
4068 VI4_DATA22_MARK, VI4_DATA23_MARK,
4069 },
6b4de408
UH		 4070};
4071static const unsigned int vin4_sync_pins[] = {
4072 /* HSYNC#, VSYNC# */
4073 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4074};
4075static const unsigned int vin4_sync_mux[] = {
4076 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4077};
4078static const unsigned int vin4_field_pins[] = {
4079 /* FIELD */
4080 RCAR_GP_PIN(1, 16),
4081};
4082static const unsigned int vin4_field_mux[] = {
4083 VI4_FIELD_MARK,
4084};
4085static const unsigned int vin4_clkenb_pins[] = {
4086 /* CLKENB */
4087 RCAR_GP_PIN(1, 19),
4088};
4089static const unsigned int vin4_clkenb_mux[] = {
4090 VI4_CLKENB_MARK,
4091};
4092static const unsigned int vin4_clk_pins[] = {
4093 /* CLK */
4094 RCAR_GP_PIN(1, 27),
4095};
4096static const unsigned int vin4_clk_mux[] = {
4097 VI4_CLK_MARK,
4098};
4099
4100/* - VIN5 ------------------------------------------------------------------- */
99fdb920
GU		 4101static const union vin_data16 vin5_data_pins = {
4102 .data16 = {
4103 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4104 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4105 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4106 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4107 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4108 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4109 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4110 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4111 },
6b4de408 4112};
99fdb920
GU		 4113static const union vin_data16 vin5_data_mux = {
4114 .data16 = {
4115 VI5_DATA0_MARK, VI5_DATA1_MARK,
4116 VI5_DATA2_MARK, VI5_DATA3_MARK,
4117 VI5_DATA4_MARK, VI5_DATA5_MARK,
4118 VI5_DATA6_MARK, VI5_DATA7_MARK,
4119 VI5_DATA8_MARK, VI5_DATA9_MARK,
4120 VI5_DATA10_MARK, VI5_DATA11_MARK,
4121 VI5_DATA12_MARK, VI5_DATA13_MARK,
4122 VI5_DATA14_MARK, VI5_DATA15_MARK,
4123 },
6b4de408
UH		 4124};
4125static const unsigned int vin5_sync_pins[] = {
4126 /* HSYNC#, VSYNC# */
4127 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4128};
4129static const unsigned int vin5_sync_mux[] = {
4130 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4131};
4132static const unsigned int vin5_field_pins[] = {
4133 RCAR_GP_PIN(1, 11),
4134};
4135static const unsigned int vin5_field_mux[] = {
4136 /* FIELD */
4137 VI5_FIELD_MARK,
4138};
4139static const unsigned int vin5_clkenb_pins[] = {
4140 RCAR_GP_PIN(1, 20),
4141};
4142static const unsigned int vin5_clkenb_mux[] = {
4143 /* CLKENB */
4144 VI5_CLKENB_MARK,
4145};
4146static const unsigned int vin5_clk_pins[] = {
4147 RCAR_GP_PIN(1, 21),
4148};
4149static const unsigned int vin5_clk_mux[] = {
4150 /* CLK */
4151 VI5_CLK_MARK,
4152};
4153
b205914c 4154static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 4155 SH_PFC_PIN_GROUP(audio_clk_a_a),
4156 SH_PFC_PIN_GROUP(audio_clk_a_b),
4157 SH_PFC_PIN_GROUP(audio_clk_a_c),
4158 SH_PFC_PIN_GROUP(audio_clk_b_a),
4159 SH_PFC_PIN_GROUP(audio_clk_b_b),
4160 SH_PFC_PIN_GROUP(audio_clk_c_a),
4161 SH_PFC_PIN_GROUP(audio_clk_c_b),
4162 SH_PFC_PIN_GROUP(audio_clkout_a),
4163 SH_PFC_PIN_GROUP(audio_clkout_b),
4164 SH_PFC_PIN_GROUP(audio_clkout_c),
4165 SH_PFC_PIN_GROUP(audio_clkout_d),
4166 SH_PFC_PIN_GROUP(audio_clkout1_a),
4167 SH_PFC_PIN_GROUP(audio_clkout1_b),
4168 SH_PFC_PIN_GROUP(audio_clkout2_a),
4169 SH_PFC_PIN_GROUP(audio_clkout2_b),
4170 SH_PFC_PIN_GROUP(audio_clkout3_a),
4171 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 4172 SH_PFC_PIN_GROUP(avb_link),
4173 SH_PFC_PIN_GROUP(avb_magic),
4174 SH_PFC_PIN_GROUP(avb_phy_int),
cbe0dd9a
GU		 4175 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4176 SH_PFC_PIN_GROUP(avb_mdio),
30c078de
GU		 4177 SH_PFC_PIN_GROUP(avb_mii),
4178 SH_PFC_PIN_GROUP(avb_avtp_pps),
4179 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4180 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4181 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4182 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a678abfe
RS		 4183 SH_PFC_PIN_GROUP(can0_data_a),
4184 SH_PFC_PIN_GROUP(can0_data_b),
4185 SH_PFC_PIN_GROUP(can1_data),
4186 SH_PFC_PIN_GROUP(can_clk),
0e1c7a94
RS		 4187 SH_PFC_PIN_GROUP(canfd0_data_a),
4188 SH_PFC_PIN_GROUP(canfd0_data_b),
4189 SH_PFC_PIN_GROUP(canfd1_data),
641b0ab8
DB		 4190 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4191 SH_PFC_PIN_GROUP(drif0_data0_a),
4192 SH_PFC_PIN_GROUP(drif0_data1_a),
4193 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4194 SH_PFC_PIN_GROUP(drif0_data0_b),
4195 SH_PFC_PIN_GROUP(drif0_data1_b),
4196 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4197 SH_PFC_PIN_GROUP(drif0_data0_c),
4198 SH_PFC_PIN_GROUP(drif0_data1_c),
4199 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4200 SH_PFC_PIN_GROUP(drif1_data0_a),
4201 SH_PFC_PIN_GROUP(drif1_data1_a),
4202 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4203 SH_PFC_PIN_GROUP(drif1_data0_b),
4204 SH_PFC_PIN_GROUP(drif1_data1_b),
4205 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4206 SH_PFC_PIN_GROUP(drif1_data0_c),
4207 SH_PFC_PIN_GROUP(drif1_data1_c),
4208 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4209 SH_PFC_PIN_GROUP(drif2_data0_a),
4210 SH_PFC_PIN_GROUP(drif2_data1_a),
4211 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4212 SH_PFC_PIN_GROUP(drif2_data0_b),
4213 SH_PFC_PIN_GROUP(drif2_data1_b),
4214 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4215 SH_PFC_PIN_GROUP(drif3_data0_a),
4216 SH_PFC_PIN_GROUP(drif3_data1_a),
4217 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4218 SH_PFC_PIN_GROUP(drif3_data0_b),
4219 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 4220 SH_PFC_PIN_GROUP(du_rgb666),
4221 SH_PFC_PIN_GROUP(du_rgb888),
4222 SH_PFC_PIN_GROUP(du_clk_out_0),
4223 SH_PFC_PIN_GROUP(du_clk_out_1),
4224 SH_PFC_PIN_GROUP(du_sync),
4225 SH_PFC_PIN_GROUP(du_oddf),
4226 SH_PFC_PIN_GROUP(du_cde),
4227 SH_PFC_PIN_GROUP(du_disp),
5722110e
TK		 4228 SH_PFC_PIN_GROUP(hdmi0_cec),
4229 SH_PFC_PIN_GROUP(hdmi1_cec),
7a362e34
WS		 4230 SH_PFC_PIN_GROUP(hscif0_data),
4231 SH_PFC_PIN_GROUP(hscif0_clk),
4232 SH_PFC_PIN_GROUP(hscif0_ctrl),
4233 SH_PFC_PIN_GROUP(hscif1_data_a),
4234 SH_PFC_PIN_GROUP(hscif1_clk_a),
4235 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4236 SH_PFC_PIN_GROUP(hscif1_data_b),
4237 SH_PFC_PIN_GROUP(hscif1_clk_b),
4238 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4239 SH_PFC_PIN_GROUP(hscif2_data_a),
4240 SH_PFC_PIN_GROUP(hscif2_clk_a),
4241 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4242 SH_PFC_PIN_GROUP(hscif2_data_b),
4243 SH_PFC_PIN_GROUP(hscif2_clk_b),
4244 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4245 SH_PFC_PIN_GROUP(hscif2_data_c),
4246 SH_PFC_PIN_GROUP(hscif2_clk_c),
4247 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4248 SH_PFC_PIN_GROUP(hscif3_data_a),
4249 SH_PFC_PIN_GROUP(hscif3_clk),
4250 SH_PFC_PIN_GROUP(hscif3_ctrl),
4251 SH_PFC_PIN_GROUP(hscif3_data_b),
4252 SH_PFC_PIN_GROUP(hscif3_data_c),
4253 SH_PFC_PIN_GROUP(hscif3_data_d),
4254 SH_PFC_PIN_GROUP(hscif4_data_a),
4255 SH_PFC_PIN_GROUP(hscif4_clk),
4256 SH_PFC_PIN_GROUP(hscif4_ctrl),
4257 SH_PFC_PIN_GROUP(hscif4_data_b),
100431b6 4258 SH_PFC_PIN_GROUP(i2c0),
f62d4c9e
WS		 4259 SH_PFC_PIN_GROUP(i2c1_a),
4260 SH_PFC_PIN_GROUP(i2c1_b),
4261 SH_PFC_PIN_GROUP(i2c2_a),
4262 SH_PFC_PIN_GROUP(i2c2_b),
100431b6
TK		 4263 SH_PFC_PIN_GROUP(i2c3),
4264 SH_PFC_PIN_GROUP(i2c5),
f62d4c9e
WS		 4265 SH_PFC_PIN_GROUP(i2c6_a),
4266 SH_PFC_PIN_GROUP(i2c6_b),
4267 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 4268 SH_PFC_PIN_GROUP(intc_ex_irq0),
4269 SH_PFC_PIN_GROUP(intc_ex_irq1),
4270 SH_PFC_PIN_GROUP(intc_ex_irq2),
4271 SH_PFC_PIN_GROUP(intc_ex_irq3),
4272 SH_PFC_PIN_GROUP(intc_ex_irq4),
4273 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 4274 SH_PFC_PIN_GROUP(msiof0_clk),
4275 SH_PFC_PIN_GROUP(msiof0_sync),
4276 SH_PFC_PIN_GROUP(msiof0_ss1),
4277 SH_PFC_PIN_GROUP(msiof0_ss2),
4278 SH_PFC_PIN_GROUP(msiof0_txd),
4279 SH_PFC_PIN_GROUP(msiof0_rxd),
4280 SH_PFC_PIN_GROUP(msiof1_clk_a),
4281 SH_PFC_PIN_GROUP(msiof1_sync_a),
4282 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4283 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4284 SH_PFC_PIN_GROUP(msiof1_txd_a),
4285 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4286 SH_PFC_PIN_GROUP(msiof1_clk_b),
4287 SH_PFC_PIN_GROUP(msiof1_sync_b),
4288 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4289 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4290 SH_PFC_PIN_GROUP(msiof1_txd_b),
4291 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4292 SH_PFC_PIN_GROUP(msiof1_clk_c),
4293 SH_PFC_PIN_GROUP(msiof1_sync_c),
4294 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4295 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4296 SH_PFC_PIN_GROUP(msiof1_txd_c),
4297 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4298 SH_PFC_PIN_GROUP(msiof1_clk_d),
4299 SH_PFC_PIN_GROUP(msiof1_sync_d),
4300 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4301 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4302 SH_PFC_PIN_GROUP(msiof1_txd_d),
4303 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4304 SH_PFC_PIN_GROUP(msiof1_clk_e),
4305 SH_PFC_PIN_GROUP(msiof1_sync_e),
4306 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4307 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4308 SH_PFC_PIN_GROUP(msiof1_txd_e),
4309 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4310 SH_PFC_PIN_GROUP(msiof1_clk_f),
4311 SH_PFC_PIN_GROUP(msiof1_sync_f),
4312 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4313 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4314 SH_PFC_PIN_GROUP(msiof1_txd_f),
4315 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4316 SH_PFC_PIN_GROUP(msiof1_clk_g),
4317 SH_PFC_PIN_GROUP(msiof1_sync_g),
4318 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4319 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4320 SH_PFC_PIN_GROUP(msiof1_txd_g),
4321 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4322 SH_PFC_PIN_GROUP(msiof2_clk_a),
4323 SH_PFC_PIN_GROUP(msiof2_sync_a),
4324 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4325 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4326 SH_PFC_PIN_GROUP(msiof2_txd_a),
4327 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4328 SH_PFC_PIN_GROUP(msiof2_clk_b),
4329 SH_PFC_PIN_GROUP(msiof2_sync_b),
4330 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4331 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4332 SH_PFC_PIN_GROUP(msiof2_txd_b),
4333 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4334 SH_PFC_PIN_GROUP(msiof2_clk_c),
4335 SH_PFC_PIN_GROUP(msiof2_sync_c),
4336 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4337 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4338 SH_PFC_PIN_GROUP(msiof2_txd_c),
4339 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4340 SH_PFC_PIN_GROUP(msiof2_clk_d),
4341 SH_PFC_PIN_GROUP(msiof2_sync_d),
4342 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4343 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4344 SH_PFC_PIN_GROUP(msiof2_txd_d),
4345 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4346 SH_PFC_PIN_GROUP(msiof3_clk_a),
4347 SH_PFC_PIN_GROUP(msiof3_sync_a),
4348 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4349 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4350 SH_PFC_PIN_GROUP(msiof3_txd_a),
4351 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4352 SH_PFC_PIN_GROUP(msiof3_clk_b),
4353 SH_PFC_PIN_GROUP(msiof3_sync_b),
4354 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4355 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4356 SH_PFC_PIN_GROUP(msiof3_txd_b),
4357 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4358 SH_PFC_PIN_GROUP(msiof3_clk_c),
4359 SH_PFC_PIN_GROUP(msiof3_sync_c),
4360 SH_PFC_PIN_GROUP(msiof3_txd_c),
4361 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4362 SH_PFC_PIN_GROUP(msiof3_clk_d),
4363 SH_PFC_PIN_GROUP(msiof3_sync_d),
4364 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4365 SH_PFC_PIN_GROUP(msiof3_txd_d),
4366 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4367 SH_PFC_PIN_GROUP(msiof3_clk_e),
4368 SH_PFC_PIN_GROUP(msiof3_sync_e),
4369 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4370 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4371 SH_PFC_PIN_GROUP(msiof3_txd_e),
4372 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4373 SH_PFC_PIN_GROUP(pwm0),
4374 SH_PFC_PIN_GROUP(pwm1_a),
4375 SH_PFC_PIN_GROUP(pwm1_b),
4376 SH_PFC_PIN_GROUP(pwm2_a),
4377 SH_PFC_PIN_GROUP(pwm2_b),
4378 SH_PFC_PIN_GROUP(pwm3_a),
4379 SH_PFC_PIN_GROUP(pwm3_b),
4380 SH_PFC_PIN_GROUP(pwm4_a),
4381 SH_PFC_PIN_GROUP(pwm4_b),
4382 SH_PFC_PIN_GROUP(pwm5_a),
4383 SH_PFC_PIN_GROUP(pwm5_b),
4384 SH_PFC_PIN_GROUP(pwm6_a),
4385 SH_PFC_PIN_GROUP(pwm6_b),
297e5b2b
WS		 4386 SH_PFC_PIN_GROUP(sata0_devslp_a),
4387 SH_PFC_PIN_GROUP(sata0_devslp_b),
e7ad4d3c
GU		 4388 SH_PFC_PIN_GROUP(scif0_data),
4389 SH_PFC_PIN_GROUP(scif0_clk),
4390 SH_PFC_PIN_GROUP(scif0_ctrl),
4391 SH_PFC_PIN_GROUP(scif1_data_a),
4392 SH_PFC_PIN_GROUP(scif1_clk),
4393 SH_PFC_PIN_GROUP(scif1_ctrl),
4394 SH_PFC_PIN_GROUP(scif1_data_b),
4395 SH_PFC_PIN_GROUP(scif2_data_a),
4396 SH_PFC_PIN_GROUP(scif2_clk),
4397 SH_PFC_PIN_GROUP(scif2_data_b),
4398 SH_PFC_PIN_GROUP(scif3_data_a),
4399 SH_PFC_PIN_GROUP(scif3_clk),
4400 SH_PFC_PIN_GROUP(scif3_ctrl),
4401 SH_PFC_PIN_GROUP(scif3_data_b),
4402 SH_PFC_PIN_GROUP(scif4_data_a),
4403 SH_PFC_PIN_GROUP(scif4_clk_a),
4404 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4405 SH_PFC_PIN_GROUP(scif4_data_b),
4406 SH_PFC_PIN_GROUP(scif4_clk_b),
4407 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4408 SH_PFC_PIN_GROUP(scif4_data_c),
4409 SH_PFC_PIN_GROUP(scif4_clk_c),
4410 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4411 SH_PFC_PIN_GROUP(scif5_data_a),
4412 SH_PFC_PIN_GROUP(scif5_clk_a),
4413 SH_PFC_PIN_GROUP(scif5_data_b),
4414 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4415 SH_PFC_PIN_GROUP(scif_clk_a),
4416 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4417 SH_PFC_PIN_GROUP(sdhi0_data1),
4418 SH_PFC_PIN_GROUP(sdhi0_data4),
4419 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4420 SH_PFC_PIN_GROUP(sdhi0_cd),
4421 SH_PFC_PIN_GROUP(sdhi0_wp),
4422 SH_PFC_PIN_GROUP(sdhi1_data1),
4423 SH_PFC_PIN_GROUP(sdhi1_data4),
4424 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4425 SH_PFC_PIN_GROUP(sdhi1_cd),
4426 SH_PFC_PIN_GROUP(sdhi1_wp),
4427 SH_PFC_PIN_GROUP(sdhi2_data1),
4428 SH_PFC_PIN_GROUP(sdhi2_data4),
4429 SH_PFC_PIN_GROUP(sdhi2_data8),
4430 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4431 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4432 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4433 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4434 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4435 SH_PFC_PIN_GROUP(sdhi2_ds),
4436 SH_PFC_PIN_GROUP(sdhi3_data1),
4437 SH_PFC_PIN_GROUP(sdhi3_data4),
4438 SH_PFC_PIN_GROUP(sdhi3_data8),
4439 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4440 SH_PFC_PIN_GROUP(sdhi3_cd),
4441 SH_PFC_PIN_GROUP(sdhi3_wp),
4442 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4443 SH_PFC_PIN_GROUP(ssi0_data),
4444 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4445 SH_PFC_PIN_GROUP(ssi1_data_a),
4446 SH_PFC_PIN_GROUP(ssi1_data_b),
4447 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4448 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4449 SH_PFC_PIN_GROUP(ssi2_data_a),
4450 SH_PFC_PIN_GROUP(ssi2_data_b),
4451 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4452 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4453 SH_PFC_PIN_GROUP(ssi3_data),
4454 SH_PFC_PIN_GROUP(ssi349_ctrl),
4455 SH_PFC_PIN_GROUP(ssi4_data),
4456 SH_PFC_PIN_GROUP(ssi4_ctrl),
4457 SH_PFC_PIN_GROUP(ssi5_data),
4458 SH_PFC_PIN_GROUP(ssi5_ctrl),
4459 SH_PFC_PIN_GROUP(ssi6_data),
4460 SH_PFC_PIN_GROUP(ssi6_ctrl),
4461 SH_PFC_PIN_GROUP(ssi7_data),
4462 SH_PFC_PIN_GROUP(ssi78_ctrl),
4463 SH_PFC_PIN_GROUP(ssi8_data),
4464 SH_PFC_PIN_GROUP(ssi9_data_a),
4465 SH_PFC_PIN_GROUP(ssi9_data_b),
4466 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4467 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
edcc14c8
TK		 4468 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4469 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4470 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4471 SH_PFC_PIN_GROUP(tmu_tclk2_b),
933ddbe5
YS		 4472 SH_PFC_PIN_GROUP(usb0),
4473 SH_PFC_PIN_GROUP(usb1),
4474 SH_PFC_PIN_GROUP(usb2),
4475 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4476 SH_PFC_PIN_GROUP(usb30),
184844cc
JM		 4477 VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
4478 VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
4479 VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
4480 VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
6b4de408 4481 SH_PFC_PIN_GROUP(vin4_data18_a),
184844cc
JM		 4482 VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
4483 VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
4484 VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
4485 VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
4486 VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
4487 VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
6b4de408 4488 SH_PFC_PIN_GROUP(vin4_data18_b),
184844cc
JM		 4489 VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
4490 VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
6b4de408
UH		 4491 SH_PFC_PIN_GROUP(vin4_sync),
4492 SH_PFC_PIN_GROUP(vin4_field),
4493 SH_PFC_PIN_GROUP(vin4_clkenb),
4494 SH_PFC_PIN_GROUP(vin4_clk),
99fdb920
GU		 4495 VIN_DATA_PIN_GROUP(vin5_data, 8),
4496 VIN_DATA_PIN_GROUP(vin5_data, 10),
4497 VIN_DATA_PIN_GROUP(vin5_data, 12),
4498 VIN_DATA_PIN_GROUP(vin5_data, 16),
6b4de408
UH		 4499 SH_PFC_PIN_GROUP(vin5_sync),
4500 SH_PFC_PIN_GROUP(vin5_field),
4501 SH_PFC_PIN_GROUP(vin5_clkenb),
4502 SH_PFC_PIN_GROUP(vin5_clk),
e7ad4d3c
GU		 4503};
4504
55bfea9f
KM		 4505static const char * const audio_clk_groups[] = {
4506 "audio_clk_a_a",
4507 "audio_clk_a_b",
4508 "audio_clk_a_c",
4509 "audio_clk_b_a",
4510 "audio_clk_b_b",
4511 "audio_clk_c_a",
4512 "audio_clk_c_b",
4513 "audio_clkout_a",
4514 "audio_clkout_b",
4515 "audio_clkout_c",
4516 "audio_clkout_d",
4517 "audio_clkout1_a",
4518 "audio_clkout1_b",
4519 "audio_clkout2_a",
4520 "audio_clkout2_b",
4521 "audio_clkout3_a",
4522 "audio_clkout3_b",
4523};
4524
30c078de
GU		 4525static const char * const avb_groups[] = {
4526 "avb_link",
4527 "avb_magic",
4528 "avb_phy_int",
cbe0dd9a
GU		 4529 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4530 "avb_mdio",
30c078de
GU		 4531 "avb_mii",
4532 "avb_avtp_pps",
4533 "avb_avtp_match_a",
4534 "avb_avtp_capture_a",
4535 "avb_avtp_match_b",
4536 "avb_avtp_capture_b",
4537};
4538
a678abfe
RS		 4539static const char * const can0_groups[] = {
4540 "can0_data_a",
4541 "can0_data_b",
4542};
4543
4544static const char * const can1_groups[] = {
4545 "can1_data",
4546};
4547
4548static const char * const can_clk_groups[] = {
4549 "can_clk",
4550};
4551
0e1c7a94
RS		 4552static const char * const canfd0_groups[] = {
4553 "canfd0_data_a",
4554 "canfd0_data_b",
4555};
4556
4557static const char * const canfd1_groups[] = {
4558 "canfd1_data",
4559};
4560
641b0ab8
DB		 4561static const char * const drif0_groups[] = {
4562 "drif0_ctrl_a",
4563 "drif0_data0_a",
4564 "drif0_data1_a",
4565 "drif0_ctrl_b",
4566 "drif0_data0_b",
4567 "drif0_data1_b",
4568 "drif0_ctrl_c",
4569 "drif0_data0_c",
4570 "drif0_data1_c",
4571};
4572
4573static const char * const drif1_groups[] = {
4574 "drif1_ctrl_a",
4575 "drif1_data0_a",
4576 "drif1_data1_a",
4577 "drif1_ctrl_b",
4578 "drif1_data0_b",
4579 "drif1_data1_b",
4580 "drif1_ctrl_c",
4581 "drif1_data0_c",
4582 "drif1_data1_c",
4583};
4584
4585static const char * const drif2_groups[] = {
4586 "drif2_ctrl_a",
4587 "drif2_data0_a",
4588 "drif2_data1_a",
4589 "drif2_ctrl_b",
4590 "drif2_data0_b",
4591 "drif2_data1_b",
4592};
4593
4594static const char * const drif3_groups[] = {
4595 "drif3_ctrl_a",
4596 "drif3_data0_a",
4597 "drif3_data1_a",
4598 "drif3_ctrl_b",
4599 "drif3_data0_b",
4600 "drif3_data1_b",
4601};
4602
a20a6585
LP		 4603static const char * const du_groups[] = {
4604 "du_rgb666",
4605 "du_rgb888",
4606 "du_clk_out_0",
4607 "du_clk_out_1",
4608 "du_sync",
4609 "du_oddf",
4610 "du_cde",
4611 "du_disp",
4612};
4613
5722110e
TK		 4614static const char * const hdmi0_groups[] = {
4615 "hdmi0_cec",
4616};
4617
4618static const char * const hdmi1_groups[] = {
4619 "hdmi1_cec",
4620};
4621
7a362e34
WS		 4622static const char * const hscif0_groups[] = {
4623 "hscif0_data",
4624 "hscif0_clk",
4625 "hscif0_ctrl",
4626};
4627
4628static const char * const hscif1_groups[] = {
4629 "hscif1_data_a",
4630 "hscif1_clk_a",
4631 "hscif1_ctrl_a",
4632 "hscif1_data_b",
4633 "hscif1_clk_b",
4634 "hscif1_ctrl_b",
4635};
4636
4637static const char * const hscif2_groups[] = {
4638 "hscif2_data_a",
4639 "hscif2_clk_a",
4640 "hscif2_ctrl_a",
4641 "hscif2_data_b",
4642 "hscif2_clk_b",
4643 "hscif2_ctrl_b",
4644 "hscif2_data_c",
4645 "hscif2_clk_c",
4646 "hscif2_ctrl_c",
4647};
4648
4649static const char * const hscif3_groups[] = {
4650 "hscif3_data_a",
4651 "hscif3_clk",
4652 "hscif3_ctrl",
4653 "hscif3_data_b",
4654 "hscif3_data_c",
4655 "hscif3_data_d",
4656};
4657
4658static const char * const hscif4_groups[] = {
4659 "hscif4_data_a",
4660 "hscif4_clk",
4661 "hscif4_ctrl",
4662 "hscif4_data_b",
4663};
4664
100431b6
TK		 4665static const char * const i2c0_groups[] = {
4666 "i2c0",
4667};
4668
f62d4c9e
WS		 4669static const char * const i2c1_groups[] = {
4670 "i2c1_a",
4671 "i2c1_b",
4672};
4673
4674static const char * const i2c2_groups[] = {
4675 "i2c2_a",
4676 "i2c2_b",
4677};
4678
100431b6
TK		 4679static const char * const i2c3_groups[] = {
4680 "i2c3",
4681};
4682
4683static const char * const i2c5_groups[] = {
4684 "i2c5",
4685};
4686
f62d4c9e
WS		 4687static const char * const i2c6_groups[] = {
4688 "i2c6_a",
4689 "i2c6_b",
4690 "i2c6_c",
4691};
4692
8480e6ca
GU		 4693static const char * const intc_ex_groups[] = {
4694 "intc_ex_irq0",
4695 "intc_ex_irq1",
4696 "intc_ex_irq2",
4697 "intc_ex_irq3",
4698 "intc_ex_irq4",
4699 "intc_ex_irq5",
4700};
4701
3e6c7727
GU		 4702static const char * const msiof0_groups[] = {
4703 "msiof0_clk",
4704 "msiof0_sync",
4705 "msiof0_ss1",
4706 "msiof0_ss2",
4707 "msiof0_txd",
4708 "msiof0_rxd",
4709};
4710
4711static const char * const msiof1_groups[] = {
4712 "msiof1_clk_a",
4713 "msiof1_sync_a",
4714 "msiof1_ss1_a",
4715 "msiof1_ss2_a",
4716 "msiof1_txd_a",
4717 "msiof1_rxd_a",
4718 "msiof1_clk_b",
4719 "msiof1_sync_b",
4720 "msiof1_ss1_b",
4721 "msiof1_ss2_b",
4722 "msiof1_txd_b",
4723 "msiof1_rxd_b",
4724 "msiof1_clk_c",
4725 "msiof1_sync_c",
4726 "msiof1_ss1_c",
4727 "msiof1_ss2_c",
4728 "msiof1_txd_c",
4729 "msiof1_rxd_c",
4730 "msiof1_clk_d",
4731 "msiof1_sync_d",
4732 "msiof1_ss1_d",
4733 "msiof1_ss2_d",
4734 "msiof1_txd_d",
4735 "msiof1_rxd_d",
4736 "msiof1_clk_e",
4737 "msiof1_sync_e",
4738 "msiof1_ss1_e",
4739 "msiof1_ss2_e",
4740 "msiof1_txd_e",
4741 "msiof1_rxd_e",
4742 "msiof1_clk_f",
4743 "msiof1_sync_f",
4744 "msiof1_ss1_f",
4745 "msiof1_ss2_f",
4746 "msiof1_txd_f",
4747 "msiof1_rxd_f",
4748 "msiof1_clk_g",
4749 "msiof1_sync_g",
4750 "msiof1_ss1_g",
4751 "msiof1_ss2_g",
4752 "msiof1_txd_g",
4753 "msiof1_rxd_g",
4754};
4755
4756static const char * const msiof2_groups[] = {
4757 "msiof2_clk_a",
4758 "msiof2_sync_a",
4759 "msiof2_ss1_a",
4760 "msiof2_ss2_a",
4761 "msiof2_txd_a",
4762 "msiof2_rxd_a",
4763 "msiof2_clk_b",
4764 "msiof2_sync_b",
4765 "msiof2_ss1_b",
4766 "msiof2_ss2_b",
4767 "msiof2_txd_b",
4768 "msiof2_rxd_b",
4769 "msiof2_clk_c",
4770 "msiof2_sync_c",
4771 "msiof2_ss1_c",
4772 "msiof2_ss2_c",
4773 "msiof2_txd_c",
4774 "msiof2_rxd_c",
4775 "msiof2_clk_d",
4776 "msiof2_sync_d",
4777 "msiof2_ss1_d",
4778 "msiof2_ss2_d",
4779 "msiof2_txd_d",
4780 "msiof2_rxd_d",
4781};
4782
4783static const char * const msiof3_groups[] = {
4784 "msiof3_clk_a",
4785 "msiof3_sync_a",
4786 "msiof3_ss1_a",
4787 "msiof3_ss2_a",
4788 "msiof3_txd_a",
4789 "msiof3_rxd_a",
4790 "msiof3_clk_b",
4791 "msiof3_sync_b",
4792 "msiof3_ss1_b",
4793 "msiof3_ss2_b",
4794 "msiof3_txd_b",
4795 "msiof3_rxd_b",
4796 "msiof3_clk_c",
4797 "msiof3_sync_c",
4798 "msiof3_txd_c",
4799 "msiof3_rxd_c",
4800 "msiof3_clk_d",
4801 "msiof3_sync_d",
4802 "msiof3_ss1_d",
4803 "msiof3_txd_d",
4804 "msiof3_rxd_d",
4805 "msiof3_clk_e",
4806 "msiof3_sync_e",
4807 "msiof3_ss1_e",
4808 "msiof3_ss2_e",
4809 "msiof3_txd_e",
4810 "msiof3_rxd_e",
4811};
4812
c03a133b
LP		 4813static const char * const pwm0_groups[] = {
4814 "pwm0",
4815};
4816
4817static const char * const pwm1_groups[] = {
4818 "pwm1_a",
4819 "pwm1_b",
4820};
4821
4822static const char * const pwm2_groups[] = {
4823 "pwm2_a",
4824 "pwm2_b",
4825};
4826
4827static const char * const pwm3_groups[] = {
4828 "pwm3_a",
4829 "pwm3_b",
4830};
4831
4832static const char * const pwm4_groups[] = {
4833 "pwm4_a",
4834 "pwm4_b",
4835};
4836
4837static const char * const pwm5_groups[] = {
4838 "pwm5_a",
4839 "pwm5_b",
4840};
4841
4842static const char * const pwm6_groups[] = {
4843 "pwm6_a",
4844 "pwm6_b",
4845};
4846
297e5b2b
WS		 4847static const char * const sata0_groups[] = {
4848 "sata0_devslp_a",
4849 "sata0_devslp_b",
4850};
4851
e7ad4d3c
GU		 4852static const char * const scif0_groups[] = {
4853 "scif0_data",
4854 "scif0_clk",
4855 "scif0_ctrl",
4856};
4857
4858static const char * const scif1_groups[] = {
4859 "scif1_data_a",
4860 "scif1_clk",
4861 "scif1_ctrl",
4862 "scif1_data_b",
4863};
4864
4865static const char * const scif2_groups[] = {
4866 "scif2_data_a",
4867 "scif2_clk",
4868 "scif2_data_b",
4869};
4870
4871static const char * const scif3_groups[] = {
4872 "scif3_data_a",
4873 "scif3_clk",
4874 "scif3_ctrl",
4875 "scif3_data_b",
4876};
4877
4878static const char * const scif4_groups[] = {
4879 "scif4_data_a",
4880 "scif4_clk_a",
4881 "scif4_ctrl_a",
4882 "scif4_data_b",
4883 "scif4_clk_b",
4884 "scif4_ctrl_b",
4885 "scif4_data_c",
4886 "scif4_clk_c",
4887 "scif4_ctrl_c",
4888};
4889
4890static const char * const scif5_groups[] = {
4891 "scif5_data_a",
4892 "scif5_clk_a",
4893 "scif5_data_b",
4894 "scif5_clk_b",
76250a6c
TK		 4895};
4896
d14a39ed
GU		 4897static const char * const scif_clk_groups[] = {
4898 "scif_clk_a",
4899 "scif_clk_b",
4900};
4901
9ed13958
TK		 4902static const char * const sdhi0_groups[] = {
4903 "sdhi0_data1",
4904 "sdhi0_data4",
4905 "sdhi0_ctrl",
4906 "sdhi0_cd",
4907 "sdhi0_wp",
4908};
4909
4910static const char * const sdhi1_groups[] = {
4911 "sdhi1_data1",
4912 "sdhi1_data4",
4913 "sdhi1_ctrl",
4914 "sdhi1_cd",
4915 "sdhi1_wp",
4916};
4917
4918static const char * const sdhi2_groups[] = {
4919 "sdhi2_data1",
4920 "sdhi2_data4",
4921 "sdhi2_data8",
4922 "sdhi2_ctrl",
4923 "sdhi2_cd_a",
4924 "sdhi2_wp_a",
4925 "sdhi2_cd_b",
4926 "sdhi2_wp_b",
4927 "sdhi2_ds",
4928};
4929
4930static const char * const sdhi3_groups[] = {
4931 "sdhi3_data1",
4932 "sdhi3_data4",
4933 "sdhi3_data8",
4934 "sdhi3_ctrl",
4935 "sdhi3_cd",
4936 "sdhi3_wp",
4937 "sdhi3_ds",
4938};
4939
0526234d
KM		 4940static const char * const ssi_groups[] = {
4941 "ssi0_data",
4942 "ssi01239_ctrl",
4943 "ssi1_data_a",
4944 "ssi1_data_b",
4945 "ssi1_ctrl_a",
4946 "ssi1_ctrl_b",
4947 "ssi2_data_a",
4948 "ssi2_data_b",
4949 "ssi2_ctrl_a",
4950 "ssi2_ctrl_b",
4951 "ssi3_data",
4952 "ssi349_ctrl",
4953 "ssi4_data",
4954 "ssi4_ctrl",
4955 "ssi5_data",
4956 "ssi5_ctrl",
4957 "ssi6_data",
4958 "ssi6_ctrl",
4959 "ssi7_data",
4960 "ssi78_ctrl",
4961 "ssi8_data",
4962 "ssi9_data_a",
4963 "ssi9_data_b",
4964 "ssi9_ctrl_a",
4965 "ssi9_ctrl_b",
4966};
4967
edcc14c8
TK		 4968static const char * const tmu_groups[] = {
4969 "tmu_tclk1_a",
4970 "tmu_tclk1_b",
4971 "tmu_tclk2_a",
4972 "tmu_tclk2_b",
4973};
4974
933ddbe5
YS		 4975static const char * const usb0_groups[] = {
4976 "usb0",
4977};
4978
4979static const char * const usb1_groups[] = {
4980 "usb1",
4981};
4982
4983static const char * const usb2_groups[] = {
4984 "usb2",
4985};
4986
4987static const char * const usb2_ch3_groups[] = {
4988 "usb2_ch3",
4989};
4990
5ec8a41a
TK		 4991static const char * const usb30_groups[] = {
4992 "usb30",
4993};
4994
6b4de408
UH		 4995static const char * const vin4_groups[] = {
4996 "vin4_data8_a",
4997 "vin4_data10_a",
4998 "vin4_data12_a",
4999 "vin4_data16_a",
5000 "vin4_data18_a",
5001 "vin4_data20_a",
5002 "vin4_data24_a",
5003 "vin4_data8_b",
5004 "vin4_data10_b",
5005 "vin4_data12_b",
5006 "vin4_data16_b",
5007 "vin4_data18_b",
5008 "vin4_data20_b",
5009 "vin4_data24_b",
5010 "vin4_sync",
5011 "vin4_field",
5012 "vin4_clkenb",
5013 "vin4_clk",
5014};
5015
5016static const char * const vin5_groups[] = {
5017 "vin5_data8",
5018 "vin5_data10",
5019 "vin5_data12",
5020 "vin5_data16",
5021 "vin5_sync",
5022 "vin5_field",
5023 "vin5_clkenb",
5024 "vin5_clk",
5025};
5026
0b0ffc96 5027static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 5028 SH_PFC_FUNCTION(audio_clk),
30c078de 5029 SH_PFC_FUNCTION(avb),
a678abfe
RS		 5030 SH_PFC_FUNCTION(can0),
5031 SH_PFC_FUNCTION(can1),
5032 SH_PFC_FUNCTION(can_clk),
0e1c7a94
RS		 5033 SH_PFC_FUNCTION(canfd0),
5034 SH_PFC_FUNCTION(canfd1),
641b0ab8
DB		 5035 SH_PFC_FUNCTION(drif0),
5036 SH_PFC_FUNCTION(drif1),
5037 SH_PFC_FUNCTION(drif2),
5038 SH_PFC_FUNCTION(drif3),
a20a6585 5039 SH_PFC_FUNCTION(du),
5722110e
TK		 5040 SH_PFC_FUNCTION(hdmi0),
5041 SH_PFC_FUNCTION(hdmi1),
7a362e34
WS		 5042 SH_PFC_FUNCTION(hscif0),
5043 SH_PFC_FUNCTION(hscif1),
5044 SH_PFC_FUNCTION(hscif2),
5045 SH_PFC_FUNCTION(hscif3),
5046 SH_PFC_FUNCTION(hscif4),
100431b6 5047 SH_PFC_FUNCTION(i2c0),
f62d4c9e
WS		 5048 SH_PFC_FUNCTION(i2c1),
5049 SH_PFC_FUNCTION(i2c2),
100431b6
TK		 5050 SH_PFC_FUNCTION(i2c3),
5051 SH_PFC_FUNCTION(i2c5),
f62d4c9e 5052 SH_PFC_FUNCTION(i2c6),
8480e6ca 5053 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 5054 SH_PFC_FUNCTION(msiof0),
5055 SH_PFC_FUNCTION(msiof1),
5056 SH_PFC_FUNCTION(msiof2),
5057 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 5058 SH_PFC_FUNCTION(pwm0),
5059 SH_PFC_FUNCTION(pwm1),
5060 SH_PFC_FUNCTION(pwm2),
5061 SH_PFC_FUNCTION(pwm3),
5062 SH_PFC_FUNCTION(pwm4),
5063 SH_PFC_FUNCTION(pwm5),
5064 SH_PFC_FUNCTION(pwm6),
297e5b2b 5065 SH_PFC_FUNCTION(sata0),
e7ad4d3c
GU		 5066 SH_PFC_FUNCTION(scif0),
5067 SH_PFC_FUNCTION(scif1),
5068 SH_PFC_FUNCTION(scif2),
5069 SH_PFC_FUNCTION(scif3),
5070 SH_PFC_FUNCTION(scif4),
5071 SH_PFC_FUNCTION(scif5),
d14a39ed 5072 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 5073 SH_PFC_FUNCTION(sdhi0),
5074 SH_PFC_FUNCTION(sdhi1),
5075 SH_PFC_FUNCTION(sdhi2),
5076 SH_PFC_FUNCTION(sdhi3),
0526234d 5077 SH_PFC_FUNCTION(ssi),
edcc14c8 5078 SH_PFC_FUNCTION(tmu),
933ddbe5
YS		 5079 SH_PFC_FUNCTION(usb0),
5080 SH_PFC_FUNCTION(usb1),
5081 SH_PFC_FUNCTION(usb2),
5082 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 5083 SH_PFC_FUNCTION(usb30),
6b4de408
UH		 5084 SH_PFC_FUNCTION(vin4),
5085 SH_PFC_FUNCTION(vin5),
0b0ffc96
TK		 5086};
5087
5088static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5089#define F_(x, y) FN_##y
5090#define FM(x) FN_##x
5091 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5092 0, 0,
5093 0, 0,
5094 0, 0,
5095 0, 0,
5096 0, 0,
5097 0, 0,
5098 0, 0,
5099 0, 0,
5100 0, 0,
5101 0, 0,
5102 0, 0,
5103 0, 0,
5104 0, 0,
5105 0, 0,
5106 0, 0,
5107 0, 0,
5108 GP_0_15_FN, GPSR0_15,
5109 GP_0_14_FN, GPSR0_14,
5110 GP_0_13_FN, GPSR0_13,
5111 GP_0_12_FN, GPSR0_12,
5112 GP_0_11_FN, GPSR0_11,
5113 GP_0_10_FN, GPSR0_10,
5114 GP_0_9_FN, GPSR0_9,
5115 GP_0_8_FN, GPSR0_8,
5116 GP_0_7_FN, GPSR0_7,
5117 GP_0_6_FN, GPSR0_6,
5118 GP_0_5_FN, GPSR0_5,
5119 GP_0_4_FN, GPSR0_4,
5120 GP_0_3_FN, GPSR0_3,
5121 GP_0_2_FN, GPSR0_2,
5122 GP_0_1_FN, GPSR0_1,
5123 GP_0_0_FN, GPSR0_0, }
5124 },
5125 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5126 0, 0,
5127 0, 0,
5128 0, 0,
82d2de5a 5129 GP_1_28_FN, GPSR1_28,
0b0ffc96
TK		 5130 GP_1_27_FN, GPSR1_27,
5131 GP_1_26_FN, GPSR1_26,
5132 GP_1_25_FN, GPSR1_25,
5133 GP_1_24_FN, GPSR1_24,
5134 GP_1_23_FN, GPSR1_23,
5135 GP_1_22_FN, GPSR1_22,
5136 GP_1_21_FN, GPSR1_21,
5137 GP_1_20_FN, GPSR1_20,
5138 GP_1_19_FN, GPSR1_19,
5139 GP_1_18_FN, GPSR1_18,
5140 GP_1_17_FN, GPSR1_17,
5141 GP_1_16_FN, GPSR1_16,
5142 GP_1_15_FN, GPSR1_15,
5143 GP_1_14_FN, GPSR1_14,
5144 GP_1_13_FN, GPSR1_13,
5145 GP_1_12_FN, GPSR1_12,
5146 GP_1_11_FN, GPSR1_11,
5147 GP_1_10_FN, GPSR1_10,
5148 GP_1_9_FN, GPSR1_9,
5149 GP_1_8_FN, GPSR1_8,
5150 GP_1_7_FN, GPSR1_7,
5151 GP_1_6_FN, GPSR1_6,
5152 GP_1_5_FN, GPSR1_5,
5153 GP_1_4_FN, GPSR1_4,
5154 GP_1_3_FN, GPSR1_3,
5155 GP_1_2_FN, GPSR1_2,
5156 GP_1_1_FN, GPSR1_1,
5157 GP_1_0_FN, GPSR1_0, }
5158 },
5159 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5160 0, 0,
5161 0, 0,
5162 0, 0,
5163 0, 0,
5164 0, 0,
5165 0, 0,
5166 0, 0,
5167 0, 0,
5168 0, 0,
5169 0, 0,
5170 0, 0,
5171 0, 0,
5172 0, 0,
5173 0, 0,
5174 0, 0,
5175 0, 0,
5176 0, 0,
5177 GP_2_14_FN, GPSR2_14,
5178 GP_2_13_FN, GPSR2_13,
5179 GP_2_12_FN, GPSR2_12,
5180 GP_2_11_FN, GPSR2_11,
5181 GP_2_10_FN, GPSR2_10,
5182 GP_2_9_FN, GPSR2_9,
5183 GP_2_8_FN, GPSR2_8,
5184 GP_2_7_FN, GPSR2_7,
5185 GP_2_6_FN, GPSR2_6,
5186 GP_2_5_FN, GPSR2_5,
5187 GP_2_4_FN, GPSR2_4,
5188 GP_2_3_FN, GPSR2_3,
5189 GP_2_2_FN, GPSR2_2,
5190 GP_2_1_FN, GPSR2_1,
5191 GP_2_0_FN, GPSR2_0, }
5192 },
5193 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5194 0, 0,
5195 0, 0,
5196 0, 0,
5197 0, 0,
5198 0, 0,
5199 0, 0,
5200 0, 0,
5201 0, 0,
5202 0, 0,
5203 0, 0,
5204 0, 0,
5205 0, 0,
5206 0, 0,
5207 0, 0,
5208 0, 0,
5209 0, 0,
5210 GP_3_15_FN, GPSR3_15,
5211 GP_3_14_FN, GPSR3_14,
5212 GP_3_13_FN, GPSR3_13,
5213 GP_3_12_FN, GPSR3_12,
5214 GP_3_11_FN, GPSR3_11,
5215 GP_3_10_FN, GPSR3_10,
5216 GP_3_9_FN, GPSR3_9,
5217 GP_3_8_FN, GPSR3_8,
5218 GP_3_7_FN, GPSR3_7,
5219 GP_3_6_FN, GPSR3_6,
5220 GP_3_5_FN, GPSR3_5,
5221 GP_3_4_FN, GPSR3_4,
5222 GP_3_3_FN, GPSR3_3,
5223 GP_3_2_FN, GPSR3_2,
5224 GP_3_1_FN, GPSR3_1,
5225 GP_3_0_FN, GPSR3_0, }
5226 },
5227 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5228 0, 0,
5229 0, 0,
5230 0, 0,
5231 0, 0,
5232 0, 0,
5233 0, 0,
5234 0, 0,
5235 0, 0,
5236 0, 0,
5237 0, 0,
5238 0, 0,
5239 0, 0,
5240 0, 0,
5241 0, 0,
5242 GP_4_17_FN, GPSR4_17,
5243 GP_4_16_FN, GPSR4_16,
5244 GP_4_15_FN, GPSR4_15,
5245 GP_4_14_FN, GPSR4_14,
5246 GP_4_13_FN, GPSR4_13,
5247 GP_4_12_FN, GPSR4_12,
5248 GP_4_11_FN, GPSR4_11,
5249 GP_4_10_FN, GPSR4_10,
5250 GP_4_9_FN, GPSR4_9,
5251 GP_4_8_FN, GPSR4_8,
5252 GP_4_7_FN, GPSR4_7,
5253 GP_4_6_FN, GPSR4_6,
5254 GP_4_5_FN, GPSR4_5,
5255 GP_4_4_FN, GPSR4_4,
5256 GP_4_3_FN, GPSR4_3,
5257 GP_4_2_FN, GPSR4_2,
5258 GP_4_1_FN, GPSR4_1,
5259 GP_4_0_FN, GPSR4_0, }
5260 },
5261 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5262 0, 0,
5263 0, 0,
5264 0, 0,
5265 0, 0,
5266 0, 0,
5267 0, 0,
5268 GP_5_25_FN, GPSR5_25,
5269 GP_5_24_FN, GPSR5_24,
5270 GP_5_23_FN, GPSR5_23,
5271 GP_5_22_FN, GPSR5_22,
5272 GP_5_21_FN, GPSR5_21,
5273 GP_5_20_FN, GPSR5_20,
5274 GP_5_19_FN, GPSR5_19,
5275 GP_5_18_FN, GPSR5_18,
5276 GP_5_17_FN, GPSR5_17,
5277 GP_5_16_FN, GPSR5_16,
5278 GP_5_15_FN, GPSR5_15,
5279 GP_5_14_FN, GPSR5_14,
5280 GP_5_13_FN, GPSR5_13,
5281 GP_5_12_FN, GPSR5_12,
5282 GP_5_11_FN, GPSR5_11,
5283 GP_5_10_FN, GPSR5_10,
5284 GP_5_9_FN, GPSR5_9,
5285 GP_5_8_FN, GPSR5_8,
5286 GP_5_7_FN, GPSR5_7,
5287 GP_5_6_FN, GPSR5_6,
5288 GP_5_5_FN, GPSR5_5,
5289 GP_5_4_FN, GPSR5_4,
5290 GP_5_3_FN, GPSR5_3,
5291 GP_5_2_FN, GPSR5_2,
5292 GP_5_1_FN, GPSR5_1,
5293 GP_5_0_FN, GPSR5_0, }
5294 },
5295 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5296 GP_6_31_FN, GPSR6_31,
5297 GP_6_30_FN, GPSR6_30,
5298 GP_6_29_FN, GPSR6_29,
5299 GP_6_28_FN, GPSR6_28,
5300 GP_6_27_FN, GPSR6_27,
5301 GP_6_26_FN, GPSR6_26,
5302 GP_6_25_FN, GPSR6_25,
5303 GP_6_24_FN, GPSR6_24,
5304 GP_6_23_FN, GPSR6_23,
5305 GP_6_22_FN, GPSR6_22,
5306 GP_6_21_FN, GPSR6_21,
5307 GP_6_20_FN, GPSR6_20,
5308 GP_6_19_FN, GPSR6_19,
5309 GP_6_18_FN, GPSR6_18,
5310 GP_6_17_FN, GPSR6_17,
5311 GP_6_16_FN, GPSR6_16,
5312 GP_6_15_FN, GPSR6_15,
5313 GP_6_14_FN, GPSR6_14,
5314 GP_6_13_FN, GPSR6_13,
5315 GP_6_12_FN, GPSR6_12,
5316 GP_6_11_FN, GPSR6_11,
5317 GP_6_10_FN, GPSR6_10,
5318 GP_6_9_FN, GPSR6_9,
5319 GP_6_8_FN, GPSR6_8,
5320 GP_6_7_FN, GPSR6_7,
5321 GP_6_6_FN, GPSR6_6,
5322 GP_6_5_FN, GPSR6_5,
5323 GP_6_4_FN, GPSR6_4,
5324 GP_6_3_FN, GPSR6_3,
5325 GP_6_2_FN, GPSR6_2,
5326 GP_6_1_FN, GPSR6_1,
5327 GP_6_0_FN, GPSR6_0, }
5328 },
5329 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5330 0, 0,
5331 0, 0,
5332 0, 0,
5333 0, 0,
5334 0, 0,
5335 0, 0,
5336 0, 0,
5337 0, 0,
5338 0, 0,
5339 0, 0,
5340 0, 0,
5341 0, 0,
5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 0, 0,
5346 0, 0,
5347 0, 0,
5348 0, 0,
5349 0, 0,
5350 0, 0,
5351 0, 0,
5352 0, 0,
5353 0, 0,
5354 0, 0,
5355 0, 0,
5356 0, 0,
5357 0, 0,
5358 GP_7_3_FN, GPSR7_3,
5359 GP_7_2_FN, GPSR7_2,
5360 GP_7_1_FN, GPSR7_1,
5361 GP_7_0_FN, GPSR7_0, }
5362 },
5363#undef F_
5364#undef FM
5365
5366#define F_(x, y) x,
5367#define FM(x) FN_##x,
5368 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5369 IP0_31_28
5370 IP0_27_24
5371 IP0_23_20
5372 IP0_19_16
5373 IP0_15_12
5374 IP0_11_8
5375 IP0_7_4
5376 IP0_3_0 }
5377 },
5378 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5379 IP1_31_28
5380 IP1_27_24
5381 IP1_23_20
5382 IP1_19_16
5383 IP1_15_12
5384 IP1_11_8
5385 IP1_7_4
5386 IP1_3_0 }
5387 },
5388 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5389 IP2_31_28
5390 IP2_27_24
5391 IP2_23_20
5392 IP2_19_16
5393 IP2_15_12
5394 IP2_11_8
5395 IP2_7_4
5396 IP2_3_0 }
5397 },
5398 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5399 IP3_31_28
5400 IP3_27_24
5401 IP3_23_20
5402 IP3_19_16
5403 IP3_15_12
5404 IP3_11_8
5405 IP3_7_4
5406 IP3_3_0 }
5407 },
5408 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5409 IP4_31_28
5410 IP4_27_24
5411 IP4_23_20
5412 IP4_19_16
5413 IP4_15_12
5414 IP4_11_8
5415 IP4_7_4
5416 IP4_3_0 }
5417 },
5418 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5419 IP5_31_28
5420 IP5_27_24
5421 IP5_23_20
5422 IP5_19_16
5423 IP5_15_12
5424 IP5_11_8
5425 IP5_7_4
5426 IP5_3_0 }
5427 },
5428 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5429 IP6_31_28
5430 IP6_27_24
5431 IP6_23_20
5432 IP6_19_16
5433 IP6_15_12
5434 IP6_11_8
5435 IP6_7_4
5436 IP6_3_0 }
5437 },
5438 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5439 IP7_31_28
5440 IP7_27_24
5441 IP7_23_20
5442 IP7_19_16
30cd1c46 5443 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5444 IP7_11_8
5445 IP7_7_4
5446 IP7_3_0 }
5447 },
5448 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5449 IP8_31_28
5450 IP8_27_24
5451 IP8_23_20
5452 IP8_19_16
5453 IP8_15_12
5454 IP8_11_8
5455 IP8_7_4
5456 IP8_3_0 }
5457 },
5458 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5459 IP9_31_28
5460 IP9_27_24
5461 IP9_23_20
5462 IP9_19_16
5463 IP9_15_12
5464 IP9_11_8
5465 IP9_7_4
5466 IP9_3_0 }
5467 },
5468 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5469 IP10_31_28
5470 IP10_27_24
5471 IP10_23_20
5472 IP10_19_16
5473 IP10_15_12
5474 IP10_11_8
5475 IP10_7_4
5476 IP10_3_0 }
5477 },
5478 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5479 IP11_31_28
5480 IP11_27_24
5481 IP11_23_20
5482 IP11_19_16
5483 IP11_15_12
5484 IP11_11_8
5485 IP11_7_4
5486 IP11_3_0 }
5487 },
5488 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5489 IP12_31_28
5490 IP12_27_24
5491 IP12_23_20
5492 IP12_19_16
5493 IP12_15_12
5494 IP12_11_8
5495 IP12_7_4
5496 IP12_3_0 }
5497 },
5498 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5499 IP13_31_28
5500 IP13_27_24
5501 IP13_23_20
5502 IP13_19_16
5503 IP13_15_12
5504 IP13_11_8
5505 IP13_7_4
5506 IP13_3_0 }
5507 },
5508 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5509 IP14_31_28
5510 IP14_27_24
5511 IP14_23_20
5512 IP14_19_16
5513 IP14_15_12
5514 IP14_11_8
5515 IP14_7_4
5516 IP14_3_0 }
5517 },
5518 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5519 IP15_31_28
5520 IP15_27_24
5521 IP15_23_20
5522 IP15_19_16
5523 IP15_15_12
5524 IP15_11_8
5525 IP15_7_4
5526 IP15_3_0 }
5527 },
5528 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5529 IP16_31_28
5530 IP16_27_24
5531 IP16_23_20
5532 IP16_19_16
5533 IP16_15_12
5534 IP16_11_8
5535 IP16_7_4
5536 IP16_3_0 }
5537 },
5538 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 5539 IP17_31_28
5540 IP17_27_24
5541 IP17_23_20
5542 IP17_19_16
5543 IP17_15_12
5544 IP17_11_8
0b0ffc96
TK		 5545 IP17_7_4
5546 IP17_3_0 }
5547 },
b205914c
GU		 5548 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5549 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5550 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5551 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5552 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5553 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5554 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5555 IP18_7_4
5556 IP18_3_0 }
5557 },
0b0ffc96
TK		 5558#undef F_
5559#undef FM
5560
5561#define F_(x, y) x,
5562#define FM(x) FN_##x,
5563 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 5564 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5565 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5566 MOD_SEL0_31_30_29
0b0ffc96
TK		 5567 MOD_SEL0_28_27
5568 MOD_SEL0_26_25_24
5569 MOD_SEL0_23
5570 MOD_SEL0_22
b205914c
GU		 5571 MOD_SEL0_21
5572 MOD_SEL0_20
0b0ffc96 5573 MOD_SEL0_19
b205914c
GU		 5574 MOD_SEL0_18_17
5575 MOD_SEL0_16
5576 0, 0, /* RESERVED 15 */
5577 MOD_SEL0_14_13
0b0ffc96
TK		 5578 MOD_SEL0_12
5579 MOD_SEL0_11
5580 MOD_SEL0_10
b205914c 5581 MOD_SEL0_9_8
0b0ffc96 5582 MOD_SEL0_7_6
b205914c
GU		 5583 MOD_SEL0_5
5584 MOD_SEL0_4_3
5585 /* RESERVED 2, 1, 0 */
5586 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 5587 },
5588 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5589 2, 3, 1, 2, 3, 1, 1, 2, 1,
5590 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5591 MOD_SEL1_31_30
5592 MOD_SEL1_29_28_27
5593 MOD_SEL1_26
5594 MOD_SEL1_25_24
5595 MOD_SEL1_23_22_21
5596 MOD_SEL1_20
5597 MOD_SEL1_19
5598 MOD_SEL1_18_17
5599 MOD_SEL1_16
5600 MOD_SEL1_15_14
5601 MOD_SEL1_13
5602 MOD_SEL1_12
5603 MOD_SEL1_11
5604 MOD_SEL1_10
5605 MOD_SEL1_9
5606 0, 0, 0, 0, /* RESERVED 8, 7 */
5607 MOD_SEL1_6
5608 MOD_SEL1_5
5609 MOD_SEL1_4
5610 MOD_SEL1_3
5611 MOD_SEL1_2
5612 MOD_SEL1_1
5613 MOD_SEL1_0 }
5614 },
5615 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 5616 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5617 4, 4, 4, 3, 1) {
0b0ffc96
TK		 5618 MOD_SEL2_31
5619 MOD_SEL2_30
5620 MOD_SEL2_29
b205914c
GU		 5621 MOD_SEL2_28_27
5622 MOD_SEL2_26
5623 MOD_SEL2_25_24_23
3c612d2c
TK		 5624 /* RESERVED 22 */
5625 0, 0,
b205914c
GU		 5626 MOD_SEL2_21
5627 MOD_SEL2_20
5628 MOD_SEL2_19
5629 MOD_SEL2_18
5630 MOD_SEL2_17
5631 /* RESERVED 16 */
0b0ffc96 5632 0, 0,
0b0ffc96
TK		 5633 /* RESERVED 15, 14, 13, 12 */
5634 0, 0, 0, 0, 0, 0, 0, 0,
5635 0, 0, 0, 0, 0, 0, 0, 0,
5636 /* RESERVED 11, 10, 9, 8 */
5637 0, 0, 0, 0, 0, 0, 0, 0,
5638 0, 0, 0, 0, 0, 0, 0, 0,
5639 /* RESERVED 7, 6, 5, 4 */
5640 0, 0, 0, 0, 0, 0, 0, 0,
5641 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5642 /* RESERVED 3, 2, 1 */
5643 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5644 MOD_SEL2_0 }
5645 },
5646 { },
5647};
5648
92e6d9a2 5649static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5650 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5651 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5652 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5653 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5654 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5655 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5656 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5657 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5658 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5659 } },
5660 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5661 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5662 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5663 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5664 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5665 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5666 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5667 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5668 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5669 } },
5670 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5671 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5672 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5673 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5674 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5675 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5676 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5677 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5678 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5679 } },
92e6d9a2 5680 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5681 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5682 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5683 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5684 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5685 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5686 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5687 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5688 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5689 } },
5690 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5691 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5692 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5693 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5694 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5695 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5696 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5697 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5698 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5699 } },
5700 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5701 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5702 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5703 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5704 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5705 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5706 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5707 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5708 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5709 } },
5710 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5711 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5712 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5713 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5714 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5715 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5716 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5717 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5718 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5719 } },
5720 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5721 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5722 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5723 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5724 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5725 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5726 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5727 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5728 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5729 } },
5730 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
82d2de5a 5731 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5732 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5733 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5734 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5735 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5736 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5737 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5738 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5739 } },
5740 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5741 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5742 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5743 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5744 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5745 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5746 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5747 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5748 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5749 } },
5750 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5751 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5752 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5753 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5754 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5755 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5756 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5757 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5758 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5759 } },
5760 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5761 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5762 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5763 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5764 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5765 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5766 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5767 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5768 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5769 } },
5770 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5771 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5772 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5773 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5774 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5775 } },
5776 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5777 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5778 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5779 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5780 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5781 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5782 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5783 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5784 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5785 } },
5786 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5787 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5788 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5789 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5790 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5791 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5792 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5793 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5794 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5795 } },
5796 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5797 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5798 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5799 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5800 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5801 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5802 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5803 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5804 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5805 } },
5806 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5807 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5808 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5809 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5810 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5811 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5812 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5813 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5814 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5815 } },
5816 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5817 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5818 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5819 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5820 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5821 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5822 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5823 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5824 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5825 } },
5826 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
8714a9c1 5827 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
92e6d9a2
LP		 5828 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5829 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5830 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
8714a9c1 5831 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
92e6d9a2
LP		 5832 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5833 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5834 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5835 } },
5836 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5837 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5838 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5839 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5840 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5841 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5842 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5843 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5844 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5845 } },
5846 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5847 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5848 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5849 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5850 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5851 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5852 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5853 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5854 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5855 } },
5856 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5857 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5858 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5859 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5860 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5861 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5862 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5863 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5864 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5865 } },
5866 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5867 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5868 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5869 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5870 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5871 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5872 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5873 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5874 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5875 } },
5876 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5877 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5878 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5879 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5880 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5881 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5882 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5883 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5884 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5885 } },
5886 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5887 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5888 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5889 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5890 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5891 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5892 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5893 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5894 } },
5895 { },
5896};
5897
e2aad846
GU		 5898enum ioctrl_regs {
5899 POCCTRL,
5900};
5901
5902static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5903 [POCCTRL] = { 0xe6060380, },
5904 { /* sentinel */ },
5905};
5906
e9eace32
WS		 5907static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5908{
5909 int bit = -EINVAL;
5910
e2aad846 5911 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
e9eace32
WS		 5912
5913 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5914 bit = pin & 0x1f;
5915
5916 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5917 bit = (pin & 0x1f) + 12;
5918
5919 return bit;
5920}
5921
6f4b74f3
GU		 5922static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5923 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5924 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5925 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5926 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5927 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5928 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5929 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5930 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5931 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5932 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5933 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5934 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5935 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5936 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5937 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5938 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5939 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5940 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5941 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5942 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5943 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5944 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5945 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5946 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5947 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5948 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5949 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5950 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5951 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5952 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5953 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5954 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5955 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5956 } },
5957 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5958 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5959 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5960 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5961 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5962 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5963 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5964 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5965 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5966 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5967 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5968 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5969 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5970 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5971 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5972 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5973 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5974 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5975 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5976 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5977 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5978 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5979 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5980 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5981 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5982 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5983 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5984 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5985 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5986 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5987 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5988 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5989 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5990 } },
5991 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
82d2de5a 5992 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
6f4b74f3
GU		 5993 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5994 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5995 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5996 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5997 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5998 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5999 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
6000 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
6001 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
6002 [10] = RCAR_GP_PIN(0, 0), /* D0 */
6003 [11] = RCAR_GP_PIN(0, 1), /* D1 */
6004 [12] = RCAR_GP_PIN(0, 2), /* D2 */
6005 [13] = RCAR_GP_PIN(0, 3), /* D3 */
6006 [14] = RCAR_GP_PIN(0, 4), /* D4 */
6007 [15] = RCAR_GP_PIN(0, 5), /* D5 */
6008 [16] = RCAR_GP_PIN(0, 6), /* D6 */
6009 [17] = RCAR_GP_PIN(0, 7), /* D7 */
6010 [18] = RCAR_GP_PIN(0, 8), /* D8 */
6011 [19] = RCAR_GP_PIN(0, 9), /* D9 */
6012 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6013 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6014 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6015 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6016 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6017 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6018 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6019 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6020 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
6021 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
6022 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6023 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6024 } },
6025 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6026 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6027 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6028 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6029 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6030 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6031 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6032 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6033 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6034 [ 8] = PIN_NONE,
6035 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6036 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6037 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6038 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6039 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6040 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6041 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6042 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6043 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6044 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6045 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6046 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6047 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6048 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6049 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6050 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6051 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6052 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6053 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6054 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6055 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6056 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6057 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6058 } },
6059 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6060 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6061 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6062 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6063 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6064 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6065 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6066 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6067 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6068 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6069 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6070 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6071 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6072 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6073 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6074 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6075 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
8714a9c1 6076 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6f4b74f3
GU		 6077 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6078 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6079 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
8714a9c1 6080 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6f4b74f3
GU		 6081 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6082 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6083 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6084 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6085 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6086 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6087 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6088 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6089 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6090 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6091 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6092 } },
6093 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6094 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6095 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6096 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6097 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6098 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6099 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6100 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6101 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6102 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6103 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6104 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6105 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6106 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6107 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6108 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6109 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6110 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6111 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6112 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6113 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6114 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6115 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6116 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6117 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6118 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6119 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6120 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6121 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6122 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6123 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6124 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6125 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6126 } },
6127 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6128 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6129 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6130 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6131 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6132 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6133 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6134 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6135 [ 7] = PIN_NONE,
6136 [ 8] = PIN_NONE,
6137 [ 9] = PIN_NONE,
6138 [10] = PIN_NONE,
6139 [11] = PIN_NONE,
6140 [12] = PIN_NONE,
6141 [13] = PIN_NONE,
6142 [14] = PIN_NONE,
6143 [15] = PIN_NONE,
6144 [16] = PIN_NONE,
6145 [17] = PIN_NONE,
6146 [18] = PIN_NONE,
6147 [19] = PIN_NONE,
6148 [20] = PIN_NONE,
6149 [21] = PIN_NONE,
6150 [22] = PIN_NONE,
6151 [23] = PIN_NONE,
6152 [24] = PIN_NONE,
6153 [25] = PIN_NONE,
6154 [26] = PIN_NONE,
6155 [27] = PIN_NONE,
6156 [28] = PIN_NONE,
6157 [29] = PIN_NONE,
6158 [30] = PIN_NONE,
6159 [31] = PIN_NONE,
6160 } },
6161 { /* sentinel */ },
56065524
UH		 6162};
6163
6164static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6165 unsigned int pin)
6166{
6f4b74f3
GU		 6167 const struct pinmux_bias_reg *reg;
6168 unsigned int bit;
56065524 6169
6f4b74f3
GU		 6170 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6171 if (!reg)
56065524
UH		 6172 return PIN_CONFIG_BIAS_DISABLE;
6173
6f4b74f3 6174 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
56065524 6175 return PIN_CONFIG_BIAS_DISABLE;
6f4b74f3 6176 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
42831cf9
NS		 6177 return PIN_CONFIG_BIAS_PULL_UP;
6178 else
6179 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 6180}
6181
6182static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6183 unsigned int bias)
6184{
6f4b74f3 6185 const struct pinmux_bias_reg *reg;
56065524 6186 u32 enable, updown;
6f4b74f3 6187 unsigned int bit;
56065524 6188
6f4b74f3
GU		 6189 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6190 if (!reg)
56065524
UH		 6191 return;
6192
6f4b74f3 6193 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
56065524 6194 if (bias != PIN_CONFIG_BIAS_DISABLE)
6f4b74f3 6195 enable |= BIT(bit);
56065524 6196
6f4b74f3 6197 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
56065524 6198 if (bias == PIN_CONFIG_BIAS_PULL_UP)
6f4b74f3 6199 updown |= BIT(bit);
56065524 6200
6f4b74f3
GU		 6201 sh_pfc_write(pfc, reg->pud, updown);
6202 sh_pfc_write(pfc, reg->puen, enable);
56065524
UH		 6203}
6204
b205914c
GU		 6205static const struct soc_device_attribute r8a7795es1[] = {
6206 { .soc_id = "r8a7795", .revision = "ES1.*" },
6207 { /* sentinel */ }
6208};
6209
6210static int r8a7795_pinmux_init(struct sh_pfc *pfc)
6211{
6212 if (soc_device_match(r8a7795es1))
6213 pfc->info = &r8a7795es1_pinmux_info;
6214
6215 return 0;
6216}
6217
e9eace32 6218static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 6219 .init = r8a7795_pinmux_init,
e9eace32 6220 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 6221 .get_bias = r8a7795_pinmux_get_bias,
6222 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 6223};
6224
0b0ffc96 6225const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 6226 .name = "r8a77951_pfc",
e9eace32 6227 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 6228 .unlock_reg = 0xe6060000, /* PMMR */
6229
6230 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6231
6232 .pins = pinmux_pins,
6233 .nr_pins = ARRAY_SIZE(pinmux_pins),
6234 .groups = pinmux_groups,
6235 .nr_groups = ARRAY_SIZE(pinmux_groups),
6236 .functions = pinmux_functions,
6237 .nr_functions = ARRAY_SIZE(pinmux_functions),
6238
6239 .cfg_regs = pinmux_config_regs,
92e6d9a2 6240 .drive_regs = pinmux_drive_regs,
6f4b74f3 6241 .bias_regs = pinmux_bias_regs,
e2aad846 6242 .ioctrl_regs = pinmux_ioctrl_regs,
0b0ffc96 6243
b8b47d67
GU		 6244 .pinmux_data = pinmux_data,
6245 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 6246};
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