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pinctrl: sh-pfc: r8a7795: Add HSCIF pins, groups, and functions
[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524
UH		 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
fc8fd9be 64#define GPSR1_21 F_(CS1_N, IP4_19_16)
0b0ffc96
TK		 65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
b205914c
GU		 105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
b205914c
GU		 123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
b205914c
GU		 143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 146#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 148#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 151#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 169
170/* GPSR6 */
f9d13080
YS		 171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
b205914c
GU		 173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
e2ab1770
TK		 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
fc8fd9be 250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
bad7cc19
TK		 363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
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TK		 365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
371 GPSR6_28 \
372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
30cd1c46 415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
0b0ffc96
TK		 416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
b205914c
GU		 439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
ae03c4ec 471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
0b0ffc96
TK		 472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
474#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
eada11ac 482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
0b0ffc96
TK		 483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
b205914c 506#define PINMUX_MOD_SELS \
0b0ffc96 507\
b205914c
GU		 508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
0b0ffc96 510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 514MOD_SEL0_23 MOD_SEL1_23_22_21 \
3c612d2c 515MOD_SEL0_22 \
b205914c
GU		 516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 522 MOD_SEL1_15_14 \
b205914c
GU		 523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
0b0ffc96
TK		 525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
b205914c 528MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
b205914c
GU		 531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
0b0ffc96
TK		 535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
ea9c7405
NS		 538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
551 FM(CLKOUT) FM(PRESETOUT) \
552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 554
555enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562#define F_(x, y)
563#define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570#undef F_
571#undef FM
572
573#define F_(x, y)
574#define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
ea9c7405 579 PINMUX_STATIC
0b0ffc96
TK		 580 PINMUX_MARK_END,
581#undef F_
582#undef FM
583};
584
585static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
8d4df573
GU		 588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
590 PINMUX_SINGLE(HDMI0_CEC),
591 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 592 PINMUX_SINGLE(I2C_SEL_0_1),
593 PINMUX_SINGLE(I2C_SEL_3_1),
594 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 595 PINMUX_SINGLE(MSIOF0_RXD),
596 PINMUX_SINGLE(MSIOF0_SCK),
597 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 598 PINMUX_SINGLE(SSI_SCK5),
599 PINMUX_SINGLE(SSI_SDATA5),
600 PINMUX_SINGLE(SSI_WS5),
601
0b0ffc96 602 /* IPSR0 */
e01678e3 603 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 604 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
605
e01678e3 606 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 607 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
608 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
609
e01678e3 610 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 611 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
612 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
613
e01678e3 614 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 615 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
619 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 621 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 622
623 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
624 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
625 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
626
e01678e3
GU		 627 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
628 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
629 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 630 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 633 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 634
e01678e3
GU		 635 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
636 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
637 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 638 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
639 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 641 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 642
643 /* IPSR1 */
e01678e3
GU		 644 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
645 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
646 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 647 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
648 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 649 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 650
e01678e3
GU		 651 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
652 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
653 PINMUX_IPSR_GPSR(IP1_7_4, A25),
654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 658
e01678e3
GU		 659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
661 PINMUX_IPSR_GPSR(IP1_11_8, A24),
662 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 663 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 665 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 666
e01678e3
GU		 667 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
668 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
669 PINMUX_IPSR_GPSR(IP1_15_12, A23),
670 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 671 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
672 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 673 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
674 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 675
e01678e3
GU		 676 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
677 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
678 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 679 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
680 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
681
682 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 683 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 684 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
685 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 689 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 690 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
692
e01678e3
GU		 693 PINMUX_IPSR_GPSR(IP1_31_28, A0),
694 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 695 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 696 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
697 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 698 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
699
700 /* IPSR2 */
e01678e3
GU		 701 PINMUX_IPSR_GPSR(IP2_3_0, A1),
702 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 703 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 704 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
705 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 706 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
707
e01678e3
GU		 708 PINMUX_IPSR_GPSR(IP2_7_4, A2),
709 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 710 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 711 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
712 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 713 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
714
e01678e3
GU		 715 PINMUX_IPSR_GPSR(IP2_11_8, A3),
716 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 717 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 718 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
719 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 720 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
721
e01678e3
GU		 722 PINMUX_IPSR_GPSR(IP2_15_12, A4),
723 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 724 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 725 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
726 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
727 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 728
e01678e3
GU		 729 PINMUX_IPSR_GPSR(IP2_19_16, A5),
730 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 731 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
732 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 733 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
734 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
735 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 736
e01678e3
GU		 737 PINMUX_IPSR_GPSR(IP2_23_20, A6),
738 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 739 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
740 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 741 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
742 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
743 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 744
e01678e3
GU		 745 PINMUX_IPSR_GPSR(IP2_27_24, A7),
746 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 747 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
748 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 749 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
750 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
751 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 752
e01678e3 753 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 754 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
755 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
756 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
760
761 /* IPSR3 */
e01678e3 762 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 763 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
764 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 765 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 766
e01678e3 767 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 768 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
769 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 770 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 771
e01678e3 772 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 773 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
774 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 776 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
777 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 778 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
779 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
781
e01678e3
GU		 782 PINMUX_IPSR_GPSR(IP3_15_12, A12),
783 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 784 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
785 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 786 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
787 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 788
e01678e3
GU		 789 PINMUX_IPSR_GPSR(IP3_19_16, A13),
790 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 791 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
792 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 793 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
794 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 795
e01678e3
GU		 796 PINMUX_IPSR_GPSR(IP3_23_20, A14),
797 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 798 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 799 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
800 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
801 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 802
e01678e3
GU		 803 PINMUX_IPSR_GPSR(IP3_27_24, A15),
804 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 805 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 806 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
807 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
808 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 809
e01678e3
GU		 810 PINMUX_IPSR_GPSR(IP3_31_28, A16),
811 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
812 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
813 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 814
815 /* IPSR4 */
e01678e3
GU		 816 PINMUX_IPSR_GPSR(IP4_3_0, A17),
817 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
818 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
820
821 PINMUX_IPSR_GPSR(IP4_7_4, A18),
822 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
823 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
824 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
825
826 PINMUX_IPSR_GPSR(IP4_11_8, A19),
827 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
828 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
829 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
830
831 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
832 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
833
fc8fd9be 834 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
e01678e3 835 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 836 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
837
e01678e3
GU		 838 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
839 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 840 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 841 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
842 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
843 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
844 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 845 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
846
e01678e3 847 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 848 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
849 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
850 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
851 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
853
e01678e3 854 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 855 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
856 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
858 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
860
861 /* IPSR5 */
e01678e3 862 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 863 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 864 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
865 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 866 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 867 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 868 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
869
e01678e3 870 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 871 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 872 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
873 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 874 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 875 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
876 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 877 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
878
879 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 880 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
881 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
882 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 883
e01678e3 884 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 885 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
886 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 887 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
888 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 889
e01678e3 890 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 891 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 893 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
894 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 895
e01678e3 896 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 897 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 898 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
899 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 900
e01678e3 901 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 902 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 903 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
904 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 905
e01678e3 906 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 907 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 908 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
909 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 910
911 /* IPSR6 */
e01678e3 912 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 913 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 914 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
915 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 916
b205914c
GU		 917 PINMUX_IPSR_GPSR(IP6_7_4, D6),
918 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
920 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 921
b205914c
GU		 922 PINMUX_IPSR_GPSR(IP6_11_8, D7),
923 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
924 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
925 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 926
b205914c
GU		 927 PINMUX_IPSR_GPSR(IP6_15_12, D8),
928 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
929 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
930 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
931 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
932 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 933
b205914c
GU		 934 PINMUX_IPSR_GPSR(IP6_19_16, D9),
935 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
936 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
937 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 939
b205914c
GU		 940 PINMUX_IPSR_GPSR(IP6_23_20, D10),
941 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
942 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
944 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
945 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
946 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 947
b205914c
GU		 948 PINMUX_IPSR_GPSR(IP6_27_24, D11),
949 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
950 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
951 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
952 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
953 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
954 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 955
b205914c
GU		 956 PINMUX_IPSR_GPSR(IP6_31_28, D12),
957 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
958 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
959 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
960 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
961 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 962
b205914c
GU		 963 /* IPSR7 */
964 PINMUX_IPSR_GPSR(IP7_3_0, D13),
965 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
966 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
967 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
968 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
969 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 970
b205914c
GU		 971 PINMUX_IPSR_GPSR(IP7_7_4, D14),
972 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
973 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
974 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
975 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
976 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
977 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 978
b205914c
GU		 979 PINMUX_IPSR_GPSR(IP7_11_8, D15),
980 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
981 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
982 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
983 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
984 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
985 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 986
b205914c
GU		 987 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
988 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
989 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
992 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 994
b205914c
GU		 995 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
996 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 999
b205914c
GU		 1000 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1001 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1002 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1003 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1004
b205914c
GU		 1005 /* IPSR8 */
1006 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1007 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1010
b205914c
GU		 1011 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1012 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1013 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1014 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1015
b205914c
GU		 1016 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1017 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1018 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1019
b205914c
GU		 1020 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1021 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
3c612d2c 1022 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
b205914c
GU		 1023 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1024 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1025
b205914c
GU		 1026 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1027 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1028 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
3c612d2c 1029 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
b205914c
GU		 1030 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1031 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1032
b205914c
GU		 1033 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1034 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1035 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
3c612d2c 1036 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
b205914c
GU		 1037 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1038 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1039
b205914c
GU		 1040 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1041 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1042 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
3c612d2c 1043 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
b205914c
GU		 1044 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1045 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1046
b205914c
GU		 1047 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1048 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1049 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
3c612d2c 1050 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
b205914c
GU		 1051 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1052 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1053
b205914c
GU		 1054 /* IPSR9 */
1055 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1056 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1057
b205914c
GU		 1058 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1059 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1060
b205914c
GU		 1061 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1062 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1063
b205914c
GU		 1064 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1065 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1066
b205914c
GU		 1067 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1068 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1069
b205914c
GU		 1070 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1071 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1072
b205914c
GU		 1073 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1074 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1075 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1076
b205914c
GU		 1077 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1078 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1079
b205914c
GU		 1080 /* IPSR10 */
1081 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1082 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1083
b205914c
GU		 1084 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1085 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1086
b205914c
GU		 1087 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1088 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1089
b205914c
GU		 1090 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1091 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1092
b205914c
GU		 1093 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1094 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1095
b205914c
GU		 1096 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1097 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1098 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1101 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1103
b205914c
GU		 1104 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1105 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1106 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1107
b205914c
GU		 1108 /* IPSR11 */
1109 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1110 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1111 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1112
1113 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1114 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1115
1116 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1117 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1118 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1119
1120 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1121 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1122
1123 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1124 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1125
1126 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1127 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1128
1129 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1130 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1131 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1132 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1136 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1137 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1139
1140 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1141 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1142 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1143 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1144 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1145
b205914c
GU		 1146 /* IPSR12 */
1147 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1148 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1152
1153 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1154 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1155 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1156 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1157 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1158 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1159 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1160 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1161
1162 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1163 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1164 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1165 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1166 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1167 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1168 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1169 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1170
1171 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1172 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1174 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1175 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1176
1177 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1178 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1179 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1180 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1181 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1182
1183 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1184 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1185 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1186 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1187 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1188 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1189 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1190
1191 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1192 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1198
1199 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
eada11ac 1200 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
b205914c
GU		 1201 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1206
b205914c
GU		 1207 /* IPSR13 */
1208 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1209 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1210 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1211 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1212 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1213 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1214
1215 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1216 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1217 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1218 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1219 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1220 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1221
1222 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1223 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1224 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1225 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1226 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1227 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1229 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1230
1231 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1232 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1233 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1237
1238 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1239 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1240 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1241 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1242 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1243 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1244
1245 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1247 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1249 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1252 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1253
1254 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1255 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1256 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1257 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1258 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1260 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1263 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1264 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1265 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1266
b205914c
GU		 1267 /* IPSR14 */
1268 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1269 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
3c612d2c 1270 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
b205914c
GU		 1271 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1272 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1273 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1274 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
ae03c4ec 1275 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
b205914c
GU		 1276
1277 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1278 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1279 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1280 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1281 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1282 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1283 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1284 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1285
1286 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1287 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1291 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1293 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1294
1295 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1296 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1297 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1298
1299 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1300 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1301
1302 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1303 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1304
1305 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1306 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1307
b205914c
GU		 1308 /* IPSR15 */
1309 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1310
1311 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1312 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1313
68e63892 1314 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1315 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1322
1323 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1324 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1326 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1327 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1328 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1332 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1340 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1348 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1354
b205914c
GU		 1355 /* IPSR16 */
1356 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1357 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1358 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1359
1360 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1361 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1362 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1365 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1366 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1367
1368 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1369 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1371 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1372 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1373 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1374 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1375
1376 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1377 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1378 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1379 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1380 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1381 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1382 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1383
1384 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1385 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1386 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1387 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1388 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1389 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1390 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
ae03c4ec 1391 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
b205914c
GU		 1392
1393 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1394 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1395 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1396 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1397 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1398 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1399 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1400
1401 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1402 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1403 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1404 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1406 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
712f36fb 1408 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
20cacae1 1409
b205914c
GU		 1410 /* IPSR17 */
1411 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1412 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1413
1414 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
eada11ac 1415 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
b205914c
GU		 1416 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1417 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
ae03c4ec 1418 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
b205914c
GU		 1419
1420 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1421 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1422 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1423 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1424 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1425 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1426 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1427
1428 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1429 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1430 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1431 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1432 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1433 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1434
1435 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1436 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1439 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1440 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1441 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1444
1445 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1446 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1447 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1448 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1449 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1450 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1451 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1452 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1453 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1454
1455 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1456 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1457 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1458 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
50d83156 1459 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
b205914c
GU		 1460 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1461 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
ae03c4ec 1462 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
b205914c
GU		 1463 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1464 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1466
1467 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1468 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1469 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1470 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1471 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1472 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1473 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1474 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1475 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1476
1477 /* IPSR18 */
f9d13080 1478 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
b205914c
GU		 1479 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1480 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1481 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1482 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1483 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1484 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1485 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1486 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1487
f9d13080 1488 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
b205914c
GU		 1489 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1490 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1491 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1492 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1493 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1494 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1495 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1496 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1497
b205914c
GU		 1498/*
1499 * Static pins can not be muxed between different functions but
1500 * still needs a mark entry in the pinmux list. Add each static
1501 * pin to the list without an associated function. The sh-pfc
1502 * core will do the right thing and skip trying to mux then pin
1503 * while still applying configuration to it
1504 */
1505#define FM(x) PINMUX_DATA(x##_MARK, 0),
1506 PINMUX_STATIC
1507#undef FM
9b132ba3
KM		 1508};
1509
b205914c
GU		 1510/*
1511 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1512 * Physical layout rows: A - AW, cols: 1 - 39.
1513 */
1514#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1515#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1516#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1517
1518static const struct sh_pfc_pin pinmux_pins[] = {
1519 PINMUX_GPIO_GP_ALL(),
76250a6c 1520
b205914c
GU		 1521 /*
1522 * Pins not associated with a GPIO port.
1523 *
1524 * The pin positions are different between different r8a7795
1525 * packages, all that is needed for the pfc driver is a unique
1526 * number for each pin. To this end use the pin layout from
1527 * R-Car H3SiP to calculate a unique number for each pin.
1528 */
1529 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1573};
1574
55bfea9f
KM		 1575/* - AUDIO CLOCK ------------------------------------------------------------ */
1576static const unsigned int audio_clk_a_a_pins[] = {
1577 /* CLK A */
1578 RCAR_GP_PIN(6, 22),
1579};
1580static const unsigned int audio_clk_a_a_mux[] = {
1581 AUDIO_CLKA_A_MARK,
1582};
1583static const unsigned int audio_clk_a_b_pins[] = {
1584 /* CLK A */
1585 RCAR_GP_PIN(5, 4),
1586};
1587static const unsigned int audio_clk_a_b_mux[] = {
1588 AUDIO_CLKA_B_MARK,
1589};
1590static const unsigned int audio_clk_a_c_pins[] = {
1591 /* CLK A */
1592 RCAR_GP_PIN(5, 19),
1593};
1594static const unsigned int audio_clk_a_c_mux[] = {
1595 AUDIO_CLKA_C_MARK,
1596};
1597static const unsigned int audio_clk_b_a_pins[] = {
1598 /* CLK B */
1599 RCAR_GP_PIN(5, 12),
1600};
1601static const unsigned int audio_clk_b_a_mux[] = {
1602 AUDIO_CLKB_A_MARK,
1603};
1604static const unsigned int audio_clk_b_b_pins[] = {
1605 /* CLK B */
1606 RCAR_GP_PIN(6, 23),
1607};
1608static const unsigned int audio_clk_b_b_mux[] = {
1609 AUDIO_CLKB_B_MARK,
1610};
1611static const unsigned int audio_clk_c_a_pins[] = {
1612 /* CLK C */
1613 RCAR_GP_PIN(5, 21),
1614};
1615static const unsigned int audio_clk_c_a_mux[] = {
1616 AUDIO_CLKC_A_MARK,
1617};
1618static const unsigned int audio_clk_c_b_pins[] = {
1619 /* CLK C */
1620 RCAR_GP_PIN(5, 0),
1621};
1622static const unsigned int audio_clk_c_b_mux[] = {
1623 AUDIO_CLKC_B_MARK,
1624};
1625static const unsigned int audio_clkout_a_pins[] = {
1626 /* CLKOUT */
1627 RCAR_GP_PIN(5, 18),
1628};
1629static const unsigned int audio_clkout_a_mux[] = {
1630 AUDIO_CLKOUT_A_MARK,
1631};
1632static const unsigned int audio_clkout_b_pins[] = {
1633 /* CLKOUT */
1634 RCAR_GP_PIN(6, 28),
1635};
1636static const unsigned int audio_clkout_b_mux[] = {
1637 AUDIO_CLKOUT_B_MARK,
1638};
1639static const unsigned int audio_clkout_c_pins[] = {
1640 /* CLKOUT */
1641 RCAR_GP_PIN(5, 3),
1642};
1643static const unsigned int audio_clkout_c_mux[] = {
1644 AUDIO_CLKOUT_C_MARK,
1645};
1646static const unsigned int audio_clkout_d_pins[] = {
1647 /* CLKOUT */
1648 RCAR_GP_PIN(5, 21),
1649};
1650static const unsigned int audio_clkout_d_mux[] = {
1651 AUDIO_CLKOUT_D_MARK,
1652};
1653static const unsigned int audio_clkout1_a_pins[] = {
1654 /* CLKOUT1 */
1655 RCAR_GP_PIN(5, 15),
1656};
1657static const unsigned int audio_clkout1_a_mux[] = {
1658 AUDIO_CLKOUT1_A_MARK,
1659};
1660static const unsigned int audio_clkout1_b_pins[] = {
1661 /* CLKOUT1 */
1662 RCAR_GP_PIN(6, 29),
1663};
1664static const unsigned int audio_clkout1_b_mux[] = {
1665 AUDIO_CLKOUT1_B_MARK,
1666};
1667static const unsigned int audio_clkout2_a_pins[] = {
1668 /* CLKOUT2 */
1669 RCAR_GP_PIN(5, 16),
1670};
1671static const unsigned int audio_clkout2_a_mux[] = {
1672 AUDIO_CLKOUT2_A_MARK,
1673};
1674static const unsigned int audio_clkout2_b_pins[] = {
1675 /* CLKOUT2 */
1676 RCAR_GP_PIN(6, 30),
1677};
1678static const unsigned int audio_clkout2_b_mux[] = {
1679 AUDIO_CLKOUT2_B_MARK,
1680};
1681static const unsigned int audio_clkout3_a_pins[] = {
1682 /* CLKOUT3 */
1683 RCAR_GP_PIN(5, 19),
1684};
1685static const unsigned int audio_clkout3_a_mux[] = {
1686 AUDIO_CLKOUT3_A_MARK,
1687};
1688static const unsigned int audio_clkout3_b_pins[] = {
1689 /* CLKOUT3 */
1690 RCAR_GP_PIN(6, 31),
1691};
1692static const unsigned int audio_clkout3_b_mux[] = {
1693 AUDIO_CLKOUT3_B_MARK,
1694};
1695
30c078de
GU		 1696/* - EtherAVB --------------------------------------------------------------- */
1697static const unsigned int avb_link_pins[] = {
1698 /* AVB_LINK */
1699 RCAR_GP_PIN(2, 12),
1700};
1701static const unsigned int avb_link_mux[] = {
1702 AVB_LINK_MARK,
1703};
1704static const unsigned int avb_magic_pins[] = {
1705 /* AVB_MAGIC_ */
1706 RCAR_GP_PIN(2, 10),
1707};
1708static const unsigned int avb_magic_mux[] = {
1709 AVB_MAGIC_MARK,
1710};
1711static const unsigned int avb_phy_int_pins[] = {
1712 /* AVB_PHY_INT */
1713 RCAR_GP_PIN(2, 11),
1714};
1715static const unsigned int avb_phy_int_mux[] = {
1716 AVB_PHY_INT_MARK,
1717};
1718static const unsigned int avb_mdc_pins[] = {
1719 /* AVB_MDC, AVB_MDIO */
1720 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1721};
1722static const unsigned int avb_mdc_mux[] = {
1723 AVB_MDC_MARK, AVB_MDIO_MARK,
1724};
1725static const unsigned int avb_mii_pins[] = {
1726 /*
1727 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1728 * AVB_TD1, AVB_TD2, AVB_TD3,
1729 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1730 * AVB_RD1, AVB_RD2, AVB_RD3,
1731 * AVB_TXCREFCLK
1732 */
1733 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1734 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1735 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1736 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1737 PIN_NUMBER('A', 12),
1738
1739};
1740static const unsigned int avb_mii_mux[] = {
1741 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1742 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1743 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1744 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1745 AVB_TXCREFCLK_MARK,
1746};
1747static const unsigned int avb_avtp_pps_pins[] = {
1748 /* AVB_AVTP_PPS */
1749 RCAR_GP_PIN(2, 6),
1750};
1751static const unsigned int avb_avtp_pps_mux[] = {
1752 AVB_AVTP_PPS_MARK,
1753};
1754static const unsigned int avb_avtp_match_a_pins[] = {
1755 /* AVB_AVTP_MATCH_A */
1756 RCAR_GP_PIN(2, 13),
1757};
1758static const unsigned int avb_avtp_match_a_mux[] = {
1759 AVB_AVTP_MATCH_A_MARK,
1760};
1761static const unsigned int avb_avtp_capture_a_pins[] = {
1762 /* AVB_AVTP_CAPTURE_A */
1763 RCAR_GP_PIN(2, 14),
1764};
1765static const unsigned int avb_avtp_capture_a_mux[] = {
1766 AVB_AVTP_CAPTURE_A_MARK,
1767};
1768static const unsigned int avb_avtp_match_b_pins[] = {
1769 /* AVB_AVTP_MATCH_B */
1770 RCAR_GP_PIN(1, 8),
1771};
1772static const unsigned int avb_avtp_match_b_mux[] = {
1773 AVB_AVTP_MATCH_B_MARK,
1774};
1775static const unsigned int avb_avtp_capture_b_pins[] = {
1776 /* AVB_AVTP_CAPTURE_B */
1777 RCAR_GP_PIN(1, 11),
1778};
1779static const unsigned int avb_avtp_capture_b_mux[] = {
1780 AVB_AVTP_CAPTURE_B_MARK,
1781};
1782
641b0ab8
DB		 1783/* - DRIF0 --------------------------------------------------------------- */
1784static const unsigned int drif0_ctrl_a_pins[] = {
1785 /* CLK, SYNC */
1786 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1787};
1788static const unsigned int drif0_ctrl_a_mux[] = {
1789 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1790};
1791static const unsigned int drif0_data0_a_pins[] = {
1792 /* D0 */
1793 RCAR_GP_PIN(6, 10),
1794};
1795static const unsigned int drif0_data0_a_mux[] = {
1796 RIF0_D0_A_MARK,
1797};
1798static const unsigned int drif0_data1_a_pins[] = {
1799 /* D1 */
1800 RCAR_GP_PIN(6, 7),
1801};
1802static const unsigned int drif0_data1_a_mux[] = {
1803 RIF0_D1_A_MARK,
1804};
1805static const unsigned int drif0_ctrl_b_pins[] = {
1806 /* CLK, SYNC */
1807 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1808};
1809static const unsigned int drif0_ctrl_b_mux[] = {
1810 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1811};
1812static const unsigned int drif0_data0_b_pins[] = {
1813 /* D0 */
1814 RCAR_GP_PIN(5, 1),
1815};
1816static const unsigned int drif0_data0_b_mux[] = {
1817 RIF0_D0_B_MARK,
1818};
1819static const unsigned int drif0_data1_b_pins[] = {
1820 /* D1 */
1821 RCAR_GP_PIN(5, 2),
1822};
1823static const unsigned int drif0_data1_b_mux[] = {
1824 RIF0_D1_B_MARK,
1825};
1826static const unsigned int drif0_ctrl_c_pins[] = {
1827 /* CLK, SYNC */
1828 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1829};
1830static const unsigned int drif0_ctrl_c_mux[] = {
1831 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1832};
1833static const unsigned int drif0_data0_c_pins[] = {
1834 /* D0 */
1835 RCAR_GP_PIN(5, 13),
1836};
1837static const unsigned int drif0_data0_c_mux[] = {
1838 RIF0_D0_C_MARK,
1839};
1840static const unsigned int drif0_data1_c_pins[] = {
1841 /* D1 */
1842 RCAR_GP_PIN(5, 14),
1843};
1844static const unsigned int drif0_data1_c_mux[] = {
1845 RIF0_D1_C_MARK,
1846};
1847/* - DRIF1 --------------------------------------------------------------- */
1848static const unsigned int drif1_ctrl_a_pins[] = {
1849 /* CLK, SYNC */
1850 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1851};
1852static const unsigned int drif1_ctrl_a_mux[] = {
1853 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1854};
1855static const unsigned int drif1_data0_a_pins[] = {
1856 /* D0 */
1857 RCAR_GP_PIN(6, 19),
1858};
1859static const unsigned int drif1_data0_a_mux[] = {
1860 RIF1_D0_A_MARK,
1861};
1862static const unsigned int drif1_data1_a_pins[] = {
1863 /* D1 */
1864 RCAR_GP_PIN(6, 20),
1865};
1866static const unsigned int drif1_data1_a_mux[] = {
1867 RIF1_D1_A_MARK,
1868};
1869static const unsigned int drif1_ctrl_b_pins[] = {
1870 /* CLK, SYNC */
1871 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1872};
1873static const unsigned int drif1_ctrl_b_mux[] = {
1874 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1875};
1876static const unsigned int drif1_data0_b_pins[] = {
1877 /* D0 */
1878 RCAR_GP_PIN(5, 7),
1879};
1880static const unsigned int drif1_data0_b_mux[] = {
1881 RIF1_D0_B_MARK,
1882};
1883static const unsigned int drif1_data1_b_pins[] = {
1884 /* D1 */
1885 RCAR_GP_PIN(5, 8),
1886};
1887static const unsigned int drif1_data1_b_mux[] = {
1888 RIF1_D1_B_MARK,
1889};
1890static const unsigned int drif1_ctrl_c_pins[] = {
1891 /* CLK, SYNC */
1892 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1893};
1894static const unsigned int drif1_ctrl_c_mux[] = {
1895 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1896};
1897static const unsigned int drif1_data0_c_pins[] = {
1898 /* D0 */
1899 RCAR_GP_PIN(5, 6),
1900};
1901static const unsigned int drif1_data0_c_mux[] = {
1902 RIF1_D0_C_MARK,
1903};
1904static const unsigned int drif1_data1_c_pins[] = {
1905 /* D1 */
1906 RCAR_GP_PIN(5, 10),
1907};
1908static const unsigned int drif1_data1_c_mux[] = {
1909 RIF1_D1_C_MARK,
1910};
1911/* - DRIF2 --------------------------------------------------------------- */
1912static const unsigned int drif2_ctrl_a_pins[] = {
1913 /* CLK, SYNC */
1914 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1915};
1916static const unsigned int drif2_ctrl_a_mux[] = {
1917 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1918};
1919static const unsigned int drif2_data0_a_pins[] = {
1920 /* D0 */
1921 RCAR_GP_PIN(6, 7),
1922};
1923static const unsigned int drif2_data0_a_mux[] = {
1924 RIF2_D0_A_MARK,
1925};
1926static const unsigned int drif2_data1_a_pins[] = {
1927 /* D1 */
1928 RCAR_GP_PIN(6, 10),
1929};
1930static const unsigned int drif2_data1_a_mux[] = {
1931 RIF2_D1_A_MARK,
1932};
1933static const unsigned int drif2_ctrl_b_pins[] = {
1934 /* CLK, SYNC */
1935 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1936};
1937static const unsigned int drif2_ctrl_b_mux[] = {
1938 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1939};
1940static const unsigned int drif2_data0_b_pins[] = {
1941 /* D0 */
1942 RCAR_GP_PIN(6, 30),
1943};
1944static const unsigned int drif2_data0_b_mux[] = {
1945 RIF2_D0_B_MARK,
1946};
1947static const unsigned int drif2_data1_b_pins[] = {
1948 /* D1 */
1949 RCAR_GP_PIN(6, 31),
1950};
1951static const unsigned int drif2_data1_b_mux[] = {
1952 RIF2_D1_B_MARK,
1953};
1954/* - DRIF3 --------------------------------------------------------------- */
1955static const unsigned int drif3_ctrl_a_pins[] = {
1956 /* CLK, SYNC */
1957 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1958};
1959static const unsigned int drif3_ctrl_a_mux[] = {
1960 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1961};
1962static const unsigned int drif3_data0_a_pins[] = {
1963 /* D0 */
1964 RCAR_GP_PIN(6, 19),
1965};
1966static const unsigned int drif3_data0_a_mux[] = {
1967 RIF3_D0_A_MARK,
1968};
1969static const unsigned int drif3_data1_a_pins[] = {
1970 /* D1 */
1971 RCAR_GP_PIN(6, 20),
1972};
1973static const unsigned int drif3_data1_a_mux[] = {
1974 RIF3_D1_A_MARK,
1975};
1976static const unsigned int drif3_ctrl_b_pins[] = {
1977 /* CLK, SYNC */
1978 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1979};
1980static const unsigned int drif3_ctrl_b_mux[] = {
1981 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1982};
1983static const unsigned int drif3_data0_b_pins[] = {
1984 /* D0 */
1985 RCAR_GP_PIN(6, 28),
1986};
1987static const unsigned int drif3_data0_b_mux[] = {
1988 RIF3_D0_B_MARK,
1989};
1990static const unsigned int drif3_data1_b_pins[] = {
1991 /* D1 */
1992 RCAR_GP_PIN(6, 29),
1993};
1994static const unsigned int drif3_data1_b_mux[] = {
1995 RIF3_D1_B_MARK,
1996};
1997
a20a6585
LP		 1998/* - DU --------------------------------------------------------------------- */
1999static const unsigned int du_rgb666_pins[] = {
2000 /* R[7:2], G[7:2], B[7:2] */
2001 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2002 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2003 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2004 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2005 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2006 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2007};
2008static const unsigned int du_rgb666_mux[] = {
2009 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2010 DU_DR3_MARK, DU_DR2_MARK,
2011 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2012 DU_DG3_MARK, DU_DG2_MARK,
2013 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2014 DU_DB3_MARK, DU_DB2_MARK,
2015};
2016static const unsigned int du_rgb888_pins[] = {
2017 /* R[7:0], G[7:0], B[7:0] */
2018 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2019 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2020 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2021 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2022 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2023 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2024 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2025 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2026 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2027};
2028static const unsigned int du_rgb888_mux[] = {
2029 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2030 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2031 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2032 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2033 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2034 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2035};
2036static const unsigned int du_clk_out_0_pins[] = {
2037 /* CLKOUT */
2038 RCAR_GP_PIN(1, 27),
2039};
2040static const unsigned int du_clk_out_0_mux[] = {
2041 DU_DOTCLKOUT0_MARK
2042};
2043static const unsigned int du_clk_out_1_pins[] = {
2044 /* CLKOUT */
2045 RCAR_GP_PIN(2, 3),
2046};
2047static const unsigned int du_clk_out_1_mux[] = {
2048 DU_DOTCLKOUT1_MARK
2049};
2050static const unsigned int du_sync_pins[] = {
2051 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2052 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2053};
2054static const unsigned int du_sync_mux[] = {
2055 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2056};
2057static const unsigned int du_oddf_pins[] = {
2058 /* EXDISP/EXODDF/EXCDE */
2059 RCAR_GP_PIN(2, 2),
2060};
2061static const unsigned int du_oddf_mux[] = {
2062 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2063};
2064static const unsigned int du_cde_pins[] = {
2065 /* CDE */
2066 RCAR_GP_PIN(2, 0),
2067};
2068static const unsigned int du_cde_mux[] = {
2069 DU_CDE_MARK,
2070};
2071static const unsigned int du_disp_pins[] = {
2072 /* DISP */
2073 RCAR_GP_PIN(2, 1),
2074};
2075static const unsigned int du_disp_mux[] = {
2076 DU_DISP_MARK,
2077};
2078
7a362e34
WS		 2079/* - HSCIF0 ----------------------------------------------------------------- */
2080static const unsigned int hscif0_data_pins[] = {
2081 /* RX, TX */
2082 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2083};
2084static const unsigned int hscif0_data_mux[] = {
2085 HRX0_MARK, HTX0_MARK,
2086};
2087static const unsigned int hscif0_clk_pins[] = {
2088 /* SCK */
2089 RCAR_GP_PIN(5, 12),
2090};
2091static const unsigned int hscif0_clk_mux[] = {
2092 HSCK0_MARK,
2093};
2094static const unsigned int hscif0_ctrl_pins[] = {
2095 /* RTS, CTS */
2096 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2097};
2098static const unsigned int hscif0_ctrl_mux[] = {
2099 HRTS0_N_MARK, HCTS0_N_MARK,
2100};
2101/* - HSCIF1 ----------------------------------------------------------------- */
2102static const unsigned int hscif1_data_a_pins[] = {
2103 /* RX, TX */
2104 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2105};
2106static const unsigned int hscif1_data_a_mux[] = {
2107 HRX1_A_MARK, HTX1_A_MARK,
2108};
2109static const unsigned int hscif1_clk_a_pins[] = {
2110 /* SCK */
2111 RCAR_GP_PIN(6, 21),
2112};
2113static const unsigned int hscif1_clk_a_mux[] = {
2114 HSCK1_A_MARK,
2115};
2116static const unsigned int hscif1_ctrl_a_pins[] = {
2117 /* RTS, CTS */
2118 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2119};
2120static const unsigned int hscif1_ctrl_a_mux[] = {
2121 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2122};
2123
2124static const unsigned int hscif1_data_b_pins[] = {
2125 /* RX, TX */
2126 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2127};
2128static const unsigned int hscif1_data_b_mux[] = {
2129 HRX1_B_MARK, HTX1_B_MARK,
2130};
2131static const unsigned int hscif1_clk_b_pins[] = {
2132 /* SCK */
2133 RCAR_GP_PIN(5, 0),
2134};
2135static const unsigned int hscif1_clk_b_mux[] = {
2136 HSCK1_B_MARK,
2137};
2138static const unsigned int hscif1_ctrl_b_pins[] = {
2139 /* RTS, CTS */
2140 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2141};
2142static const unsigned int hscif1_ctrl_b_mux[] = {
2143 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2144};
2145/* - HSCIF2 ----------------------------------------------------------------- */
2146static const unsigned int hscif2_data_a_pins[] = {
2147 /* RX, TX */
2148 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2149};
2150static const unsigned int hscif2_data_a_mux[] = {
2151 HRX2_A_MARK, HTX2_A_MARK,
2152};
2153static const unsigned int hscif2_clk_a_pins[] = {
2154 /* SCK */
2155 RCAR_GP_PIN(6, 10),
2156};
2157static const unsigned int hscif2_clk_a_mux[] = {
2158 HSCK2_A_MARK,
2159};
2160static const unsigned int hscif2_ctrl_a_pins[] = {
2161 /* RTS, CTS */
2162 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2163};
2164static const unsigned int hscif2_ctrl_a_mux[] = {
2165 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2166};
2167
2168static const unsigned int hscif2_data_b_pins[] = {
2169 /* RX, TX */
2170 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2171};
2172static const unsigned int hscif2_data_b_mux[] = {
2173 HRX2_B_MARK, HTX2_B_MARK,
2174};
2175static const unsigned int hscif2_clk_b_pins[] = {
2176 /* SCK */
2177 RCAR_GP_PIN(6, 21),
2178};
2179static const unsigned int hscif2_clk_b_mux[] = {
2180 HSCK2_B_MARK,
2181};
2182static const unsigned int hscif2_ctrl_b_pins[] = {
2183 /* RTS, CTS */
2184 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2185};
2186static const unsigned int hscif2_ctrl_b_mux[] = {
2187 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2188};
2189
2190static const unsigned int hscif2_data_c_pins[] = {
2191 /* RX, TX */
2192 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2193};
2194static const unsigned int hscif2_data_c_mux[] = {
2195 HRX2_C_MARK, HTX2_C_MARK,
2196};
2197static const unsigned int hscif2_clk_c_pins[] = {
2198 /* SCK */
2199 RCAR_GP_PIN(6, 24),
2200};
2201static const unsigned int hscif2_clk_c_mux[] = {
2202 HSCK2_C_MARK,
2203};
2204static const unsigned int hscif2_ctrl_c_pins[] = {
2205 /* RTS, CTS */
2206 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2207};
2208static const unsigned int hscif2_ctrl_c_mux[] = {
2209 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2210};
2211/* - HSCIF3 ----------------------------------------------------------------- */
2212static const unsigned int hscif3_data_a_pins[] = {
2213 /* RX, TX */
2214 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2215};
2216static const unsigned int hscif3_data_a_mux[] = {
2217 HRX3_A_MARK, HTX3_A_MARK,
2218};
2219static const unsigned int hscif3_clk_pins[] = {
2220 /* SCK */
2221 RCAR_GP_PIN(1, 22),
2222};
2223static const unsigned int hscif3_clk_mux[] = {
2224 HSCK3_MARK,
2225};
2226static const unsigned int hscif3_ctrl_pins[] = {
2227 /* RTS, CTS */
2228 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2229};
2230static const unsigned int hscif3_ctrl_mux[] = {
2231 HRTS3_N_MARK, HCTS3_N_MARK,
2232};
2233
2234static const unsigned int hscif3_data_b_pins[] = {
2235 /* RX, TX */
2236 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2237};
2238static const unsigned int hscif3_data_b_mux[] = {
2239 HRX3_B_MARK, HTX3_B_MARK,
2240};
2241static const unsigned int hscif3_data_c_pins[] = {
2242 /* RX, TX */
2243 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2244};
2245static const unsigned int hscif3_data_c_mux[] = {
2246 HRX3_C_MARK, HTX3_C_MARK,
2247};
2248static const unsigned int hscif3_data_d_pins[] = {
2249 /* RX, TX */
2250 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2251};
2252static const unsigned int hscif3_data_d_mux[] = {
2253 HRX3_D_MARK, HTX3_D_MARK,
2254};
2255/* - HSCIF4 ----------------------------------------------------------------- */
2256static const unsigned int hscif4_data_a_pins[] = {
2257 /* RX, TX */
2258 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2259};
2260static const unsigned int hscif4_data_a_mux[] = {
2261 HRX4_A_MARK, HTX4_A_MARK,
2262};
2263static const unsigned int hscif4_clk_pins[] = {
2264 /* SCK */
2265 RCAR_GP_PIN(1, 11),
2266};
2267static const unsigned int hscif4_clk_mux[] = {
2268 HSCK4_MARK,
2269};
2270static const unsigned int hscif4_ctrl_pins[] = {
2271 /* RTS, CTS */
2272 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2273};
2274static const unsigned int hscif4_ctrl_mux[] = {
2275 HRTS4_N_MARK, HCTS4_N_MARK,
2276};
2277
2278static const unsigned int hscif4_data_b_pins[] = {
2279 /* RX, TX */
2280 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2281};
2282static const unsigned int hscif4_data_b_mux[] = {
2283 HRX4_B_MARK, HTX4_B_MARK,
2284};
2285
f62d4c9e
WS		 2286/* - I2C -------------------------------------------------------------------- */
2287static const unsigned int i2c1_a_pins[] = {
2288 /* SDA, SCL */
2289 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2290};
2291static const unsigned int i2c1_a_mux[] = {
2292 SDA1_A_MARK, SCL1_A_MARK,
2293};
2294static const unsigned int i2c1_b_pins[] = {
2295 /* SDA, SCL */
2296 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2297};
2298static const unsigned int i2c1_b_mux[] = {
2299 SDA1_B_MARK, SCL1_B_MARK,
2300};
2301static const unsigned int i2c2_a_pins[] = {
2302 /* SDA, SCL */
2303 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2304};
2305static const unsigned int i2c2_a_mux[] = {
2306 SDA2_A_MARK, SCL2_A_MARK,
2307};
2308static const unsigned int i2c2_b_pins[] = {
2309 /* SDA, SCL */
2310 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2311};
2312static const unsigned int i2c2_b_mux[] = {
2313 SDA2_B_MARK, SCL2_B_MARK,
2314};
2315static const unsigned int i2c6_a_pins[] = {
2316 /* SDA, SCL */
2317 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2318};
2319static const unsigned int i2c6_a_mux[] = {
2320 SDA6_A_MARK, SCL6_A_MARK,
2321};
2322static const unsigned int i2c6_b_pins[] = {
2323 /* SDA, SCL */
2324 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2325};
2326static const unsigned int i2c6_b_mux[] = {
2327 SDA6_B_MARK, SCL6_B_MARK,
2328};
2329static const unsigned int i2c6_c_pins[] = {
2330 /* SDA, SCL */
2331 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2332};
2333static const unsigned int i2c6_c_mux[] = {
2334 SDA6_C_MARK, SCL6_C_MARK,
2335};
2336
8480e6ca
GU		 2337/* - INTC-EX ---------------------------------------------------------------- */
2338static const unsigned int intc_ex_irq0_pins[] = {
2339 /* IRQ0 */
2340 RCAR_GP_PIN(2, 0),
2341};
2342static const unsigned int intc_ex_irq0_mux[] = {
2343 IRQ0_MARK,
2344};
2345static const unsigned int intc_ex_irq1_pins[] = {
2346 /* IRQ1 */
2347 RCAR_GP_PIN(2, 1),
2348};
2349static const unsigned int intc_ex_irq1_mux[] = {
2350 IRQ1_MARK,
2351};
2352static const unsigned int intc_ex_irq2_pins[] = {
2353 /* IRQ2 */
2354 RCAR_GP_PIN(2, 2),
2355};
2356static const unsigned int intc_ex_irq2_mux[] = {
2357 IRQ2_MARK,
2358};
2359static const unsigned int intc_ex_irq3_pins[] = {
2360 /* IRQ3 */
2361 RCAR_GP_PIN(2, 3),
2362};
2363static const unsigned int intc_ex_irq3_mux[] = {
2364 IRQ3_MARK,
2365};
2366static const unsigned int intc_ex_irq4_pins[] = {
2367 /* IRQ4 */
2368 RCAR_GP_PIN(2, 4),
2369};
2370static const unsigned int intc_ex_irq4_mux[] = {
2371 IRQ4_MARK,
2372};
2373static const unsigned int intc_ex_irq5_pins[] = {
2374 /* IRQ5 */
2375 RCAR_GP_PIN(2, 5),
2376};
2377static const unsigned int intc_ex_irq5_mux[] = {
2378 IRQ5_MARK,
2379};
2380
3e6c7727
GU		 2381/* - MSIOF0 ----------------------------------------------------------------- */
2382static const unsigned int msiof0_clk_pins[] = {
2383 /* SCK */
2384 RCAR_GP_PIN(5, 17),
2385};
2386static const unsigned int msiof0_clk_mux[] = {
2387 MSIOF0_SCK_MARK,
2388};
2389static const unsigned int msiof0_sync_pins[] = {
2390 /* SYNC */
2391 RCAR_GP_PIN(5, 18),
2392};
2393static const unsigned int msiof0_sync_mux[] = {
2394 MSIOF0_SYNC_MARK,
2395};
2396static const unsigned int msiof0_ss1_pins[] = {
2397 /* SS1 */
2398 RCAR_GP_PIN(5, 19),
2399};
2400static const unsigned int msiof0_ss1_mux[] = {
2401 MSIOF0_SS1_MARK,
2402};
2403static const unsigned int msiof0_ss2_pins[] = {
2404 /* SS2 */
2405 RCAR_GP_PIN(5, 21),
2406};
2407static const unsigned int msiof0_ss2_mux[] = {
2408 MSIOF0_SS2_MARK,
2409};
2410static const unsigned int msiof0_txd_pins[] = {
2411 /* TXD */
2412 RCAR_GP_PIN(5, 20),
2413};
2414static const unsigned int msiof0_txd_mux[] = {
2415 MSIOF0_TXD_MARK,
2416};
2417static const unsigned int msiof0_rxd_pins[] = {
2418 /* RXD */
2419 RCAR_GP_PIN(5, 22),
2420};
2421static const unsigned int msiof0_rxd_mux[] = {
2422 MSIOF0_RXD_MARK,
2423};
2424/* - MSIOF1 ----------------------------------------------------------------- */
2425static const unsigned int msiof1_clk_a_pins[] = {
2426 /* SCK */
2427 RCAR_GP_PIN(6, 8),
2428};
2429static const unsigned int msiof1_clk_a_mux[] = {
2430 MSIOF1_SCK_A_MARK,
2431};
2432static const unsigned int msiof1_sync_a_pins[] = {
2433 /* SYNC */
2434 RCAR_GP_PIN(6, 9),
2435};
2436static const unsigned int msiof1_sync_a_mux[] = {
2437 MSIOF1_SYNC_A_MARK,
2438};
2439static const unsigned int msiof1_ss1_a_pins[] = {
2440 /* SS1 */
2441 RCAR_GP_PIN(6, 5),
2442};
2443static const unsigned int msiof1_ss1_a_mux[] = {
2444 MSIOF1_SS1_A_MARK,
2445};
2446static const unsigned int msiof1_ss2_a_pins[] = {
2447 /* SS2 */
2448 RCAR_GP_PIN(6, 6),
2449};
2450static const unsigned int msiof1_ss2_a_mux[] = {
2451 MSIOF1_SS2_A_MARK,
2452};
2453static const unsigned int msiof1_txd_a_pins[] = {
2454 /* TXD */
2455 RCAR_GP_PIN(6, 7),
2456};
2457static const unsigned int msiof1_txd_a_mux[] = {
2458 MSIOF1_TXD_A_MARK,
2459};
2460static const unsigned int msiof1_rxd_a_pins[] = {
2461 /* RXD */
2462 RCAR_GP_PIN(6, 10),
2463};
2464static const unsigned int msiof1_rxd_a_mux[] = {
2465 MSIOF1_RXD_A_MARK,
2466};
2467static const unsigned int msiof1_clk_b_pins[] = {
2468 /* SCK */
2469 RCAR_GP_PIN(5, 9),
2470};
2471static const unsigned int msiof1_clk_b_mux[] = {
2472 MSIOF1_SCK_B_MARK,
2473};
2474static const unsigned int msiof1_sync_b_pins[] = {
2475 /* SYNC */
2476 RCAR_GP_PIN(5, 3),
2477};
2478static const unsigned int msiof1_sync_b_mux[] = {
2479 MSIOF1_SYNC_B_MARK,
2480};
2481static const unsigned int msiof1_ss1_b_pins[] = {
2482 /* SS1 */
2483 RCAR_GP_PIN(5, 4),
2484};
2485static const unsigned int msiof1_ss1_b_mux[] = {
2486 MSIOF1_SS1_B_MARK,
2487};
2488static const unsigned int msiof1_ss2_b_pins[] = {
2489 /* SS2 */
2490 RCAR_GP_PIN(5, 0),
2491};
2492static const unsigned int msiof1_ss2_b_mux[] = {
2493 MSIOF1_SS2_B_MARK,
2494};
2495static const unsigned int msiof1_txd_b_pins[] = {
2496 /* TXD */
2497 RCAR_GP_PIN(5, 8),
2498};
2499static const unsigned int msiof1_txd_b_mux[] = {
2500 MSIOF1_TXD_B_MARK,
2501};
2502static const unsigned int msiof1_rxd_b_pins[] = {
2503 /* RXD */
2504 RCAR_GP_PIN(5, 7),
2505};
2506static const unsigned int msiof1_rxd_b_mux[] = {
2507 MSIOF1_RXD_B_MARK,
2508};
2509static const unsigned int msiof1_clk_c_pins[] = {
2510 /* SCK */
2511 RCAR_GP_PIN(6, 17),
2512};
2513static const unsigned int msiof1_clk_c_mux[] = {
2514 MSIOF1_SCK_C_MARK,
2515};
2516static const unsigned int msiof1_sync_c_pins[] = {
2517 /* SYNC */
2518 RCAR_GP_PIN(6, 18),
2519};
2520static const unsigned int msiof1_sync_c_mux[] = {
2521 MSIOF1_SYNC_C_MARK,
2522};
2523static const unsigned int msiof1_ss1_c_pins[] = {
2524 /* SS1 */
2525 RCAR_GP_PIN(6, 21),
2526};
2527static const unsigned int msiof1_ss1_c_mux[] = {
2528 MSIOF1_SS1_C_MARK,
2529};
2530static const unsigned int msiof1_ss2_c_pins[] = {
2531 /* SS2 */
2532 RCAR_GP_PIN(6, 27),
2533};
2534static const unsigned int msiof1_ss2_c_mux[] = {
2535 MSIOF1_SS2_C_MARK,
2536};
2537static const unsigned int msiof1_txd_c_pins[] = {
2538 /* TXD */
2539 RCAR_GP_PIN(6, 20),
2540};
2541static const unsigned int msiof1_txd_c_mux[] = {
2542 MSIOF1_TXD_C_MARK,
2543};
2544static const unsigned int msiof1_rxd_c_pins[] = {
2545 /* RXD */
2546 RCAR_GP_PIN(6, 19),
2547};
2548static const unsigned int msiof1_rxd_c_mux[] = {
2549 MSIOF1_RXD_C_MARK,
2550};
2551static const unsigned int msiof1_clk_d_pins[] = {
2552 /* SCK */
2553 RCAR_GP_PIN(5, 12),
2554};
2555static const unsigned int msiof1_clk_d_mux[] = {
2556 MSIOF1_SCK_D_MARK,
2557};
2558static const unsigned int msiof1_sync_d_pins[] = {
2559 /* SYNC */
2560 RCAR_GP_PIN(5, 15),
2561};
2562static const unsigned int msiof1_sync_d_mux[] = {
2563 MSIOF1_SYNC_D_MARK,
2564};
2565static const unsigned int msiof1_ss1_d_pins[] = {
2566 /* SS1 */
2567 RCAR_GP_PIN(5, 16),
2568};
2569static const unsigned int msiof1_ss1_d_mux[] = {
2570 MSIOF1_SS1_D_MARK,
2571};
2572static const unsigned int msiof1_ss2_d_pins[] = {
2573 /* SS2 */
2574 RCAR_GP_PIN(5, 21),
2575};
2576static const unsigned int msiof1_ss2_d_mux[] = {
2577 MSIOF1_SS2_D_MARK,
2578};
2579static const unsigned int msiof1_txd_d_pins[] = {
2580 /* TXD */
2581 RCAR_GP_PIN(5, 14),
2582};
2583static const unsigned int msiof1_txd_d_mux[] = {
2584 MSIOF1_TXD_D_MARK,
2585};
2586static const unsigned int msiof1_rxd_d_pins[] = {
2587 /* RXD */
2588 RCAR_GP_PIN(5, 13),
2589};
2590static const unsigned int msiof1_rxd_d_mux[] = {
2591 MSIOF1_RXD_D_MARK,
2592};
2593static const unsigned int msiof1_clk_e_pins[] = {
2594 /* SCK */
2595 RCAR_GP_PIN(3, 0),
2596};
2597static const unsigned int msiof1_clk_e_mux[] = {
2598 MSIOF1_SCK_E_MARK,
2599};
2600static const unsigned int msiof1_sync_e_pins[] = {
2601 /* SYNC */
2602 RCAR_GP_PIN(3, 1),
2603};
2604static const unsigned int msiof1_sync_e_mux[] = {
2605 MSIOF1_SYNC_E_MARK,
2606};
2607static const unsigned int msiof1_ss1_e_pins[] = {
2608 /* SS1 */
2609 RCAR_GP_PIN(3, 4),
2610};
2611static const unsigned int msiof1_ss1_e_mux[] = {
2612 MSIOF1_SS1_E_MARK,
2613};
2614static const unsigned int msiof1_ss2_e_pins[] = {
2615 /* SS2 */
2616 RCAR_GP_PIN(3, 5),
2617};
2618static const unsigned int msiof1_ss2_e_mux[] = {
2619 MSIOF1_SS2_E_MARK,
2620};
2621static const unsigned int msiof1_txd_e_pins[] = {
2622 /* TXD */
2623 RCAR_GP_PIN(3, 3),
2624};
2625static const unsigned int msiof1_txd_e_mux[] = {
2626 MSIOF1_TXD_E_MARK,
2627};
2628static const unsigned int msiof1_rxd_e_pins[] = {
2629 /* RXD */
2630 RCAR_GP_PIN(3, 2),
2631};
2632static const unsigned int msiof1_rxd_e_mux[] = {
2633 MSIOF1_RXD_E_MARK,
2634};
2635static const unsigned int msiof1_clk_f_pins[] = {
2636 /* SCK */
2637 RCAR_GP_PIN(5, 23),
2638};
2639static const unsigned int msiof1_clk_f_mux[] = {
2640 MSIOF1_SCK_F_MARK,
2641};
2642static const unsigned int msiof1_sync_f_pins[] = {
2643 /* SYNC */
2644 RCAR_GP_PIN(5, 24),
2645};
2646static const unsigned int msiof1_sync_f_mux[] = {
2647 MSIOF1_SYNC_F_MARK,
2648};
2649static const unsigned int msiof1_ss1_f_pins[] = {
2650 /* SS1 */
2651 RCAR_GP_PIN(6, 1),
2652};
2653static const unsigned int msiof1_ss1_f_mux[] = {
2654 MSIOF1_SS1_F_MARK,
2655};
2656static const unsigned int msiof1_ss2_f_pins[] = {
2657 /* SS2 */
2658 RCAR_GP_PIN(6, 2),
2659};
2660static const unsigned int msiof1_ss2_f_mux[] = {
2661 MSIOF1_SS2_F_MARK,
2662};
2663static const unsigned int msiof1_txd_f_pins[] = {
2664 /* TXD */
2665 RCAR_GP_PIN(6, 0),
2666};
2667static const unsigned int msiof1_txd_f_mux[] = {
2668 MSIOF1_TXD_F_MARK,
2669};
2670static const unsigned int msiof1_rxd_f_pins[] = {
2671 /* RXD */
2672 RCAR_GP_PIN(5, 25),
2673};
2674static const unsigned int msiof1_rxd_f_mux[] = {
2675 MSIOF1_RXD_F_MARK,
2676};
2677static const unsigned int msiof1_clk_g_pins[] = {
2678 /* SCK */
2679 RCAR_GP_PIN(3, 6),
2680};
2681static const unsigned int msiof1_clk_g_mux[] = {
2682 MSIOF1_SCK_G_MARK,
2683};
2684static const unsigned int msiof1_sync_g_pins[] = {
2685 /* SYNC */
2686 RCAR_GP_PIN(3, 7),
2687};
2688static const unsigned int msiof1_sync_g_mux[] = {
2689 MSIOF1_SYNC_G_MARK,
2690};
2691static const unsigned int msiof1_ss1_g_pins[] = {
2692 /* SS1 */
2693 RCAR_GP_PIN(3, 10),
2694};
2695static const unsigned int msiof1_ss1_g_mux[] = {
2696 MSIOF1_SS1_G_MARK,
2697};
2698static const unsigned int msiof1_ss2_g_pins[] = {
2699 /* SS2 */
2700 RCAR_GP_PIN(3, 11),
2701};
2702static const unsigned int msiof1_ss2_g_mux[] = {
2703 MSIOF1_SS2_G_MARK,
2704};
2705static const unsigned int msiof1_txd_g_pins[] = {
2706 /* TXD */
2707 RCAR_GP_PIN(3, 9),
2708};
2709static const unsigned int msiof1_txd_g_mux[] = {
2710 MSIOF1_TXD_G_MARK,
2711};
2712static const unsigned int msiof1_rxd_g_pins[] = {
2713 /* RXD */
2714 RCAR_GP_PIN(3, 8),
2715};
2716static const unsigned int msiof1_rxd_g_mux[] = {
2717 MSIOF1_RXD_G_MARK,
2718};
2719/* - MSIOF2 ----------------------------------------------------------------- */
2720static const unsigned int msiof2_clk_a_pins[] = {
2721 /* SCK */
2722 RCAR_GP_PIN(1, 9),
2723};
2724static const unsigned int msiof2_clk_a_mux[] = {
2725 MSIOF2_SCK_A_MARK,
2726};
2727static const unsigned int msiof2_sync_a_pins[] = {
2728 /* SYNC */
2729 RCAR_GP_PIN(1, 8),
2730};
2731static const unsigned int msiof2_sync_a_mux[] = {
2732 MSIOF2_SYNC_A_MARK,
2733};
2734static const unsigned int msiof2_ss1_a_pins[] = {
2735 /* SS1 */
2736 RCAR_GP_PIN(1, 6),
2737};
2738static const unsigned int msiof2_ss1_a_mux[] = {
2739 MSIOF2_SS1_A_MARK,
2740};
2741static const unsigned int msiof2_ss2_a_pins[] = {
2742 /* SS2 */
2743 RCAR_GP_PIN(1, 7),
2744};
2745static const unsigned int msiof2_ss2_a_mux[] = {
2746 MSIOF2_SS2_A_MARK,
2747};
2748static const unsigned int msiof2_txd_a_pins[] = {
2749 /* TXD */
2750 RCAR_GP_PIN(1, 11),
2751};
2752static const unsigned int msiof2_txd_a_mux[] = {
2753 MSIOF2_TXD_A_MARK,
2754};
2755static const unsigned int msiof2_rxd_a_pins[] = {
2756 /* RXD */
2757 RCAR_GP_PIN(1, 10),
2758};
2759static const unsigned int msiof2_rxd_a_mux[] = {
2760 MSIOF2_RXD_A_MARK,
2761};
2762static const unsigned int msiof2_clk_b_pins[] = {
2763 /* SCK */
2764 RCAR_GP_PIN(0, 4),
2765};
2766static const unsigned int msiof2_clk_b_mux[] = {
2767 MSIOF2_SCK_B_MARK,
2768};
2769static const unsigned int msiof2_sync_b_pins[] = {
2770 /* SYNC */
2771 RCAR_GP_PIN(0, 5),
2772};
2773static const unsigned int msiof2_sync_b_mux[] = {
2774 MSIOF2_SYNC_B_MARK,
2775};
2776static const unsigned int msiof2_ss1_b_pins[] = {
2777 /* SS1 */
2778 RCAR_GP_PIN(0, 0),
2779};
2780static const unsigned int msiof2_ss1_b_mux[] = {
2781 MSIOF2_SS1_B_MARK,
2782};
2783static const unsigned int msiof2_ss2_b_pins[] = {
2784 /* SS2 */
2785 RCAR_GP_PIN(0, 1),
2786};
2787static const unsigned int msiof2_ss2_b_mux[] = {
2788 MSIOF2_SS2_B_MARK,
2789};
2790static const unsigned int msiof2_txd_b_pins[] = {
2791 /* TXD */
2792 RCAR_GP_PIN(0, 7),
2793};
2794static const unsigned int msiof2_txd_b_mux[] = {
2795 MSIOF2_TXD_B_MARK,
2796};
2797static const unsigned int msiof2_rxd_b_pins[] = {
2798 /* RXD */
2799 RCAR_GP_PIN(0, 6),
2800};
2801static const unsigned int msiof2_rxd_b_mux[] = {
2802 MSIOF2_RXD_B_MARK,
2803};
2804static const unsigned int msiof2_clk_c_pins[] = {
2805 /* SCK */
2806 RCAR_GP_PIN(2, 12),
2807};
2808static const unsigned int msiof2_clk_c_mux[] = {
2809 MSIOF2_SCK_C_MARK,
2810};
2811static const unsigned int msiof2_sync_c_pins[] = {
2812 /* SYNC */
2813 RCAR_GP_PIN(2, 11),
2814};
2815static const unsigned int msiof2_sync_c_mux[] = {
2816 MSIOF2_SYNC_C_MARK,
2817};
2818static const unsigned int msiof2_ss1_c_pins[] = {
2819 /* SS1 */
2820 RCAR_GP_PIN(2, 10),
2821};
2822static const unsigned int msiof2_ss1_c_mux[] = {
2823 MSIOF2_SS1_C_MARK,
2824};
2825static const unsigned int msiof2_ss2_c_pins[] = {
2826 /* SS2 */
2827 RCAR_GP_PIN(2, 9),
2828};
2829static const unsigned int msiof2_ss2_c_mux[] = {
2830 MSIOF2_SS2_C_MARK,
2831};
2832static const unsigned int msiof2_txd_c_pins[] = {
2833 /* TXD */
2834 RCAR_GP_PIN(2, 14),
2835};
2836static const unsigned int msiof2_txd_c_mux[] = {
2837 MSIOF2_TXD_C_MARK,
2838};
2839static const unsigned int msiof2_rxd_c_pins[] = {
2840 /* RXD */
2841 RCAR_GP_PIN(2, 13),
2842};
2843static const unsigned int msiof2_rxd_c_mux[] = {
2844 MSIOF2_RXD_C_MARK,
2845};
2846static const unsigned int msiof2_clk_d_pins[] = {
2847 /* SCK */
2848 RCAR_GP_PIN(0, 8),
2849};
2850static const unsigned int msiof2_clk_d_mux[] = {
2851 MSIOF2_SCK_D_MARK,
2852};
2853static const unsigned int msiof2_sync_d_pins[] = {
2854 /* SYNC */
2855 RCAR_GP_PIN(0, 9),
2856};
2857static const unsigned int msiof2_sync_d_mux[] = {
2858 MSIOF2_SYNC_D_MARK,
2859};
2860static const unsigned int msiof2_ss1_d_pins[] = {
2861 /* SS1 */
2862 RCAR_GP_PIN(0, 12),
2863};
2864static const unsigned int msiof2_ss1_d_mux[] = {
2865 MSIOF2_SS1_D_MARK,
2866};
2867static const unsigned int msiof2_ss2_d_pins[] = {
2868 /* SS2 */
2869 RCAR_GP_PIN(0, 13),
2870};
2871static const unsigned int msiof2_ss2_d_mux[] = {
2872 MSIOF2_SS2_D_MARK,
2873};
2874static const unsigned int msiof2_txd_d_pins[] = {
2875 /* TXD */
2876 RCAR_GP_PIN(0, 11),
2877};
2878static const unsigned int msiof2_txd_d_mux[] = {
2879 MSIOF2_TXD_D_MARK,
2880};
2881static const unsigned int msiof2_rxd_d_pins[] = {
2882 /* RXD */
2883 RCAR_GP_PIN(0, 10),
2884};
2885static const unsigned int msiof2_rxd_d_mux[] = {
2886 MSIOF2_RXD_D_MARK,
2887};
2888/* - MSIOF3 ----------------------------------------------------------------- */
2889static const unsigned int msiof3_clk_a_pins[] = {
2890 /* SCK */
2891 RCAR_GP_PIN(0, 0),
2892};
2893static const unsigned int msiof3_clk_a_mux[] = {
2894 MSIOF3_SCK_A_MARK,
2895};
2896static const unsigned int msiof3_sync_a_pins[] = {
2897 /* SYNC */
2898 RCAR_GP_PIN(0, 1),
2899};
2900static const unsigned int msiof3_sync_a_mux[] = {
2901 MSIOF3_SYNC_A_MARK,
2902};
2903static const unsigned int msiof3_ss1_a_pins[] = {
2904 /* SS1 */
2905 RCAR_GP_PIN(0, 14),
2906};
2907static const unsigned int msiof3_ss1_a_mux[] = {
2908 MSIOF3_SS1_A_MARK,
2909};
2910static const unsigned int msiof3_ss2_a_pins[] = {
2911 /* SS2 */
2912 RCAR_GP_PIN(0, 15),
2913};
2914static const unsigned int msiof3_ss2_a_mux[] = {
2915 MSIOF3_SS2_A_MARK,
2916};
2917static const unsigned int msiof3_txd_a_pins[] = {
2918 /* TXD */
2919 RCAR_GP_PIN(0, 3),
2920};
2921static const unsigned int msiof3_txd_a_mux[] = {
2922 MSIOF3_TXD_A_MARK,
2923};
2924static const unsigned int msiof3_rxd_a_pins[] = {
2925 /* RXD */
2926 RCAR_GP_PIN(0, 2),
2927};
2928static const unsigned int msiof3_rxd_a_mux[] = {
2929 MSIOF3_RXD_A_MARK,
2930};
2931static const unsigned int msiof3_clk_b_pins[] = {
2932 /* SCK */
2933 RCAR_GP_PIN(1, 2),
2934};
2935static const unsigned int msiof3_clk_b_mux[] = {
2936 MSIOF3_SCK_B_MARK,
2937};
2938static const unsigned int msiof3_sync_b_pins[] = {
2939 /* SYNC */
2940 RCAR_GP_PIN(1, 0),
2941};
2942static const unsigned int msiof3_sync_b_mux[] = {
2943 MSIOF3_SYNC_B_MARK,
2944};
2945static const unsigned int msiof3_ss1_b_pins[] = {
2946 /* SS1 */
2947 RCAR_GP_PIN(1, 4),
2948};
2949static const unsigned int msiof3_ss1_b_mux[] = {
2950 MSIOF3_SS1_B_MARK,
2951};
2952static const unsigned int msiof3_ss2_b_pins[] = {
2953 /* SS2 */
2954 RCAR_GP_PIN(1, 5),
2955};
2956static const unsigned int msiof3_ss2_b_mux[] = {
2957 MSIOF3_SS2_B_MARK,
2958};
2959static const unsigned int msiof3_txd_b_pins[] = {
2960 /* TXD */
2961 RCAR_GP_PIN(1, 1),
2962};
2963static const unsigned int msiof3_txd_b_mux[] = {
2964 MSIOF3_TXD_B_MARK,
2965};
2966static const unsigned int msiof3_rxd_b_pins[] = {
2967 /* RXD */
2968 RCAR_GP_PIN(1, 3),
2969};
2970static const unsigned int msiof3_rxd_b_mux[] = {
2971 MSIOF3_RXD_B_MARK,
2972};
2973static const unsigned int msiof3_clk_c_pins[] = {
2974 /* SCK */
2975 RCAR_GP_PIN(1, 12),
2976};
2977static const unsigned int msiof3_clk_c_mux[] = {
2978 MSIOF3_SCK_C_MARK,
2979};
2980static const unsigned int msiof3_sync_c_pins[] = {
2981 /* SYNC */
2982 RCAR_GP_PIN(1, 13),
2983};
2984static const unsigned int msiof3_sync_c_mux[] = {
2985 MSIOF3_SYNC_C_MARK,
2986};
2987static const unsigned int msiof3_txd_c_pins[] = {
2988 /* TXD */
2989 RCAR_GP_PIN(1, 15),
2990};
2991static const unsigned int msiof3_txd_c_mux[] = {
2992 MSIOF3_TXD_C_MARK,
2993};
2994static const unsigned int msiof3_rxd_c_pins[] = {
2995 /* RXD */
2996 RCAR_GP_PIN(1, 14),
2997};
2998static const unsigned int msiof3_rxd_c_mux[] = {
2999 MSIOF3_RXD_C_MARK,
3000};
3001static const unsigned int msiof3_clk_d_pins[] = {
3002 /* SCK */
3003 RCAR_GP_PIN(1, 22),
3004};
3005static const unsigned int msiof3_clk_d_mux[] = {
3006 MSIOF3_SCK_D_MARK,
3007};
3008static const unsigned int msiof3_sync_d_pins[] = {
3009 /* SYNC */
3010 RCAR_GP_PIN(1, 23),
3011};
3012static const unsigned int msiof3_sync_d_mux[] = {
3013 MSIOF3_SYNC_D_MARK,
3014};
3015static const unsigned int msiof3_ss1_d_pins[] = {
3016 /* SS1 */
3017 RCAR_GP_PIN(1, 26),
3018};
3019static const unsigned int msiof3_ss1_d_mux[] = {
3020 MSIOF3_SS1_D_MARK,
3021};
3022static const unsigned int msiof3_txd_d_pins[] = {
3023 /* TXD */
3024 RCAR_GP_PIN(1, 25),
3025};
3026static const unsigned int msiof3_txd_d_mux[] = {
3027 MSIOF3_TXD_D_MARK,
3028};
3029static const unsigned int msiof3_rxd_d_pins[] = {
3030 /* RXD */
3031 RCAR_GP_PIN(1, 24),
3032};
3033static const unsigned int msiof3_rxd_d_mux[] = {
3034 MSIOF3_RXD_D_MARK,
3035};
3036static const unsigned int msiof3_clk_e_pins[] = {
3037 /* SCK */
3038 RCAR_GP_PIN(2, 3),
3039};
3040static const unsigned int msiof3_clk_e_mux[] = {
3041 MSIOF3_SCK_E_MARK,
3042};
3043static const unsigned int msiof3_sync_e_pins[] = {
3044 /* SYNC */
3045 RCAR_GP_PIN(2, 2),
3046};
3047static const unsigned int msiof3_sync_e_mux[] = {
3048 MSIOF3_SYNC_E_MARK,
3049};
3050static const unsigned int msiof3_ss1_e_pins[] = {
3051 /* SS1 */
3052 RCAR_GP_PIN(2, 1),
3053};
3054static const unsigned int msiof3_ss1_e_mux[] = {
3055 MSIOF3_SS1_E_MARK,
3056};
3057static const unsigned int msiof3_ss2_e_pins[] = {
3058 /* SS1 */
3059 RCAR_GP_PIN(2, 0),
3060};
3061static const unsigned int msiof3_ss2_e_mux[] = {
3062 MSIOF3_SS2_E_MARK,
3063};
3064static const unsigned int msiof3_txd_e_pins[] = {
3065 /* TXD */
3066 RCAR_GP_PIN(2, 5),
3067};
3068static const unsigned int msiof3_txd_e_mux[] = {
3069 MSIOF3_TXD_E_MARK,
3070};
3071static const unsigned int msiof3_rxd_e_pins[] = {
3072 /* RXD */
3073 RCAR_GP_PIN(2, 4),
3074};
3075static const unsigned int msiof3_rxd_e_mux[] = {
3076 MSIOF3_RXD_E_MARK,
3077};
3078
c03a133b
LP		 3079/* - PWM0 --------------------------------------------------------------------*/
3080static const unsigned int pwm0_pins[] = {
3081 /* PWM */
3082 RCAR_GP_PIN(2, 6),
3083};
3084static const unsigned int pwm0_mux[] = {
3085 PWM0_MARK,
3086};
3087/* - PWM1 --------------------------------------------------------------------*/
3088static const unsigned int pwm1_a_pins[] = {
3089 /* PWM */
3090 RCAR_GP_PIN(2, 7),
3091};
3092static const unsigned int pwm1_a_mux[] = {
3093 PWM1_A_MARK,
3094};
3095static const unsigned int pwm1_b_pins[] = {
3096 /* PWM */
3097 RCAR_GP_PIN(1, 8),
3098};
3099static const unsigned int pwm1_b_mux[] = {
3100 PWM1_B_MARK,
3101};
3102/* - PWM2 --------------------------------------------------------------------*/
3103static const unsigned int pwm2_a_pins[] = {
3104 /* PWM */
3105 RCAR_GP_PIN(2, 8),
3106};
3107static const unsigned int pwm2_a_mux[] = {
3108 PWM2_A_MARK,
3109};
3110static const unsigned int pwm2_b_pins[] = {
3111 /* PWM */
3112 RCAR_GP_PIN(1, 11),
3113};
3114static const unsigned int pwm2_b_mux[] = {
3115 PWM2_B_MARK,
3116};
3117/* - PWM3 --------------------------------------------------------------------*/
3118static const unsigned int pwm3_a_pins[] = {
3119 /* PWM */
3120 RCAR_GP_PIN(1, 0),
3121};
3122static const unsigned int pwm3_a_mux[] = {
3123 PWM3_A_MARK,
3124};
3125static const unsigned int pwm3_b_pins[] = {
3126 /* PWM */
3127 RCAR_GP_PIN(2, 2),
3128};
3129static const unsigned int pwm3_b_mux[] = {
3130 PWM3_B_MARK,
3131};
3132/* - PWM4 --------------------------------------------------------------------*/
3133static const unsigned int pwm4_a_pins[] = {
3134 /* PWM */
3135 RCAR_GP_PIN(1, 1),
3136};
3137static const unsigned int pwm4_a_mux[] = {
3138 PWM4_A_MARK,
3139};
3140static const unsigned int pwm4_b_pins[] = {
3141 /* PWM */
3142 RCAR_GP_PIN(2, 3),
3143};
3144static const unsigned int pwm4_b_mux[] = {
3145 PWM4_B_MARK,
3146};
3147/* - PWM5 --------------------------------------------------------------------*/
3148static const unsigned int pwm5_a_pins[] = {
3149 /* PWM */
3150 RCAR_GP_PIN(1, 2),
3151};
3152static const unsigned int pwm5_a_mux[] = {
3153 PWM5_A_MARK,
3154};
3155static const unsigned int pwm5_b_pins[] = {
3156 /* PWM */
3157 RCAR_GP_PIN(2, 4),
3158};
3159static const unsigned int pwm5_b_mux[] = {
3160 PWM5_B_MARK,
3161};
3162/* - PWM6 --------------------------------------------------------------------*/
3163static const unsigned int pwm6_a_pins[] = {
3164 /* PWM */
3165 RCAR_GP_PIN(1, 3),
3166};
3167static const unsigned int pwm6_a_mux[] = {
3168 PWM6_A_MARK,
3169};
3170static const unsigned int pwm6_b_pins[] = {
3171 /* PWM */
3172 RCAR_GP_PIN(2, 5),
3173};
3174static const unsigned int pwm6_b_mux[] = {
3175 PWM6_B_MARK,
3176};
3177
e7ad4d3c
GU		 3178/* - SCIF0 ------------------------------------------------------------------ */
3179static const unsigned int scif0_data_pins[] = {
3180 /* RX, TX */
3181 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3182};
3183static const unsigned int scif0_data_mux[] = {
3184 RX0_MARK, TX0_MARK,
3185};
3186static const unsigned int scif0_clk_pins[] = {
3187 /* SCK */
3188 RCAR_GP_PIN(5, 0),
3189};
3190static const unsigned int scif0_clk_mux[] = {
3191 SCK0_MARK,
3192};
3193static const unsigned int scif0_ctrl_pins[] = {
3194 /* RTS, CTS */
3195 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3196};
3197static const unsigned int scif0_ctrl_mux[] = {
3198 RTS0_N_TANS_MARK, CTS0_N_MARK,
3199};
3200/* - SCIF1 ------------------------------------------------------------------ */
3201static const unsigned int scif1_data_a_pins[] = {
3202 /* RX, TX */
3203 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3204};
3205static const unsigned int scif1_data_a_mux[] = {
3206 RX1_A_MARK, TX1_A_MARK,
3207};
3208static const unsigned int scif1_clk_pins[] = {
3209 /* SCK */
3210 RCAR_GP_PIN(6, 21),
3211};
3212static const unsigned int scif1_clk_mux[] = {
3213 SCK1_MARK,
3214};
3215static const unsigned int scif1_ctrl_pins[] = {
3216 /* RTS, CTS */
3217 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3218};
3219static const unsigned int scif1_ctrl_mux[] = {
3220 RTS1_N_TANS_MARK, CTS1_N_MARK,
3221};
3222
3223static const unsigned int scif1_data_b_pins[] = {
3224 /* RX, TX */
3225 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3226};
3227static const unsigned int scif1_data_b_mux[] = {
3228 RX1_B_MARK, TX1_B_MARK,
3229};
3230/* - SCIF2 ------------------------------------------------------------------ */
3231static const unsigned int scif2_data_a_pins[] = {
3232 /* RX, TX */
3233 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3234};
3235static const unsigned int scif2_data_a_mux[] = {
3236 RX2_A_MARK, TX2_A_MARK,
3237};
3238static const unsigned int scif2_clk_pins[] = {
3239 /* SCK */
3240 RCAR_GP_PIN(5, 9),
3241};
3242static const unsigned int scif2_clk_mux[] = {
3243 SCK2_MARK,
3244};
3245static const unsigned int scif2_data_b_pins[] = {
3246 /* RX, TX */
3247 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3248};
3249static const unsigned int scif2_data_b_mux[] = {
3250 RX2_B_MARK, TX2_B_MARK,
3251};
3252/* - SCIF3 ------------------------------------------------------------------ */
3253static const unsigned int scif3_data_a_pins[] = {
3254 /* RX, TX */
3255 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3256};
3257static const unsigned int scif3_data_a_mux[] = {
3258 RX3_A_MARK, TX3_A_MARK,
3259};
3260static const unsigned int scif3_clk_pins[] = {
3261 /* SCK */
3262 RCAR_GP_PIN(1, 22),
3263};
3264static const unsigned int scif3_clk_mux[] = {
3265 SCK3_MARK,
3266};
3267static const unsigned int scif3_ctrl_pins[] = {
3268 /* RTS, CTS */
3269 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3270};
3271static const unsigned int scif3_ctrl_mux[] = {
3272 RTS3_N_TANS_MARK, CTS3_N_MARK,
3273};
3274static const unsigned int scif3_data_b_pins[] = {
3275 /* RX, TX */
3276 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3277};
3278static const unsigned int scif3_data_b_mux[] = {
3279 RX3_B_MARK, TX3_B_MARK,
3280};
3281/* - SCIF4 ------------------------------------------------------------------ */
3282static const unsigned int scif4_data_a_pins[] = {
3283 /* RX, TX */
3284 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3285};
3286static const unsigned int scif4_data_a_mux[] = {
3287 RX4_A_MARK, TX4_A_MARK,
3288};
3289static const unsigned int scif4_clk_a_pins[] = {
3290 /* SCK */
3291 RCAR_GP_PIN(2, 10),
3292};
3293static const unsigned int scif4_clk_a_mux[] = {
3294 SCK4_A_MARK,
3295};
3296static const unsigned int scif4_ctrl_a_pins[] = {
3297 /* RTS, CTS */
3298 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3299};
3300static const unsigned int scif4_ctrl_a_mux[] = {
3301 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3302};
3303static const unsigned int scif4_data_b_pins[] = {
3304 /* RX, TX */
3305 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3306};
3307static const unsigned int scif4_data_b_mux[] = {
3308 RX4_B_MARK, TX4_B_MARK,
3309};
3310static const unsigned int scif4_clk_b_pins[] = {
3311 /* SCK */
3312 RCAR_GP_PIN(1, 5),
3313};
3314static const unsigned int scif4_clk_b_mux[] = {
3315 SCK4_B_MARK,
3316};
3317static const unsigned int scif4_ctrl_b_pins[] = {
3318 /* RTS, CTS */
3319 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3320};
3321static const unsigned int scif4_ctrl_b_mux[] = {
3322 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3323};
3324static const unsigned int scif4_data_c_pins[] = {
3325 /* RX, TX */
3326 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3327};
3328static const unsigned int scif4_data_c_mux[] = {
3329 RX4_C_MARK, TX4_C_MARK,
3330};
3331static const unsigned int scif4_clk_c_pins[] = {
3332 /* SCK */
3333 RCAR_GP_PIN(0, 8),
3334};
3335static const unsigned int scif4_clk_c_mux[] = {
3336 SCK4_C_MARK,
3337};
3338static const unsigned int scif4_ctrl_c_pins[] = {
3339 /* RTS, CTS */
3340 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3341};
3342static const unsigned int scif4_ctrl_c_mux[] = {
3343 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3344};
3345/* - SCIF5 ------------------------------------------------------------------ */
3346static const unsigned int scif5_data_a_pins[] = {
3347 /* RX, TX */
3348 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3349};
3350static const unsigned int scif5_data_a_mux[] = {
3351 RX5_A_MARK, TX5_A_MARK,
3352};
3353static const unsigned int scif5_clk_a_pins[] = {
3354 /* SCK */
3355 RCAR_GP_PIN(6, 21),
3356};
3357static const unsigned int scif5_clk_a_mux[] = {
3358 SCK5_A_MARK,
3359};
3360static const unsigned int scif5_data_b_pins[] = {
3361 /* RX, TX */
3362 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3363};
3364static const unsigned int scif5_data_b_mux[] = {
3365 RX5_B_MARK, TX5_B_MARK,
3366};
3367static const unsigned int scif5_clk_b_pins[] = {
3368 /* SCK */
3369 RCAR_GP_PIN(5, 0),
3370};
3371static const unsigned int scif5_clk_b_mux[] = {
3372 SCK5_B_MARK,
3373};
3374
b4062b46
GU		 3375/* - SCIF Clock ------------------------------------------------------------- */
3376static const unsigned int scif_clk_a_pins[] = {
3377 /* SCIF_CLK */
3378 RCAR_GP_PIN(6, 23),
3379};
3380static const unsigned int scif_clk_a_mux[] = {
3381 SCIF_CLK_A_MARK,
3382};
3383static const unsigned int scif_clk_b_pins[] = {
3384 /* SCIF_CLK */
3385 RCAR_GP_PIN(5, 9),
3386};
3387static const unsigned int scif_clk_b_mux[] = {
3388 SCIF_CLK_B_MARK,
3389};
3390
9ed13958
TK		 3391/* - SDHI0 ------------------------------------------------------------------ */
3392static const unsigned int sdhi0_data1_pins[] = {
3393 /* D0 */
3394 RCAR_GP_PIN(3, 2),
3395};
3396static const unsigned int sdhi0_data1_mux[] = {
3397 SD0_DAT0_MARK,
3398};
3399static const unsigned int sdhi0_data4_pins[] = {
3400 /* D[0:3] */
3401 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3402 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3403};
3404static const unsigned int sdhi0_data4_mux[] = {
3405 SD0_DAT0_MARK, SD0_DAT1_MARK,
3406 SD0_DAT2_MARK, SD0_DAT3_MARK,
3407};
3408static const unsigned int sdhi0_ctrl_pins[] = {
3409 /* CLK, CMD */
3410 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3411};
3412static const unsigned int sdhi0_ctrl_mux[] = {
3413 SD0_CLK_MARK, SD0_CMD_MARK,
3414};
3415static const unsigned int sdhi0_cd_pins[] = {
3416 /* CD */
3417 RCAR_GP_PIN(3, 12),
3418};
3419static const unsigned int sdhi0_cd_mux[] = {
3420 SD0_CD_MARK,
3421};
3422static const unsigned int sdhi0_wp_pins[] = {
3423 /* WP */
3424 RCAR_GP_PIN(3, 13),
3425};
3426static const unsigned int sdhi0_wp_mux[] = {
3427 SD0_WP_MARK,
3428};
3429/* - SDHI1 ------------------------------------------------------------------ */
3430static const unsigned int sdhi1_data1_pins[] = {
3431 /* D0 */
3432 RCAR_GP_PIN(3, 8),
3433};
3434static const unsigned int sdhi1_data1_mux[] = {
3435 SD1_DAT0_MARK,
3436};
3437static const unsigned int sdhi1_data4_pins[] = {
3438 /* D[0:3] */
3439 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3440 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3441};
3442static const unsigned int sdhi1_data4_mux[] = {
3443 SD1_DAT0_MARK, SD1_DAT1_MARK,
3444 SD1_DAT2_MARK, SD1_DAT3_MARK,
3445};
3446static const unsigned int sdhi1_ctrl_pins[] = {
3447 /* CLK, CMD */
3448 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3449};
3450static const unsigned int sdhi1_ctrl_mux[] = {
3451 SD1_CLK_MARK, SD1_CMD_MARK,
3452};
3453static const unsigned int sdhi1_cd_pins[] = {
3454 /* CD */
3455 RCAR_GP_PIN(3, 14),
3456};
3457static const unsigned int sdhi1_cd_mux[] = {
3458 SD1_CD_MARK,
3459};
3460static const unsigned int sdhi1_wp_pins[] = {
3461 /* WP */
3462 RCAR_GP_PIN(3, 15),
3463};
3464static const unsigned int sdhi1_wp_mux[] = {
3465 SD1_WP_MARK,
3466};
3467/* - SDHI2 ------------------------------------------------------------------ */
3468static const unsigned int sdhi2_data1_pins[] = {
3469 /* D0 */
3470 RCAR_GP_PIN(4, 2),
3471};
3472static const unsigned int sdhi2_data1_mux[] = {
3473 SD2_DAT0_MARK,
3474};
3475static const unsigned int sdhi2_data4_pins[] = {
3476 /* D[0:3] */
3477 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3478 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3479};
3480static const unsigned int sdhi2_data4_mux[] = {
3481 SD2_DAT0_MARK, SD2_DAT1_MARK,
3482 SD2_DAT2_MARK, SD2_DAT3_MARK,
3483};
3484static const unsigned int sdhi2_data8_pins[] = {
3485 /* D[0:7] */
3486 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3487 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3488 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3489 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3490};
3491static const unsigned int sdhi2_data8_mux[] = {
3492 SD2_DAT0_MARK, SD2_DAT1_MARK,
3493 SD2_DAT2_MARK, SD2_DAT3_MARK,
3494 SD2_DAT4_MARK, SD2_DAT5_MARK,
3495 SD2_DAT6_MARK, SD2_DAT7_MARK,
3496};
3497static const unsigned int sdhi2_ctrl_pins[] = {
3498 /* CLK, CMD */
3499 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3500};
3501static const unsigned int sdhi2_ctrl_mux[] = {
3502 SD2_CLK_MARK, SD2_CMD_MARK,
3503};
3504static const unsigned int sdhi2_cd_a_pins[] = {
3505 /* CD */
3506 RCAR_GP_PIN(4, 13),
3507};
3508static const unsigned int sdhi2_cd_a_mux[] = {
3509 SD2_CD_A_MARK,
3510};
3511static const unsigned int sdhi2_cd_b_pins[] = {
3512 /* CD */
3513 RCAR_GP_PIN(5, 10),
3514};
3515static const unsigned int sdhi2_cd_b_mux[] = {
3516 SD2_CD_B_MARK,
3517};
3518static const unsigned int sdhi2_wp_a_pins[] = {
3519 /* WP */
3520 RCAR_GP_PIN(4, 14),
3521};
3522static const unsigned int sdhi2_wp_a_mux[] = {
3523 SD2_WP_A_MARK,
3524};
3525static const unsigned int sdhi2_wp_b_pins[] = {
3526 /* WP */
3527 RCAR_GP_PIN(5, 11),
3528};
3529static const unsigned int sdhi2_wp_b_mux[] = {
3530 SD2_WP_B_MARK,
3531};
3532static const unsigned int sdhi2_ds_pins[] = {
3533 /* DS */
3534 RCAR_GP_PIN(4, 6),
3535};
3536static const unsigned int sdhi2_ds_mux[] = {
3537 SD2_DS_MARK,
3538};
3539/* - SDHI3 ------------------------------------------------------------------ */
3540static const unsigned int sdhi3_data1_pins[] = {
3541 /* D0 */
3542 RCAR_GP_PIN(4, 9),
3543};
3544static const unsigned int sdhi3_data1_mux[] = {
3545 SD3_DAT0_MARK,
3546};
3547static const unsigned int sdhi3_data4_pins[] = {
3548 /* D[0:3] */
3549 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3550 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3551};
3552static const unsigned int sdhi3_data4_mux[] = {
3553 SD3_DAT0_MARK, SD3_DAT1_MARK,
3554 SD3_DAT2_MARK, SD3_DAT3_MARK,
3555};
3556static const unsigned int sdhi3_data8_pins[] = {
3557 /* D[0:7] */
3558 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3559 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3560 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3561 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3562};
3563static const unsigned int sdhi3_data8_mux[] = {
3564 SD3_DAT0_MARK, SD3_DAT1_MARK,
3565 SD3_DAT2_MARK, SD3_DAT3_MARK,
3566 SD3_DAT4_MARK, SD3_DAT5_MARK,
3567 SD3_DAT6_MARK, SD3_DAT7_MARK,
3568};
3569static const unsigned int sdhi3_ctrl_pins[] = {
3570 /* CLK, CMD */
3571 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3572};
3573static const unsigned int sdhi3_ctrl_mux[] = {
3574 SD3_CLK_MARK, SD3_CMD_MARK,
3575};
3576static const unsigned int sdhi3_cd_pins[] = {
3577 /* CD */
3578 RCAR_GP_PIN(4, 15),
3579};
3580static const unsigned int sdhi3_cd_mux[] = {
3581 SD3_CD_MARK,
3582};
3583static const unsigned int sdhi3_wp_pins[] = {
3584 /* WP */
3585 RCAR_GP_PIN(4, 16),
3586};
3587static const unsigned int sdhi3_wp_mux[] = {
3588 SD3_WP_MARK,
3589};
3590static const unsigned int sdhi3_ds_pins[] = {
3591 /* DS */
3592 RCAR_GP_PIN(4, 17),
3593};
3594static const unsigned int sdhi3_ds_mux[] = {
3595 SD3_DS_MARK,
3596};
3597
0526234d
KM		 3598/* - SSI -------------------------------------------------------------------- */
3599static const unsigned int ssi0_data_pins[] = {
3600 /* SDATA */
3601 RCAR_GP_PIN(6, 2),
3602};
3603static const unsigned int ssi0_data_mux[] = {
3604 SSI_SDATA0_MARK,
3605};
3606static const unsigned int ssi01239_ctrl_pins[] = {
3607 /* SCK, WS */
3608 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3609};
3610static const unsigned int ssi01239_ctrl_mux[] = {
3611 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3612};
3613static const unsigned int ssi1_data_a_pins[] = {
3614 /* SDATA */
3615 RCAR_GP_PIN(6, 3),
3616};
3617static const unsigned int ssi1_data_a_mux[] = {
3618 SSI_SDATA1_A_MARK,
3619};
3620static const unsigned int ssi1_data_b_pins[] = {
3621 /* SDATA */
3622 RCAR_GP_PIN(5, 12),
3623};
3624static const unsigned int ssi1_data_b_mux[] = {
3625 SSI_SDATA1_B_MARK,
3626};
3627static const unsigned int ssi1_ctrl_a_pins[] = {
3628 /* SCK, WS */
3629 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3630};
3631static const unsigned int ssi1_ctrl_a_mux[] = {
3632 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3633};
3634static const unsigned int ssi1_ctrl_b_pins[] = {
3635 /* SCK, WS */
3636 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3637};
3638static const unsigned int ssi1_ctrl_b_mux[] = {
3639 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3640};
3641static const unsigned int ssi2_data_a_pins[] = {
3642 /* SDATA */
3643 RCAR_GP_PIN(6, 4),
3644};
3645static const unsigned int ssi2_data_a_mux[] = {
3646 SSI_SDATA2_A_MARK,
3647};
3648static const unsigned int ssi2_data_b_pins[] = {
3649 /* SDATA */
3650 RCAR_GP_PIN(5, 13),
3651};
3652static const unsigned int ssi2_data_b_mux[] = {
3653 SSI_SDATA2_B_MARK,
3654};
3655static const unsigned int ssi2_ctrl_a_pins[] = {
3656 /* SCK, WS */
3657 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3658};
3659static const unsigned int ssi2_ctrl_a_mux[] = {
3660 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3661};
3662static const unsigned int ssi2_ctrl_b_pins[] = {
3663 /* SCK, WS */
3664 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3665};
3666static const unsigned int ssi2_ctrl_b_mux[] = {
3667 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3668};
3669static const unsigned int ssi3_data_pins[] = {
3670 /* SDATA */
3671 RCAR_GP_PIN(6, 7),
3672};
3673static const unsigned int ssi3_data_mux[] = {
3674 SSI_SDATA3_MARK,
3675};
3676static const unsigned int ssi349_ctrl_pins[] = {
3677 /* SCK, WS */
3678 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3679};
3680static const unsigned int ssi349_ctrl_mux[] = {
3681 SSI_SCK349_MARK, SSI_WS349_MARK,
3682};
3683static const unsigned int ssi4_data_pins[] = {
3684 /* SDATA */
3685 RCAR_GP_PIN(6, 10),
3686};
3687static const unsigned int ssi4_data_mux[] = {
3688 SSI_SDATA4_MARK,
3689};
3690static const unsigned int ssi4_ctrl_pins[] = {
3691 /* SCK, WS */
3692 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3693};
3694static const unsigned int ssi4_ctrl_mux[] = {
3695 SSI_SCK4_MARK, SSI_WS4_MARK,
3696};
3697static const unsigned int ssi5_data_pins[] = {
3698 /* SDATA */
3699 RCAR_GP_PIN(6, 13),
3700};
3701static const unsigned int ssi5_data_mux[] = {
3702 SSI_SDATA5_MARK,
3703};
3704static const unsigned int ssi5_ctrl_pins[] = {
3705 /* SCK, WS */
3706 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3707};
3708static const unsigned int ssi5_ctrl_mux[] = {
3709 SSI_SCK5_MARK, SSI_WS5_MARK,
3710};
3711static const unsigned int ssi6_data_pins[] = {
3712 /* SDATA */
3713 RCAR_GP_PIN(6, 16),
3714};
3715static const unsigned int ssi6_data_mux[] = {
3716 SSI_SDATA6_MARK,
3717};
3718static const unsigned int ssi6_ctrl_pins[] = {
3719 /* SCK, WS */
3720 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3721};
3722static const unsigned int ssi6_ctrl_mux[] = {
3723 SSI_SCK6_MARK, SSI_WS6_MARK,
3724};
3725static const unsigned int ssi7_data_pins[] = {
3726 /* SDATA */
3727 RCAR_GP_PIN(6, 19),
3728};
3729static const unsigned int ssi7_data_mux[] = {
3730 SSI_SDATA7_MARK,
3731};
3732static const unsigned int ssi78_ctrl_pins[] = {
3733 /* SCK, WS */
3734 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3735};
3736static const unsigned int ssi78_ctrl_mux[] = {
3737 SSI_SCK78_MARK, SSI_WS78_MARK,
3738};
3739static const unsigned int ssi8_data_pins[] = {
3740 /* SDATA */
3741 RCAR_GP_PIN(6, 20),
3742};
3743static const unsigned int ssi8_data_mux[] = {
3744 SSI_SDATA8_MARK,
3745};
3746static const unsigned int ssi9_data_a_pins[] = {
3747 /* SDATA */
3748 RCAR_GP_PIN(6, 21),
3749};
3750static const unsigned int ssi9_data_a_mux[] = {
3751 SSI_SDATA9_A_MARK,
3752};
3753static const unsigned int ssi9_data_b_pins[] = {
3754 /* SDATA */
3755 RCAR_GP_PIN(5, 14),
3756};
3757static const unsigned int ssi9_data_b_mux[] = {
3758 SSI_SDATA9_B_MARK,
3759};
3760static const unsigned int ssi9_ctrl_a_pins[] = {
3761 /* SCK, WS */
3762 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3763};
3764static const unsigned int ssi9_ctrl_a_mux[] = {
3765 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3766};
3767static const unsigned int ssi9_ctrl_b_pins[] = {
3768 /* SCK, WS */
3769 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3770};
3771static const unsigned int ssi9_ctrl_b_mux[] = {
3772 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3773};
3774
933ddbe5
YS		 3775/* - USB0 ------------------------------------------------------------------- */
3776static const unsigned int usb0_pins[] = {
3777 /* PWEN, OVC */
3778 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3779};
3780static const unsigned int usb0_mux[] = {
3781 USB0_PWEN_MARK, USB0_OVC_MARK,
3782};
3783/* - USB1 ------------------------------------------------------------------- */
3784static const unsigned int usb1_pins[] = {
3785 /* PWEN, OVC */
3786 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3787};
3788static const unsigned int usb1_mux[] = {
3789 USB1_PWEN_MARK, USB1_OVC_MARK,
3790};
3791/* - USB2 ------------------------------------------------------------------- */
3792static const unsigned int usb2_pins[] = {
3793 /* PWEN, OVC */
3794 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3795};
3796static const unsigned int usb2_mux[] = {
3797 USB2_PWEN_MARK, USB2_OVC_MARK,
3798};
3799/* - USB2_CH3 --------------------------------------------------------------- */
3800static const unsigned int usb2_ch3_pins[] = {
3801 /* PWEN, OVC */
3802 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3803};
3804static const unsigned int usb2_ch3_mux[] = {
3805 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3806};
3807
5ec8a41a
TK		 3808/* - USB30 ------------------------------------------------------------------ */
3809static const unsigned int usb30_pins[] = {
3810 /* PWEN, OVC */
3811 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3812};
3813static const unsigned int usb30_mux[] = {
3814 USB30_PWEN_MARK, USB30_OVC_MARK,
3815};
3816
b205914c 3817static const struct sh_pfc_pin_group pinmux_groups[] = {
55bfea9f
KM		 3818 SH_PFC_PIN_GROUP(audio_clk_a_a),
3819 SH_PFC_PIN_GROUP(audio_clk_a_b),
3820 SH_PFC_PIN_GROUP(audio_clk_a_c),
3821 SH_PFC_PIN_GROUP(audio_clk_b_a),
3822 SH_PFC_PIN_GROUP(audio_clk_b_b),
3823 SH_PFC_PIN_GROUP(audio_clk_c_a),
3824 SH_PFC_PIN_GROUP(audio_clk_c_b),
3825 SH_PFC_PIN_GROUP(audio_clkout_a),
3826 SH_PFC_PIN_GROUP(audio_clkout_b),
3827 SH_PFC_PIN_GROUP(audio_clkout_c),
3828 SH_PFC_PIN_GROUP(audio_clkout_d),
3829 SH_PFC_PIN_GROUP(audio_clkout1_a),
3830 SH_PFC_PIN_GROUP(audio_clkout1_b),
3831 SH_PFC_PIN_GROUP(audio_clkout2_a),
3832 SH_PFC_PIN_GROUP(audio_clkout2_b),
3833 SH_PFC_PIN_GROUP(audio_clkout3_a),
3834 SH_PFC_PIN_GROUP(audio_clkout3_b),
30c078de
GU		 3835 SH_PFC_PIN_GROUP(avb_link),
3836 SH_PFC_PIN_GROUP(avb_magic),
3837 SH_PFC_PIN_GROUP(avb_phy_int),
3838 SH_PFC_PIN_GROUP(avb_mdc),
3839 SH_PFC_PIN_GROUP(avb_mii),
3840 SH_PFC_PIN_GROUP(avb_avtp_pps),
3841 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3842 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3843 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3844 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
641b0ab8
DB		 3845 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3846 SH_PFC_PIN_GROUP(drif0_data0_a),
3847 SH_PFC_PIN_GROUP(drif0_data1_a),
3848 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3849 SH_PFC_PIN_GROUP(drif0_data0_b),
3850 SH_PFC_PIN_GROUP(drif0_data1_b),
3851 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3852 SH_PFC_PIN_GROUP(drif0_data0_c),
3853 SH_PFC_PIN_GROUP(drif0_data1_c),
3854 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3855 SH_PFC_PIN_GROUP(drif1_data0_a),
3856 SH_PFC_PIN_GROUP(drif1_data1_a),
3857 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3858 SH_PFC_PIN_GROUP(drif1_data0_b),
3859 SH_PFC_PIN_GROUP(drif1_data1_b),
3860 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3861 SH_PFC_PIN_GROUP(drif1_data0_c),
3862 SH_PFC_PIN_GROUP(drif1_data1_c),
3863 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3864 SH_PFC_PIN_GROUP(drif2_data0_a),
3865 SH_PFC_PIN_GROUP(drif2_data1_a),
3866 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3867 SH_PFC_PIN_GROUP(drif2_data0_b),
3868 SH_PFC_PIN_GROUP(drif2_data1_b),
3869 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3870 SH_PFC_PIN_GROUP(drif3_data0_a),
3871 SH_PFC_PIN_GROUP(drif3_data1_a),
3872 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3873 SH_PFC_PIN_GROUP(drif3_data0_b),
3874 SH_PFC_PIN_GROUP(drif3_data1_b),
a20a6585
LP		 3875 SH_PFC_PIN_GROUP(du_rgb666),
3876 SH_PFC_PIN_GROUP(du_rgb888),
3877 SH_PFC_PIN_GROUP(du_clk_out_0),
3878 SH_PFC_PIN_GROUP(du_clk_out_1),
3879 SH_PFC_PIN_GROUP(du_sync),
3880 SH_PFC_PIN_GROUP(du_oddf),
3881 SH_PFC_PIN_GROUP(du_cde),
3882 SH_PFC_PIN_GROUP(du_disp),
7a362e34
WS		 3883 SH_PFC_PIN_GROUP(hscif0_data),
3884 SH_PFC_PIN_GROUP(hscif0_clk),
3885 SH_PFC_PIN_GROUP(hscif0_ctrl),
3886 SH_PFC_PIN_GROUP(hscif1_data_a),
3887 SH_PFC_PIN_GROUP(hscif1_clk_a),
3888 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3889 SH_PFC_PIN_GROUP(hscif1_data_b),
3890 SH_PFC_PIN_GROUP(hscif1_clk_b),
3891 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3892 SH_PFC_PIN_GROUP(hscif2_data_a),
3893 SH_PFC_PIN_GROUP(hscif2_clk_a),
3894 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3895 SH_PFC_PIN_GROUP(hscif2_data_b),
3896 SH_PFC_PIN_GROUP(hscif2_clk_b),
3897 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3898 SH_PFC_PIN_GROUP(hscif2_data_c),
3899 SH_PFC_PIN_GROUP(hscif2_clk_c),
3900 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3901 SH_PFC_PIN_GROUP(hscif3_data_a),
3902 SH_PFC_PIN_GROUP(hscif3_clk),
3903 SH_PFC_PIN_GROUP(hscif3_ctrl),
3904 SH_PFC_PIN_GROUP(hscif3_data_b),
3905 SH_PFC_PIN_GROUP(hscif3_data_c),
3906 SH_PFC_PIN_GROUP(hscif3_data_d),
3907 SH_PFC_PIN_GROUP(hscif4_data_a),
3908 SH_PFC_PIN_GROUP(hscif4_clk),
3909 SH_PFC_PIN_GROUP(hscif4_ctrl),
3910 SH_PFC_PIN_GROUP(hscif4_data_b),
f62d4c9e
WS		 3911 SH_PFC_PIN_GROUP(i2c1_a),
3912 SH_PFC_PIN_GROUP(i2c1_b),
3913 SH_PFC_PIN_GROUP(i2c2_a),
3914 SH_PFC_PIN_GROUP(i2c2_b),
3915 SH_PFC_PIN_GROUP(i2c6_a),
3916 SH_PFC_PIN_GROUP(i2c6_b),
3917 SH_PFC_PIN_GROUP(i2c6_c),
8480e6ca
GU		 3918 SH_PFC_PIN_GROUP(intc_ex_irq0),
3919 SH_PFC_PIN_GROUP(intc_ex_irq1),
3920 SH_PFC_PIN_GROUP(intc_ex_irq2),
3921 SH_PFC_PIN_GROUP(intc_ex_irq3),
3922 SH_PFC_PIN_GROUP(intc_ex_irq4),
3923 SH_PFC_PIN_GROUP(intc_ex_irq5),
3e6c7727
GU		 3924 SH_PFC_PIN_GROUP(msiof0_clk),
3925 SH_PFC_PIN_GROUP(msiof0_sync),
3926 SH_PFC_PIN_GROUP(msiof0_ss1),
3927 SH_PFC_PIN_GROUP(msiof0_ss2),
3928 SH_PFC_PIN_GROUP(msiof0_txd),
3929 SH_PFC_PIN_GROUP(msiof0_rxd),
3930 SH_PFC_PIN_GROUP(msiof1_clk_a),
3931 SH_PFC_PIN_GROUP(msiof1_sync_a),
3932 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3933 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3934 SH_PFC_PIN_GROUP(msiof1_txd_a),
3935 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3936 SH_PFC_PIN_GROUP(msiof1_clk_b),
3937 SH_PFC_PIN_GROUP(msiof1_sync_b),
3938 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3939 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3940 SH_PFC_PIN_GROUP(msiof1_txd_b),
3941 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3942 SH_PFC_PIN_GROUP(msiof1_clk_c),
3943 SH_PFC_PIN_GROUP(msiof1_sync_c),
3944 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3945 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3946 SH_PFC_PIN_GROUP(msiof1_txd_c),
3947 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3948 SH_PFC_PIN_GROUP(msiof1_clk_d),
3949 SH_PFC_PIN_GROUP(msiof1_sync_d),
3950 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3951 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3952 SH_PFC_PIN_GROUP(msiof1_txd_d),
3953 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3954 SH_PFC_PIN_GROUP(msiof1_clk_e),
3955 SH_PFC_PIN_GROUP(msiof1_sync_e),
3956 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3957 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3958 SH_PFC_PIN_GROUP(msiof1_txd_e),
3959 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3960 SH_PFC_PIN_GROUP(msiof1_clk_f),
3961 SH_PFC_PIN_GROUP(msiof1_sync_f),
3962 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3963 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3964 SH_PFC_PIN_GROUP(msiof1_txd_f),
3965 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3966 SH_PFC_PIN_GROUP(msiof1_clk_g),
3967 SH_PFC_PIN_GROUP(msiof1_sync_g),
3968 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3969 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3970 SH_PFC_PIN_GROUP(msiof1_txd_g),
3971 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3972 SH_PFC_PIN_GROUP(msiof2_clk_a),
3973 SH_PFC_PIN_GROUP(msiof2_sync_a),
3974 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3975 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3976 SH_PFC_PIN_GROUP(msiof2_txd_a),
3977 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3978 SH_PFC_PIN_GROUP(msiof2_clk_b),
3979 SH_PFC_PIN_GROUP(msiof2_sync_b),
3980 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3981 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3982 SH_PFC_PIN_GROUP(msiof2_txd_b),
3983 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3984 SH_PFC_PIN_GROUP(msiof2_clk_c),
3985 SH_PFC_PIN_GROUP(msiof2_sync_c),
3986 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3987 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3988 SH_PFC_PIN_GROUP(msiof2_txd_c),
3989 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3990 SH_PFC_PIN_GROUP(msiof2_clk_d),
3991 SH_PFC_PIN_GROUP(msiof2_sync_d),
3992 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3993 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3994 SH_PFC_PIN_GROUP(msiof2_txd_d),
3995 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3996 SH_PFC_PIN_GROUP(msiof3_clk_a),
3997 SH_PFC_PIN_GROUP(msiof3_sync_a),
3998 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3999 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4000 SH_PFC_PIN_GROUP(msiof3_txd_a),
4001 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4002 SH_PFC_PIN_GROUP(msiof3_clk_b),
4003 SH_PFC_PIN_GROUP(msiof3_sync_b),
4004 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4005 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4006 SH_PFC_PIN_GROUP(msiof3_txd_b),
4007 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4008 SH_PFC_PIN_GROUP(msiof3_clk_c),
4009 SH_PFC_PIN_GROUP(msiof3_sync_c),
4010 SH_PFC_PIN_GROUP(msiof3_txd_c),
4011 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4012 SH_PFC_PIN_GROUP(msiof3_clk_d),
4013 SH_PFC_PIN_GROUP(msiof3_sync_d),
4014 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4015 SH_PFC_PIN_GROUP(msiof3_txd_d),
4016 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4017 SH_PFC_PIN_GROUP(msiof3_clk_e),
4018 SH_PFC_PIN_GROUP(msiof3_sync_e),
4019 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4020 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4021 SH_PFC_PIN_GROUP(msiof3_txd_e),
4022 SH_PFC_PIN_GROUP(msiof3_rxd_e),
c03a133b
LP		 4023 SH_PFC_PIN_GROUP(pwm0),
4024 SH_PFC_PIN_GROUP(pwm1_a),
4025 SH_PFC_PIN_GROUP(pwm1_b),
4026 SH_PFC_PIN_GROUP(pwm2_a),
4027 SH_PFC_PIN_GROUP(pwm2_b),
4028 SH_PFC_PIN_GROUP(pwm3_a),
4029 SH_PFC_PIN_GROUP(pwm3_b),
4030 SH_PFC_PIN_GROUP(pwm4_a),
4031 SH_PFC_PIN_GROUP(pwm4_b),
4032 SH_PFC_PIN_GROUP(pwm5_a),
4033 SH_PFC_PIN_GROUP(pwm5_b),
4034 SH_PFC_PIN_GROUP(pwm6_a),
4035 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 4036 SH_PFC_PIN_GROUP(scif0_data),
4037 SH_PFC_PIN_GROUP(scif0_clk),
4038 SH_PFC_PIN_GROUP(scif0_ctrl),
4039 SH_PFC_PIN_GROUP(scif1_data_a),
4040 SH_PFC_PIN_GROUP(scif1_clk),
4041 SH_PFC_PIN_GROUP(scif1_ctrl),
4042 SH_PFC_PIN_GROUP(scif1_data_b),
4043 SH_PFC_PIN_GROUP(scif2_data_a),
4044 SH_PFC_PIN_GROUP(scif2_clk),
4045 SH_PFC_PIN_GROUP(scif2_data_b),
4046 SH_PFC_PIN_GROUP(scif3_data_a),
4047 SH_PFC_PIN_GROUP(scif3_clk),
4048 SH_PFC_PIN_GROUP(scif3_ctrl),
4049 SH_PFC_PIN_GROUP(scif3_data_b),
4050 SH_PFC_PIN_GROUP(scif4_data_a),
4051 SH_PFC_PIN_GROUP(scif4_clk_a),
4052 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4053 SH_PFC_PIN_GROUP(scif4_data_b),
4054 SH_PFC_PIN_GROUP(scif4_clk_b),
4055 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4056 SH_PFC_PIN_GROUP(scif4_data_c),
4057 SH_PFC_PIN_GROUP(scif4_clk_c),
4058 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4059 SH_PFC_PIN_GROUP(scif5_data_a),
4060 SH_PFC_PIN_GROUP(scif5_clk_a),
4061 SH_PFC_PIN_GROUP(scif5_data_b),
4062 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 4063 SH_PFC_PIN_GROUP(scif_clk_a),
4064 SH_PFC_PIN_GROUP(scif_clk_b),
9ed13958
TK		 4065 SH_PFC_PIN_GROUP(sdhi0_data1),
4066 SH_PFC_PIN_GROUP(sdhi0_data4),
4067 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4068 SH_PFC_PIN_GROUP(sdhi0_cd),
4069 SH_PFC_PIN_GROUP(sdhi0_wp),
4070 SH_PFC_PIN_GROUP(sdhi1_data1),
4071 SH_PFC_PIN_GROUP(sdhi1_data4),
4072 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4073 SH_PFC_PIN_GROUP(sdhi1_cd),
4074 SH_PFC_PIN_GROUP(sdhi1_wp),
4075 SH_PFC_PIN_GROUP(sdhi2_data1),
4076 SH_PFC_PIN_GROUP(sdhi2_data4),
4077 SH_PFC_PIN_GROUP(sdhi2_data8),
4078 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4079 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4080 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4081 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4082 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4083 SH_PFC_PIN_GROUP(sdhi2_ds),
4084 SH_PFC_PIN_GROUP(sdhi3_data1),
4085 SH_PFC_PIN_GROUP(sdhi3_data4),
4086 SH_PFC_PIN_GROUP(sdhi3_data8),
4087 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4088 SH_PFC_PIN_GROUP(sdhi3_cd),
4089 SH_PFC_PIN_GROUP(sdhi3_wp),
4090 SH_PFC_PIN_GROUP(sdhi3_ds),
0526234d
KM		 4091 SH_PFC_PIN_GROUP(ssi0_data),
4092 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4093 SH_PFC_PIN_GROUP(ssi1_data_a),
4094 SH_PFC_PIN_GROUP(ssi1_data_b),
4095 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4096 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4097 SH_PFC_PIN_GROUP(ssi2_data_a),
4098 SH_PFC_PIN_GROUP(ssi2_data_b),
4099 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4100 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4101 SH_PFC_PIN_GROUP(ssi3_data),
4102 SH_PFC_PIN_GROUP(ssi349_ctrl),
4103 SH_PFC_PIN_GROUP(ssi4_data),
4104 SH_PFC_PIN_GROUP(ssi4_ctrl),
4105 SH_PFC_PIN_GROUP(ssi5_data),
4106 SH_PFC_PIN_GROUP(ssi5_ctrl),
4107 SH_PFC_PIN_GROUP(ssi6_data),
4108 SH_PFC_PIN_GROUP(ssi6_ctrl),
4109 SH_PFC_PIN_GROUP(ssi7_data),
4110 SH_PFC_PIN_GROUP(ssi78_ctrl),
4111 SH_PFC_PIN_GROUP(ssi8_data),
4112 SH_PFC_PIN_GROUP(ssi9_data_a),
4113 SH_PFC_PIN_GROUP(ssi9_data_b),
4114 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4115 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
933ddbe5
YS		 4116 SH_PFC_PIN_GROUP(usb0),
4117 SH_PFC_PIN_GROUP(usb1),
4118 SH_PFC_PIN_GROUP(usb2),
4119 SH_PFC_PIN_GROUP(usb2_ch3),
5ec8a41a 4120 SH_PFC_PIN_GROUP(usb30),
e7ad4d3c
GU		 4121};
4122
55bfea9f
KM		 4123static const char * const audio_clk_groups[] = {
4124 "audio_clk_a_a",
4125 "audio_clk_a_b",
4126 "audio_clk_a_c",
4127 "audio_clk_b_a",
4128 "audio_clk_b_b",
4129 "audio_clk_c_a",
4130 "audio_clk_c_b",
4131 "audio_clkout_a",
4132 "audio_clkout_b",
4133 "audio_clkout_c",
4134 "audio_clkout_d",
4135 "audio_clkout1_a",
4136 "audio_clkout1_b",
4137 "audio_clkout2_a",
4138 "audio_clkout2_b",
4139 "audio_clkout3_a",
4140 "audio_clkout3_b",
4141};
4142
30c078de
GU		 4143static const char * const avb_groups[] = {
4144 "avb_link",
4145 "avb_magic",
4146 "avb_phy_int",
4147 "avb_mdc",
4148 "avb_mii",
4149 "avb_avtp_pps",
4150 "avb_avtp_match_a",
4151 "avb_avtp_capture_a",
4152 "avb_avtp_match_b",
4153 "avb_avtp_capture_b",
4154};
4155
641b0ab8
DB		 4156static const char * const drif0_groups[] = {
4157 "drif0_ctrl_a",
4158 "drif0_data0_a",
4159 "drif0_data1_a",
4160 "drif0_ctrl_b",
4161 "drif0_data0_b",
4162 "drif0_data1_b",
4163 "drif0_ctrl_c",
4164 "drif0_data0_c",
4165 "drif0_data1_c",
4166};
4167
4168static const char * const drif1_groups[] = {
4169 "drif1_ctrl_a",
4170 "drif1_data0_a",
4171 "drif1_data1_a",
4172 "drif1_ctrl_b",
4173 "drif1_data0_b",
4174 "drif1_data1_b",
4175 "drif1_ctrl_c",
4176 "drif1_data0_c",
4177 "drif1_data1_c",
4178};
4179
4180static const char * const drif2_groups[] = {
4181 "drif2_ctrl_a",
4182 "drif2_data0_a",
4183 "drif2_data1_a",
4184 "drif2_ctrl_b",
4185 "drif2_data0_b",
4186 "drif2_data1_b",
4187};
4188
4189static const char * const drif3_groups[] = {
4190 "drif3_ctrl_a",
4191 "drif3_data0_a",
4192 "drif3_data1_a",
4193 "drif3_ctrl_b",
4194 "drif3_data0_b",
4195 "drif3_data1_b",
4196};
4197
a20a6585
LP		 4198static const char * const du_groups[] = {
4199 "du_rgb666",
4200 "du_rgb888",
4201 "du_clk_out_0",
4202 "du_clk_out_1",
4203 "du_sync",
4204 "du_oddf",
4205 "du_cde",
4206 "du_disp",
4207};
4208
7a362e34
WS		 4209static const char * const hscif0_groups[] = {
4210 "hscif0_data",
4211 "hscif0_clk",
4212 "hscif0_ctrl",
4213};
4214
4215static const char * const hscif1_groups[] = {
4216 "hscif1_data_a",
4217 "hscif1_clk_a",
4218 "hscif1_ctrl_a",
4219 "hscif1_data_b",
4220 "hscif1_clk_b",
4221 "hscif1_ctrl_b",
4222};
4223
4224static const char * const hscif2_groups[] = {
4225 "hscif2_data_a",
4226 "hscif2_clk_a",
4227 "hscif2_ctrl_a",
4228 "hscif2_data_b",
4229 "hscif2_clk_b",
4230 "hscif2_ctrl_b",
4231 "hscif2_data_c",
4232 "hscif2_clk_c",
4233 "hscif2_ctrl_c",
4234};
4235
4236static const char * const hscif3_groups[] = {
4237 "hscif3_data_a",
4238 "hscif3_clk",
4239 "hscif3_ctrl",
4240 "hscif3_data_b",
4241 "hscif3_data_c",
4242 "hscif3_data_d",
4243};
4244
4245static const char * const hscif4_groups[] = {
4246 "hscif4_data_a",
4247 "hscif4_clk",
4248 "hscif4_ctrl",
4249 "hscif4_data_b",
4250};
4251
f62d4c9e
WS		 4252static const char * const i2c1_groups[] = {
4253 "i2c1_a",
4254 "i2c1_b",
4255};
4256
4257static const char * const i2c2_groups[] = {
4258 "i2c2_a",
4259 "i2c2_b",
4260};
4261
4262static const char * const i2c6_groups[] = {
4263 "i2c6_a",
4264 "i2c6_b",
4265 "i2c6_c",
4266};
4267
8480e6ca
GU		 4268static const char * const intc_ex_groups[] = {
4269 "intc_ex_irq0",
4270 "intc_ex_irq1",
4271 "intc_ex_irq2",
4272 "intc_ex_irq3",
4273 "intc_ex_irq4",
4274 "intc_ex_irq5",
4275};
4276
3e6c7727
GU		 4277static const char * const msiof0_groups[] = {
4278 "msiof0_clk",
4279 "msiof0_sync",
4280 "msiof0_ss1",
4281 "msiof0_ss2",
4282 "msiof0_txd",
4283 "msiof0_rxd",
4284};
4285
4286static const char * const msiof1_groups[] = {
4287 "msiof1_clk_a",
4288 "msiof1_sync_a",
4289 "msiof1_ss1_a",
4290 "msiof1_ss2_a",
4291 "msiof1_txd_a",
4292 "msiof1_rxd_a",
4293 "msiof1_clk_b",
4294 "msiof1_sync_b",
4295 "msiof1_ss1_b",
4296 "msiof1_ss2_b",
4297 "msiof1_txd_b",
4298 "msiof1_rxd_b",
4299 "msiof1_clk_c",
4300 "msiof1_sync_c",
4301 "msiof1_ss1_c",
4302 "msiof1_ss2_c",
4303 "msiof1_txd_c",
4304 "msiof1_rxd_c",
4305 "msiof1_clk_d",
4306 "msiof1_sync_d",
4307 "msiof1_ss1_d",
4308 "msiof1_ss2_d",
4309 "msiof1_txd_d",
4310 "msiof1_rxd_d",
4311 "msiof1_clk_e",
4312 "msiof1_sync_e",
4313 "msiof1_ss1_e",
4314 "msiof1_ss2_e",
4315 "msiof1_txd_e",
4316 "msiof1_rxd_e",
4317 "msiof1_clk_f",
4318 "msiof1_sync_f",
4319 "msiof1_ss1_f",
4320 "msiof1_ss2_f",
4321 "msiof1_txd_f",
4322 "msiof1_rxd_f",
4323 "msiof1_clk_g",
4324 "msiof1_sync_g",
4325 "msiof1_ss1_g",
4326 "msiof1_ss2_g",
4327 "msiof1_txd_g",
4328 "msiof1_rxd_g",
4329};
4330
4331static const char * const msiof2_groups[] = {
4332 "msiof2_clk_a",
4333 "msiof2_sync_a",
4334 "msiof2_ss1_a",
4335 "msiof2_ss2_a",
4336 "msiof2_txd_a",
4337 "msiof2_rxd_a",
4338 "msiof2_clk_b",
4339 "msiof2_sync_b",
4340 "msiof2_ss1_b",
4341 "msiof2_ss2_b",
4342 "msiof2_txd_b",
4343 "msiof2_rxd_b",
4344 "msiof2_clk_c",
4345 "msiof2_sync_c",
4346 "msiof2_ss1_c",
4347 "msiof2_ss2_c",
4348 "msiof2_txd_c",
4349 "msiof2_rxd_c",
4350 "msiof2_clk_d",
4351 "msiof2_sync_d",
4352 "msiof2_ss1_d",
4353 "msiof2_ss2_d",
4354 "msiof2_txd_d",
4355 "msiof2_rxd_d",
4356};
4357
4358static const char * const msiof3_groups[] = {
4359 "msiof3_clk_a",
4360 "msiof3_sync_a",
4361 "msiof3_ss1_a",
4362 "msiof3_ss2_a",
4363 "msiof3_txd_a",
4364 "msiof3_rxd_a",
4365 "msiof3_clk_b",
4366 "msiof3_sync_b",
4367 "msiof3_ss1_b",
4368 "msiof3_ss2_b",
4369 "msiof3_txd_b",
4370 "msiof3_rxd_b",
4371 "msiof3_clk_c",
4372 "msiof3_sync_c",
4373 "msiof3_txd_c",
4374 "msiof3_rxd_c",
4375 "msiof3_clk_d",
4376 "msiof3_sync_d",
4377 "msiof3_ss1_d",
4378 "msiof3_txd_d",
4379 "msiof3_rxd_d",
4380 "msiof3_clk_e",
4381 "msiof3_sync_e",
4382 "msiof3_ss1_e",
4383 "msiof3_ss2_e",
4384 "msiof3_txd_e",
4385 "msiof3_rxd_e",
4386};
4387
c03a133b
LP		 4388static const char * const pwm0_groups[] = {
4389 "pwm0",
4390};
4391
4392static const char * const pwm1_groups[] = {
4393 "pwm1_a",
4394 "pwm1_b",
4395};
4396
4397static const char * const pwm2_groups[] = {
4398 "pwm2_a",
4399 "pwm2_b",
4400};
4401
4402static const char * const pwm3_groups[] = {
4403 "pwm3_a",
4404 "pwm3_b",
4405};
4406
4407static const char * const pwm4_groups[] = {
4408 "pwm4_a",
4409 "pwm4_b",
4410};
4411
4412static const char * const pwm5_groups[] = {
4413 "pwm5_a",
4414 "pwm5_b",
4415};
4416
4417static const char * const pwm6_groups[] = {
4418 "pwm6_a",
4419 "pwm6_b",
4420};
4421
e7ad4d3c
GU		 4422static const char * const scif0_groups[] = {
4423 "scif0_data",
4424 "scif0_clk",
4425 "scif0_ctrl",
4426};
4427
4428static const char * const scif1_groups[] = {
4429 "scif1_data_a",
4430 "scif1_clk",
4431 "scif1_ctrl",
4432 "scif1_data_b",
4433};
4434
4435static const char * const scif2_groups[] = {
4436 "scif2_data_a",
4437 "scif2_clk",
4438 "scif2_data_b",
4439};
4440
4441static const char * const scif3_groups[] = {
4442 "scif3_data_a",
4443 "scif3_clk",
4444 "scif3_ctrl",
4445 "scif3_data_b",
4446};
4447
4448static const char * const scif4_groups[] = {
4449 "scif4_data_a",
4450 "scif4_clk_a",
4451 "scif4_ctrl_a",
4452 "scif4_data_b",
4453 "scif4_clk_b",
4454 "scif4_ctrl_b",
4455 "scif4_data_c",
4456 "scif4_clk_c",
4457 "scif4_ctrl_c",
4458};
4459
4460static const char * const scif5_groups[] = {
4461 "scif5_data_a",
4462 "scif5_clk_a",
4463 "scif5_data_b",
4464 "scif5_clk_b",
76250a6c
TK		 4465};
4466
d14a39ed
GU		 4467static const char * const scif_clk_groups[] = {
4468 "scif_clk_a",
4469 "scif_clk_b",
4470};
4471
9ed13958
TK		 4472static const char * const sdhi0_groups[] = {
4473 "sdhi0_data1",
4474 "sdhi0_data4",
4475 "sdhi0_ctrl",
4476 "sdhi0_cd",
4477 "sdhi0_wp",
4478};
4479
4480static const char * const sdhi1_groups[] = {
4481 "sdhi1_data1",
4482 "sdhi1_data4",
4483 "sdhi1_ctrl",
4484 "sdhi1_cd",
4485 "sdhi1_wp",
4486};
4487
4488static const char * const sdhi2_groups[] = {
4489 "sdhi2_data1",
4490 "sdhi2_data4",
4491 "sdhi2_data8",
4492 "sdhi2_ctrl",
4493 "sdhi2_cd_a",
4494 "sdhi2_wp_a",
4495 "sdhi2_cd_b",
4496 "sdhi2_wp_b",
4497 "sdhi2_ds",
4498};
4499
4500static const char * const sdhi3_groups[] = {
4501 "sdhi3_data1",
4502 "sdhi3_data4",
4503 "sdhi3_data8",
4504 "sdhi3_ctrl",
4505 "sdhi3_cd",
4506 "sdhi3_wp",
4507 "sdhi3_ds",
4508};
4509
0526234d
KM		 4510static const char * const ssi_groups[] = {
4511 "ssi0_data",
4512 "ssi01239_ctrl",
4513 "ssi1_data_a",
4514 "ssi1_data_b",
4515 "ssi1_ctrl_a",
4516 "ssi1_ctrl_b",
4517 "ssi2_data_a",
4518 "ssi2_data_b",
4519 "ssi2_ctrl_a",
4520 "ssi2_ctrl_b",
4521 "ssi3_data",
4522 "ssi349_ctrl",
4523 "ssi4_data",
4524 "ssi4_ctrl",
4525 "ssi5_data",
4526 "ssi5_ctrl",
4527 "ssi6_data",
4528 "ssi6_ctrl",
4529 "ssi7_data",
4530 "ssi78_ctrl",
4531 "ssi8_data",
4532 "ssi9_data_a",
4533 "ssi9_data_b",
4534 "ssi9_ctrl_a",
4535 "ssi9_ctrl_b",
4536};
4537
933ddbe5
YS		 4538static const char * const usb0_groups[] = {
4539 "usb0",
4540};
4541
4542static const char * const usb1_groups[] = {
4543 "usb1",
4544};
4545
4546static const char * const usb2_groups[] = {
4547 "usb2",
4548};
4549
4550static const char * const usb2_ch3_groups[] = {
4551 "usb2_ch3",
4552};
4553
5ec8a41a
TK		 4554static const char * const usb30_groups[] = {
4555 "usb30",
4556};
4557
0b0ffc96 4558static const struct sh_pfc_function pinmux_functions[] = {
55bfea9f 4559 SH_PFC_FUNCTION(audio_clk),
30c078de 4560 SH_PFC_FUNCTION(avb),
641b0ab8
DB		 4561 SH_PFC_FUNCTION(drif0),
4562 SH_PFC_FUNCTION(drif1),
4563 SH_PFC_FUNCTION(drif2),
4564 SH_PFC_FUNCTION(drif3),
a20a6585 4565 SH_PFC_FUNCTION(du),
7a362e34
WS		 4566 SH_PFC_FUNCTION(hscif0),
4567 SH_PFC_FUNCTION(hscif1),
4568 SH_PFC_FUNCTION(hscif2),
4569 SH_PFC_FUNCTION(hscif3),
4570 SH_PFC_FUNCTION(hscif4),
f62d4c9e
WS		 4571 SH_PFC_FUNCTION(i2c1),
4572 SH_PFC_FUNCTION(i2c2),
4573 SH_PFC_FUNCTION(i2c6),
8480e6ca 4574 SH_PFC_FUNCTION(intc_ex),
3e6c7727
GU		 4575 SH_PFC_FUNCTION(msiof0),
4576 SH_PFC_FUNCTION(msiof1),
4577 SH_PFC_FUNCTION(msiof2),
4578 SH_PFC_FUNCTION(msiof3),
c03a133b
LP		 4579 SH_PFC_FUNCTION(pwm0),
4580 SH_PFC_FUNCTION(pwm1),
4581 SH_PFC_FUNCTION(pwm2),
4582 SH_PFC_FUNCTION(pwm3),
4583 SH_PFC_FUNCTION(pwm4),
4584 SH_PFC_FUNCTION(pwm5),
4585 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 4586 SH_PFC_FUNCTION(scif0),
4587 SH_PFC_FUNCTION(scif1),
4588 SH_PFC_FUNCTION(scif2),
4589 SH_PFC_FUNCTION(scif3),
4590 SH_PFC_FUNCTION(scif4),
4591 SH_PFC_FUNCTION(scif5),
d14a39ed 4592 SH_PFC_FUNCTION(scif_clk),
9ed13958
TK		 4593 SH_PFC_FUNCTION(sdhi0),
4594 SH_PFC_FUNCTION(sdhi1),
4595 SH_PFC_FUNCTION(sdhi2),
4596 SH_PFC_FUNCTION(sdhi3),
0526234d 4597 SH_PFC_FUNCTION(ssi),
933ddbe5
YS		 4598 SH_PFC_FUNCTION(usb0),
4599 SH_PFC_FUNCTION(usb1),
4600 SH_PFC_FUNCTION(usb2),
4601 SH_PFC_FUNCTION(usb2_ch3),
5ec8a41a 4602 SH_PFC_FUNCTION(usb30),
0b0ffc96
TK		 4603};
4604
4605static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4606#define F_(x, y) FN_##y
4607#define FM(x) FN_##x
4608 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4609 0, 0,
4610 0, 0,
4611 0, 0,
4612 0, 0,
4613 0, 0,
4614 0, 0,
4615 0, 0,
4616 0, 0,
4617 0, 0,
4618 0, 0,
4619 0, 0,
4620 0, 0,
4621 0, 0,
4622 0, 0,
4623 0, 0,
4624 0, 0,
4625 GP_0_15_FN, GPSR0_15,
4626 GP_0_14_FN, GPSR0_14,
4627 GP_0_13_FN, GPSR0_13,
4628 GP_0_12_FN, GPSR0_12,
4629 GP_0_11_FN, GPSR0_11,
4630 GP_0_10_FN, GPSR0_10,
4631 GP_0_9_FN, GPSR0_9,
4632 GP_0_8_FN, GPSR0_8,
4633 GP_0_7_FN, GPSR0_7,
4634 GP_0_6_FN, GPSR0_6,
4635 GP_0_5_FN, GPSR0_5,
4636 GP_0_4_FN, GPSR0_4,
4637 GP_0_3_FN, GPSR0_3,
4638 GP_0_2_FN, GPSR0_2,
4639 GP_0_1_FN, GPSR0_1,
4640 GP_0_0_FN, GPSR0_0, }
4641 },
4642 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4643 0, 0,
4644 0, 0,
4645 0, 0,
4646 0, 0,
4647 GP_1_27_FN, GPSR1_27,
4648 GP_1_26_FN, GPSR1_26,
4649 GP_1_25_FN, GPSR1_25,
4650 GP_1_24_FN, GPSR1_24,
4651 GP_1_23_FN, GPSR1_23,
4652 GP_1_22_FN, GPSR1_22,
4653 GP_1_21_FN, GPSR1_21,
4654 GP_1_20_FN, GPSR1_20,
4655 GP_1_19_FN, GPSR1_19,
4656 GP_1_18_FN, GPSR1_18,
4657 GP_1_17_FN, GPSR1_17,
4658 GP_1_16_FN, GPSR1_16,
4659 GP_1_15_FN, GPSR1_15,
4660 GP_1_14_FN, GPSR1_14,
4661 GP_1_13_FN, GPSR1_13,
4662 GP_1_12_FN, GPSR1_12,
4663 GP_1_11_FN, GPSR1_11,
4664 GP_1_10_FN, GPSR1_10,
4665 GP_1_9_FN, GPSR1_9,
4666 GP_1_8_FN, GPSR1_8,
4667 GP_1_7_FN, GPSR1_7,
4668 GP_1_6_FN, GPSR1_6,
4669 GP_1_5_FN, GPSR1_5,
4670 GP_1_4_FN, GPSR1_4,
4671 GP_1_3_FN, GPSR1_3,
4672 GP_1_2_FN, GPSR1_2,
4673 GP_1_1_FN, GPSR1_1,
4674 GP_1_0_FN, GPSR1_0, }
4675 },
4676 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4677 0, 0,
4678 0, 0,
4679 0, 0,
4680 0, 0,
4681 0, 0,
4682 0, 0,
4683 0, 0,
4684 0, 0,
4685 0, 0,
4686 0, 0,
4687 0, 0,
4688 0, 0,
4689 0, 0,
4690 0, 0,
4691 0, 0,
4692 0, 0,
4693 0, 0,
4694 GP_2_14_FN, GPSR2_14,
4695 GP_2_13_FN, GPSR2_13,
4696 GP_2_12_FN, GPSR2_12,
4697 GP_2_11_FN, GPSR2_11,
4698 GP_2_10_FN, GPSR2_10,
4699 GP_2_9_FN, GPSR2_9,
4700 GP_2_8_FN, GPSR2_8,
4701 GP_2_7_FN, GPSR2_7,
4702 GP_2_6_FN, GPSR2_6,
4703 GP_2_5_FN, GPSR2_5,
4704 GP_2_4_FN, GPSR2_4,
4705 GP_2_3_FN, GPSR2_3,
4706 GP_2_2_FN, GPSR2_2,
4707 GP_2_1_FN, GPSR2_1,
4708 GP_2_0_FN, GPSR2_0, }
4709 },
4710 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4711 0, 0,
4712 0, 0,
4713 0, 0,
4714 0, 0,
4715 0, 0,
4716 0, 0,
4717 0, 0,
4718 0, 0,
4719 0, 0,
4720 0, 0,
4721 0, 0,
4722 0, 0,
4723 0, 0,
4724 0, 0,
4725 0, 0,
4726 0, 0,
4727 GP_3_15_FN, GPSR3_15,
4728 GP_3_14_FN, GPSR3_14,
4729 GP_3_13_FN, GPSR3_13,
4730 GP_3_12_FN, GPSR3_12,
4731 GP_3_11_FN, GPSR3_11,
4732 GP_3_10_FN, GPSR3_10,
4733 GP_3_9_FN, GPSR3_9,
4734 GP_3_8_FN, GPSR3_8,
4735 GP_3_7_FN, GPSR3_7,
4736 GP_3_6_FN, GPSR3_6,
4737 GP_3_5_FN, GPSR3_5,
4738 GP_3_4_FN, GPSR3_4,
4739 GP_3_3_FN, GPSR3_3,
4740 GP_3_2_FN, GPSR3_2,
4741 GP_3_1_FN, GPSR3_1,
4742 GP_3_0_FN, GPSR3_0, }
4743 },
4744 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4745 0, 0,
4746 0, 0,
4747 0, 0,
4748 0, 0,
4749 0, 0,
4750 0, 0,
4751 0, 0,
4752 0, 0,
4753 0, 0,
4754 0, 0,
4755 0, 0,
4756 0, 0,
4757 0, 0,
4758 0, 0,
4759 GP_4_17_FN, GPSR4_17,
4760 GP_4_16_FN, GPSR4_16,
4761 GP_4_15_FN, GPSR4_15,
4762 GP_4_14_FN, GPSR4_14,
4763 GP_4_13_FN, GPSR4_13,
4764 GP_4_12_FN, GPSR4_12,
4765 GP_4_11_FN, GPSR4_11,
4766 GP_4_10_FN, GPSR4_10,
4767 GP_4_9_FN, GPSR4_9,
4768 GP_4_8_FN, GPSR4_8,
4769 GP_4_7_FN, GPSR4_7,
4770 GP_4_6_FN, GPSR4_6,
4771 GP_4_5_FN, GPSR4_5,
4772 GP_4_4_FN, GPSR4_4,
4773 GP_4_3_FN, GPSR4_3,
4774 GP_4_2_FN, GPSR4_2,
4775 GP_4_1_FN, GPSR4_1,
4776 GP_4_0_FN, GPSR4_0, }
4777 },
4778 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4779 0, 0,
4780 0, 0,
4781 0, 0,
4782 0, 0,
4783 0, 0,
4784 0, 0,
4785 GP_5_25_FN, GPSR5_25,
4786 GP_5_24_FN, GPSR5_24,
4787 GP_5_23_FN, GPSR5_23,
4788 GP_5_22_FN, GPSR5_22,
4789 GP_5_21_FN, GPSR5_21,
4790 GP_5_20_FN, GPSR5_20,
4791 GP_5_19_FN, GPSR5_19,
4792 GP_5_18_FN, GPSR5_18,
4793 GP_5_17_FN, GPSR5_17,
4794 GP_5_16_FN, GPSR5_16,
4795 GP_5_15_FN, GPSR5_15,
4796 GP_5_14_FN, GPSR5_14,
4797 GP_5_13_FN, GPSR5_13,
4798 GP_5_12_FN, GPSR5_12,
4799 GP_5_11_FN, GPSR5_11,
4800 GP_5_10_FN, GPSR5_10,
4801 GP_5_9_FN, GPSR5_9,
4802 GP_5_8_FN, GPSR5_8,
4803 GP_5_7_FN, GPSR5_7,
4804 GP_5_6_FN, GPSR5_6,
4805 GP_5_5_FN, GPSR5_5,
4806 GP_5_4_FN, GPSR5_4,
4807 GP_5_3_FN, GPSR5_3,
4808 GP_5_2_FN, GPSR5_2,
4809 GP_5_1_FN, GPSR5_1,
4810 GP_5_0_FN, GPSR5_0, }
4811 },
4812 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4813 GP_6_31_FN, GPSR6_31,
4814 GP_6_30_FN, GPSR6_30,
4815 GP_6_29_FN, GPSR6_29,
4816 GP_6_28_FN, GPSR6_28,
4817 GP_6_27_FN, GPSR6_27,
4818 GP_6_26_FN, GPSR6_26,
4819 GP_6_25_FN, GPSR6_25,
4820 GP_6_24_FN, GPSR6_24,
4821 GP_6_23_FN, GPSR6_23,
4822 GP_6_22_FN, GPSR6_22,
4823 GP_6_21_FN, GPSR6_21,
4824 GP_6_20_FN, GPSR6_20,
4825 GP_6_19_FN, GPSR6_19,
4826 GP_6_18_FN, GPSR6_18,
4827 GP_6_17_FN, GPSR6_17,
4828 GP_6_16_FN, GPSR6_16,
4829 GP_6_15_FN, GPSR6_15,
4830 GP_6_14_FN, GPSR6_14,
4831 GP_6_13_FN, GPSR6_13,
4832 GP_6_12_FN, GPSR6_12,
4833 GP_6_11_FN, GPSR6_11,
4834 GP_6_10_FN, GPSR6_10,
4835 GP_6_9_FN, GPSR6_9,
4836 GP_6_8_FN, GPSR6_8,
4837 GP_6_7_FN, GPSR6_7,
4838 GP_6_6_FN, GPSR6_6,
4839 GP_6_5_FN, GPSR6_5,
4840 GP_6_4_FN, GPSR6_4,
4841 GP_6_3_FN, GPSR6_3,
4842 GP_6_2_FN, GPSR6_2,
4843 GP_6_1_FN, GPSR6_1,
4844 GP_6_0_FN, GPSR6_0, }
4845 },
4846 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4847 0, 0,
4848 0, 0,
4849 0, 0,
4850 0, 0,
4851 0, 0,
4852 0, 0,
4853 0, 0,
4854 0, 0,
4855 0, 0,
4856 0, 0,
4857 0, 0,
4858 0, 0,
4859 0, 0,
4860 0, 0,
4861 0, 0,
4862 0, 0,
4863 0, 0,
4864 0, 0,
4865 0, 0,
4866 0, 0,
4867 0, 0,
4868 0, 0,
4869 0, 0,
4870 0, 0,
4871 0, 0,
4872 0, 0,
4873 0, 0,
4874 0, 0,
4875 GP_7_3_FN, GPSR7_3,
4876 GP_7_2_FN, GPSR7_2,
4877 GP_7_1_FN, GPSR7_1,
4878 GP_7_0_FN, GPSR7_0, }
4879 },
4880#undef F_
4881#undef FM
4882
4883#define F_(x, y) x,
4884#define FM(x) FN_##x,
4885 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4886 IP0_31_28
4887 IP0_27_24
4888 IP0_23_20
4889 IP0_19_16
4890 IP0_15_12
4891 IP0_11_8
4892 IP0_7_4
4893 IP0_3_0 }
4894 },
4895 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4896 IP1_31_28
4897 IP1_27_24
4898 IP1_23_20
4899 IP1_19_16
4900 IP1_15_12
4901 IP1_11_8
4902 IP1_7_4
4903 IP1_3_0 }
4904 },
4905 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4906 IP2_31_28
4907 IP2_27_24
4908 IP2_23_20
4909 IP2_19_16
4910 IP2_15_12
4911 IP2_11_8
4912 IP2_7_4
4913 IP2_3_0 }
4914 },
4915 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4916 IP3_31_28
4917 IP3_27_24
4918 IP3_23_20
4919 IP3_19_16
4920 IP3_15_12
4921 IP3_11_8
4922 IP3_7_4
4923 IP3_3_0 }
4924 },
4925 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4926 IP4_31_28
4927 IP4_27_24
4928 IP4_23_20
4929 IP4_19_16
4930 IP4_15_12
4931 IP4_11_8
4932 IP4_7_4
4933 IP4_3_0 }
4934 },
4935 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4936 IP5_31_28
4937 IP5_27_24
4938 IP5_23_20
4939 IP5_19_16
4940 IP5_15_12
4941 IP5_11_8
4942 IP5_7_4
4943 IP5_3_0 }
4944 },
4945 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4946 IP6_31_28
4947 IP6_27_24
4948 IP6_23_20
4949 IP6_19_16
4950 IP6_15_12
4951 IP6_11_8
4952 IP6_7_4
4953 IP6_3_0 }
4954 },
4955 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4956 IP7_31_28
4957 IP7_27_24
4958 IP7_23_20
4959 IP7_19_16
30cd1c46 4960 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 4961 IP7_11_8
4962 IP7_7_4
4963 IP7_3_0 }
4964 },
4965 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4966 IP8_31_28
4967 IP8_27_24
4968 IP8_23_20
4969 IP8_19_16
4970 IP8_15_12
4971 IP8_11_8
4972 IP8_7_4
4973 IP8_3_0 }
4974 },
4975 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4976 IP9_31_28
4977 IP9_27_24
4978 IP9_23_20
4979 IP9_19_16
4980 IP9_15_12
4981 IP9_11_8
4982 IP9_7_4
4983 IP9_3_0 }
4984 },
4985 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4986 IP10_31_28
4987 IP10_27_24
4988 IP10_23_20
4989 IP10_19_16
4990 IP10_15_12
4991 IP10_11_8
4992 IP10_7_4
4993 IP10_3_0 }
4994 },
4995 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4996 IP11_31_28
4997 IP11_27_24
4998 IP11_23_20
4999 IP11_19_16
5000 IP11_15_12
5001 IP11_11_8
5002 IP11_7_4
5003 IP11_3_0 }
5004 },
5005 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5006 IP12_31_28
5007 IP12_27_24
5008 IP12_23_20
5009 IP12_19_16
5010 IP12_15_12
5011 IP12_11_8
5012 IP12_7_4
5013 IP12_3_0 }
5014 },
5015 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5016 IP13_31_28
5017 IP13_27_24
5018 IP13_23_20
5019 IP13_19_16
5020 IP13_15_12
5021 IP13_11_8
5022 IP13_7_4
5023 IP13_3_0 }
5024 },
5025 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5026 IP14_31_28
5027 IP14_27_24
5028 IP14_23_20
5029 IP14_19_16
5030 IP14_15_12
5031 IP14_11_8
5032 IP14_7_4
5033 IP14_3_0 }
5034 },
5035 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5036 IP15_31_28
5037 IP15_27_24
5038 IP15_23_20
5039 IP15_19_16
5040 IP15_15_12
5041 IP15_11_8
5042 IP15_7_4
5043 IP15_3_0 }
5044 },
5045 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5046 IP16_31_28
5047 IP16_27_24
5048 IP16_23_20
5049 IP16_19_16
5050 IP16_15_12
5051 IP16_11_8
5052 IP16_7_4
5053 IP16_3_0 }
5054 },
5055 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 5056 IP17_31_28
5057 IP17_27_24
5058 IP17_23_20
5059 IP17_19_16
5060 IP17_15_12
5061 IP17_11_8
0b0ffc96
TK		 5062 IP17_7_4
5063 IP17_3_0 }
5064 },
b205914c
GU		 5065 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5066 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5067 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5068 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5069 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5070 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5071 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5072 IP18_7_4
5073 IP18_3_0 }
5074 },
0b0ffc96
TK		 5075#undef F_
5076#undef FM
5077
5078#define F_(x, y) x,
5079#define FM(x) FN_##x,
5080 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 5081 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5082 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5083 MOD_SEL0_31_30_29
0b0ffc96
TK		 5084 MOD_SEL0_28_27
5085 MOD_SEL0_26_25_24
5086 MOD_SEL0_23
5087 MOD_SEL0_22
b205914c
GU		 5088 MOD_SEL0_21
5089 MOD_SEL0_20
0b0ffc96 5090 MOD_SEL0_19
b205914c
GU		 5091 MOD_SEL0_18_17
5092 MOD_SEL0_16
5093 0, 0, /* RESERVED 15 */
5094 MOD_SEL0_14_13
0b0ffc96
TK		 5095 MOD_SEL0_12
5096 MOD_SEL0_11
5097 MOD_SEL0_10
b205914c 5098 MOD_SEL0_9_8
0b0ffc96 5099 MOD_SEL0_7_6
b205914c
GU		 5100 MOD_SEL0_5
5101 MOD_SEL0_4_3
5102 /* RESERVED 2, 1, 0 */
5103 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 5104 },
5105 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5106 2, 3, 1, 2, 3, 1, 1, 2, 1,
5107 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5108 MOD_SEL1_31_30
5109 MOD_SEL1_29_28_27
5110 MOD_SEL1_26
5111 MOD_SEL1_25_24
5112 MOD_SEL1_23_22_21
5113 MOD_SEL1_20
5114 MOD_SEL1_19
5115 MOD_SEL1_18_17
5116 MOD_SEL1_16
5117 MOD_SEL1_15_14
5118 MOD_SEL1_13
5119 MOD_SEL1_12
5120 MOD_SEL1_11
5121 MOD_SEL1_10
5122 MOD_SEL1_9
5123 0, 0, 0, 0, /* RESERVED 8, 7 */
5124 MOD_SEL1_6
5125 MOD_SEL1_5
5126 MOD_SEL1_4
5127 MOD_SEL1_3
5128 MOD_SEL1_2
5129 MOD_SEL1_1
5130 MOD_SEL1_0 }
5131 },
5132 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 5133 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5134 4, 4, 4, 3, 1) {
0b0ffc96
TK		 5135 MOD_SEL2_31
5136 MOD_SEL2_30
5137 MOD_SEL2_29
b205914c
GU		 5138 MOD_SEL2_28_27
5139 MOD_SEL2_26
5140 MOD_SEL2_25_24_23
3c612d2c
TK		 5141 /* RESERVED 22 */
5142 0, 0,
b205914c
GU		 5143 MOD_SEL2_21
5144 MOD_SEL2_20
5145 MOD_SEL2_19
5146 MOD_SEL2_18
5147 MOD_SEL2_17
5148 /* RESERVED 16 */
0b0ffc96 5149 0, 0,
0b0ffc96
TK		 5150 /* RESERVED 15, 14, 13, 12 */
5151 0, 0, 0, 0, 0, 0, 0, 0,
5152 0, 0, 0, 0, 0, 0, 0, 0,
5153 /* RESERVED 11, 10, 9, 8 */
5154 0, 0, 0, 0, 0, 0, 0, 0,
5155 0, 0, 0, 0, 0, 0, 0, 0,
5156 /* RESERVED 7, 6, 5, 4 */
5157 0, 0, 0, 0, 0, 0, 0, 0,
5158 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 5159 /* RESERVED 3, 2, 1 */
5160 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 5161 MOD_SEL2_0 }
5162 },
5163 { },
5164};
5165
92e6d9a2 5166static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 5167 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5168 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5169 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5170 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5171 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5172 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5173 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5174 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5175 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5176 } },
5177 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5178 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5179 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5180 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5181 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5182 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5183 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5184 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5185 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5186 } },
5187 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5188 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5189 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5190 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5191 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5192 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5193 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5194 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5195 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5196 } },
92e6d9a2 5197 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 5198 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5199 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5200 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5201 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5202 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5203 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5204 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5205 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 5206 } },
5207 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5208 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5209 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5210 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5211 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5212 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5213 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5214 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5215 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5216 } },
5217 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5218 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5219 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5220 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5221 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5222 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5223 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5224 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5225 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5226 } },
5227 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5228 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5229 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5230 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5231 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5232 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5233 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5234 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5235 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5236 } },
5237 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5238 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5239 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5240 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5241 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5242 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5243 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5244 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5245 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5246 } },
5247 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
ea9c7405 5248 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 5249 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5250 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5251 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5252 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5253 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5254 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5255 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5256 } },
5257 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5258 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 5259 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 5260 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5261 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5262 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5263 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5264 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5265 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5266 } },
5267 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5268 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5269 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5270 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5271 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5272 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5273 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5274 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5275 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5276 } },
5277 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 5278 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5279 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5280 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5281 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5282 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5283 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5284 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5285 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5286 } },
5287 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5288 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5289 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5290 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5291 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 5292 } },
5293 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 5294 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5295 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5296 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5297 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5298 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5299 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5300 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5301 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 5302 } },
5303 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5304 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5305 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5306 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5307 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5308 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5309 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5310 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5311 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5312 } },
5313 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5314 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5315 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5316 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5317 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5318 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5319 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5320 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5321 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5322 } },
5323 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5324 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5325 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5326 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5327 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5328 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5329 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5330 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5331 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5332 } },
5333 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5334 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5335 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5336 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5337 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5338 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5339 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5340 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5341 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5342 } },
5343 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
5344 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
5345 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5346 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5347 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
5348 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
5349 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5350 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5351 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5352 } },
5353 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5354 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5355 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5356 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5357 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5358 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5359 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5360 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5361 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5362 } },
5363 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5364 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5365 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5366 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5367 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5368 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5369 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 5370 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 5371 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5372 } },
5373 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5374 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5375 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5376 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5377 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 5378 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5379 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 5380 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5381 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5382 } },
5383 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5384 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5385 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5386 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5387 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5388 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5389 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5390 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5391 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5392 } },
5393 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5394 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5395 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5396 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5397 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5398 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5399 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5400 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5401 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5402 } },
5403 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5404 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5405 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5406 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5407 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5408 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
f9d13080
YS		 5409 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5410 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
92e6d9a2
LP		 5411 } },
5412 { },
5413};
5414
e9eace32
WS		 5415static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5416{
5417 int bit = -EINVAL;
5418
5419 *pocctrl = 0xe6060380;
5420
5421 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5422 bit = pin & 0x1f;
5423
5424 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5425 bit = (pin & 0x1f) + 12;
5426
5427 return bit;
5428}
5429
56065524
UH		 5430#define PUEN 0xe6060400
5431#define PUD 0xe6060440
5432
5433#define PU0 0x00
5434#define PU1 0x04
5435#define PU2 0x08
5436#define PU3 0x0c
5437#define PU4 0x10
5438#define PU5 0x14
5439#define PU6 0x18
5440
d3b861bc 5441static const struct sh_pfc_bias_info bias_info[] = {
4c2fb44d
NS		 5442 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
5443 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
5444 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
5445 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
5446 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
5447 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
5448 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
5449 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
5450 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
5451 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
5452 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
5453 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
5454 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
5455 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
5456 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
5457 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
5458 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
5459 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
5460 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
5461 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
5462 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
5463 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
5464 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
5465 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
5466 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
5467 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
5468 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
5469 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
5470 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
5471 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
5472 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
5473 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
5474
5475 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
5476 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
5477 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
5478 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
5479 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
5480 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
5481 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
5482 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
5483 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
5484 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
5485 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
5486 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
5487 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
5488 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
5489 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
5490 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
5491 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
5492 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
5493 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
5494 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
5495 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
5496 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
5497 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
5498 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
5499 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
5500 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
5501 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
5502 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
5503 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
5504 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
5505 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
5506 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
5507
5508 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
5509 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
5510 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
5511 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
5512 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
5513 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
5514 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
5515 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
5516 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
5517 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
5518 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
5519 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
5520 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
5521 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
5522 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
5523 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
5524 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
5525 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
5526 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
5527 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
5528 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
5529 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
5530 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
5531 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
5532 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
5533 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
5534 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
5535 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
5536 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
fc8fd9be 5537 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N */
4c2fb44d
NS		 5538 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
5539 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
5540
5541 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
5542 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
5543 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
5544 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
5545 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
5546 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
5547 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
5548 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
5549 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
5550 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
5551 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
5552 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
5553 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
5554 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
5555 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
5556 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
5557 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
5558 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
5559 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
5560 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
5561 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
5562 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
5563 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
5564 /* bit 8 n/a */
5565 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
5566 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
5567 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
5568 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
5569 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
5570 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
5571 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
5572 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
5573
5574 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
5575 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
5576 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
5577 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
5578 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
5579 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
5580 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
5581 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
5582 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
5583 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
5584 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
5585 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
5586 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
5587 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
5588 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
5589 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
5590 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
5591 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
5592 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
5593 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
5594 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
5595 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
5596 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
5597 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
5598 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
5599 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5600 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5601 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5602 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5603 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5604 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5605 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5606
5607 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5608 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5609 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5610 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5611 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5612 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5613 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5614 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5615 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5616 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5617 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5618 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5619 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5620 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5621 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5622 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5623 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5624 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
68e63892
KM		 5625 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
5626 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4c2fb44d
NS		 5627 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5628 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5629 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5630 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5631 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5632 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
5633 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5634 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5635 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5636 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5637 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5638 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5639
f9d13080
YS		 5640 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB2_CH3_OVC */
5641 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB2_CH3_PWEN */
4c2fb44d
NS		 5642 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5643 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5644 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5645 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5646 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
56065524
UH		 5647};
5648
5649static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
5650 unsigned int pin)
5651{
d3b861bc 5652 const struct sh_pfc_bias_info *info;
56065524
UH		 5653 u32 reg;
5654 u32 bit;
5655
d3b861bc
NS		 5656 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5657 if (!info)
56065524
UH		 5658 return PIN_CONFIG_BIAS_DISABLE;
5659
d3b861bc
NS		 5660 reg = info->reg;
5661 bit = BIT(info->bit);
56065524 5662
42831cf9 5663 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
56065524 5664 return PIN_CONFIG_BIAS_DISABLE;
42831cf9
NS		 5665 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5666 return PIN_CONFIG_BIAS_PULL_UP;
5667 else
5668 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 5669}
5670
5671static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5672 unsigned int bias)
5673{
d3b861bc 5674 const struct sh_pfc_bias_info *info;
56065524
UH		 5675 u32 enable, updown;
5676 u32 reg;
5677 u32 bit;
5678
d3b861bc
NS		 5679 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5680 if (!info)
56065524
UH		 5681 return;
5682
d3b861bc
NS		 5683 reg = info->reg;
5684 bit = BIT(info->bit);
56065524
UH		 5685
5686 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5687 if (bias != PIN_CONFIG_BIAS_DISABLE)
5688 enable |= bit;
5689
5690 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5691 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5692 updown |= bit;
5693
5694 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5695 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5696}
5697
b205914c
GU		 5698static const struct soc_device_attribute r8a7795es1[] = {
5699 { .soc_id = "r8a7795", .revision = "ES1.*" },
5700 { /* sentinel */ }
5701};
5702
5703static int r8a7795_pinmux_init(struct sh_pfc *pfc)
5704{
5705 if (soc_device_match(r8a7795es1))
5706 pfc->info = &r8a7795es1_pinmux_info;
5707
5708 return 0;
5709}
5710
e9eace32 5711static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 5712 .init = r8a7795_pinmux_init,
e9eace32 5713 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 5714 .get_bias = r8a7795_pinmux_get_bias,
5715 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 5716};
5717
0b0ffc96 5718const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 5719 .name = "r8a77951_pfc",
e9eace32 5720 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 5721 .unlock_reg = 0xe6060000, /* PMMR */
5722
5723 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5724
5725 .pins = pinmux_pins,
5726 .nr_pins = ARRAY_SIZE(pinmux_pins),
5727 .groups = pinmux_groups,
5728 .nr_groups = ARRAY_SIZE(pinmux_groups),
5729 .functions = pinmux_functions,
5730 .nr_functions = ARRAY_SIZE(pinmux_functions),
5731
5732 .cfg_regs = pinmux_config_regs,
92e6d9a2 5733 .drive_regs = pinmux_drive_regs,
0b0ffc96 5734
b8b47d67
GU		 5735 .pinmux_data = pinmux_data,
5736 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 5737};
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