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pinctrl: sh-pfc: Convert to devm_gpiochip_add_data()
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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TK		 1/*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
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TK		 12
13#include "core.h"
14#include "sh_pfc.h"
15
0b0ffc96 16#define CPU_ALL_PORT(fn, sfx) \
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LP		 17 PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
18 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
19 PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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WS		 20 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
25 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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LP		 26 PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
27 PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
28 PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
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TK		 29/*
30 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK
32 */
33
34/* GPSR0 */
35#define GPSR0_15 F_(D15, IP7_11_8)
36#define GPSR0_14 F_(D14, IP7_7_4)
37#define GPSR0_13 F_(D13, IP7_3_0)
38#define GPSR0_12 F_(D12, IP6_31_28)
39#define GPSR0_11 F_(D11, IP6_27_24)
40#define GPSR0_10 F_(D10, IP6_23_20)
41#define GPSR0_9 F_(D9, IP6_19_16)
42#define GPSR0_8 F_(D8, IP6_15_12)
43#define GPSR0_7 F_(D7, IP6_11_8)
44#define GPSR0_6 F_(D6, IP6_7_4)
45#define GPSR0_5 F_(D5, IP6_3_0)
46#define GPSR0_4 F_(D4, IP5_31_28)
47#define GPSR0_3 F_(D3, IP5_27_24)
48#define GPSR0_2 F_(D2, IP5_23_20)
49#define GPSR0_1 F_(D1, IP5_19_16)
50#define GPSR0_0 F_(D0, IP5_15_12)
51
52/* GPSR1 */
53#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
54#define GPSR1_26 F_(WE1_N, IP5_7_4)
55#define GPSR1_25 F_(WE0_N, IP5_3_0)
56#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
57#define GPSR1_23 F_(RD_N, IP4_27_24)
58#define GPSR1_22 F_(BS_N, IP4_23_20)
59#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
60#define GPSR1_20 F_(CS0_N, IP4_15_12)
61#define GPSR1_19 F_(A19, IP4_11_8)
62#define GPSR1_18 F_(A18, IP4_7_4)
63#define GPSR1_17 F_(A17, IP4_3_0)
64#define GPSR1_16 F_(A16, IP3_31_28)
65#define GPSR1_15 F_(A15, IP3_27_24)
66#define GPSR1_14 F_(A14, IP3_23_20)
67#define GPSR1_13 F_(A13, IP3_19_16)
68#define GPSR1_12 F_(A12, IP3_15_12)
69#define GPSR1_11 F_(A11, IP3_11_8)
70#define GPSR1_10 F_(A10, IP3_7_4)
71#define GPSR1_9 F_(A9, IP3_3_0)
72#define GPSR1_8 F_(A8, IP2_31_28)
73#define GPSR1_7 F_(A7, IP2_27_24)
74#define GPSR1_6 F_(A6, IP2_23_20)
75#define GPSR1_5 F_(A5, IP2_19_16)
76#define GPSR1_4 F_(A4, IP2_15_12)
77#define GPSR1_3 F_(A3, IP2_11_8)
78#define GPSR1_2 F_(A2, IP2_7_4)
79#define GPSR1_1 F_(A1, IP2_3_0)
80#define GPSR1_0 F_(A0, IP1_31_28)
81
82/* GPSR2 */
83#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
84#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
85#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
86#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
87#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
88#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
89#define GPSR2_8 F_(PWM2_A, IP1_27_24)
90#define GPSR2_7 F_(PWM1_A, IP1_23_20)
91#define GPSR2_6 F_(PWM0, IP1_19_16)
92#define GPSR2_5 F_(IRQ5, IP1_15_12)
93#define GPSR2_4 F_(IRQ4, IP1_11_8)
94#define GPSR2_3 F_(IRQ3, IP1_7_4)
95#define GPSR2_2 F_(IRQ2, IP1_3_0)
96#define GPSR2_1 F_(IRQ1, IP0_31_28)
97#define GPSR2_0 F_(IRQ0, IP0_27_24)
98
99/* GPSR3 */
100#define GPSR3_15 F_(SD1_WP, IP10_23_20)
101#define GPSR3_14 F_(SD1_CD, IP10_19_16)
102#define GPSR3_13 F_(SD0_WP, IP10_15_12)
103#define GPSR3_12 F_(SD0_CD, IP10_11_8)
104#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
105#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
106#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
107#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
108#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
109#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
110#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
111#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
112#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
113#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
114#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
115#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
116
117/* GPSR4 */
118#define GPSR4_17 FM(SD3_DS)
119#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
120#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
121#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
122#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
123#define GPSR4_12 FM(SD3_DAT3)
124#define GPSR4_11 FM(SD3_DAT2)
125#define GPSR4_10 FM(SD3_DAT1)
126#define GPSR4_9 FM(SD3_DAT0)
127#define GPSR4_8 FM(SD3_CMD)
128#define GPSR4_7 FM(SD3_CLK)
129#define GPSR4_6 F_(SD2_DS, IP9_23_20)
130#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
131#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
132#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
133#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
134#define GPSR4_1 FM(SD2_CMD)
135#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
136
137/* GPSR5 */
138#define GPSR5_25 F_(MLB_DAT, IP13_19_16)
139#define GPSR5_24 F_(MLB_SIG, IP13_15_12)
140#define GPSR5_23 F_(MLB_CLK, IP13_11_8)
141#define GPSR5_22 FM(MSIOF0_RXD)
142#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
143#define GPSR5_20 FM(MSIOF0_TXD)
144#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
145#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
146#define GPSR5_17 FM(MSIOF0_SCK)
147#define GPSR5_16 F_(HRTS0_N, IP12_27_24)
148#define GPSR5_15 F_(HCTS0_N, IP12_23_20)
149#define GPSR5_14 F_(HTX0, IP12_19_16)
150#define GPSR5_13 F_(HRX0, IP12_15_12)
151#define GPSR5_12 F_(HSCK0, IP12_11_8)
152#define GPSR5_11 F_(RX2_A, IP12_7_4)
153#define GPSR5_10 F_(TX2_A, IP12_3_0)
154#define GPSR5_9 F_(SCK2, IP11_31_28)
155#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
156#define GPSR5_7 F_(CTS1_N, IP11_23_20)
157#define GPSR5_6 F_(TX1_A, IP11_19_16)
158#define GPSR5_5 F_(RX1_A, IP11_15_12)
159#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
160#define GPSR5_3 F_(CTS0_N, IP11_7_4)
161#define GPSR5_2 F_(TX0, IP11_3_0)
162#define GPSR5_1 F_(RX0, IP10_31_28)
163#define GPSR5_0 F_(SCK0, IP10_27_24)
164
165/* GPSR6 */
166#define GPSR6_31 F_(USB31_OVC, IP17_7_4)
167#define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
168#define GPSR6_29 F_(USB30_OVC, IP16_31_28)
169#define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
170#define GPSR6_27 F_(USB1_OVC, IP16_23_20)
171#define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
172#define GPSR6_25 F_(USB0_OVC, IP16_15_12)
173#define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
174#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
175#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
176#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
177#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
178#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
179#define GPSR6_18 F_(SSI_WS78, IP15_19_16)
180#define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
181#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
182#define GPSR6_15 F_(SSI_WS6, IP15_7_4)
183#define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
184#define GPSR6_13 FM(SSI_SDATA5)
185#define GPSR6_12 FM(SSI_WS5)
186#define GPSR6_11 FM(SSI_SCK5)
187#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
188#define GPSR6_9 F_(SSI_WS4, IP14_27_24)
189#define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
190#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
191#define GPSR6_6 F_(SSI_WS34, IP14_15_12)
192#define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
193#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
194#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
195#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
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GU		 196#define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
197#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
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TK		 198
199/* GPSR7 */
200#define GPSR7_3 FM(HDMI1_CEC)
201#define GPSR7_2 FM(HDMI0_CEC)
202#define GPSR7_1 FM(AVS2)
203#define GPSR7_0 FM(AVS1)
204
205
206/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
207#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226
227/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
228#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270
271/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
272#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
315/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
316#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
00edf542
GU		 322#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 324#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351
352#define PINMUX_GPSR \
353\
354 GPSR6_31 \
355 GPSR6_30 \
356 GPSR6_29 \
357 GPSR6_28 \
358 GPSR1_27 GPSR6_27 \
359 GPSR1_26 GPSR6_26 \
360 GPSR1_25 GPSR5_25 GPSR6_25 \
361 GPSR1_24 GPSR5_24 GPSR6_24 \
362 GPSR1_23 GPSR5_23 GPSR6_23 \
363 GPSR1_22 GPSR5_22 GPSR6_22 \
364 GPSR1_21 GPSR5_21 GPSR6_21 \
365 GPSR1_20 GPSR5_20 GPSR6_20 \
366 GPSR1_19 GPSR5_19 GPSR6_19 \
367 GPSR1_18 GPSR5_18 GPSR6_18 \
368 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
369 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
370GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
371GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
372GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
373GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
374GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
375GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
376GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
377GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
378GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
379GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
380GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
381GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
382GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
383GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
384GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
385GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
386
387#define PINMUX_IPSR \
388\
389FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
390FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
391FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
392FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
393FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
394FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
395FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
396FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
397\
398FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
399FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
400FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
401FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
402FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
403FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
404FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
405FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
406\
407FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
408FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
409FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
410FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
411FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
412FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
413FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
414FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
415\
416FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
417FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
418FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
419FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
420FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
421FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
422FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
423FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
424\
425FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
426FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
427FM(IP16_11_8) IP16_11_8 \
428FM(IP16_15_12) IP16_15_12 \
429FM(IP16_19_16) IP16_19_16 \
430FM(IP16_23_20) IP16_23_20 \
431FM(IP16_27_24) IP16_27_24 \
432FM(IP16_31_28) IP16_31_28
433
434/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
435#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
436#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
437#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
438#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
439#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
440#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
441#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
442#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
443#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
444#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
445#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
446#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
447#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
448#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
449#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
450#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
451#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
452#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
453#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
454#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
455#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
456
457/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
458#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
459#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
460#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
461#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
462#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
463#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
464#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
465#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
466#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
467#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
468#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
469#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
470#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
fd1aa743 471#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
0b0ffc96
TK		 472#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
473#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
474#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
475#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
476#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
477#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
478#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
479#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
480
481/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
482#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
483#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
484#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
0b0ffc96
TK		 485#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
486
487#define PINMUX_MOD_SELS\
488\
489 MOD_SEL1_31_30 MOD_SEL2_31 \
490MOD_SEL0_30_29 MOD_SEL2_30 \
491 MOD_SEL1_29_28_27 MOD_SEL2_29 \
492MOD_SEL0_28_27 \
493\
494MOD_SEL0_26_25_24 MOD_SEL1_26 \
495 MOD_SEL1_25_24 \
496\
497MOD_SEL0_23 MOD_SEL1_23_22_21 \
498MOD_SEL0_22 \
499MOD_SEL0_21_20 \
500 MOD_SEL1_20 \
501MOD_SEL0_19 MOD_SEL1_19 \
502MOD_SEL0_18 MOD_SEL1_18_17 \
503MOD_SEL0_17 \
504MOD_SEL0_16_15 MOD_SEL1_16 \
505 MOD_SEL1_15_14 \
506MOD_SEL0_14 \
507MOD_SEL0_13 MOD_SEL1_13 \
508MOD_SEL0_12 MOD_SEL1_12 \
509MOD_SEL0_11 MOD_SEL1_11 \
510MOD_SEL0_10 MOD_SEL1_10 \
511MOD_SEL0_9 MOD_SEL1_9 \
512MOD_SEL0_8 \
513MOD_SEL0_7_6 \
514 MOD_SEL1_6 \
515MOD_SEL0_5_4 MOD_SEL1_5 \
516 MOD_SEL1_4 \
517MOD_SEL0_3 MOD_SEL1_3 \
a5d2dade 518MOD_SEL0_2_1 MOD_SEL1_2 \
0b0ffc96
TK		 519 MOD_SEL1_1 \
520 MOD_SEL1_0 MOD_SEL2_0
521
522
523enum {
524 PINMUX_RESERVED = 0,
525
526 PINMUX_DATA_BEGIN,
527 GP_ALL(DATA),
528 PINMUX_DATA_END,
529
530#define F_(x, y)
531#define FM(x) FN_##x,
532 PINMUX_FUNCTION_BEGIN,
533 GP_ALL(FN),
534 PINMUX_GPSR
535 PINMUX_IPSR
536 PINMUX_MOD_SELS
537 PINMUX_FUNCTION_END,
538#undef F_
539#undef FM
540
541#define F_(x, y)
542#define FM(x) x##_MARK,
543 PINMUX_MARK_BEGIN,
544 PINMUX_GPSR
545 PINMUX_IPSR
546 PINMUX_MOD_SELS
547 PINMUX_MARK_END,
548#undef F_
549#undef FM
550};
551
552static const u16 pinmux_data[] = {
553 PINMUX_DATA_GP_ALL(),
554
8d4df573
GU		 555 PINMUX_SINGLE(AVS1),
556 PINMUX_SINGLE(AVS2),
557 PINMUX_SINGLE(HDMI0_CEC),
558 PINMUX_SINGLE(HDMI1_CEC),
559 PINMUX_SINGLE(MSIOF0_RXD),
560 PINMUX_SINGLE(MSIOF0_SCK),
561 PINMUX_SINGLE(MSIOF0_TXD),
562 PINMUX_SINGLE(SD2_CMD),
563 PINMUX_SINGLE(SD3_CLK),
564 PINMUX_SINGLE(SD3_CMD),
565 PINMUX_SINGLE(SD3_DAT0),
566 PINMUX_SINGLE(SD3_DAT1),
567 PINMUX_SINGLE(SD3_DAT2),
568 PINMUX_SINGLE(SD3_DAT3),
569 PINMUX_SINGLE(SD3_DS),
570 PINMUX_SINGLE(SSI_SCK5),
571 PINMUX_SINGLE(SSI_SDATA5),
572 PINMUX_SINGLE(SSI_WS5),
573
0b0ffc96 574 /* IPSR0 */
e01678e3 575 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 576 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
577
e01678e3 578 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 579 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
580 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
581
e01678e3 582 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 583 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
584 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
585
e01678e3 586 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 587 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
588 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
589
590 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
591 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
592 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
593
594 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
595 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
596 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
597
e01678e3
GU		 598 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
599 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
600 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 601 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
602 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
603 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
604
e01678e3
GU		 605 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
606 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
607 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 608 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
609 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
610 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
611
612 /* IPSR1 */
e01678e3
GU		 613 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
614 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
615 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 616 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
617 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
618
e01678e3
GU		 619 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
620 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
621 PINMUX_IPSR_GPSR(IP1_7_4, A25),
622 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 623 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
624 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
625
e01678e3
GU		 626 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
627 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
628 PINMUX_IPSR_GPSR(IP1_11_8, A24),
629 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 630 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
631 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
632
e01678e3
GU		 633 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
634 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
635 PINMUX_IPSR_GPSR(IP1_15_12, A23),
636 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 637 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
638 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
639
e01678e3
GU		 640 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
641 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
642 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 643 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
644 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
645
646 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 647 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 648 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
649 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
651
652 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 653 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 654 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
655 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
656
e01678e3
GU		 657 PINMUX_IPSR_GPSR(IP1_31_28, A0),
658 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 659 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 660 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
661 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 662 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
663
664 /* IPSR2 */
e01678e3
GU		 665 PINMUX_IPSR_GPSR(IP2_3_0, A1),
666 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 667 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 668 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
669 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 670 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
671
e01678e3
GU		 672 PINMUX_IPSR_GPSR(IP2_7_4, A2),
673 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 674 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 675 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
676 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 677 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
678
e01678e3
GU		 679 PINMUX_IPSR_GPSR(IP2_11_8, A3),
680 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 681 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 682 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
683 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 684 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
685
e01678e3
GU		 686 PINMUX_IPSR_GPSR(IP2_15_12, A4),
687 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 688 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 689 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
690 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
691 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 692
e01678e3
GU		 693 PINMUX_IPSR_GPSR(IP2_19_16, A5),
694 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 695 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
696 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 697 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
698 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
699 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 700
e01678e3
GU		 701 PINMUX_IPSR_GPSR(IP2_23_20, A6),
702 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 703 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
704 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 705 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
706 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
707 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 708
e01678e3
GU		 709 PINMUX_IPSR_GPSR(IP2_27_24, A7),
710 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 711 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
712 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 713 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
714 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
715 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 716
e01678e3 717 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 718 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
719 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
720 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
721 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
722 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
723 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
724
725 /* IPSR3 */
e01678e3 726 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 727 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
728 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 729 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 730
e01678e3 731 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 732 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
733 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 734 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 735
e01678e3 736 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 737 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
738 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
739 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 740 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
741 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 742 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
743 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
744 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
745
e01678e3
GU		 746 PINMUX_IPSR_GPSR(IP3_15_12, A12),
747 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 748 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
749 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 750 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
751 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 752
e01678e3
GU		 753 PINMUX_IPSR_GPSR(IP3_19_16, A13),
754 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 755 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
756 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 757 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
758 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 759
e01678e3
GU		 760 PINMUX_IPSR_GPSR(IP3_23_20, A14),
761 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 762 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 763 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
764 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
765 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 766
e01678e3
GU		 767 PINMUX_IPSR_GPSR(IP3_27_24, A15),
768 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 769 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 770 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
771 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
772 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 773
e01678e3
GU		 774 PINMUX_IPSR_GPSR(IP3_31_28, A16),
775 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
776 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
777 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 778
779 /* IPSR4 */
e01678e3
GU		 780 PINMUX_IPSR_GPSR(IP4_3_0, A17),
781 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
782 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
783 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
784
785 PINMUX_IPSR_GPSR(IP4_7_4, A18),
786 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
787 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
788 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
789
790 PINMUX_IPSR_GPSR(IP4_11_8, A19),
791 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
792 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
793 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
794
795 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
796 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
797
798 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
799 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 800 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
801
e01678e3
GU		 802 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
803 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 804 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
806 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
807 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
808 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 809 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
810
e01678e3 811 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 812 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
813 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
814 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
815 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
816 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
817
e01678e3 818 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 819 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
820 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
821 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
822 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
823 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
824
825 /* IPSR5 */
e01678e3 826 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 827 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 828 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
829 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 830 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 831 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 832 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
833
e01678e3 834 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 835 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 836 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
837 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 838 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 839 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
840 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 841 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
842
843 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 844 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
845 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
846 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 847
e01678e3 848 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 849 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
850 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 851 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
852 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 853
e01678e3 854 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 855 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
856 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 857 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
858 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 859
e01678e3 860 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 861 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 862 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
863 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 864
e01678e3 865 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 866 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 867 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
868 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 869
e01678e3 870 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 871 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 872 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
873 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 874
875 /* IPSR6 */
e01678e3 876 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 877 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 878 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
879 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 880
e01678e3 881 PINMUX_IPSR_GPSR(IP6_7_4, D6),
0b0ffc96 882 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
e01678e3
GU		 883 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
884 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
0b0ffc96 885
e01678e3 886 PINMUX_IPSR_GPSR(IP6_11_8, D7),
0b0ffc96 887 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
e01678e3
GU		 888 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
889 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
0b0ffc96 890
e01678e3
GU		 891 PINMUX_IPSR_GPSR(IP6_15_12, D8),
892 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
0b0ffc96
TK		 893 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
894 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
895 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
e01678e3 896 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
0b0ffc96 897
e01678e3
GU		 898 PINMUX_IPSR_GPSR(IP6_19_16, D9),
899 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
0b0ffc96
TK		 900 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
901 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
e01678e3 902 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
0b0ffc96 903
e01678e3
GU		 904 PINMUX_IPSR_GPSR(IP6_23_20, D10),
905 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
0b0ffc96
TK		 906 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
907 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
908 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
909 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
e01678e3 910 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
0b0ffc96 911
e01678e3
GU		 912 PINMUX_IPSR_GPSR(IP6_27_24, D11),
913 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
0b0ffc96
TK		 914 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
915 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
916 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
917 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
e01678e3 918 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
0b0ffc96 919
e01678e3
GU		 920 PINMUX_IPSR_GPSR(IP6_31_28, D12),
921 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
0b0ffc96
TK		 922 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
923 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
924 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
e01678e3 925 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
0b0ffc96
TK		 926
927 /* IPSR7 */
e01678e3
GU		 928 PINMUX_IPSR_GPSR(IP7_3_0, D13),
929 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
0b0ffc96
TK		 930 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
931 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
932 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
e01678e3 933 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
0b0ffc96 934
e01678e3
GU		 935 PINMUX_IPSR_GPSR(IP7_7_4, D14),
936 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
0b0ffc96
TK		 937 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
938 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
939 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
e01678e3 940 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
0b0ffc96
TK		 941 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
942
e01678e3
GU		 943 PINMUX_IPSR_GPSR(IP7_11_8, D15),
944 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
0b0ffc96
TK		 945 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
946 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
947 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
e01678e3 948 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
0b0ffc96
TK		 949 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
950
e01678e3 951 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
0b0ffc96 952
e01678e3 953 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
0b0ffc96
TK		 954 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
955 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
956
e01678e3 957 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
0b0ffc96
TK		 958 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
959 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
960
e01678e3 961 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
0b0ffc96
TK		 962 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
963 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
964 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
965
e01678e3 966 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
0b0ffc96
TK		 967 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
968 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
969 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
970
971 /* IPSR8 */
e01678e3 972 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
0b0ffc96
TK		 973 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
974 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
975 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
976
e01678e3 977 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
0b0ffc96
TK		 978 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
979 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
980 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
981
e01678e3 982 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
0b0ffc96
TK		 983 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
984 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
985
e01678e3 986 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
0b0ffc96
TK		 987 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
988 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
989 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
990
e01678e3
GU		 991 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
992 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
0b0ffc96
TK		 993 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
994 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
995 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
996
e01678e3
GU		 997 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
998 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
0b0ffc96
TK		 999 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1000 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1001 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1002
e01678e3
GU		 1003 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1004 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
0b0ffc96
TK		 1005 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1006 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1007 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1008
e01678e3
GU		 1009 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1010 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
0b0ffc96
TK		 1011 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1012 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1013 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1014
1015 /* IPSR9 */
e01678e3 1016 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
0b0ffc96 1017
e01678e3 1018 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
0b0ffc96 1019
e01678e3 1020 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
0b0ffc96 1021
e01678e3 1022 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
0b0ffc96 1023
e01678e3 1024 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
0b0ffc96 1025
e01678e3 1026 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
fd1aa743 1027 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
0b0ffc96 1028
e01678e3 1029 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
0b0ffc96
TK		 1030 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1031
e01678e3 1032 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
0b0ffc96
TK		 1033 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1034
1035 /* IPSR10 */
e01678e3
GU		 1036 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1037 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
0b0ffc96 1038
e01678e3
GU		 1039 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1040 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
0b0ffc96 1041
e01678e3 1042 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
0b0ffc96
TK		 1043 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1044 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1045
e01678e3 1046 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
0b0ffc96
TK		 1047 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1048
e01678e3 1049 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
0b0ffc96
TK		 1050 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1051
e01678e3 1052 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
0b0ffc96
TK		 1053 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1054
e01678e3 1055 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
0b0ffc96
TK		 1056 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1057 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1058 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1059 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1060 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1061 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1062 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
e01678e3 1063 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
0b0ffc96 1064
e01678e3 1065 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
0b0ffc96
TK		 1066 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1067 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1068 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1069 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1070
1071 /* IPSR11 */
e01678e3 1072 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
0b0ffc96
TK		 1073 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1074 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1075 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1076 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1077
e01678e3 1078 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
0b0ffc96
TK		 1079 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1080 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1081 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1082 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1083 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1084 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
e01678e3 1085 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
0b0ffc96 1086
e01678e3 1087 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
0b0ffc96
TK		 1088 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1089 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1090 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1091 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1092 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1093 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
e01678e3 1094 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
0b0ffc96
TK		 1095
1096 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1097 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1098 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1099 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1100 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1101
1102 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1103 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1104 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1105 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1106 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1107
e01678e3 1108 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
0b0ffc96
TK		 1109 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1110 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1111 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1112 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1113 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
e01678e3 1114 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
0b0ffc96 1115
e01678e3 1116 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
0b0ffc96
TK		 1117 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1118 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1119 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1120 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1121 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
e01678e3 1122 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
0b0ffc96 1123
e01678e3 1124 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
0b0ffc96
TK		 1125 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1126 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1127 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1128 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1129 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
e01678e3 1130 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
0b0ffc96
TK		 1131
1132 /* IPSR12 */
1133 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1134 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1135 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1136 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1137 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1138 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1139
1140 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1141 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1142 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1143 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1144 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1145 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1146
e01678e3 1147 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
0b0ffc96
TK		 1148 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1149 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1150 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1151 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1152 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1153 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1154
e01678e3 1155 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
0b0ffc96
TK		 1156 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1157 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1158 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1159 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1160 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1161
e01678e3 1162 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
0b0ffc96
TK		 1163 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1164 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1165 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1166 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1167 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1168
e01678e3 1169 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
0b0ffc96
TK		 1170 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1171 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1172 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1173 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1174 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1175 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1176 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1177
e01678e3 1178 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
0b0ffc96
TK		 1179 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1180 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1181 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1182 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1183 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1184 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1185
e01678e3 1186 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
0b0ffc96
TK		 1187 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1188
1189 /* IPSR13 */
e01678e3
GU		 1190 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1191 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
0b0ffc96
TK		 1192 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1193 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1194 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1195 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1196 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1197
e01678e3
GU		 1198 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1199 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
0b0ffc96
TK		 1200 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1201 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1202 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1203 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1204 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1205 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1206
e01678e3 1207 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
0b0ffc96
TK		 1208 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1209 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1210
e01678e3 1211 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
0b0ffc96
TK		 1212 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1213 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1214 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1215
e01678e3 1216 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
0b0ffc96
TK		 1217 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1218 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1219
00edf542 1220 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
0b0ffc96
TK		 1221 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1222
00edf542 1223 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
0b0ffc96
TK		 1224 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1225
e01678e3 1226 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
0b0ffc96
TK		 1227 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1228
1229 /* IPSR14 */
1230 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1231
1232 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1233 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1234
e01678e3 1235 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
0b0ffc96
TK		 1236 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1237 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1238
e01678e3 1239 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
0b0ffc96
TK		 1240 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1241 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1242 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1243
e01678e3 1244 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
0b0ffc96
TK		 1245 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1246 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1247 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1248 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1249 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1250 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1251
e01678e3 1252 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
0b0ffc96
TK		 1253 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1254 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1255 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1256 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1257 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1258 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1259
e01678e3 1260 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
0b0ffc96
TK		 1261 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1262 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1263 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1264 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1265 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1266 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1267
e01678e3 1268 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
0b0ffc96
TK		 1269 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1270 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1271 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1272 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1273 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1274 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1275
1276 /* IPSR15 */
e01678e3
GU		 1277 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1278 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
0b0ffc96
TK		 1279 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1280
e01678e3
GU		 1281 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1282 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
0b0ffc96
TK		 1283 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1284
e01678e3 1285 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
0b0ffc96 1286 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
fd1aa743 1287 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
0b0ffc96 1288
e01678e3 1289 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
0b0ffc96
TK		 1290 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1291 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1292 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1293 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1294 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1295 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1296
e01678e3 1297 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
0b0ffc96
TK		 1298 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1299 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1300 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1301 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1302 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1303 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1304
e01678e3 1305 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
0b0ffc96
TK		 1306 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1307 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1308 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1309 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1310 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1311 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1312 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1313
e01678e3 1314 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
0b0ffc96
TK		 1315 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1316 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1317 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1318 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1319 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1320 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1321
1322 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1323 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1324 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1325 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1326 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
e01678e3 1327 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
0b0ffc96 1328 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
e01678e3 1329 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
0b0ffc96
TK		 1330
1331 /* IPSR16 */
1332 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
e01678e3 1333 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
0b0ffc96
TK		 1334
1335 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1336 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1337 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1338 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1339 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1340
e01678e3 1341 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
0b0ffc96
TK		 1342 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1343 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1344 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1345 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1346 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1347
e01678e3 1348 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
0b0ffc96
TK		 1349 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1350 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1351 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1352 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1353
e01678e3 1354 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
0b0ffc96
TK		 1355 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1356 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1357 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1358 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1359 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1360 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1361 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1362
e01678e3 1363 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
0b0ffc96
TK		 1364 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1365 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1366 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1367 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1368 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1369 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1370 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1371
e01678e3 1372 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
0b0ffc96
TK		 1373 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1374 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1375 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1376 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1377 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1378 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1379 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
e01678e3 1380 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
0b0ffc96 1381
e01678e3 1382 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
0b0ffc96
TK		 1383 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1384 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1385 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1386 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1387 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1388 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1389 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
e01678e3 1390 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
0b0ffc96
TK		 1391
1392 /* IPSR17 */
e01678e3 1393 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
0b0ffc96
TK		 1394 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1395 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1396 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1397 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1398 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
e01678e3 1399 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
0b0ffc96 1400
e01678e3 1401 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
0b0ffc96
TK		 1402 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1403 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1404 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1405 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1406 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
e01678e3 1407 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
0b0ffc96
TK		 1408
1409 /* I2C */
1410 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1411 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1412 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1413};
1414
1415static const struct sh_pfc_pin pinmux_pins[] = {
1416 PINMUX_GPIO_GP_ALL(),
1417};
1418
c33a7fe3
KM		 1419/* - AUDIO CLOCK ------------------------------------------------------------ */
1420static const unsigned int audio_clk_a_a_pins[] = {
1421 /* CLK A */
1422 RCAR_GP_PIN(6, 22),
1423};
1424static const unsigned int audio_clk_a_a_mux[] = {
1425 AUDIO_CLKA_A_MARK,
1426};
1427static const unsigned int audio_clk_a_b_pins[] = {
1428 /* CLK A */
1429 RCAR_GP_PIN(5, 4),
1430};
1431static const unsigned int audio_clk_a_b_mux[] = {
1432 AUDIO_CLKA_B_MARK,
1433};
1434static const unsigned int audio_clk_a_c_pins[] = {
1435 /* CLK A */
1436 RCAR_GP_PIN(5, 19),
1437};
1438static const unsigned int audio_clk_a_c_mux[] = {
1439 AUDIO_CLKA_C_MARK,
1440};
1441static const unsigned int audio_clk_b_a_pins[] = {
1442 /* CLK B */
1443 RCAR_GP_PIN(5, 12),
1444};
1445static const unsigned int audio_clk_b_a_mux[] = {
1446 AUDIO_CLKB_A_MARK,
1447};
1448static const unsigned int audio_clk_b_b_pins[] = {
1449 /* CLK B */
1450 RCAR_GP_PIN(6, 23),
1451};
1452static const unsigned int audio_clk_b_b_mux[] = {
1453 AUDIO_CLKB_B_MARK,
1454};
1455static const unsigned int audio_clk_c_a_pins[] = {
1456 /* CLK C */
1457 RCAR_GP_PIN(5, 21),
1458};
1459static const unsigned int audio_clk_c_a_mux[] = {
1460 AUDIO_CLKC_A_MARK,
1461};
1462static const unsigned int audio_clk_c_b_pins[] = {
1463 /* CLK C */
1464 RCAR_GP_PIN(5, 0),
1465};
1466static const unsigned int audio_clk_c_b_mux[] = {
1467 AUDIO_CLKC_B_MARK,
1468};
1469static const unsigned int audio_clkout_a_pins[] = {
1470 /* CLKOUT */
1471 RCAR_GP_PIN(5, 18),
1472};
1473static const unsigned int audio_clkout_a_mux[] = {
1474 AUDIO_CLKOUT_A_MARK,
1475};
1476static const unsigned int audio_clkout_b_pins[] = {
1477 /* CLKOUT */
1478 RCAR_GP_PIN(6, 28),
1479};
1480static const unsigned int audio_clkout_b_mux[] = {
1481 AUDIO_CLKOUT_B_MARK,
1482};
1483static const unsigned int audio_clkout_c_pins[] = {
1484 /* CLKOUT */
1485 RCAR_GP_PIN(5, 3),
1486};
1487static const unsigned int audio_clkout_c_mux[] = {
1488 AUDIO_CLKOUT_C_MARK,
1489};
1490static const unsigned int audio_clkout_d_pins[] = {
1491 /* CLKOUT */
1492 RCAR_GP_PIN(5, 21),
1493};
1494static const unsigned int audio_clkout_d_mux[] = {
1495 AUDIO_CLKOUT_D_MARK,
1496};
1497static const unsigned int audio_clkout1_a_pins[] = {
1498 /* CLKOUT1 */
1499 RCAR_GP_PIN(5, 15),
1500};
1501static const unsigned int audio_clkout1_a_mux[] = {
1502 AUDIO_CLKOUT1_A_MARK,
1503};
1504static const unsigned int audio_clkout1_b_pins[] = {
1505 /* CLKOUT1 */
1506 RCAR_GP_PIN(6, 29),
1507};
1508static const unsigned int audio_clkout1_b_mux[] = {
1509 AUDIO_CLKOUT1_B_MARK,
1510};
1511static const unsigned int audio_clkout2_a_pins[] = {
1512 /* CLKOUT2 */
1513 RCAR_GP_PIN(5, 16),
1514};
1515static const unsigned int audio_clkout2_a_mux[] = {
1516 AUDIO_CLKOUT2_A_MARK,
1517};
1518static const unsigned int audio_clkout2_b_pins[] = {
1519 /* CLKOUT2 */
1520 RCAR_GP_PIN(6, 30),
1521};
1522static const unsigned int audio_clkout2_b_mux[] = {
1523 AUDIO_CLKOUT2_B_MARK,
1524};
1525
1526static const unsigned int audio_clkout3_a_pins[] = {
1527 /* CLKOUT3 */
1528 RCAR_GP_PIN(5, 19),
1529};
1530static const unsigned int audio_clkout3_a_mux[] = {
1531 AUDIO_CLKOUT3_A_MARK,
1532};
1533static const unsigned int audio_clkout3_b_pins[] = {
1534 /* CLKOUT3 */
1535 RCAR_GP_PIN(6, 31),
1536};
1537static const unsigned int audio_clkout3_b_mux[] = {
1538 AUDIO_CLKOUT3_B_MARK,
1539};
1540
819fd4bf
TK		 1541/* - EtherAVB --------------------------------------------------------------- */
1542static const unsigned int avb_link_pins[] = {
1543 /* AVB_LINK */
1544 RCAR_GP_PIN(2, 12),
1545};
1546static const unsigned int avb_link_mux[] = {
1547 AVB_LINK_MARK,
1548};
1549static const unsigned int avb_magic_pins[] = {
1550 /* AVB_MAGIC_ */
1551 RCAR_GP_PIN(2, 10),
1552};
1553static const unsigned int avb_magic_mux[] = {
1554 AVB_MAGIC_MARK,
1555};
1556static const unsigned int avb_phy_int_pins[] = {
1557 /* AVB_PHY_INT */
1558 RCAR_GP_PIN(2, 11),
1559};
1560static const unsigned int avb_phy_int_mux[] = {
1561 AVB_PHY_INT_MARK,
1562};
1563static const unsigned int avb_mdc_pins[] = {
1564 /* AVB_MDC */
1565 RCAR_GP_PIN(2, 9),
1566};
1567static const unsigned int avb_mdc_mux[] = {
1568 AVB_MDC_MARK,
1569};
1570static const unsigned int avb_avtp_pps_pins[] = {
1571 /* AVB_AVTP_PPS */
1572 RCAR_GP_PIN(2, 6),
1573};
1574static const unsigned int avb_avtp_pps_mux[] = {
1575 AVB_AVTP_PPS_MARK,
1576};
1577static const unsigned int avb_avtp_match_a_pins[] = {
1578 /* AVB_AVTP_MATCH_A */
1579 RCAR_GP_PIN(2, 13),
1580};
1581static const unsigned int avb_avtp_match_a_mux[] = {
1582 AVB_AVTP_MATCH_A_MARK,
1583};
1584static const unsigned int avb_avtp_capture_a_pins[] = {
1585 /* AVB_AVTP_CAPTURE_A */
1586 RCAR_GP_PIN(2, 14),
1587};
1588static const unsigned int avb_avtp_capture_a_mux[] = {
1589 AVB_AVTP_CAPTURE_A_MARK,
1590};
1591static const unsigned int avb_avtp_match_b_pins[] = {
1592 /* AVB_AVTP_MATCH_B */
1593 RCAR_GP_PIN(1, 8),
1594};
1595static const unsigned int avb_avtp_match_b_mux[] = {
1596 AVB_AVTP_MATCH_B_MARK,
1597};
1598static const unsigned int avb_avtp_capture_b_pins[] = {
1599 /* AVB_AVTP_CAPTURE_B */
1600 RCAR_GP_PIN(1, 11),
1601};
1602static const unsigned int avb_avtp_capture_b_mux[] = {
1603 AVB_AVTP_CAPTURE_B_MARK,
1604};
1605
a4d9791f
RS		 1606/* - CAN ------------------------------------------------------------------ */
1607static const unsigned int can0_data_a_pins[] = {
1608 /* TX, RX */
1609 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1610};
1611static const unsigned int can0_data_a_mux[] = {
1612 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1613};
1614static const unsigned int can0_data_b_pins[] = {
1615 /* TX, RX */
1616 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1617};
1618static const unsigned int can0_data_b_mux[] = {
1619 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1620};
1621static const unsigned int can1_data_pins[] = {
1622 /* TX, RX */
1623 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1624};
1625static const unsigned int can1_data_mux[] = {
1626 CAN1_TX_MARK, CAN1_RX_MARK,
1627};
1628
1629/* - CAN Clock -------------------------------------------------------------- */
1630static const unsigned int can_clk_pins[] = {
1631 /* CLK */
1632 RCAR_GP_PIN(1, 25),
1633};
1634static const unsigned int can_clk_mux[] = {
1635 CAN_CLK_MARK,
1636};
1637
4412bb5d
RS		 1638/* - CAN FD --------------------------------------------------------------- */
1639static const unsigned int canfd0_data_a_pins[] = {
1640 /* TX, RX */
1641 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1642};
1643static const unsigned int canfd0_data_a_mux[] = {
1644 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1645};
1646static const unsigned int canfd0_data_b_pins[] = {
1647 /* TX, RX */
1648 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1649};
1650static const unsigned int canfd0_data_b_mux[] = {
1651 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1652};
1653static const unsigned int canfd1_data_pins[] = {
1654 /* TX, RX */
1655 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1656};
1657static const unsigned int canfd1_data_mux[] = {
1658 CANFD1_TX_MARK, CANFD1_RX_MARK,
1659};
1660
a56069c4
GU		 1661/* - HSCIF0 ----------------------------------------------------------------- */
1662static const unsigned int hscif0_data_pins[] = {
1663 /* RX, TX */
1664 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1665};
1666static const unsigned int hscif0_data_mux[] = {
1667 HRX0_MARK, HTX0_MARK,
1668};
1669static const unsigned int hscif0_clk_pins[] = {
1670 /* SCK */
1671 RCAR_GP_PIN(5, 12),
1672};
1673static const unsigned int hscif0_clk_mux[] = {
1674 HSCK0_MARK,
1675};
1676static const unsigned int hscif0_ctrl_pins[] = {
1677 /* RTS, CTS */
1678 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1679};
1680static const unsigned int hscif0_ctrl_mux[] = {
1681 HRTS0_N_MARK, HCTS0_N_MARK,
1682};
1683/* - HSCIF1 ----------------------------------------------------------------- */
1684static const unsigned int hscif1_data_a_pins[] = {
1685 /* RX, TX */
1686 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1687};
1688static const unsigned int hscif1_data_a_mux[] = {
1689 HRX1_A_MARK, HTX1_A_MARK,
1690};
1691static const unsigned int hscif1_clk_a_pins[] = {
1692 /* SCK */
1693 RCAR_GP_PIN(6, 21),
1694};
1695static const unsigned int hscif1_clk_a_mux[] = {
1696 HSCK1_A_MARK,
1697};
1698static const unsigned int hscif1_ctrl_a_pins[] = {
1699 /* RTS, CTS */
1700 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1701};
1702static const unsigned int hscif1_ctrl_a_mux[] = {
1703 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1704};
1705
1706static const unsigned int hscif1_data_b_pins[] = {
1707 /* RX, TX */
1708 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1709};
1710static const unsigned int hscif1_data_b_mux[] = {
1711 HRX1_B_MARK, HTX1_B_MARK,
1712};
1713static const unsigned int hscif1_clk_b_pins[] = {
1714 /* SCK */
1715 RCAR_GP_PIN(5, 0),
1716};
1717static const unsigned int hscif1_clk_b_mux[] = {
1718 HSCK1_B_MARK,
1719};
1720static const unsigned int hscif1_ctrl_b_pins[] = {
1721 /* RTS, CTS */
1722 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1723};
1724static const unsigned int hscif1_ctrl_b_mux[] = {
1725 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1726};
1727/* - HSCIF2 ----------------------------------------------------------------- */
1728static const unsigned int hscif2_data_a_pins[] = {
1729 /* RX, TX */
1730 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1731};
1732static const unsigned int hscif2_data_a_mux[] = {
1733 HRX2_A_MARK, HTX2_A_MARK,
1734};
1735static const unsigned int hscif2_clk_a_pins[] = {
1736 /* SCK */
1737 RCAR_GP_PIN(6, 10),
1738};
1739static const unsigned int hscif2_clk_a_mux[] = {
1740 HSCK2_A_MARK,
1741};
1742static const unsigned int hscif2_ctrl_a_pins[] = {
1743 /* RTS, CTS */
1744 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1745};
1746static const unsigned int hscif2_ctrl_a_mux[] = {
1747 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1748};
1749
1750static const unsigned int hscif2_data_b_pins[] = {
1751 /* RX, TX */
1752 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1753};
1754static const unsigned int hscif2_data_b_mux[] = {
1755 HRX2_B_MARK, HTX2_B_MARK,
1756};
1757static const unsigned int hscif2_clk_b_pins[] = {
1758 /* SCK */
1759 RCAR_GP_PIN(6, 21),
1760};
1761static const unsigned int hscif2_clk_b_mux[] = {
1762 HSCK1_B_MARK,
1763};
1764static const unsigned int hscif2_ctrl_b_pins[] = {
1765 /* RTS, CTS */
1766 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1767};
1768static const unsigned int hscif2_ctrl_b_mux[] = {
1769 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1770};
1771/* - HSCIF3 ----------------------------------------------------------------- */
1772static const unsigned int hscif3_data_a_pins[] = {
1773 /* RX, TX */
1774 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1775};
1776static const unsigned int hscif3_data_a_mux[] = {
1777 HRX3_A_MARK, HTX3_A_MARK,
1778};
1779static const unsigned int hscif3_clk_pins[] = {
1780 /* SCK */
1781 RCAR_GP_PIN(1, 22),
1782};
1783static const unsigned int hscif3_clk_mux[] = {
1784 HSCK3_MARK,
1785};
1786static const unsigned int hscif3_ctrl_pins[] = {
1787 /* RTS, CTS */
1788 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1789};
1790static const unsigned int hscif3_ctrl_mux[] = {
1791 HRTS3_N_MARK, HCTS3_N_MARK,
1792};
1793
1794static const unsigned int hscif3_data_b_pins[] = {
1795 /* RX, TX */
1796 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1797};
1798static const unsigned int hscif3_data_b_mux[] = {
1799 HRX3_B_MARK, HTX3_B_MARK,
1800};
1801static const unsigned int hscif3_data_c_pins[] = {
1802 /* RX, TX */
1803 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1804};
1805static const unsigned int hscif3_data_c_mux[] = {
1806 HRX3_C_MARK, HTX3_C_MARK,
1807};
1808static const unsigned int hscif3_data_d_pins[] = {
1809 /* RX, TX */
1810 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1811};
1812static const unsigned int hscif3_data_d_mux[] = {
1813 HRX3_D_MARK, HTX3_D_MARK,
1814};
1815/* - HSCIF4 ----------------------------------------------------------------- */
1816static const unsigned int hscif4_data_a_pins[] = {
1817 /* RX, TX */
1818 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
1819};
1820static const unsigned int hscif4_data_a_mux[] = {
1821 HRX4_A_MARK, HTX4_A_MARK,
1822};
1823static const unsigned int hscif4_clk_pins[] = {
1824 /* SCK */
1825 RCAR_GP_PIN(1, 11),
1826};
1827static const unsigned int hscif4_clk_mux[] = {
1828 HSCK4_MARK,
1829};
1830static const unsigned int hscif4_ctrl_pins[] = {
1831 /* RTS, CTS */
1832 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1833};
1834static const unsigned int hscif4_ctrl_mux[] = {
1835 HRTS4_N_MARK, HCTS3_N_MARK,
1836};
1837
1838static const unsigned int hscif4_data_b_pins[] = {
1839 /* RX, TX */
1840 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1841};
1842static const unsigned int hscif4_data_b_mux[] = {
1843 HRX4_B_MARK, HTX4_B_MARK,
1844};
1845
2544ef72
KM		 1846/* - I2C -------------------------------------------------------------------- */
1847static const unsigned int i2c1_a_pins[] = {
1848 /* SDA, SCL */
1849 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1850};
1851static const unsigned int i2c1_a_mux[] = {
1852 SDA1_A_MARK, SCL1_A_MARK,
1853};
1854static const unsigned int i2c1_b_pins[] = {
1855 /* SDA, SCL */
1856 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1857};
1858static const unsigned int i2c1_b_mux[] = {
1859 SDA1_B_MARK, SCL1_B_MARK,
1860};
1861static const unsigned int i2c2_a_pins[] = {
1862 /* SDA, SCL */
1863 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1864};
1865static const unsigned int i2c2_a_mux[] = {
1866 SDA2_A_MARK, SCL2_A_MARK,
1867};
1868static const unsigned int i2c2_b_pins[] = {
1869 /* SDA, SCL */
1870 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1871};
1872static const unsigned int i2c2_b_mux[] = {
1873 SDA2_B_MARK, SCL2_B_MARK,
1874};
1875static const unsigned int i2c6_a_pins[] = {
1876 /* SDA, SCL */
1877 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1878};
1879static const unsigned int i2c6_a_mux[] = {
1880 SDA6_A_MARK, SCL6_A_MARK,
1881};
1882static const unsigned int i2c6_b_pins[] = {
1883 /* SDA, SCL */
1884 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1885};
1886static const unsigned int i2c6_b_mux[] = {
1887 SDA6_B_MARK, SCL6_B_MARK,
1888};
1889static const unsigned int i2c6_c_pins[] = {
1890 /* SDA, SCL */
1891 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1892};
1893static const unsigned int i2c6_c_mux[] = {
1894 SDA6_C_MARK, SCL6_C_MARK,
1895};
1896
bb46f6f3
MD		 1897/* - INTC-EX ---------------------------------------------------------------- */
1898static const unsigned int intc_ex_irq0_pins[] = {
1899 /* IRQ0 */
1900 RCAR_GP_PIN(2, 0),
1901};
1902static const unsigned int intc_ex_irq0_mux[] = {
1903 IRQ0_MARK,
1904};
1905static const unsigned int intc_ex_irq1_pins[] = {
1906 /* IRQ1 */
1907 RCAR_GP_PIN(2, 1),
1908};
1909static const unsigned int intc_ex_irq1_mux[] = {
1910 IRQ1_MARK,
1911};
1912static const unsigned int intc_ex_irq2_pins[] = {
1913 /* IRQ2 */
1914 RCAR_GP_PIN(2, 2),
1915};
1916static const unsigned int intc_ex_irq2_mux[] = {
1917 IRQ2_MARK,
1918};
1919static const unsigned int intc_ex_irq3_pins[] = {
1920 /* IRQ3 */
1921 RCAR_GP_PIN(2, 3),
1922};
1923static const unsigned int intc_ex_irq3_mux[] = {
1924 IRQ3_MARK,
1925};
1926static const unsigned int intc_ex_irq4_pins[] = {
1927 /* IRQ4 */
1928 RCAR_GP_PIN(2, 4),
1929};
1930static const unsigned int intc_ex_irq4_mux[] = {
1931 IRQ4_MARK,
1932};
1933static const unsigned int intc_ex_irq5_pins[] = {
1934 /* IRQ5 */
1935 RCAR_GP_PIN(2, 5),
1936};
1937static const unsigned int intc_ex_irq5_mux[] = {
1938 IRQ5_MARK,
1939};
1940
e7419b81
GU		 1941/* - MSIOF0 ----------------------------------------------------------------- */
1942static const unsigned int msiof0_clk_pins[] = {
1943 /* SCK */
1944 RCAR_GP_PIN(5, 17),
1945};
1946static const unsigned int msiof0_clk_mux[] = {
1947 MSIOF0_SCK_MARK,
1948};
1949static const unsigned int msiof0_sync_pins[] = {
1950 /* SYNC */
1951 RCAR_GP_PIN(5, 18),
1952};
1953static const unsigned int msiof0_sync_mux[] = {
1954 MSIOF0_SYNC_MARK,
1955};
1956static const unsigned int msiof0_ss1_pins[] = {
1957 /* SS1 */
1958 RCAR_GP_PIN(5, 19),
1959};
1960static const unsigned int msiof0_ss1_mux[] = {
1961 MSIOF0_SS1_MARK,
1962};
1963static const unsigned int msiof0_ss2_pins[] = {
1964 /* SS2 */
1965 RCAR_GP_PIN(5, 21),
1966};
1967static const unsigned int msiof0_ss2_mux[] = {
1968 MSIOF0_SS2_MARK,
1969};
1970static const unsigned int msiof0_txd_pins[] = {
1971 /* TXD */
1972 RCAR_GP_PIN(5, 20),
1973};
1974static const unsigned int msiof0_txd_mux[] = {
1975 MSIOF0_TXD_MARK,
1976};
1977static const unsigned int msiof0_rxd_pins[] = {
1978 /* RXD */
1979 RCAR_GP_PIN(5, 22),
1980};
1981static const unsigned int msiof0_rxd_mux[] = {
1982 MSIOF0_RXD_MARK,
1983};
1984/* - MSIOF1 ----------------------------------------------------------------- */
1985static const unsigned int msiof1_clk_a_pins[] = {
1986 /* SCK */
1987 RCAR_GP_PIN(6, 8),
1988};
1989static const unsigned int msiof1_clk_a_mux[] = {
1990 MSIOF1_SCK_A_MARK,
1991};
1992static const unsigned int msiof1_sync_a_pins[] = {
1993 /* SYNC */
1994 RCAR_GP_PIN(6, 9),
1995};
1996static const unsigned int msiof1_sync_a_mux[] = {
1997 MSIOF1_SYNC_A_MARK,
1998};
1999static const unsigned int msiof1_ss1_a_pins[] = {
2000 /* SS1 */
2001 RCAR_GP_PIN(6, 5),
2002};
2003static const unsigned int msiof1_ss1_a_mux[] = {
2004 MSIOF1_SS1_A_MARK,
2005};
2006static const unsigned int msiof1_ss2_a_pins[] = {
2007 /* SS2 */
2008 RCAR_GP_PIN(6, 6),
2009};
2010static const unsigned int msiof1_ss2_a_mux[] = {
2011 MSIOF1_SS2_A_MARK,
2012};
2013static const unsigned int msiof1_txd_a_pins[] = {
2014 /* TXD */
2015 RCAR_GP_PIN(6, 7),
2016};
2017static const unsigned int msiof1_txd_a_mux[] = {
2018 MSIOF1_TXD_A_MARK,
2019};
2020static const unsigned int msiof1_rxd_a_pins[] = {
2021 /* RXD */
2022 RCAR_GP_PIN(6, 10),
2023};
2024static const unsigned int msiof1_rxd_a_mux[] = {
2025 MSIOF1_RXD_A_MARK,
2026};
2027static const unsigned int msiof1_clk_b_pins[] = {
2028 /* SCK */
2029 RCAR_GP_PIN(5, 9),
2030};
2031static const unsigned int msiof1_clk_b_mux[] = {
2032 MSIOF1_SCK_B_MARK,
2033};
2034static const unsigned int msiof1_sync_b_pins[] = {
2035 /* SYNC */
2036 RCAR_GP_PIN(5, 3),
2037};
2038static const unsigned int msiof1_sync_b_mux[] = {
2039 MSIOF1_SYNC_B_MARK,
2040};
2041static const unsigned int msiof1_ss1_b_pins[] = {
2042 /* SS1 */
2043 RCAR_GP_PIN(5, 4),
2044};
2045static const unsigned int msiof1_ss1_b_mux[] = {
2046 MSIOF1_SS1_B_MARK,
2047};
2048static const unsigned int msiof1_ss2_b_pins[] = {
2049 /* SS2 */
2050 RCAR_GP_PIN(5, 0),
2051};
2052static const unsigned int msiof1_ss2_b_mux[] = {
2053 MSIOF1_SS2_B_MARK,
2054};
2055static const unsigned int msiof1_txd_b_pins[] = {
2056 /* TXD */
2057 RCAR_GP_PIN(5, 8),
2058};
2059static const unsigned int msiof1_txd_b_mux[] = {
2060 MSIOF1_TXD_B_MARK,
2061};
2062static const unsigned int msiof1_rxd_b_pins[] = {
2063 /* RXD */
2064 RCAR_GP_PIN(5, 7),
2065};
2066static const unsigned int msiof1_rxd_b_mux[] = {
2067 MSIOF1_RXD_B_MARK,
2068};
2069static const unsigned int msiof1_clk_c_pins[] = {
2070 /* SCK */
2071 RCAR_GP_PIN(6, 17),
2072};
2073static const unsigned int msiof1_clk_c_mux[] = {
2074 MSIOF1_SCK_C_MARK,
2075};
2076static const unsigned int msiof1_sync_c_pins[] = {
2077 /* SYNC */
2078 RCAR_GP_PIN(6, 18),
2079};
2080static const unsigned int msiof1_sync_c_mux[] = {
2081 MSIOF1_SYNC_C_MARK,
2082};
2083static const unsigned int msiof1_ss1_c_pins[] = {
2084 /* SS1 */
2085 RCAR_GP_PIN(6, 21),
2086};
2087static const unsigned int msiof1_ss1_c_mux[] = {
2088 MSIOF1_SS1_C_MARK,
2089};
2090static const unsigned int msiof1_ss2_c_pins[] = {
2091 /* SS2 */
2092 RCAR_GP_PIN(6, 27),
2093};
2094static const unsigned int msiof1_ss2_c_mux[] = {
2095 MSIOF1_SS2_C_MARK,
2096};
2097static const unsigned int msiof1_txd_c_pins[] = {
2098 /* TXD */
2099 RCAR_GP_PIN(6, 20),
2100};
2101static const unsigned int msiof1_txd_c_mux[] = {
2102 MSIOF1_TXD_C_MARK,
2103};
2104static const unsigned int msiof1_rxd_c_pins[] = {
2105 /* RXD */
2106 RCAR_GP_PIN(6, 19),
2107};
2108static const unsigned int msiof1_rxd_c_mux[] = {
2109 MSIOF1_RXD_C_MARK,
2110};
2111static const unsigned int msiof1_clk_d_pins[] = {
2112 /* SCK */
2113 RCAR_GP_PIN(5, 12),
2114};
2115static const unsigned int msiof1_clk_d_mux[] = {
2116 MSIOF1_SCK_D_MARK,
2117};
2118static const unsigned int msiof1_sync_d_pins[] = {
2119 /* SYNC */
2120 RCAR_GP_PIN(5, 15),
2121};
2122static const unsigned int msiof1_sync_d_mux[] = {
2123 MSIOF1_SYNC_D_MARK,
2124};
2125static const unsigned int msiof1_ss1_d_pins[] = {
2126 /* SS1 */
2127 RCAR_GP_PIN(5, 16),
2128};
2129static const unsigned int msiof1_ss1_d_mux[] = {
2130 MSIOF1_SS1_D_MARK,
2131};
2132static const unsigned int msiof1_ss2_d_pins[] = {
2133 /* SS2 */
2134 RCAR_GP_PIN(5, 21),
2135};
2136static const unsigned int msiof1_ss2_d_mux[] = {
2137 MSIOF1_SS2_D_MARK,
2138};
2139static const unsigned int msiof1_txd_d_pins[] = {
2140 /* TXD */
2141 RCAR_GP_PIN(5, 14),
2142};
2143static const unsigned int msiof1_txd_d_mux[] = {
2144 MSIOF1_TXD_D_MARK,
2145};
2146static const unsigned int msiof1_rxd_d_pins[] = {
2147 /* RXD */
2148 RCAR_GP_PIN(5, 13),
2149};
2150static const unsigned int msiof1_rxd_d_mux[] = {
2151 MSIOF1_RXD_D_MARK,
2152};
2153static const unsigned int msiof1_clk_e_pins[] = {
2154 /* SCK */
2155 RCAR_GP_PIN(3, 0),
2156};
2157static const unsigned int msiof1_clk_e_mux[] = {
2158 MSIOF1_SCK_E_MARK,
2159};
2160static const unsigned int msiof1_sync_e_pins[] = {
2161 /* SYNC */
2162 RCAR_GP_PIN(3, 1),
2163};
2164static const unsigned int msiof1_sync_e_mux[] = {
2165 MSIOF1_SYNC_E_MARK,
2166};
2167static const unsigned int msiof1_ss1_e_pins[] = {
2168 /* SS1 */
2169 RCAR_GP_PIN(3, 4),
2170};
2171static const unsigned int msiof1_ss1_e_mux[] = {
2172 MSIOF1_SS1_E_MARK,
2173};
2174static const unsigned int msiof1_ss2_e_pins[] = {
2175 /* SS2 */
2176 RCAR_GP_PIN(3, 5),
2177};
2178static const unsigned int msiof1_ss2_e_mux[] = {
2179 MSIOF1_SS2_E_MARK,
2180};
2181static const unsigned int msiof1_txd_e_pins[] = {
2182 /* TXD */
2183 RCAR_GP_PIN(3, 3),
2184};
2185static const unsigned int msiof1_txd_e_mux[] = {
2186 MSIOF1_TXD_E_MARK,
2187};
2188static const unsigned int msiof1_rxd_e_pins[] = {
2189 /* RXD */
2190 RCAR_GP_PIN(3, 2),
2191};
2192static const unsigned int msiof1_rxd_e_mux[] = {
2193 MSIOF1_RXD_E_MARK,
2194};
2195static const unsigned int msiof1_clk_f_pins[] = {
2196 /* SCK */
2197 RCAR_GP_PIN(5, 23),
2198};
2199static const unsigned int msiof1_clk_f_mux[] = {
2200 MSIOF1_SCK_F_MARK,
2201};
2202static const unsigned int msiof1_sync_f_pins[] = {
2203 /* SYNC */
2204 RCAR_GP_PIN(5, 24),
2205};
2206static const unsigned int msiof1_sync_f_mux[] = {
2207 MSIOF1_SYNC_F_MARK,
2208};
2209static const unsigned int msiof1_ss1_f_pins[] = {
2210 /* SS1 */
2211 RCAR_GP_PIN(6, 1),
2212};
2213static const unsigned int msiof1_ss1_f_mux[] = {
2214 MSIOF1_SS1_F_MARK,
2215};
2216static const unsigned int msiof1_ss2_f_pins[] = {
2217 /* SS2 */
2218 RCAR_GP_PIN(6, 2),
2219};
2220static const unsigned int msiof1_ss2_f_mux[] = {
2221 MSIOF1_SS2_F_MARK,
2222};
2223static const unsigned int msiof1_txd_f_pins[] = {
2224 /* TXD */
2225 RCAR_GP_PIN(6, 0),
2226};
2227static const unsigned int msiof1_txd_f_mux[] = {
2228 MSIOF1_TXD_F_MARK,
2229};
2230static const unsigned int msiof1_rxd_f_pins[] = {
2231 /* RXD */
2232 RCAR_GP_PIN(5, 25),
2233};
2234static const unsigned int msiof1_rxd_f_mux[] = {
2235 MSIOF1_RXD_F_MARK,
2236};
2237static const unsigned int msiof1_clk_g_pins[] = {
2238 /* SCK */
2239 RCAR_GP_PIN(3, 6),
2240};
2241static const unsigned int msiof1_clk_g_mux[] = {
2242 MSIOF1_SCK_G_MARK,
2243};
2244static const unsigned int msiof1_sync_g_pins[] = {
2245 /* SYNC */
2246 RCAR_GP_PIN(3, 7),
2247};
2248static const unsigned int msiof1_sync_g_mux[] = {
2249 MSIOF1_SYNC_G_MARK,
2250};
2251static const unsigned int msiof1_ss1_g_pins[] = {
2252 /* SS1 */
2253 RCAR_GP_PIN(3, 10),
2254};
2255static const unsigned int msiof1_ss1_g_mux[] = {
2256 MSIOF1_SS1_G_MARK,
2257};
2258static const unsigned int msiof1_ss2_g_pins[] = {
2259 /* SS2 */
2260 RCAR_GP_PIN(3, 11),
2261};
2262static const unsigned int msiof1_ss2_g_mux[] = {
2263 MSIOF1_SS2_G_MARK,
2264};
2265static const unsigned int msiof1_txd_g_pins[] = {
2266 /* TXD */
2267 RCAR_GP_PIN(3, 9),
2268};
2269static const unsigned int msiof1_txd_g_mux[] = {
2270 MSIOF1_TXD_G_MARK,
2271};
2272static const unsigned int msiof1_rxd_g_pins[] = {
2273 /* RXD */
2274 RCAR_GP_PIN(3, 8),
2275};
2276static const unsigned int msiof1_rxd_g_mux[] = {
2277 MSIOF1_RXD_G_MARK,
2278};
2279/* - MSIOF2 ----------------------------------------------------------------- */
2280static const unsigned int msiof2_clk_a_pins[] = {
2281 /* SCK */
2282 RCAR_GP_PIN(1, 9),
2283};
2284static const unsigned int msiof2_clk_a_mux[] = {
2285 MSIOF2_SCK_A_MARK,
2286};
2287static const unsigned int msiof2_sync_a_pins[] = {
2288 /* SYNC */
2289 RCAR_GP_PIN(1, 8),
2290};
2291static const unsigned int msiof2_sync_a_mux[] = {
2292 MSIOF2_SYNC_A_MARK,
2293};
2294static const unsigned int msiof2_ss1_a_pins[] = {
2295 /* SS1 */
2296 RCAR_GP_PIN(1, 6),
2297};
2298static const unsigned int msiof2_ss1_a_mux[] = {
2299 MSIOF2_SS1_A_MARK,
2300};
2301static const unsigned int msiof2_ss2_a_pins[] = {
2302 /* SS2 */
2303 RCAR_GP_PIN(1, 7),
2304};
2305static const unsigned int msiof2_ss2_a_mux[] = {
2306 MSIOF2_SS2_A_MARK,
2307};
2308static const unsigned int msiof2_txd_a_pins[] = {
2309 /* TXD */
2310 RCAR_GP_PIN(1, 11),
2311};
2312static const unsigned int msiof2_txd_a_mux[] = {
2313 MSIOF2_TXD_A_MARK,
2314};
2315static const unsigned int msiof2_rxd_a_pins[] = {
2316 /* RXD */
2317 RCAR_GP_PIN(1, 10),
2318};
2319static const unsigned int msiof2_rxd_a_mux[] = {
2320 MSIOF2_RXD_A_MARK,
2321};
2322static const unsigned int msiof2_clk_b_pins[] = {
2323 /* SCK */
2324 RCAR_GP_PIN(0, 4),
2325};
2326static const unsigned int msiof2_clk_b_mux[] = {
2327 MSIOF2_SCK_B_MARK,
2328};
2329static const unsigned int msiof2_sync_b_pins[] = {
2330 /* SYNC */
2331 RCAR_GP_PIN(0, 5),
2332};
2333static const unsigned int msiof2_sync_b_mux[] = {
2334 MSIOF2_SYNC_B_MARK,
2335};
2336static const unsigned int msiof2_ss1_b_pins[] = {
2337 /* SS1 */
2338 RCAR_GP_PIN(0, 0),
2339};
2340static const unsigned int msiof2_ss1_b_mux[] = {
2341 MSIOF2_SS1_B_MARK,
2342};
2343static const unsigned int msiof2_ss2_b_pins[] = {
2344 /* SS2 */
2345 RCAR_GP_PIN(0, 1),
2346};
2347static const unsigned int msiof2_ss2_b_mux[] = {
2348 MSIOF2_SS2_B_MARK,
2349};
2350static const unsigned int msiof2_txd_b_pins[] = {
2351 /* TXD */
2352 RCAR_GP_PIN(0, 7),
2353};
2354static const unsigned int msiof2_txd_b_mux[] = {
2355 MSIOF2_TXD_B_MARK,
2356};
2357static const unsigned int msiof2_rxd_b_pins[] = {
2358 /* RXD */
2359 RCAR_GP_PIN(0, 6),
2360};
2361static const unsigned int msiof2_rxd_b_mux[] = {
2362 MSIOF2_RXD_B_MARK,
2363};
2364static const unsigned int msiof2_clk_c_pins[] = {
2365 /* SCK */
2366 RCAR_GP_PIN(2, 12),
2367};
2368static const unsigned int msiof2_clk_c_mux[] = {
2369 MSIOF2_SCK_C_MARK,
2370};
2371static const unsigned int msiof2_sync_c_pins[] = {
2372 /* SYNC */
2373 RCAR_GP_PIN(2, 11),
2374};
2375static const unsigned int msiof2_sync_c_mux[] = {
2376 MSIOF2_SYNC_C_MARK,
2377};
2378static const unsigned int msiof2_ss1_c_pins[] = {
2379 /* SS1 */
2380 RCAR_GP_PIN(2, 10),
2381};
2382static const unsigned int msiof2_ss1_c_mux[] = {
2383 MSIOF2_SS1_C_MARK,
2384};
2385static const unsigned int msiof2_ss2_c_pins[] = {
2386 /* SS2 */
2387 RCAR_GP_PIN(2, 9),
2388};
2389static const unsigned int msiof2_ss2_c_mux[] = {
2390 MSIOF2_SS2_C_MARK,
2391};
2392static const unsigned int msiof2_txd_c_pins[] = {
2393 /* TXD */
2394 RCAR_GP_PIN(2, 14),
2395};
2396static const unsigned int msiof2_txd_c_mux[] = {
2397 MSIOF2_TXD_C_MARK,
2398};
2399static const unsigned int msiof2_rxd_c_pins[] = {
2400 /* RXD */
2401 RCAR_GP_PIN(2, 13),
2402};
2403static const unsigned int msiof2_rxd_c_mux[] = {
2404 MSIOF2_RXD_C_MARK,
2405};
2406static const unsigned int msiof2_clk_d_pins[] = {
2407 /* SCK */
2408 RCAR_GP_PIN(0, 8),
2409};
2410static const unsigned int msiof2_clk_d_mux[] = {
2411 MSIOF2_SCK_D_MARK,
2412};
2413static const unsigned int msiof2_sync_d_pins[] = {
2414 /* SYNC */
2415 RCAR_GP_PIN(0, 9),
2416};
2417static const unsigned int msiof2_sync_d_mux[] = {
2418 MSIOF2_SYNC_D_MARK,
2419};
2420static const unsigned int msiof2_ss1_d_pins[] = {
2421 /* SS1 */
2422 RCAR_GP_PIN(0, 12),
2423};
2424static const unsigned int msiof2_ss1_d_mux[] = {
2425 MSIOF2_SS1_D_MARK,
2426};
2427static const unsigned int msiof2_ss2_d_pins[] = {
2428 /* SS2 */
2429 RCAR_GP_PIN(0, 13),
2430};
2431static const unsigned int msiof2_ss2_d_mux[] = {
2432 MSIOF2_SS2_D_MARK,
2433};
2434static const unsigned int msiof2_txd_d_pins[] = {
2435 /* TXD */
2436 RCAR_GP_PIN(0, 11),
2437};
2438static const unsigned int msiof2_txd_d_mux[] = {
2439 MSIOF2_TXD_D_MARK,
2440};
2441static const unsigned int msiof2_rxd_d_pins[] = {
2442 /* RXD */
2443 RCAR_GP_PIN(0, 10),
2444};
2445static const unsigned int msiof2_rxd_d_mux[] = {
2446 MSIOF2_RXD_D_MARK,
2447};
2448/* - MSIOF3 ----------------------------------------------------------------- */
2449static const unsigned int msiof3_clk_a_pins[] = {
2450 /* SCK */
2451 RCAR_GP_PIN(0, 0),
2452};
2453static const unsigned int msiof3_clk_a_mux[] = {
2454 MSIOF3_SCK_A_MARK,
2455};
2456static const unsigned int msiof3_sync_a_pins[] = {
2457 /* SYNC */
2458 RCAR_GP_PIN(0, 1),
2459};
2460static const unsigned int msiof3_sync_a_mux[] = {
2461 MSIOF3_SYNC_A_MARK,
2462};
2463static const unsigned int msiof3_ss1_a_pins[] = {
2464 /* SS1 */
2465 RCAR_GP_PIN(0, 14),
2466};
2467static const unsigned int msiof3_ss1_a_mux[] = {
2468 MSIOF3_SS1_A_MARK,
2469};
2470static const unsigned int msiof3_ss2_a_pins[] = {
2471 /* SS2 */
2472 RCAR_GP_PIN(0, 15),
2473};
2474static const unsigned int msiof3_ss2_a_mux[] = {
2475 MSIOF3_SS2_A_MARK,
2476};
2477static const unsigned int msiof3_txd_a_pins[] = {
2478 /* TXD */
2479 RCAR_GP_PIN(0, 3),
2480};
2481static const unsigned int msiof3_txd_a_mux[] = {
2482 MSIOF3_TXD_A_MARK,
2483};
2484static const unsigned int msiof3_rxd_a_pins[] = {
2485 /* RXD */
2486 RCAR_GP_PIN(0, 2),
2487};
2488static const unsigned int msiof3_rxd_a_mux[] = {
2489 MSIOF3_RXD_A_MARK,
2490};
2491static const unsigned int msiof3_clk_b_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(1, 2),
2494};
2495static const unsigned int msiof3_clk_b_mux[] = {
2496 MSIOF3_SCK_B_MARK,
2497};
2498static const unsigned int msiof3_sync_b_pins[] = {
2499 /* SYNC */
2500 RCAR_GP_PIN(1, 0),
2501};
2502static const unsigned int msiof3_sync_b_mux[] = {
2503 MSIOF3_SYNC_B_MARK,
2504};
2505static const unsigned int msiof3_ss1_b_pins[] = {
2506 /* SS1 */
2507 RCAR_GP_PIN(1, 4),
2508};
2509static const unsigned int msiof3_ss1_b_mux[] = {
2510 MSIOF3_SS1_B_MARK,
2511};
2512static const unsigned int msiof3_ss2_b_pins[] = {
2513 /* SS2 */
2514 RCAR_GP_PIN(1, 5),
2515};
2516static const unsigned int msiof3_ss2_b_mux[] = {
2517 MSIOF3_SS2_B_MARK,
2518};
2519static const unsigned int msiof3_txd_b_pins[] = {
2520 /* TXD */
2521 RCAR_GP_PIN(1, 1),
2522};
2523static const unsigned int msiof3_txd_b_mux[] = {
2524 MSIOF3_TXD_B_MARK,
2525};
2526static const unsigned int msiof3_rxd_b_pins[] = {
2527 /* RXD */
2528 RCAR_GP_PIN(1, 3),
2529};
2530static const unsigned int msiof3_rxd_b_mux[] = {
2531 MSIOF3_RXD_B_MARK,
2532};
2533static const unsigned int msiof3_clk_c_pins[] = {
2534 /* SCK */
2535 RCAR_GP_PIN(1, 12),
2536};
2537static const unsigned int msiof3_clk_c_mux[] = {
2538 MSIOF3_SCK_C_MARK,
2539};
2540static const unsigned int msiof3_sync_c_pins[] = {
2541 /* SYNC */
2542 RCAR_GP_PIN(1, 13),
2543};
2544static const unsigned int msiof3_sync_c_mux[] = {
2545 MSIOF3_SYNC_C_MARK,
2546};
2547static const unsigned int msiof3_txd_c_pins[] = {
2548 /* TXD */
2549 RCAR_GP_PIN(1, 15),
2550};
2551static const unsigned int msiof3_txd_c_mux[] = {
2552 MSIOF3_TXD_C_MARK,
2553};
2554static const unsigned int msiof3_rxd_c_pins[] = {
2555 /* RXD */
2556 RCAR_GP_PIN(1, 14),
2557};
2558static const unsigned int msiof3_rxd_c_mux[] = {
2559 MSIOF3_RXD_C_MARK,
2560};
2561static const unsigned int msiof3_clk_d_pins[] = {
2562 /* SCK */
2563 RCAR_GP_PIN(1, 22),
2564};
2565static const unsigned int msiof3_clk_d_mux[] = {
2566 MSIOF3_SCK_D_MARK,
2567};
2568static const unsigned int msiof3_sync_d_pins[] = {
2569 /* SYNC */
2570 RCAR_GP_PIN(1, 23),
2571};
2572static const unsigned int msiof3_sync_d_mux[] = {
2573 MSIOF3_SYNC_D_MARK,
2574};
2575static const unsigned int msiof3_ss1_d_pins[] = {
2576 /* SS1 */
2577 RCAR_GP_PIN(1, 26),
2578};
2579static const unsigned int msiof3_ss1_d_mux[] = {
2580 MSIOF3_SS1_D_MARK,
2581};
2582static const unsigned int msiof3_txd_d_pins[] = {
2583 /* TXD */
2584 RCAR_GP_PIN(1, 25),
2585};
2586static const unsigned int msiof3_txd_d_mux[] = {
2587 MSIOF3_TXD_D_MARK,
2588};
2589static const unsigned int msiof3_rxd_d_pins[] = {
2590 /* RXD */
2591 RCAR_GP_PIN(1, 24),
2592};
2593static const unsigned int msiof3_rxd_d_mux[] = {
2594 MSIOF3_RXD_D_MARK,
2595};
2596
4ca88cf6
TK		 2597/* - PWM0 --------------------------------------------------------------------*/
2598static const unsigned int pwm0_pins[] = {
2599 /* PWM */
2600 RCAR_GP_PIN(2, 6),
2601};
2602static const unsigned int pwm0_mux[] = {
2603 PWM0_MARK,
2604};
2605/* - PWM1 --------------------------------------------------------------------*/
2606static const unsigned int pwm1_a_pins[] = {
2607 /* PWM */
2608 RCAR_GP_PIN(2, 7),
2609};
2610static const unsigned int pwm1_a_mux[] = {
2611 PWM1_A_MARK,
2612};
2613static const unsigned int pwm1_b_pins[] = {
2614 /* PWM */
2615 RCAR_GP_PIN(1, 8),
2616};
2617static const unsigned int pwm1_b_mux[] = {
2618 PWM1_B_MARK,
2619};
2620/* - PWM2 --------------------------------------------------------------------*/
2621static const unsigned int pwm2_a_pins[] = {
2622 /* PWM */
2623 RCAR_GP_PIN(2, 8),
2624};
2625static const unsigned int pwm2_a_mux[] = {
2626 PWM2_A_MARK,
2627};
2628static const unsigned int pwm2_b_pins[] = {
2629 /* PWM */
2630 RCAR_GP_PIN(1, 11),
2631};
2632static const unsigned int pwm2_b_mux[] = {
2633 PWM2_B_MARK,
2634};
2635/* - PWM3 --------------------------------------------------------------------*/
2636static const unsigned int pwm3_a_pins[] = {
2637 /* PWM */
2638 RCAR_GP_PIN(1, 0),
2639};
2640static const unsigned int pwm3_a_mux[] = {
2641 PWM3_A_MARK,
2642};
2643static const unsigned int pwm3_b_pins[] = {
2644 /* PWM */
2645 RCAR_GP_PIN(2, 2),
2646};
2647static const unsigned int pwm3_b_mux[] = {
2648 PWM3_B_MARK,
2649};
2650/* - PWM4 --------------------------------------------------------------------*/
2651static const unsigned int pwm4_a_pins[] = {
2652 /* PWM */
2653 RCAR_GP_PIN(1, 1),
2654};
2655static const unsigned int pwm4_a_mux[] = {
2656 PWM4_A_MARK,
2657};
2658static const unsigned int pwm4_b_pins[] = {
2659 /* PWM */
2660 RCAR_GP_PIN(2, 3),
2661};
2662static const unsigned int pwm4_b_mux[] = {
2663 PWM4_B_MARK,
2664};
2665/* - PWM5 --------------------------------------------------------------------*/
2666static const unsigned int pwm5_a_pins[] = {
2667 /* PWM */
2668 RCAR_GP_PIN(1, 2),
2669};
2670static const unsigned int pwm5_a_mux[] = {
2671 PWM5_A_MARK,
2672};
2673static const unsigned int pwm5_b_pins[] = {
2674 /* PWM */
2675 RCAR_GP_PIN(2, 4),
2676};
2677static const unsigned int pwm5_b_mux[] = {
2678 PWM5_B_MARK,
2679};
2680/* - PWM6 --------------------------------------------------------------------*/
2681static const unsigned int pwm6_a_pins[] = {
2682 /* PWM */
2683 RCAR_GP_PIN(1, 3),
2684};
2685static const unsigned int pwm6_a_mux[] = {
2686 PWM6_A_MARK,
2687};
2688static const unsigned int pwm6_b_pins[] = {
2689 /* PWM */
2690 RCAR_GP_PIN(2, 5),
2691};
2692static const unsigned int pwm6_b_mux[] = {
2693 PWM6_B_MARK,
2694};
2695
34dc4e16
TK		 2696/* - SATA --------------------------------------------------------------------*/
2697static const unsigned int sata0_devslp_a_pins[] = {
2698 /* DEVSLP */
2699 RCAR_GP_PIN(6, 16),
2700};
2701static const unsigned int sata0_devslp_a_mux[] = {
2702 SATA_DEVSLP_A_MARK,
2703};
2704static const unsigned int sata0_devslp_b_pins[] = {
2705 /* DEVSLP */
2706 RCAR_GP_PIN(4, 6),
2707};
2708static const unsigned int sata0_devslp_b_mux[] = {
2709 SATA_DEVSLP_B_MARK,
2710};
2711
ff8459a5
GU		 2712/* - SCIF0 ------------------------------------------------------------------ */
2713static const unsigned int scif0_data_pins[] = {
2714 /* RX, TX */
2715 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2716};
2717static const unsigned int scif0_data_mux[] = {
2718 RX0_MARK, TX0_MARK,
2719};
2720static const unsigned int scif0_clk_pins[] = {
2721 /* SCK */
2722 RCAR_GP_PIN(5, 0),
2723};
2724static const unsigned int scif0_clk_mux[] = {
2725 SCK0_MARK,
2726};
2727static const unsigned int scif0_ctrl_pins[] = {
2728 /* RTS, CTS */
2729 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2730};
2731static const unsigned int scif0_ctrl_mux[] = {
2732 RTS0_N_TANS_MARK, CTS0_N_MARK,
2733};
2734/* - SCIF1 ------------------------------------------------------------------ */
2735static const unsigned int scif1_data_a_pins[] = {
2736 /* RX, TX */
2737 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2738};
2739static const unsigned int scif1_data_a_mux[] = {
2740 RX1_A_MARK, TX1_A_MARK,
2741};
2742static const unsigned int scif1_clk_pins[] = {
2743 /* SCK */
2744 RCAR_GP_PIN(6, 21),
2745};
2746static const unsigned int scif1_clk_mux[] = {
2747 SCK1_MARK,
2748};
2749static const unsigned int scif1_ctrl_pins[] = {
2750 /* RTS, CTS */
2751 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2752};
2753static const unsigned int scif1_ctrl_mux[] = {
2754 RTS1_N_TANS_MARK, CTS1_N_MARK,
2755};
2756
2757static const unsigned int scif1_data_b_pins[] = {
2758 /* RX, TX */
2759 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2760};
2761static const unsigned int scif1_data_b_mux[] = {
2762 RX1_B_MARK, TX1_B_MARK,
2763};
2764/* - SCIF2 ------------------------------------------------------------------ */
2765static const unsigned int scif2_data_a_pins[] = {
2766 /* RX, TX */
2767 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2768};
2769static const unsigned int scif2_data_a_mux[] = {
2770 RX2_A_MARK, TX2_A_MARK,
2771};
2772static const unsigned int scif2_clk_pins[] = {
2773 /* SCK */
2774 RCAR_GP_PIN(5, 9),
2775};
2776static const unsigned int scif2_clk_mux[] = {
2777 SCK2_MARK,
2778};
2779static const unsigned int scif2_data_b_pins[] = {
2780 /* RX, TX */
2781 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2782};
2783static const unsigned int scif2_data_b_mux[] = {
2784 RX2_B_MARK, TX2_B_MARK,
2785};
2786/* - SCIF3 ------------------------------------------------------------------ */
2787static const unsigned int scif3_data_a_pins[] = {
2788 /* RX, TX */
2789 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2790};
2791static const unsigned int scif3_data_a_mux[] = {
2792 RX3_A_MARK, TX3_A_MARK,
2793};
2794static const unsigned int scif3_clk_pins[] = {
2795 /* SCK */
2796 RCAR_GP_PIN(1, 22),
2797};
2798static const unsigned int scif3_clk_mux[] = {
2799 SCK3_MARK,
2800};
2801static const unsigned int scif3_ctrl_pins[] = {
2802 /* RTS, CTS */
2803 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2804};
2805static const unsigned int scif3_ctrl_mux[] = {
2806 RTS3_N_TANS_MARK, CTS3_N_MARK,
2807};
2808static const unsigned int scif3_data_b_pins[] = {
2809 /* RX, TX */
2810 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2811};
2812static const unsigned int scif3_data_b_mux[] = {
2813 RX3_B_MARK, TX3_B_MARK,
2814};
2815/* - SCIF4 ------------------------------------------------------------------ */
2816static const unsigned int scif4_data_a_pins[] = {
2817 /* RX, TX */
2818 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2819};
2820static const unsigned int scif4_data_a_mux[] = {
2821 RX4_A_MARK, TX4_A_MARK,
2822};
2823static const unsigned int scif4_clk_a_pins[] = {
2824 /* SCK */
2825 RCAR_GP_PIN(2, 10),
2826};
2827static const unsigned int scif4_clk_a_mux[] = {
2828 SCK4_A_MARK,
2829};
2830static const unsigned int scif4_ctrl_a_pins[] = {
2831 /* RTS, CTS */
2832 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2833};
2834static const unsigned int scif4_ctrl_a_mux[] = {
2835 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2836};
2837static const unsigned int scif4_data_b_pins[] = {
2838 /* RX, TX */
2839 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2840};
2841static const unsigned int scif4_data_b_mux[] = {
2842 RX4_B_MARK, TX4_B_MARK,
2843};
2844static const unsigned int scif4_clk_b_pins[] = {
2845 /* SCK */
2846 RCAR_GP_PIN(1, 5),
2847};
2848static const unsigned int scif4_clk_b_mux[] = {
2849 SCK4_B_MARK,
2850};
2851static const unsigned int scif4_ctrl_b_pins[] = {
2852 /* RTS, CTS */
2853 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2854};
2855static const unsigned int scif4_ctrl_b_mux[] = {
2856 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2857};
2858static const unsigned int scif4_data_c_pins[] = {
2859 /* RX, TX */
2860 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2861};
2862static const unsigned int scif4_data_c_mux[] = {
2863 RX4_C_MARK, TX4_C_MARK,
2864};
2865static const unsigned int scif4_clk_c_pins[] = {
2866 /* SCK */
2867 RCAR_GP_PIN(0, 8),
2868};
2869static const unsigned int scif4_clk_c_mux[] = {
2870 SCK4_C_MARK,
2871};
2872static const unsigned int scif4_ctrl_c_pins[] = {
2873 /* RTS, CTS */
2874 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2875};
2876static const unsigned int scif4_ctrl_c_mux[] = {
2877 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2878};
2879/* - SCIF5 ------------------------------------------------------------------ */
2880static const unsigned int scif5_data_pins[] = {
2881 /* RX, TX */
2882 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2883};
2884static const unsigned int scif5_data_mux[] = {
2885 RX5_MARK, TX5_MARK,
2886};
2887static const unsigned int scif5_clk_pins[] = {
2888 /* SCK */
2889 RCAR_GP_PIN(6, 21),
2890};
2891static const unsigned int scif5_clk_mux[] = {
2892 SCK5_MARK,
2893};
20cacae1
TK		 2894/* - SDHI0 ------------------------------------------------------------------ */
2895static const unsigned int sdhi0_data1_pins[] = {
2896 /* D0 */
2897 RCAR_GP_PIN(3, 2),
2898};
2899static const unsigned int sdhi0_data1_mux[] = {
2900 SD0_DAT0_MARK,
2901};
2902static const unsigned int sdhi0_data4_pins[] = {
2903 /* D[0:3] */
2904 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2905 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2906};
2907static const unsigned int sdhi0_data4_mux[] = {
2908 SD0_DAT0_MARK, SD0_DAT1_MARK,
2909 SD0_DAT2_MARK, SD0_DAT3_MARK,
2910};
2911static const unsigned int sdhi0_ctrl_pins[] = {
2912 /* CLK, CMD */
2913 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2914};
2915static const unsigned int sdhi0_ctrl_mux[] = {
2916 SD0_CLK_MARK, SD0_CMD_MARK,
2917};
2918static const unsigned int sdhi0_cd_pins[] = {
2919 /* CD */
2920 RCAR_GP_PIN(3, 12),
2921};
2922static const unsigned int sdhi0_cd_mux[] = {
2923 SD0_CD_MARK,
2924};
2925static const unsigned int sdhi0_wp_pins[] = {
2926 /* WP */
2927 RCAR_GP_PIN(3, 13),
2928};
2929static const unsigned int sdhi0_wp_mux[] = {
2930 SD0_WP_MARK,
2931};
2932/* - SDHI1 ------------------------------------------------------------------ */
2933static const unsigned int sdhi1_data1_pins[] = {
2934 /* D0 */
2935 RCAR_GP_PIN(3, 8),
2936};
2937static const unsigned int sdhi1_data1_mux[] = {
2938 SD1_DAT0_MARK,
2939};
2940static const unsigned int sdhi1_data4_pins[] = {
2941 /* D[0:3] */
2942 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2943 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2944};
2945static const unsigned int sdhi1_data4_mux[] = {
2946 SD1_DAT0_MARK, SD1_DAT1_MARK,
2947 SD1_DAT2_MARK, SD1_DAT3_MARK,
2948};
2949static const unsigned int sdhi1_ctrl_pins[] = {
2950 /* CLK, CMD */
2951 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2952};
2953static const unsigned int sdhi1_ctrl_mux[] = {
2954 SD1_CLK_MARK, SD1_CMD_MARK,
2955};
2956static const unsigned int sdhi1_cd_pins[] = {
2957 /* CD */
2958 RCAR_GP_PIN(3, 14),
2959};
2960static const unsigned int sdhi1_cd_mux[] = {
2961 SD1_CD_MARK,
2962};
2963static const unsigned int sdhi1_wp_pins[] = {
2964 /* WP */
2965 RCAR_GP_PIN(3, 15),
2966};
2967static const unsigned int sdhi1_wp_mux[] = {
2968 SD1_WP_MARK,
2969};
2970/* - SDHI2 ------------------------------------------------------------------ */
2971static const unsigned int sdhi2_data1_pins[] = {
2972 /* D0 */
2973 RCAR_GP_PIN(4, 2),
2974};
2975static const unsigned int sdhi2_data1_mux[] = {
2976 SD2_DAT0_MARK,
2977};
2978static const unsigned int sdhi2_data4_pins[] = {
2979 /* D[0:3] */
2980 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2981 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2982};
2983static const unsigned int sdhi2_data4_mux[] = {
2984 SD2_DAT0_MARK, SD2_DAT1_MARK,
2985 SD2_DAT2_MARK, SD2_DAT3_MARK,
2986};
2987static const unsigned int sdhi2_data8_pins[] = {
2988 /* D[0:7] */
2989 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2990 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2991 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2992 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2993};
2994static const unsigned int sdhi2_data8_mux[] = {
2995 SD2_DAT0_MARK, SD2_DAT1_MARK,
2996 SD2_DAT2_MARK, SD2_DAT3_MARK,
2997 SD2_DAT4_MARK, SD2_DAT5_MARK,
2998 SD2_DAT6_MARK, SD2_DAT7_MARK,
2999};
3000static const unsigned int sdhi2_ctrl_pins[] = {
3001 /* CLK, CMD */
3002 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3003};
3004static const unsigned int sdhi2_ctrl_mux[] = {
3005 SD2_CLK_MARK, SD2_CMD_MARK,
3006};
3007static const unsigned int sdhi2_cd_a_pins[] = {
3008 /* CD */
3009 RCAR_GP_PIN(4, 13),
3010};
3011static const unsigned int sdhi2_cd_a_mux[] = {
3012 SD2_CD_A_MARK,
3013};
3014static const unsigned int sdhi2_cd_b_pins[] = {
3015 /* CD */
3016 RCAR_GP_PIN(5, 10),
3017};
3018static const unsigned int sdhi2_cd_b_mux[] = {
3019 SD2_CD_B_MARK,
3020};
3021static const unsigned int sdhi2_wp_a_pins[] = {
3022 /* WP */
3023 RCAR_GP_PIN(4, 14),
3024};
3025static const unsigned int sdhi2_wp_a_mux[] = {
3026 SD2_WP_A_MARK,
3027};
3028static const unsigned int sdhi2_wp_b_pins[] = {
3029 /* WP */
3030 RCAR_GP_PIN(5, 11),
3031};
3032static const unsigned int sdhi2_wp_b_mux[] = {
3033 SD2_WP_B_MARK,
3034};
3035static const unsigned int sdhi2_ds_pins[] = {
3036 /* DS */
3037 RCAR_GP_PIN(4, 6),
3038};
3039static const unsigned int sdhi2_ds_mux[] = {
3040 SD2_DS_MARK,
3041};
3042/* - SDHI3 ------------------------------------------------------------------ */
3043static const unsigned int sdhi3_data1_pins[] = {
3044 /* D0 */
3045 RCAR_GP_PIN(4, 9),
3046};
3047static const unsigned int sdhi3_data1_mux[] = {
3048 SD3_DAT0_MARK,
3049};
3050static const unsigned int sdhi3_data4_pins[] = {
3051 /* D[0:3] */
3052 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3053 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3054};
3055static const unsigned int sdhi3_data4_mux[] = {
3056 SD3_DAT0_MARK, SD3_DAT1_MARK,
3057 SD3_DAT2_MARK, SD3_DAT3_MARK,
3058};
3059static const unsigned int sdhi3_data8_pins[] = {
3060 /* D[0:7] */
3061 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3062 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3063 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3064 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3065};
3066static const unsigned int sdhi3_data8_mux[] = {
3067 SD3_DAT0_MARK, SD3_DAT1_MARK,
3068 SD3_DAT2_MARK, SD3_DAT3_MARK,
3069 SD3_DAT4_MARK, SD3_DAT5_MARK,
3070 SD3_DAT6_MARK, SD3_DAT7_MARK,
3071};
3072static const unsigned int sdhi3_ctrl_pins[] = {
3073 /* CLK, CMD */
3074 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3075};
3076static const unsigned int sdhi3_ctrl_mux[] = {
3077 SD3_CLK_MARK, SD3_CMD_MARK,
3078};
3079static const unsigned int sdhi3_cd_pins[] = {
3080 /* CD */
3081 RCAR_GP_PIN(4, 15),
3082};
3083static const unsigned int sdhi3_cd_mux[] = {
3084 SD3_CD_MARK,
3085};
3086static const unsigned int sdhi3_wp_pins[] = {
3087 /* WP */
3088 RCAR_GP_PIN(4, 16),
3089};
3090static const unsigned int sdhi3_wp_mux[] = {
3091 SD3_WP_MARK,
3092};
3093static const unsigned int sdhi3_ds_pins[] = {
3094 /* DS */
3095 RCAR_GP_PIN(4, 17),
3096};
3097static const unsigned int sdhi3_ds_mux[] = {
3098 SD3_DS_MARK,
3099};
ff8459a5 3100
f27200f9
GU		 3101/* - SCIF Clock ------------------------------------------------------------- */
3102static const unsigned int scif_clk_a_pins[] = {
3103 /* SCIF_CLK */
3104 RCAR_GP_PIN(6, 23),
3105};
3106static const unsigned int scif_clk_a_mux[] = {
3107 SCIF_CLK_A_MARK,
3108};
3109static const unsigned int scif_clk_b_pins[] = {
3110 /* SCIF_CLK */
3111 RCAR_GP_PIN(5, 9),
3112};
3113static const unsigned int scif_clk_b_mux[] = {
3114 SCIF_CLK_B_MARK,
3115};
3116
9b132ba3
KM		 3117/* - SSI -------------------------------------------------------------------- */
3118static const unsigned int ssi0_data_pins[] = {
3119 /* SDATA */
3120 RCAR_GP_PIN(6, 2),
3121};
3122static const unsigned int ssi0_data_mux[] = {
3123 SSI_SDATA0_MARK,
3124};
3125static const unsigned int ssi01239_ctrl_pins[] = {
3126 /* SCK, WS */
3127 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3128};
3129static const unsigned int ssi01239_ctrl_mux[] = {
00edf542 3130 SSI_SCK01239_MARK, SSI_WS01239_MARK,
9b132ba3
KM		 3131};
3132static const unsigned int ssi1_data_a_pins[] = {
3133 /* SDATA */
3134 RCAR_GP_PIN(6, 3),
3135};
3136static const unsigned int ssi1_data_a_mux[] = {
3137 SSI_SDATA1_A_MARK,
3138};
3139static const unsigned int ssi1_data_b_pins[] = {
3140 /* SDATA */
3141 RCAR_GP_PIN(5, 12),
3142};
3143static const unsigned int ssi1_data_b_mux[] = {
3144 SSI_SDATA1_B_MARK,
3145};
3146static const unsigned int ssi1_ctrl_a_pins[] = {
3147 /* SCK, WS */
3148 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3149};
3150static const unsigned int ssi1_ctrl_a_mux[] = {
3151 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3152};
3153static const unsigned int ssi1_ctrl_b_pins[] = {
3154 /* SCK, WS */
3155 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3156};
3157static const unsigned int ssi1_ctrl_b_mux[] = {
3158 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3159};
3160static const unsigned int ssi2_data_a_pins[] = {
3161 /* SDATA */
3162 RCAR_GP_PIN(6, 4),
3163};
3164static const unsigned int ssi2_data_a_mux[] = {
3165 SSI_SDATA2_A_MARK,
3166};
3167static const unsigned int ssi2_data_b_pins[] = {
3168 /* SDATA */
3169 RCAR_GP_PIN(5, 13),
3170};
3171static const unsigned int ssi2_data_b_mux[] = {
3172 SSI_SDATA2_B_MARK,
3173};
3174static const unsigned int ssi2_ctrl_a_pins[] = {
3175 /* SCK, WS */
3176 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3177};
3178static const unsigned int ssi2_ctrl_a_mux[] = {
3179 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3180};
3181static const unsigned int ssi2_ctrl_b_pins[] = {
3182 /* SCK, WS */
3183 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3184};
3185static const unsigned int ssi2_ctrl_b_mux[] = {
3186 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3187};
3188static const unsigned int ssi3_data_pins[] = {
3189 /* SDATA */
3190 RCAR_GP_PIN(6, 7),
3191};
3192static const unsigned int ssi3_data_mux[] = {
3193 SSI_SDATA3_MARK,
3194};
3195static const unsigned int ssi34_ctrl_pins[] = {
3196 /* SCK, WS */
3197 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3198};
3199static const unsigned int ssi34_ctrl_mux[] = {
3200 SSI_SCK34_MARK, SSI_WS34_MARK,
3201};
3202static const unsigned int ssi4_data_pins[] = {
3203 /* SDATA */
3204 RCAR_GP_PIN(6, 10),
3205};
3206static const unsigned int ssi4_data_mux[] = {
3207 SSI_SDATA4_MARK,
3208};
3209static const unsigned int ssi4_ctrl_pins[] = {
3210 /* SCK, WS */
3211 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3212};
3213static const unsigned int ssi4_ctrl_mux[] = {
3214 SSI_SCK4_MARK, SSI_WS4_MARK,
3215};
3216static const unsigned int ssi5_data_pins[] = {
3217 /* SDATA */
3218 RCAR_GP_PIN(6, 13),
3219};
3220static const unsigned int ssi5_data_mux[] = {
3221 SSI_SDATA5_MARK,
3222};
3223static const unsigned int ssi5_ctrl_pins[] = {
3224 /* SCK, WS */
3225 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3226};
3227static const unsigned int ssi5_ctrl_mux[] = {
3228 SSI_SCK5_MARK, SSI_WS5_MARK,
3229};
3230static const unsigned int ssi6_data_pins[] = {
3231 /* SDATA */
3232 RCAR_GP_PIN(6, 16),
3233};
3234static const unsigned int ssi6_data_mux[] = {
3235 SSI_SDATA6_MARK,
3236};
3237static const unsigned int ssi6_ctrl_pins[] = {
3238 /* SCK, WS */
3239 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3240};
3241static const unsigned int ssi6_ctrl_mux[] = {
3242 SSI_SCK6_MARK, SSI_WS6_MARK,
3243};
3244static const unsigned int ssi7_data_pins[] = {
3245 /* SDATA */
3246 RCAR_GP_PIN(6, 19),
3247};
3248static const unsigned int ssi7_data_mux[] = {
3249 SSI_SDATA7_MARK,
3250};
3251static const unsigned int ssi78_ctrl_pins[] = {
3252 /* SCK, WS */
3253 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3254};
3255static const unsigned int ssi78_ctrl_mux[] = {
3256 SSI_SCK78_MARK, SSI_WS78_MARK,
3257};
3258static const unsigned int ssi8_data_pins[] = {
3259 /* SDATA */
3260 RCAR_GP_PIN(6, 20),
3261};
3262static const unsigned int ssi8_data_mux[] = {
3263 SSI_SDATA8_MARK,
3264};
3265static const unsigned int ssi9_data_a_pins[] = {
3266 /* SDATA */
3267 RCAR_GP_PIN(6, 21),
3268};
3269static const unsigned int ssi9_data_a_mux[] = {
3270 SSI_SDATA9_A_MARK,
3271};
3272static const unsigned int ssi9_data_b_pins[] = {
3273 /* SDATA */
3274 RCAR_GP_PIN(5, 14),
3275};
3276static const unsigned int ssi9_data_b_mux[] = {
3277 SSI_SDATA9_B_MARK,
3278};
3279static const unsigned int ssi9_ctrl_a_pins[] = {
3280 /* SCK, WS */
3281 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3282};
3283static const unsigned int ssi9_ctrl_a_mux[] = {
3284 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3285};
3286static const unsigned int ssi9_ctrl_b_pins[] = {
3287 /* SCK, WS */
3288 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3289};
3290static const unsigned int ssi9_ctrl_b_mux[] = {
3291 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3292};
3293
76250a6c
TK		 3294/* - USB0 ------------------------------------------------------------------- */
3295static const unsigned int usb0_pins[] = {
3296 /* PWEN, OVC */
3297 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3298};
3299static const unsigned int usb0_mux[] = {
3300 USB0_PWEN_MARK, USB0_OVC_MARK,
3301};
3302/* - USB1 ------------------------------------------------------------------- */
3303static const unsigned int usb1_pins[] = {
3304 /* PWEN, OVC */
3305 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3306};
3307static const unsigned int usb1_mux[] = {
3308 USB1_PWEN_MARK, USB1_OVC_MARK,
3309};
3310/* - USB2 ------------------------------------------------------------------- */
3311static const unsigned int usb2_pins[] = {
3312 /* PWEN, OVC */
3313 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3314};
3315static const unsigned int usb2_mux[] = {
3316 USB2_PWEN_MARK, USB2_OVC_MARK,
3317};
3318
0b0ffc96 3319static const struct sh_pfc_pin_group pinmux_groups[] = {
c33a7fe3
KM		 3320 SH_PFC_PIN_GROUP(audio_clk_a_a),
3321 SH_PFC_PIN_GROUP(audio_clk_a_b),
3322 SH_PFC_PIN_GROUP(audio_clk_a_c),
3323 SH_PFC_PIN_GROUP(audio_clk_b_a),
3324 SH_PFC_PIN_GROUP(audio_clk_b_b),
3325 SH_PFC_PIN_GROUP(audio_clk_c_a),
3326 SH_PFC_PIN_GROUP(audio_clk_c_b),
3327 SH_PFC_PIN_GROUP(audio_clkout_a),
3328 SH_PFC_PIN_GROUP(audio_clkout_b),
3329 SH_PFC_PIN_GROUP(audio_clkout_c),
3330 SH_PFC_PIN_GROUP(audio_clkout_d),
3331 SH_PFC_PIN_GROUP(audio_clkout1_a),
3332 SH_PFC_PIN_GROUP(audio_clkout1_b),
3333 SH_PFC_PIN_GROUP(audio_clkout2_a),
3334 SH_PFC_PIN_GROUP(audio_clkout2_b),
3335 SH_PFC_PIN_GROUP(audio_clkout3_a),
3336 SH_PFC_PIN_GROUP(audio_clkout3_b),
819fd4bf
TK		 3337 SH_PFC_PIN_GROUP(avb_link),
3338 SH_PFC_PIN_GROUP(avb_magic),
3339 SH_PFC_PIN_GROUP(avb_phy_int),
3340 SH_PFC_PIN_GROUP(avb_mdc),
3341 SH_PFC_PIN_GROUP(avb_avtp_pps),
3342 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3343 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3344 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3345 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a4d9791f
RS		 3346 SH_PFC_PIN_GROUP(can0_data_a),
3347 SH_PFC_PIN_GROUP(can0_data_b),
3348 SH_PFC_PIN_GROUP(can1_data),
3349 SH_PFC_PIN_GROUP(can_clk),
4412bb5d
RS		 3350 SH_PFC_PIN_GROUP(canfd0_data_a),
3351 SH_PFC_PIN_GROUP(canfd0_data_b),
3352 SH_PFC_PIN_GROUP(canfd1_data),
a56069c4
GU		 3353 SH_PFC_PIN_GROUP(hscif0_data),
3354 SH_PFC_PIN_GROUP(hscif0_clk),
3355 SH_PFC_PIN_GROUP(hscif0_ctrl),
3356 SH_PFC_PIN_GROUP(hscif1_data_a),
3357 SH_PFC_PIN_GROUP(hscif1_clk_a),
3358 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3359 SH_PFC_PIN_GROUP(hscif1_data_b),
3360 SH_PFC_PIN_GROUP(hscif1_clk_b),
3361 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3362 SH_PFC_PIN_GROUP(hscif2_data_a),
3363 SH_PFC_PIN_GROUP(hscif2_clk_a),
3364 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3365 SH_PFC_PIN_GROUP(hscif2_data_b),
3366 SH_PFC_PIN_GROUP(hscif2_clk_b),
3367 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3368 SH_PFC_PIN_GROUP(hscif3_data_a),
3369 SH_PFC_PIN_GROUP(hscif3_clk),
3370 SH_PFC_PIN_GROUP(hscif3_ctrl),
3371 SH_PFC_PIN_GROUP(hscif3_data_b),
3372 SH_PFC_PIN_GROUP(hscif3_data_c),
3373 SH_PFC_PIN_GROUP(hscif3_data_d),
3374 SH_PFC_PIN_GROUP(hscif4_data_a),
3375 SH_PFC_PIN_GROUP(hscif4_clk),
3376 SH_PFC_PIN_GROUP(hscif4_ctrl),
3377 SH_PFC_PIN_GROUP(hscif4_data_b),
2544ef72
KM		 3378 SH_PFC_PIN_GROUP(i2c1_a),
3379 SH_PFC_PIN_GROUP(i2c1_b),
3380 SH_PFC_PIN_GROUP(i2c2_a),
3381 SH_PFC_PIN_GROUP(i2c2_b),
3382 SH_PFC_PIN_GROUP(i2c6_a),
3383 SH_PFC_PIN_GROUP(i2c6_b),
3384 SH_PFC_PIN_GROUP(i2c6_c),
bb46f6f3
MD		 3385 SH_PFC_PIN_GROUP(intc_ex_irq0),
3386 SH_PFC_PIN_GROUP(intc_ex_irq1),
3387 SH_PFC_PIN_GROUP(intc_ex_irq2),
3388 SH_PFC_PIN_GROUP(intc_ex_irq3),
3389 SH_PFC_PIN_GROUP(intc_ex_irq4),
3390 SH_PFC_PIN_GROUP(intc_ex_irq5),
e7419b81
GU		 3391 SH_PFC_PIN_GROUP(msiof0_clk),
3392 SH_PFC_PIN_GROUP(msiof0_sync),
3393 SH_PFC_PIN_GROUP(msiof0_ss1),
3394 SH_PFC_PIN_GROUP(msiof0_ss2),
3395 SH_PFC_PIN_GROUP(msiof0_txd),
3396 SH_PFC_PIN_GROUP(msiof0_rxd),
3397 SH_PFC_PIN_GROUP(msiof1_clk_a),
3398 SH_PFC_PIN_GROUP(msiof1_sync_a),
3399 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3400 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3401 SH_PFC_PIN_GROUP(msiof1_txd_a),
3402 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3403 SH_PFC_PIN_GROUP(msiof1_clk_b),
3404 SH_PFC_PIN_GROUP(msiof1_sync_b),
3405 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3406 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3407 SH_PFC_PIN_GROUP(msiof1_txd_b),
3408 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3409 SH_PFC_PIN_GROUP(msiof1_clk_c),
3410 SH_PFC_PIN_GROUP(msiof1_sync_c),
3411 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3412 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3413 SH_PFC_PIN_GROUP(msiof1_txd_c),
3414 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3415 SH_PFC_PIN_GROUP(msiof1_clk_d),
3416 SH_PFC_PIN_GROUP(msiof1_sync_d),
3417 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3418 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3419 SH_PFC_PIN_GROUP(msiof1_txd_d),
3420 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3421 SH_PFC_PIN_GROUP(msiof1_clk_e),
3422 SH_PFC_PIN_GROUP(msiof1_sync_e),
3423 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3424 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3425 SH_PFC_PIN_GROUP(msiof1_txd_e),
3426 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3427 SH_PFC_PIN_GROUP(msiof1_clk_f),
3428 SH_PFC_PIN_GROUP(msiof1_sync_f),
3429 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3430 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3431 SH_PFC_PIN_GROUP(msiof1_txd_f),
3432 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3433 SH_PFC_PIN_GROUP(msiof1_clk_g),
3434 SH_PFC_PIN_GROUP(msiof1_sync_g),
3435 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3436 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3437 SH_PFC_PIN_GROUP(msiof1_txd_g),
3438 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3439 SH_PFC_PIN_GROUP(msiof2_clk_a),
3440 SH_PFC_PIN_GROUP(msiof2_sync_a),
3441 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3442 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3443 SH_PFC_PIN_GROUP(msiof2_txd_a),
3444 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3445 SH_PFC_PIN_GROUP(msiof2_clk_b),
3446 SH_PFC_PIN_GROUP(msiof2_sync_b),
3447 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3448 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3449 SH_PFC_PIN_GROUP(msiof2_txd_b),
3450 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3451 SH_PFC_PIN_GROUP(msiof2_clk_c),
3452 SH_PFC_PIN_GROUP(msiof2_sync_c),
3453 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3454 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3455 SH_PFC_PIN_GROUP(msiof2_txd_c),
3456 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3457 SH_PFC_PIN_GROUP(msiof2_clk_d),
3458 SH_PFC_PIN_GROUP(msiof2_sync_d),
3459 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3460 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3461 SH_PFC_PIN_GROUP(msiof2_txd_d),
3462 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3463 SH_PFC_PIN_GROUP(msiof3_clk_a),
3464 SH_PFC_PIN_GROUP(msiof3_sync_a),
3465 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3466 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3467 SH_PFC_PIN_GROUP(msiof3_txd_a),
3468 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3469 SH_PFC_PIN_GROUP(msiof3_clk_b),
3470 SH_PFC_PIN_GROUP(msiof3_sync_b),
3471 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3472 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3473 SH_PFC_PIN_GROUP(msiof3_txd_b),
3474 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3475 SH_PFC_PIN_GROUP(msiof3_clk_c),
3476 SH_PFC_PIN_GROUP(msiof3_sync_c),
3477 SH_PFC_PIN_GROUP(msiof3_txd_c),
3478 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3479 SH_PFC_PIN_GROUP(msiof3_clk_d),
3480 SH_PFC_PIN_GROUP(msiof3_sync_d),
3481 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3482 SH_PFC_PIN_GROUP(msiof3_txd_d),
3483 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4ca88cf6
TK		 3484 SH_PFC_PIN_GROUP(pwm0),
3485 SH_PFC_PIN_GROUP(pwm1_a),
3486 SH_PFC_PIN_GROUP(pwm1_b),
3487 SH_PFC_PIN_GROUP(pwm2_a),
3488 SH_PFC_PIN_GROUP(pwm2_b),
3489 SH_PFC_PIN_GROUP(pwm3_a),
3490 SH_PFC_PIN_GROUP(pwm3_b),
3491 SH_PFC_PIN_GROUP(pwm4_a),
3492 SH_PFC_PIN_GROUP(pwm4_b),
3493 SH_PFC_PIN_GROUP(pwm5_a),
3494 SH_PFC_PIN_GROUP(pwm5_b),
3495 SH_PFC_PIN_GROUP(pwm6_a),
3496 SH_PFC_PIN_GROUP(pwm6_b),
34dc4e16
TK		 3497 SH_PFC_PIN_GROUP(sata0_devslp_a),
3498 SH_PFC_PIN_GROUP(sata0_devslp_b),
ff8459a5
GU		 3499 SH_PFC_PIN_GROUP(scif0_data),
3500 SH_PFC_PIN_GROUP(scif0_clk),
3501 SH_PFC_PIN_GROUP(scif0_ctrl),
3502 SH_PFC_PIN_GROUP(scif1_data_a),
3503 SH_PFC_PIN_GROUP(scif1_clk),
3504 SH_PFC_PIN_GROUP(scif1_ctrl),
3505 SH_PFC_PIN_GROUP(scif1_data_b),
3506 SH_PFC_PIN_GROUP(scif2_data_a),
3507 SH_PFC_PIN_GROUP(scif2_clk),
3508 SH_PFC_PIN_GROUP(scif2_data_b),
3509 SH_PFC_PIN_GROUP(scif3_data_a),
3510 SH_PFC_PIN_GROUP(scif3_clk),
3511 SH_PFC_PIN_GROUP(scif3_ctrl),
3512 SH_PFC_PIN_GROUP(scif3_data_b),
3513 SH_PFC_PIN_GROUP(scif4_data_a),
3514 SH_PFC_PIN_GROUP(scif4_clk_a),
3515 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3516 SH_PFC_PIN_GROUP(scif4_data_b),
3517 SH_PFC_PIN_GROUP(scif4_clk_b),
3518 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3519 SH_PFC_PIN_GROUP(scif4_data_c),
3520 SH_PFC_PIN_GROUP(scif4_clk_c),
3521 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3522 SH_PFC_PIN_GROUP(scif5_data),
3523 SH_PFC_PIN_GROUP(scif5_clk),
f27200f9
GU		 3524 SH_PFC_PIN_GROUP(scif_clk_a),
3525 SH_PFC_PIN_GROUP(scif_clk_b),
20cacae1
TK		 3526 SH_PFC_PIN_GROUP(sdhi0_data1),
3527 SH_PFC_PIN_GROUP(sdhi0_data4),
3528 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3529 SH_PFC_PIN_GROUP(sdhi0_cd),
3530 SH_PFC_PIN_GROUP(sdhi0_wp),
3531 SH_PFC_PIN_GROUP(sdhi1_data1),
3532 SH_PFC_PIN_GROUP(sdhi1_data4),
3533 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3534 SH_PFC_PIN_GROUP(sdhi1_cd),
3535 SH_PFC_PIN_GROUP(sdhi1_wp),
3536 SH_PFC_PIN_GROUP(sdhi2_data1),
3537 SH_PFC_PIN_GROUP(sdhi2_data4),
3538 SH_PFC_PIN_GROUP(sdhi2_data8),
3539 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3540 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3541 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3542 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3543 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3544 SH_PFC_PIN_GROUP(sdhi2_ds),
3545 SH_PFC_PIN_GROUP(sdhi3_data1),
3546 SH_PFC_PIN_GROUP(sdhi3_data4),
3547 SH_PFC_PIN_GROUP(sdhi3_data8),
3548 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3549 SH_PFC_PIN_GROUP(sdhi3_cd),
3550 SH_PFC_PIN_GROUP(sdhi3_wp),
3551 SH_PFC_PIN_GROUP(sdhi3_ds),
9b132ba3
KM		 3552 SH_PFC_PIN_GROUP(ssi0_data),
3553 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3554 SH_PFC_PIN_GROUP(ssi1_data_a),
3555 SH_PFC_PIN_GROUP(ssi1_data_b),
3556 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3557 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3558 SH_PFC_PIN_GROUP(ssi2_data_a),
3559 SH_PFC_PIN_GROUP(ssi2_data_b),
3560 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3561 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3562 SH_PFC_PIN_GROUP(ssi3_data),
3563 SH_PFC_PIN_GROUP(ssi34_ctrl),
3564 SH_PFC_PIN_GROUP(ssi4_data),
3565 SH_PFC_PIN_GROUP(ssi4_ctrl),
3566 SH_PFC_PIN_GROUP(ssi5_data),
3567 SH_PFC_PIN_GROUP(ssi5_ctrl),
3568 SH_PFC_PIN_GROUP(ssi6_data),
3569 SH_PFC_PIN_GROUP(ssi6_ctrl),
3570 SH_PFC_PIN_GROUP(ssi7_data),
3571 SH_PFC_PIN_GROUP(ssi78_ctrl),
3572 SH_PFC_PIN_GROUP(ssi8_data),
3573 SH_PFC_PIN_GROUP(ssi9_data_a),
3574 SH_PFC_PIN_GROUP(ssi9_data_b),
3575 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3576 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
76250a6c
TK		 3577 SH_PFC_PIN_GROUP(usb0),
3578 SH_PFC_PIN_GROUP(usb1),
3579 SH_PFC_PIN_GROUP(usb2),
ff8459a5
GU		 3580};
3581
c33a7fe3
KM		 3582static const char * const audio_clk_groups[] = {
3583 "audio_clk_a_a",
3584 "audio_clk_a_b",
3585 "audio_clk_a_c",
3586 "audio_clk_b_a",
3587 "audio_clk_b_b",
3588 "audio_clk_c_a",
3589 "audio_clk_c_b",
3590 "audio_clkout_a",
3591 "audio_clkout_b",
3592 "audio_clkout_c",
3593 "audio_clkout_d",
3594 "audio_clkout1_a",
3595 "audio_clkout1_b",
3596 "audio_clkout2_a",
3597 "audio_clkout2_b",
3598 "audio_clkout3_a",
3599 "audio_clkout3_b",
3600};
3601
819fd4bf
TK		 3602static const char * const avb_groups[] = {
3603 "avb_link",
3604 "avb_magic",
3605 "avb_phy_int",
3606 "avb_mdc",
3607 "avb_avtp_pps",
3608 "avb_avtp_match_a",
3609 "avb_avtp_capture_a",
3610 "avb_avtp_match_b",
3611 "avb_avtp_capture_b",
3612};
3613
a4d9791f
RS		 3614static const char * const can0_groups[] = {
3615 "can0_data_a",
3616 "can0_data_b",
3617};
3618
3619static const char * const can1_groups[] = {
3620 "can1_data",
3621};
3622
3623static const char * const can_clk_groups[] = {
3624 "can_clk",
3625};
3626
4412bb5d
RS		 3627static const char * const canfd0_groups[] = {
3628 "canfd0_data_a",
3629 "canfd0_data_b",
3630};
3631
3632static const char * const canfd1_groups[] = {
3633 "canfd1_data",
3634};
3635
a56069c4
GU		 3636static const char * const hscif0_groups[] = {
3637 "hscif0_data",
3638 "hscif0_clk",
3639 "hscif0_ctrl",
3640};
3641
3642static const char * const hscif1_groups[] = {
3643 "hscif1_data_a",
3644 "hscif1_clk_a",
3645 "hscif1_ctrl_a",
3646 "hscif1_data_b",
3647 "hscif1_clk_b",
3648 "hscif1_ctrl_b",
3649};
3650
3651static const char * const hscif2_groups[] = {
3652 "hscif2_data_a",
3653 "hscif2_clk_a",
3654 "hscif2_ctrl_a",
3655 "hscif2_data_b",
3656 "hscif2_clk_b",
3657 "hscif2_ctrl_b",
3658};
3659
3660static const char * const hscif3_groups[] = {
3661 "hscif3_data_a",
3662 "hscif3_clk",
3663 "hscif3_ctrl",
3664 "hscif3_data_b",
3665 "hscif3_data_c",
3666 "hscif3_data_d",
3667};
3668
3669static const char * const hscif4_groups[] = {
3670 "hscif4_data_a",
3671 "hscif4_clk",
3672 "hscif4_ctrl",
3673 "hscif4_data_b",
3674};
3675
2544ef72
KM		 3676static const char * const i2c1_groups[] = {
3677 "i2c1_a",
3678 "i2c1_b",
3679};
3680
3681static const char * const i2c2_groups[] = {
3682 "i2c2_a",
3683 "i2c2_b",
3684};
3685
3686static const char * const i2c6_groups[] = {
3687 "i2c6_a",
3688 "i2c6_b",
3689 "i2c6_c",
3690};
3691
bb46f6f3
MD		 3692static const char * const intc_ex_groups[] = {
3693 "intc_ex_irq0",
3694 "intc_ex_irq1",
3695 "intc_ex_irq2",
3696 "intc_ex_irq3",
3697 "intc_ex_irq4",
3698 "intc_ex_irq5",
3699};
3700
e7419b81
GU		 3701static const char * const msiof0_groups[] = {
3702 "msiof0_clk",
3703 "msiof0_sync",
3704 "msiof0_ss1",
3705 "msiof0_ss2",
3706 "msiof0_txd",
3707 "msiof0_rxd",
3708};
3709
3710static const char * const msiof1_groups[] = {
3711 "msiof1_clk_a",
3712 "msiof1_sync_a",
3713 "msiof1_ss1_a",
3714 "msiof1_ss2_a",
3715 "msiof1_txd_a",
3716 "msiof1_rxd_a",
3717 "msiof1_clk_b",
3718 "msiof1_sync_b",
3719 "msiof1_ss1_b",
3720 "msiof1_ss2_b",
3721 "msiof1_txd_b",
3722 "msiof1_rxd_b",
3723 "msiof1_clk_c",
3724 "msiof1_sync_c",
3725 "msiof1_ss1_c",
3726 "msiof1_ss2_c",
3727 "msiof1_txd_c",
3728 "msiof1_rxd_c",
3729 "msiof1_clk_d",
3730 "msiof1_sync_d",
3731 "msiof1_ss1_d",
3732 "msiof1_ss2_d",
3733 "msiof1_txd_d",
3734 "msiof1_rxd_d",
3735 "msiof1_clk_e",
3736 "msiof1_sync_e",
3737 "msiof1_ss1_e",
3738 "msiof1_ss2_e",
3739 "msiof1_txd_e",
3740 "msiof1_rxd_e",
3741 "msiof1_clk_f",
3742 "msiof1_sync_f",
3743 "msiof1_ss1_f",
3744 "msiof1_ss2_f",
3745 "msiof1_txd_f",
3746 "msiof1_rxd_f",
3747 "msiof1_clk_g",
3748 "msiof1_sync_g",
3749 "msiof1_ss1_g",
3750 "msiof1_ss2_g",
3751 "msiof1_txd_g",
3752 "msiof1_rxd_g",
3753};
3754
3755static const char * const msiof2_groups[] = {
3756 "msiof2_clk_a",
3757 "msiof2_sync_a",
3758 "msiof2_ss1_a",
3759 "msiof2_ss2_a",
3760 "msiof2_txd_a",
3761 "msiof2_rxd_a",
3762 "msiof2_clk_b",
3763 "msiof2_sync_b",
3764 "msiof2_ss1_b",
3765 "msiof2_ss2_b",
3766 "msiof2_txd_b",
3767 "msiof2_rxd_b",
3768 "msiof2_clk_c",
3769 "msiof2_sync_c",
3770 "msiof2_ss1_c",
3771 "msiof2_ss2_c",
3772 "msiof2_txd_c",
3773 "msiof2_rxd_c",
3774 "msiof2_clk_d",
3775 "msiof2_sync_d",
3776 "msiof2_ss1_d",
3777 "msiof2_ss2_d",
3778 "msiof2_txd_d",
3779 "msiof2_rxd_d",
3780};
3781
3782static const char * const msiof3_groups[] = {
3783 "msiof3_clk_a",
3784 "msiof3_sync_a",
3785 "msiof3_ss1_a",
3786 "msiof3_ss2_a",
3787 "msiof3_txd_a",
3788 "msiof3_rxd_a",
3789 "msiof3_clk_b",
3790 "msiof3_sync_b",
3791 "msiof3_ss1_b",
3792 "msiof3_ss2_b",
3793 "msiof3_txd_b",
3794 "msiof3_rxd_b",
3795 "msiof3_clk_c",
3796 "msiof3_sync_c",
3797 "msiof3_txd_c",
3798 "msiof3_rxd_c",
3799 "msiof3_clk_d",
3800 "msiof3_sync_d",
3801 "msiof3_ss1_d",
3802 "msiof3_txd_d",
3803 "msiof3_rxd_d",
3804};
3805
4ca88cf6
TK		 3806static const char * const pwm0_groups[] = {
3807 "pwm0",
3808};
3809
3810static const char * const pwm1_groups[] = {
3811 "pwm1_a",
3812 "pwm1_b",
3813};
3814
3815static const char * const pwm2_groups[] = {
3816 "pwm2_a",
3817 "pwm2_b",
3818};
3819
3820static const char * const pwm3_groups[] = {
3821 "pwm3_a",
3822 "pwm3_b",
3823};
3824
3825static const char * const pwm4_groups[] = {
3826 "pwm4_a",
3827 "pwm4_b",
3828};
3829
3830static const char * const pwm5_groups[] = {
3831 "pwm5_a",
3832 "pwm5_b",
3833};
3834
3835static const char * const pwm6_groups[] = {
3836 "pwm6_a",
3837 "pwm6_b",
3838};
3839
34dc4e16
TK		 3840static const char * const sata0_groups[] = {
3841 "sata0_devslp_a",
3842 "sata0_devslp_b",
3843};
3844
ff8459a5
GU		 3845static const char * const scif0_groups[] = {
3846 "scif0_data",
3847 "scif0_clk",
3848 "scif0_ctrl",
3849};
3850
3851static const char * const scif1_groups[] = {
3852 "scif1_data_a",
3853 "scif1_clk",
3854 "scif1_ctrl",
3855 "scif1_data_b",
3856};
3857
3858static const char * const scif2_groups[] = {
3859 "scif2_data_a",
3860 "scif2_clk",
3861 "scif2_data_b",
3862};
3863
3864static const char * const scif3_groups[] = {
3865 "scif3_data_a",
3866 "scif3_clk",
3867 "scif3_ctrl",
3868 "scif3_data_b",
3869};
3870
3871static const char * const scif4_groups[] = {
3872 "scif4_data_a",
3873 "scif4_clk_a",
3874 "scif4_ctrl_a",
3875 "scif4_data_b",
3876 "scif4_clk_b",
3877 "scif4_ctrl_b",
3878 "scif4_data_c",
3879 "scif4_clk_c",
3880 "scif4_ctrl_c",
3881};
3882
3883static const char * const scif5_groups[] = {
3884 "scif5_data",
3885 "scif5_clk",
0b0ffc96
TK		 3886};
3887
f27200f9
GU		 3888static const char * const scif_clk_groups[] = {
3889 "scif_clk_a",
3890 "scif_clk_b",
3891};
3892
20cacae1
TK		 3893static const char * const sdhi0_groups[] = {
3894 "sdhi0_data1",
3895 "sdhi0_data4",
3896 "sdhi0_ctrl",
3897 "sdhi0_cd",
3898 "sdhi0_wp",
3899};
3900
3901static const char * const sdhi1_groups[] = {
3902 "sdhi1_data1",
3903 "sdhi1_data4",
3904 "sdhi1_ctrl",
3905 "sdhi1_cd",
3906 "sdhi1_wp",
3907};
3908
3909static const char * const sdhi2_groups[] = {
3910 "sdhi2_data1",
3911 "sdhi2_data4",
3912 "sdhi2_data8",
3913 "sdhi2_ctrl",
3914 "sdhi2_cd_a",
3915 "sdhi2_wp_a",
3916 "sdhi2_cd_b",
3917 "sdhi2_wp_b",
3918 "sdhi2_ds",
3919};
3920
3921static const char * const sdhi3_groups[] = {
3922 "sdhi3_data1",
3923 "sdhi3_data4",
3924 "sdhi3_data8",
3925 "sdhi3_ctrl",
3926 "sdhi3_cd",
3927 "sdhi3_wp",
3928 "sdhi3_ds",
3929};
3930
9b132ba3
KM		 3931static const char * const ssi_groups[] = {
3932 "ssi0_data",
3933 "ssi01239_ctrl",
3934 "ssi1_data_a",
3935 "ssi1_data_b",
3936 "ssi1_ctrl_a",
3937 "ssi1_ctrl_b",
3938 "ssi2_data_a",
3939 "ssi2_data_b",
3940 "ssi2_ctrl_a",
3941 "ssi2_ctrl_b",
3942 "ssi3_data",
3943 "ssi34_ctrl",
3944 "ssi4_data",
3945 "ssi4_ctrl",
3946 "ssi5_data",
3947 "ssi5_ctrl",
3948 "ssi6_data",
3949 "ssi6_ctrl",
3950 "ssi7_data",
3951 "ssi78_ctrl",
3952 "ssi8_data",
3953 "ssi9_data_a",
3954 "ssi9_data_b",
3955 "ssi9_ctrl_a",
3956 "ssi9_ctrl_b",
3957};
3958
76250a6c
TK		 3959static const char * const usb0_groups[] = {
3960 "usb0",
3961};
3962
3963static const char * const usb1_groups[] = {
3964 "usb1",
3965};
3966
3967static const char * const usb2_groups[] = {
3968 "usb2",
3969};
3970
0b0ffc96 3971static const struct sh_pfc_function pinmux_functions[] = {
c33a7fe3 3972 SH_PFC_FUNCTION(audio_clk),
819fd4bf 3973 SH_PFC_FUNCTION(avb),
a4d9791f
RS		 3974 SH_PFC_FUNCTION(can0),
3975 SH_PFC_FUNCTION(can1),
3976 SH_PFC_FUNCTION(can_clk),
4412bb5d
RS		 3977 SH_PFC_FUNCTION(canfd0),
3978 SH_PFC_FUNCTION(canfd1),
a56069c4
GU		 3979 SH_PFC_FUNCTION(hscif0),
3980 SH_PFC_FUNCTION(hscif1),
3981 SH_PFC_FUNCTION(hscif2),
3982 SH_PFC_FUNCTION(hscif3),
3983 SH_PFC_FUNCTION(hscif4),
2544ef72
KM		 3984 SH_PFC_FUNCTION(i2c1),
3985 SH_PFC_FUNCTION(i2c2),
3986 SH_PFC_FUNCTION(i2c6),
bb46f6f3 3987 SH_PFC_FUNCTION(intc_ex),
e7419b81
GU		 3988 SH_PFC_FUNCTION(msiof0),
3989 SH_PFC_FUNCTION(msiof1),
3990 SH_PFC_FUNCTION(msiof2),
3991 SH_PFC_FUNCTION(msiof3),
4ca88cf6
TK		 3992 SH_PFC_FUNCTION(pwm0),
3993 SH_PFC_FUNCTION(pwm1),
3994 SH_PFC_FUNCTION(pwm2),
3995 SH_PFC_FUNCTION(pwm3),
3996 SH_PFC_FUNCTION(pwm4),
3997 SH_PFC_FUNCTION(pwm5),
3998 SH_PFC_FUNCTION(pwm6),
34dc4e16 3999 SH_PFC_FUNCTION(sata0),
ff8459a5
GU		 4000 SH_PFC_FUNCTION(scif0),
4001 SH_PFC_FUNCTION(scif1),
4002 SH_PFC_FUNCTION(scif2),
4003 SH_PFC_FUNCTION(scif3),
4004 SH_PFC_FUNCTION(scif4),
4005 SH_PFC_FUNCTION(scif5),
f27200f9 4006 SH_PFC_FUNCTION(scif_clk),
20cacae1
TK		 4007 SH_PFC_FUNCTION(sdhi0),
4008 SH_PFC_FUNCTION(sdhi1),
4009 SH_PFC_FUNCTION(sdhi2),
4010 SH_PFC_FUNCTION(sdhi3),
9b132ba3 4011 SH_PFC_FUNCTION(ssi),
76250a6c
TK		 4012 SH_PFC_FUNCTION(usb0),
4013 SH_PFC_FUNCTION(usb1),
4014 SH_PFC_FUNCTION(usb2),
0b0ffc96
TK		 4015};
4016
4017static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4018#define F_(x, y) FN_##y
4019#define FM(x) FN_##x
4020 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4021 0, 0,
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 0, 0,
4028 0, 0,
4029 0, 0,
4030 0, 0,
4031 0, 0,
4032 0, 0,
4033 0, 0,
4034 0, 0,
4035 0, 0,
4036 0, 0,
4037 GP_0_15_FN, GPSR0_15,
4038 GP_0_14_FN, GPSR0_14,
4039 GP_0_13_FN, GPSR0_13,
4040 GP_0_12_FN, GPSR0_12,
4041 GP_0_11_FN, GPSR0_11,
4042 GP_0_10_FN, GPSR0_10,
4043 GP_0_9_FN, GPSR0_9,
4044 GP_0_8_FN, GPSR0_8,
4045 GP_0_7_FN, GPSR0_7,
4046 GP_0_6_FN, GPSR0_6,
4047 GP_0_5_FN, GPSR0_5,
4048 GP_0_4_FN, GPSR0_4,
4049 GP_0_3_FN, GPSR0_3,
4050 GP_0_2_FN, GPSR0_2,
4051 GP_0_1_FN, GPSR0_1,
4052 GP_0_0_FN, GPSR0_0, }
4053 },
4054 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4055 0, 0,
4056 0, 0,
4057 0, 0,
4058 0, 0,
4059 GP_1_27_FN, GPSR1_27,
4060 GP_1_26_FN, GPSR1_26,
4061 GP_1_25_FN, GPSR1_25,
4062 GP_1_24_FN, GPSR1_24,
4063 GP_1_23_FN, GPSR1_23,
4064 GP_1_22_FN, GPSR1_22,
4065 GP_1_21_FN, GPSR1_21,
4066 GP_1_20_FN, GPSR1_20,
4067 GP_1_19_FN, GPSR1_19,
4068 GP_1_18_FN, GPSR1_18,
4069 GP_1_17_FN, GPSR1_17,
4070 GP_1_16_FN, GPSR1_16,
4071 GP_1_15_FN, GPSR1_15,
4072 GP_1_14_FN, GPSR1_14,
4073 GP_1_13_FN, GPSR1_13,
4074 GP_1_12_FN, GPSR1_12,
4075 GP_1_11_FN, GPSR1_11,
4076 GP_1_10_FN, GPSR1_10,
4077 GP_1_9_FN, GPSR1_9,
4078 GP_1_8_FN, GPSR1_8,
4079 GP_1_7_FN, GPSR1_7,
4080 GP_1_6_FN, GPSR1_6,
4081 GP_1_5_FN, GPSR1_5,
4082 GP_1_4_FN, GPSR1_4,
4083 GP_1_3_FN, GPSR1_3,
4084 GP_1_2_FN, GPSR1_2,
4085 GP_1_1_FN, GPSR1_1,
4086 GP_1_0_FN, GPSR1_0, }
4087 },
4088 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4089 0, 0,
4090 0, 0,
4091 0, 0,
4092 0, 0,
4093 0, 0,
4094 0, 0,
4095 0, 0,
4096 0, 0,
4097 0, 0,
4098 0, 0,
4099 0, 0,
4100 0, 0,
4101 0, 0,
4102 0, 0,
4103 0, 0,
4104 0, 0,
4105 0, 0,
4106 GP_2_14_FN, GPSR2_14,
4107 GP_2_13_FN, GPSR2_13,
4108 GP_2_12_FN, GPSR2_12,
4109 GP_2_11_FN, GPSR2_11,
4110 GP_2_10_FN, GPSR2_10,
4111 GP_2_9_FN, GPSR2_9,
4112 GP_2_8_FN, GPSR2_8,
4113 GP_2_7_FN, GPSR2_7,
4114 GP_2_6_FN, GPSR2_6,
4115 GP_2_5_FN, GPSR2_5,
4116 GP_2_4_FN, GPSR2_4,
4117 GP_2_3_FN, GPSR2_3,
4118 GP_2_2_FN, GPSR2_2,
4119 GP_2_1_FN, GPSR2_1,
4120 GP_2_0_FN, GPSR2_0, }
4121 },
4122 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4123 0, 0,
4124 0, 0,
4125 0, 0,
4126 0, 0,
4127 0, 0,
4128 0, 0,
4129 0, 0,
4130 0, 0,
4131 0, 0,
4132 0, 0,
4133 0, 0,
4134 0, 0,
4135 0, 0,
4136 0, 0,
4137 0, 0,
4138 0, 0,
4139 GP_3_15_FN, GPSR3_15,
4140 GP_3_14_FN, GPSR3_14,
4141 GP_3_13_FN, GPSR3_13,
4142 GP_3_12_FN, GPSR3_12,
4143 GP_3_11_FN, GPSR3_11,
4144 GP_3_10_FN, GPSR3_10,
4145 GP_3_9_FN, GPSR3_9,
4146 GP_3_8_FN, GPSR3_8,
4147 GP_3_7_FN, GPSR3_7,
4148 GP_3_6_FN, GPSR3_6,
4149 GP_3_5_FN, GPSR3_5,
4150 GP_3_4_FN, GPSR3_4,
4151 GP_3_3_FN, GPSR3_3,
4152 GP_3_2_FN, GPSR3_2,
4153 GP_3_1_FN, GPSR3_1,
4154 GP_3_0_FN, GPSR3_0, }
4155 },
4156 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4157 0, 0,
4158 0, 0,
4159 0, 0,
4160 0, 0,
4161 0, 0,
4162 0, 0,
4163 0, 0,
4164 0, 0,
4165 0, 0,
4166 0, 0,
4167 0, 0,
4168 0, 0,
4169 0, 0,
4170 0, 0,
4171 GP_4_17_FN, GPSR4_17,
4172 GP_4_16_FN, GPSR4_16,
4173 GP_4_15_FN, GPSR4_15,
4174 GP_4_14_FN, GPSR4_14,
4175 GP_4_13_FN, GPSR4_13,
4176 GP_4_12_FN, GPSR4_12,
4177 GP_4_11_FN, GPSR4_11,
4178 GP_4_10_FN, GPSR4_10,
4179 GP_4_9_FN, GPSR4_9,
4180 GP_4_8_FN, GPSR4_8,
4181 GP_4_7_FN, GPSR4_7,
4182 GP_4_6_FN, GPSR4_6,
4183 GP_4_5_FN, GPSR4_5,
4184 GP_4_4_FN, GPSR4_4,
4185 GP_4_3_FN, GPSR4_3,
4186 GP_4_2_FN, GPSR4_2,
4187 GP_4_1_FN, GPSR4_1,
4188 GP_4_0_FN, GPSR4_0, }
4189 },
4190 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4191 0, 0,
4192 0, 0,
4193 0, 0,
4194 0, 0,
4195 0, 0,
4196 0, 0,
4197 GP_5_25_FN, GPSR5_25,
4198 GP_5_24_FN, GPSR5_24,
4199 GP_5_23_FN, GPSR5_23,
4200 GP_5_22_FN, GPSR5_22,
4201 GP_5_21_FN, GPSR5_21,
4202 GP_5_20_FN, GPSR5_20,
4203 GP_5_19_FN, GPSR5_19,
4204 GP_5_18_FN, GPSR5_18,
4205 GP_5_17_FN, GPSR5_17,
4206 GP_5_16_FN, GPSR5_16,
4207 GP_5_15_FN, GPSR5_15,
4208 GP_5_14_FN, GPSR5_14,
4209 GP_5_13_FN, GPSR5_13,
4210 GP_5_12_FN, GPSR5_12,
4211 GP_5_11_FN, GPSR5_11,
4212 GP_5_10_FN, GPSR5_10,
4213 GP_5_9_FN, GPSR5_9,
4214 GP_5_8_FN, GPSR5_8,
4215 GP_5_7_FN, GPSR5_7,
4216 GP_5_6_FN, GPSR5_6,
4217 GP_5_5_FN, GPSR5_5,
4218 GP_5_4_FN, GPSR5_4,
4219 GP_5_3_FN, GPSR5_3,
4220 GP_5_2_FN, GPSR5_2,
4221 GP_5_1_FN, GPSR5_1,
4222 GP_5_0_FN, GPSR5_0, }
4223 },
4224 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4225 GP_6_31_FN, GPSR6_31,
4226 GP_6_30_FN, GPSR6_30,
4227 GP_6_29_FN, GPSR6_29,
4228 GP_6_28_FN, GPSR6_28,
4229 GP_6_27_FN, GPSR6_27,
4230 GP_6_26_FN, GPSR6_26,
4231 GP_6_25_FN, GPSR6_25,
4232 GP_6_24_FN, GPSR6_24,
4233 GP_6_23_FN, GPSR6_23,
4234 GP_6_22_FN, GPSR6_22,
4235 GP_6_21_FN, GPSR6_21,
4236 GP_6_20_FN, GPSR6_20,
4237 GP_6_19_FN, GPSR6_19,
4238 GP_6_18_FN, GPSR6_18,
4239 GP_6_17_FN, GPSR6_17,
4240 GP_6_16_FN, GPSR6_16,
4241 GP_6_15_FN, GPSR6_15,
4242 GP_6_14_FN, GPSR6_14,
4243 GP_6_13_FN, GPSR6_13,
4244 GP_6_12_FN, GPSR6_12,
4245 GP_6_11_FN, GPSR6_11,
4246 GP_6_10_FN, GPSR6_10,
4247 GP_6_9_FN, GPSR6_9,
4248 GP_6_8_FN, GPSR6_8,
4249 GP_6_7_FN, GPSR6_7,
4250 GP_6_6_FN, GPSR6_6,
4251 GP_6_5_FN, GPSR6_5,
4252 GP_6_4_FN, GPSR6_4,
4253 GP_6_3_FN, GPSR6_3,
4254 GP_6_2_FN, GPSR6_2,
4255 GP_6_1_FN, GPSR6_1,
4256 GP_6_0_FN, GPSR6_0, }
4257 },
4258 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4259 0, 0,
4260 0, 0,
4261 0, 0,
4262 0, 0,
4263 0, 0,
4264 0, 0,
4265 0, 0,
4266 0, 0,
4267 0, 0,
4268 0, 0,
4269 0, 0,
4270 0, 0,
4271 0, 0,
4272 0, 0,
4273 0, 0,
4274 0, 0,
4275 0, 0,
4276 0, 0,
4277 0, 0,
4278 0, 0,
4279 0, 0,
4280 0, 0,
4281 0, 0,
4282 0, 0,
4283 0, 0,
4284 0, 0,
4285 0, 0,
4286 0, 0,
4287 GP_7_3_FN, GPSR7_3,
4288 GP_7_2_FN, GPSR7_2,
4289 GP_7_1_FN, GPSR7_1,
4290 GP_7_0_FN, GPSR7_0, }
4291 },
4292#undef F_
4293#undef FM
4294
4295#define F_(x, y) x,
4296#define FM(x) FN_##x,
4297 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4298 IP0_31_28
4299 IP0_27_24
4300 IP0_23_20
4301 IP0_19_16
4302 IP0_15_12
4303 IP0_11_8
4304 IP0_7_4
4305 IP0_3_0 }
4306 },
4307 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4308 IP1_31_28
4309 IP1_27_24
4310 IP1_23_20
4311 IP1_19_16
4312 IP1_15_12
4313 IP1_11_8
4314 IP1_7_4
4315 IP1_3_0 }
4316 },
4317 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4318 IP2_31_28
4319 IP2_27_24
4320 IP2_23_20
4321 IP2_19_16
4322 IP2_15_12
4323 IP2_11_8
4324 IP2_7_4
4325 IP2_3_0 }
4326 },
4327 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4328 IP3_31_28
4329 IP3_27_24
4330 IP3_23_20
4331 IP3_19_16
4332 IP3_15_12
4333 IP3_11_8
4334 IP3_7_4
4335 IP3_3_0 }
4336 },
4337 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4338 IP4_31_28
4339 IP4_27_24
4340 IP4_23_20
4341 IP4_19_16
4342 IP4_15_12
4343 IP4_11_8
4344 IP4_7_4
4345 IP4_3_0 }
4346 },
4347 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4348 IP5_31_28
4349 IP5_27_24
4350 IP5_23_20
4351 IP5_19_16
4352 IP5_15_12
4353 IP5_11_8
4354 IP5_7_4
4355 IP5_3_0 }
4356 },
4357 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4358 IP6_31_28
4359 IP6_27_24
4360 IP6_23_20
4361 IP6_19_16
4362 IP6_15_12
4363 IP6_11_8
4364 IP6_7_4
4365 IP6_3_0 }
4366 },
4367 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4368 IP7_31_28
4369 IP7_27_24
4370 IP7_23_20
4371 IP7_19_16
4372 IP7_15_12
4373 IP7_11_8
4374 IP7_7_4
4375 IP7_3_0 }
4376 },
4377 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4378 IP8_31_28
4379 IP8_27_24
4380 IP8_23_20
4381 IP8_19_16
4382 IP8_15_12
4383 IP8_11_8
4384 IP8_7_4
4385 IP8_3_0 }
4386 },
4387 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4388 IP9_31_28
4389 IP9_27_24
4390 IP9_23_20
4391 IP9_19_16
4392 IP9_15_12
4393 IP9_11_8
4394 IP9_7_4
4395 IP9_3_0 }
4396 },
4397 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4398 IP10_31_28
4399 IP10_27_24
4400 IP10_23_20
4401 IP10_19_16
4402 IP10_15_12
4403 IP10_11_8
4404 IP10_7_4
4405 IP10_3_0 }
4406 },
4407 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4408 IP11_31_28
4409 IP11_27_24
4410 IP11_23_20
4411 IP11_19_16
4412 IP11_15_12
4413 IP11_11_8
4414 IP11_7_4
4415 IP11_3_0 }
4416 },
4417 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4418 IP12_31_28
4419 IP12_27_24
4420 IP12_23_20
4421 IP12_19_16
4422 IP12_15_12
4423 IP12_11_8
4424 IP12_7_4
4425 IP12_3_0 }
4426 },
4427 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4428 IP13_31_28
4429 IP13_27_24
4430 IP13_23_20
4431 IP13_19_16
4432 IP13_15_12
4433 IP13_11_8
4434 IP13_7_4
4435 IP13_3_0 }
4436 },
4437 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4438 IP14_31_28
4439 IP14_27_24
4440 IP14_23_20
4441 IP14_19_16
4442 IP14_15_12
4443 IP14_11_8
4444 IP14_7_4
4445 IP14_3_0 }
4446 },
4447 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4448 IP15_31_28
4449 IP15_27_24
4450 IP15_23_20
4451 IP15_19_16
4452 IP15_15_12
4453 IP15_11_8
4454 IP15_7_4
4455 IP15_3_0 }
4456 },
4457 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4458 IP16_31_28
4459 IP16_27_24
4460 IP16_23_20
4461 IP16_19_16
4462 IP16_15_12
4463 IP16_11_8
4464 IP16_7_4
4465 IP16_3_0 }
4466 },
4467 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4468 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4469 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4470 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4471 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4472 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4473 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4474 IP17_7_4
4475 IP17_3_0 }
4476 },
4477#undef F_
4478#undef FM
4479
4480#define F_(x, y) x,
4481#define FM(x) FN_##x,
4482 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4483 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4484 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4485 0, 0, /* RESERVED 31 */
4486 MOD_SEL0_30_29
4487 MOD_SEL0_28_27
4488 MOD_SEL0_26_25_24
4489 MOD_SEL0_23
4490 MOD_SEL0_22
4491 MOD_SEL0_21_20
4492 MOD_SEL0_19
4493 MOD_SEL0_18
4494 MOD_SEL0_17
4495 MOD_SEL0_16_15
4496 MOD_SEL0_14
4497 MOD_SEL0_13
4498 MOD_SEL0_12
4499 MOD_SEL0_11
4500 MOD_SEL0_10
4501 MOD_SEL0_9
4502 MOD_SEL0_8
4503 MOD_SEL0_7_6
4504 MOD_SEL0_5_4
4505 MOD_SEL0_3
4506 MOD_SEL0_2_1
4507 0, 0, /* RESERVED 0 */ }
4508 },
4509 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4510 2, 3, 1, 2, 3, 1, 1, 2, 1,
4511 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4512 MOD_SEL1_31_30
4513 MOD_SEL1_29_28_27
4514 MOD_SEL1_26
4515 MOD_SEL1_25_24
4516 MOD_SEL1_23_22_21
4517 MOD_SEL1_20
4518 MOD_SEL1_19
4519 MOD_SEL1_18_17
4520 MOD_SEL1_16
4521 MOD_SEL1_15_14
4522 MOD_SEL1_13
4523 MOD_SEL1_12
4524 MOD_SEL1_11
4525 MOD_SEL1_10
4526 MOD_SEL1_9
4527 0, 0, 0, 0, /* RESERVED 8, 7 */
4528 MOD_SEL1_6
4529 MOD_SEL1_5
4530 MOD_SEL1_4
4531 MOD_SEL1_3
4532 MOD_SEL1_2
4533 MOD_SEL1_1
4534 MOD_SEL1_0 }
4535 },
4536 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4537 1, 1, 1, 1, 4, 4, 4,
4538 4, 4, 4, 1, 2, 1) {
4539 MOD_SEL2_31
4540 MOD_SEL2_30
4541 MOD_SEL2_29
4542 /* RESERVED 28 */
4543 0, 0,
4544 /* RESERVED 27, 26, 25, 24 */
4545 0, 0, 0, 0, 0, 0, 0, 0,
4546 0, 0, 0, 0, 0, 0, 0, 0,
4547 /* RESERVED 23, 22, 21, 20 */
4548 0, 0, 0, 0, 0, 0, 0, 0,
4549 0, 0, 0, 0, 0, 0, 0, 0,
4550 /* RESERVED 19, 18, 17, 16 */
4551 0, 0, 0, 0, 0, 0, 0, 0,
4552 0, 0, 0, 0, 0, 0, 0, 0,
4553 /* RESERVED 15, 14, 13, 12 */
4554 0, 0, 0, 0, 0, 0, 0, 0,
4555 0, 0, 0, 0, 0, 0, 0, 0,
4556 /* RESERVED 11, 10, 9, 8 */
4557 0, 0, 0, 0, 0, 0, 0, 0,
4558 0, 0, 0, 0, 0, 0, 0, 0,
4559 /* RESERVED 7, 6, 5, 4 */
4560 0, 0, 0, 0, 0, 0, 0, 0,
4561 0, 0, 0, 0, 0, 0, 0, 0,
4562 /* RESERVED 3 */
4563 0, 0,
a5d2dade
GU		 4564 /* RESERVED 2, 1 */
4565 0, 0, 0, 0,
0b0ffc96
TK		 4566 MOD_SEL2_0 }
4567 },
4568 { },
4569};
4570
92e6d9a2
LP		 4571static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4572 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4573 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4574 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4575 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4576 } },
4577 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4578 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4579 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4580 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4581 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4582 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4583 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4584 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4585 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4586 } },
4587 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4588 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4589 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4590 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4591 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4592 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4593 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4594 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4595 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4596 } },
4597 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4598 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4599 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4600 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4601 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4602 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4603 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4604 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4605 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4606 } },
4607 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4608 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4609 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4610 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4611 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4612 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4613 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4614 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4615 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4616 } },
4617 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4618 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4619 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4620 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4621 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4622 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4623 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4624 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4625 } },
4626 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4627 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4628 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4629 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4630 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4631 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4632 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4633 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4634 } },
4635 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4636 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4637 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4638 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4639 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4640 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4641 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4642 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4643 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4644 } },
4645 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4646 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4647 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4648 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4649 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4650 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4651 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4652 } },
4653 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4654 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4655 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4656 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4657 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4658 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4659 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4660 } },
4661 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4662 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4663 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4664 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4665 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4666 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4667 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4668 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4669 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4670 } },
4671 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4672 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4673 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4674 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4675 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4676 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4677 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4678 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4679 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4680 } },
4681 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4682 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4683 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4684 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4685 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4686 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4687 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4688 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4689 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4690 } },
4691 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4692 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4693 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4694 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4695 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4696 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4697 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4698 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4699 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4700 } },
4701 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4702 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4703 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4704 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4705 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4706 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4707 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4708 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4709 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4710 } },
4711 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4712 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4713 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4714 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4715 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4716 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4717 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4718 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4719 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4720 } },
4721 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4722 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4723 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4724 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4725 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4726 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4727 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4728 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4729 } },
4730 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4731 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4732 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4733 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4734 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4735 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
4736 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
4737 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4738 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4739 } },
4740 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4741 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4742 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4743 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4744 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4745 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4746 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4747 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4748 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4749 } },
4750 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4751 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4752 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4753 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4754 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4755 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4756 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4757 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4758 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4759 } },
4760 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4761 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4762 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4763 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4764 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4765 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4766 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
4767 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
4768 } },
4769 { },
4770};
4771
e9eace32
WS		 4772static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4773{
4774 int bit = -EINVAL;
4775
4776 *pocctrl = 0xe6060380;
4777
4778 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4779 bit = pin & 0x1f;
4780
4781 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4782 bit = (pin & 0x1f) + 12;
4783
4784 return bit;
4785}
4786
4787static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
4788 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
4789};
4790
0b0ffc96
TK		 4791const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4792 .name = "r8a77950_pfc",
e9eace32 4793 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 4794 .unlock_reg = 0xe6060000, /* PMMR */
4795
4796 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4797
4798 .pins = pinmux_pins,
4799 .nr_pins = ARRAY_SIZE(pinmux_pins),
4800 .groups = pinmux_groups,
4801 .nr_groups = ARRAY_SIZE(pinmux_groups),
4802 .functions = pinmux_functions,
4803 .nr_functions = ARRAY_SIZE(pinmux_functions),
4804
4805 .cfg_regs = pinmux_config_regs,
92e6d9a2 4806 .drive_regs = pinmux_drive_regs,
0b0ffc96 4807
b8b47d67
GU		 4808 .pinmux_data = pinmux_data,
4809 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 4810};
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