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pinctrl: sh-pfc: r8a7795: Use PINMUX_SINGLE() for I2C
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
CommitLineData
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TK		 1/*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
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TK		 12
13#include "core.h"
14#include "sh_pfc.h"
15
0b0ffc96 16#define CPU_ALL_PORT(fn, sfx) \
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LP		 17 PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
18 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
19 PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
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WS		 20 PORT_GP_CFG_12(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
21 PORT_GP_CFG_1(3, 12, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
22 PORT_GP_CFG_1(3, 13, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
23 PORT_GP_CFG_1(3, 14, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
24 PORT_GP_CFG_1(3, 15, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
25 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_IO_VOLTAGE), \
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LP		 26 PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
27 PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
28 PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
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TK		 29/*
30 * F_() : just information
31 * FM() : macro for FN_xxx / xxx_MARK
32 */
33
34/* GPSR0 */
35#define GPSR0_15 F_(D15, IP7_11_8)
36#define GPSR0_14 F_(D14, IP7_7_4)
37#define GPSR0_13 F_(D13, IP7_3_0)
38#define GPSR0_12 F_(D12, IP6_31_28)
39#define GPSR0_11 F_(D11, IP6_27_24)
40#define GPSR0_10 F_(D10, IP6_23_20)
41#define GPSR0_9 F_(D9, IP6_19_16)
42#define GPSR0_8 F_(D8, IP6_15_12)
43#define GPSR0_7 F_(D7, IP6_11_8)
44#define GPSR0_6 F_(D6, IP6_7_4)
45#define GPSR0_5 F_(D5, IP6_3_0)
46#define GPSR0_4 F_(D4, IP5_31_28)
47#define GPSR0_3 F_(D3, IP5_27_24)
48#define GPSR0_2 F_(D2, IP5_23_20)
49#define GPSR0_1 F_(D1, IP5_19_16)
50#define GPSR0_0 F_(D0, IP5_15_12)
51
52/* GPSR1 */
53#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
54#define GPSR1_26 F_(WE1_N, IP5_7_4)
55#define GPSR1_25 F_(WE0_N, IP5_3_0)
56#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
57#define GPSR1_23 F_(RD_N, IP4_27_24)
58#define GPSR1_22 F_(BS_N, IP4_23_20)
59#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
60#define GPSR1_20 F_(CS0_N, IP4_15_12)
61#define GPSR1_19 F_(A19, IP4_11_8)
62#define GPSR1_18 F_(A18, IP4_7_4)
63#define GPSR1_17 F_(A17, IP4_3_0)
64#define GPSR1_16 F_(A16, IP3_31_28)
65#define GPSR1_15 F_(A15, IP3_27_24)
66#define GPSR1_14 F_(A14, IP3_23_20)
67#define GPSR1_13 F_(A13, IP3_19_16)
68#define GPSR1_12 F_(A12, IP3_15_12)
69#define GPSR1_11 F_(A11, IP3_11_8)
70#define GPSR1_10 F_(A10, IP3_7_4)
71#define GPSR1_9 F_(A9, IP3_3_0)
72#define GPSR1_8 F_(A8, IP2_31_28)
73#define GPSR1_7 F_(A7, IP2_27_24)
74#define GPSR1_6 F_(A6, IP2_23_20)
75#define GPSR1_5 F_(A5, IP2_19_16)
76#define GPSR1_4 F_(A4, IP2_15_12)
77#define GPSR1_3 F_(A3, IP2_11_8)
78#define GPSR1_2 F_(A2, IP2_7_4)
79#define GPSR1_1 F_(A1, IP2_3_0)
80#define GPSR1_0 F_(A0, IP1_31_28)
81
82/* GPSR2 */
83#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
84#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
85#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
86#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
87#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
88#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
89#define GPSR2_8 F_(PWM2_A, IP1_27_24)
90#define GPSR2_7 F_(PWM1_A, IP1_23_20)
91#define GPSR2_6 F_(PWM0, IP1_19_16)
92#define GPSR2_5 F_(IRQ5, IP1_15_12)
93#define GPSR2_4 F_(IRQ4, IP1_11_8)
94#define GPSR2_3 F_(IRQ3, IP1_7_4)
95#define GPSR2_2 F_(IRQ2, IP1_3_0)
96#define GPSR2_1 F_(IRQ1, IP0_31_28)
97#define GPSR2_0 F_(IRQ0, IP0_27_24)
98
99/* GPSR3 */
100#define GPSR3_15 F_(SD1_WP, IP10_23_20)
101#define GPSR3_14 F_(SD1_CD, IP10_19_16)
102#define GPSR3_13 F_(SD0_WP, IP10_15_12)
103#define GPSR3_12 F_(SD0_CD, IP10_11_8)
104#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
105#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
106#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
107#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
108#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
109#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
110#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
111#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
112#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
113#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
114#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
115#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
116
117/* GPSR4 */
118#define GPSR4_17 FM(SD3_DS)
119#define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
120#define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
121#define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
122#define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
123#define GPSR4_12 FM(SD3_DAT3)
124#define GPSR4_11 FM(SD3_DAT2)
125#define GPSR4_10 FM(SD3_DAT1)
126#define GPSR4_9 FM(SD3_DAT0)
127#define GPSR4_8 FM(SD3_CMD)
128#define GPSR4_7 FM(SD3_CLK)
129#define GPSR4_6 F_(SD2_DS, IP9_23_20)
130#define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
131#define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
132#define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
133#define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
134#define GPSR4_1 FM(SD2_CMD)
135#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
136
137/* GPSR5 */
138#define GPSR5_25 F_(MLB_DAT, IP13_19_16)
139#define GPSR5_24 F_(MLB_SIG, IP13_15_12)
140#define GPSR5_23 F_(MLB_CLK, IP13_11_8)
141#define GPSR5_22 FM(MSIOF0_RXD)
142#define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
143#define GPSR5_20 FM(MSIOF0_TXD)
144#define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
145#define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
146#define GPSR5_17 FM(MSIOF0_SCK)
147#define GPSR5_16 F_(HRTS0_N, IP12_27_24)
148#define GPSR5_15 F_(HCTS0_N, IP12_23_20)
149#define GPSR5_14 F_(HTX0, IP12_19_16)
150#define GPSR5_13 F_(HRX0, IP12_15_12)
151#define GPSR5_12 F_(HSCK0, IP12_11_8)
152#define GPSR5_11 F_(RX2_A, IP12_7_4)
153#define GPSR5_10 F_(TX2_A, IP12_3_0)
154#define GPSR5_9 F_(SCK2, IP11_31_28)
155#define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
156#define GPSR5_7 F_(CTS1_N, IP11_23_20)
157#define GPSR5_6 F_(TX1_A, IP11_19_16)
158#define GPSR5_5 F_(RX1_A, IP11_15_12)
159#define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
160#define GPSR5_3 F_(CTS0_N, IP11_7_4)
161#define GPSR5_2 F_(TX0, IP11_3_0)
162#define GPSR5_1 F_(RX0, IP10_31_28)
163#define GPSR5_0 F_(SCK0, IP10_27_24)
164
165/* GPSR6 */
166#define GPSR6_31 F_(USB31_OVC, IP17_7_4)
167#define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
168#define GPSR6_29 F_(USB30_OVC, IP16_31_28)
169#define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
170#define GPSR6_27 F_(USB1_OVC, IP16_23_20)
171#define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
172#define GPSR6_25 F_(USB0_OVC, IP16_15_12)
173#define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
174#define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
175#define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
176#define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
177#define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
178#define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
179#define GPSR6_18 F_(SSI_WS78, IP15_19_16)
180#define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
181#define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
182#define GPSR6_15 F_(SSI_WS6, IP15_7_4)
183#define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
184#define GPSR6_13 FM(SSI_SDATA5)
185#define GPSR6_12 FM(SSI_WS5)
186#define GPSR6_11 FM(SSI_SCK5)
187#define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
188#define GPSR6_9 F_(SSI_WS4, IP14_27_24)
189#define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
190#define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
191#define GPSR6_6 F_(SSI_WS34, IP14_15_12)
192#define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
193#define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
194#define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
195#define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
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GU		 196#define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
197#define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
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TK		 198
199/* GPSR7 */
200#define GPSR7_3 FM(HDMI1_CEC)
201#define GPSR7_2 FM(HDMI0_CEC)
202#define GPSR7_1 FM(AVS2)
203#define GPSR7_0 FM(AVS1)
204
205
206/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
207#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226
227/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
228#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270
271/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
272#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314
315/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
316#define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
00edf542
GU		 322#define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 324#define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351
352#define PINMUX_GPSR \
353\
354 GPSR6_31 \
355 GPSR6_30 \
356 GPSR6_29 \
357 GPSR6_28 \
358 GPSR1_27 GPSR6_27 \
359 GPSR1_26 GPSR6_26 \
360 GPSR1_25 GPSR5_25 GPSR6_25 \
361 GPSR1_24 GPSR5_24 GPSR6_24 \
362 GPSR1_23 GPSR5_23 GPSR6_23 \
363 GPSR1_22 GPSR5_22 GPSR6_22 \
364 GPSR1_21 GPSR5_21 GPSR6_21 \
365 GPSR1_20 GPSR5_20 GPSR6_20 \
366 GPSR1_19 GPSR5_19 GPSR6_19 \
367 GPSR1_18 GPSR5_18 GPSR6_18 \
368 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
369 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
370GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
371GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
372GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
373GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
374GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
375GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
376GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
377GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
378GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
379GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
380GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
381GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
382GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
383GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
384GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
385GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
386
387#define PINMUX_IPSR \
388\
389FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
390FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
391FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
392FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
393FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
394FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
395FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
396FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
397\
398FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
399FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
400FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
401FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
402FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
403FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
404FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
405FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
406\
407FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
408FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
409FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
410FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
411FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
412FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
413FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
414FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
415\
416FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
417FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
418FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
419FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
420FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
421FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
422FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
423FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
424\
425FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
426FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
427FM(IP16_11_8) IP16_11_8 \
428FM(IP16_15_12) IP16_15_12 \
429FM(IP16_19_16) IP16_19_16 \
430FM(IP16_23_20) IP16_23_20 \
431FM(IP16_27_24) IP16_27_24 \
432FM(IP16_31_28) IP16_31_28
433
434/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
435#define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
436#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
437#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
438#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
439#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
440#define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
441#define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
442#define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
443#define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
444#define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
445#define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
446#define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
447#define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
448#define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
449#define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
450#define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
451#define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
452#define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
453#define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
454#define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
455#define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
456
457/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
458#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
459#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
460#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
461#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
462#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
463#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
464#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
465#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
466#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
467#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
468#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
469#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
470#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
fd1aa743 471#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
0b0ffc96
TK		 472#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
473#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
474#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
475#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
476#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
477#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
478#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
479#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
480
481/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
482#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
483#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
484#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
0b0ffc96
TK		 485#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
486
487#define PINMUX_MOD_SELS\
488\
489 MOD_SEL1_31_30 MOD_SEL2_31 \
490MOD_SEL0_30_29 MOD_SEL2_30 \
491 MOD_SEL1_29_28_27 MOD_SEL2_29 \
492MOD_SEL0_28_27 \
493\
494MOD_SEL0_26_25_24 MOD_SEL1_26 \
495 MOD_SEL1_25_24 \
496\
497MOD_SEL0_23 MOD_SEL1_23_22_21 \
498MOD_SEL0_22 \
499MOD_SEL0_21_20 \
500 MOD_SEL1_20 \
501MOD_SEL0_19 MOD_SEL1_19 \
502MOD_SEL0_18 MOD_SEL1_18_17 \
503MOD_SEL0_17 \
504MOD_SEL0_16_15 MOD_SEL1_16 \
505 MOD_SEL1_15_14 \
506MOD_SEL0_14 \
507MOD_SEL0_13 MOD_SEL1_13 \
508MOD_SEL0_12 MOD_SEL1_12 \
509MOD_SEL0_11 MOD_SEL1_11 \
510MOD_SEL0_10 MOD_SEL1_10 \
511MOD_SEL0_9 MOD_SEL1_9 \
512MOD_SEL0_8 \
513MOD_SEL0_7_6 \
514 MOD_SEL1_6 \
515MOD_SEL0_5_4 MOD_SEL1_5 \
516 MOD_SEL1_4 \
517MOD_SEL0_3 MOD_SEL1_3 \
a5d2dade 518MOD_SEL0_2_1 MOD_SEL1_2 \
0b0ffc96
TK		 519 MOD_SEL1_1 \
520 MOD_SEL1_0 MOD_SEL2_0
521
522
523enum {
524 PINMUX_RESERVED = 0,
525
526 PINMUX_DATA_BEGIN,
527 GP_ALL(DATA),
528 PINMUX_DATA_END,
529
530#define F_(x, y)
531#define FM(x) FN_##x,
532 PINMUX_FUNCTION_BEGIN,
533 GP_ALL(FN),
534 PINMUX_GPSR
535 PINMUX_IPSR
536 PINMUX_MOD_SELS
537 PINMUX_FUNCTION_END,
538#undef F_
539#undef FM
540
541#define F_(x, y)
542#define FM(x) x##_MARK,
543 PINMUX_MARK_BEGIN,
544 PINMUX_GPSR
545 PINMUX_IPSR
546 PINMUX_MOD_SELS
547 PINMUX_MARK_END,
548#undef F_
549#undef FM
550};
551
552static const u16 pinmux_data[] = {
553 PINMUX_DATA_GP_ALL(),
554
8d4df573
GU		 555 PINMUX_SINGLE(AVS1),
556 PINMUX_SINGLE(AVS2),
557 PINMUX_SINGLE(HDMI0_CEC),
558 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 559 PINMUX_SINGLE(I2C_SEL_0_1),
560 PINMUX_SINGLE(I2C_SEL_3_1),
561 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 562 PINMUX_SINGLE(MSIOF0_RXD),
563 PINMUX_SINGLE(MSIOF0_SCK),
564 PINMUX_SINGLE(MSIOF0_TXD),
565 PINMUX_SINGLE(SD2_CMD),
566 PINMUX_SINGLE(SD3_CLK),
567 PINMUX_SINGLE(SD3_CMD),
568 PINMUX_SINGLE(SD3_DAT0),
569 PINMUX_SINGLE(SD3_DAT1),
570 PINMUX_SINGLE(SD3_DAT2),
571 PINMUX_SINGLE(SD3_DAT3),
572 PINMUX_SINGLE(SD3_DS),
573 PINMUX_SINGLE(SSI_SCK5),
574 PINMUX_SINGLE(SSI_SDATA5),
575 PINMUX_SINGLE(SSI_WS5),
576
0b0ffc96 577 /* IPSR0 */
e01678e3 578 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 579 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
580
e01678e3 581 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 582 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
583 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
584
e01678e3 585 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 586 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
587 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
588
e01678e3 589 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 590 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
591 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
592
593 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
594 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
595 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
596
597 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
598 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
599 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
600
e01678e3
GU		 601 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
602 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
603 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 604 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
605 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
606 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
607
e01678e3
GU		 608 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
609 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
610 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 611 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
612 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
613 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
614
615 /* IPSR1 */
e01678e3
GU		 616 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
617 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
618 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 619 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
620 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
621
e01678e3
GU		 622 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
623 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
624 PINMUX_IPSR_GPSR(IP1_7_4, A25),
625 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 626 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
627 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
630 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
631 PINMUX_IPSR_GPSR(IP1_11_8, A24),
632 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 633 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
635
e01678e3
GU		 636 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
637 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
638 PINMUX_IPSR_GPSR(IP1_15_12, A23),
639 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
642
e01678e3
GU		 643 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
644 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
645 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 646 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
647 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
648
649 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 650 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 651 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
652 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
653 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
654
655 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 656 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 657 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
658 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
659
e01678e3
GU		 660 PINMUX_IPSR_GPSR(IP1_31_28, A0),
661 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 662 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 663 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
664 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 665 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
666
667 /* IPSR2 */
e01678e3
GU		 668 PINMUX_IPSR_GPSR(IP2_3_0, A1),
669 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 670 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 671 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
672 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 673 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
674
e01678e3
GU		 675 PINMUX_IPSR_GPSR(IP2_7_4, A2),
676 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 677 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 678 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
679 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 680 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
681
e01678e3
GU		 682 PINMUX_IPSR_GPSR(IP2_11_8, A3),
683 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 684 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 685 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
686 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 687 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
688
e01678e3
GU		 689 PINMUX_IPSR_GPSR(IP2_15_12, A4),
690 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 691 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 692 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
693 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
694 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 695
e01678e3
GU		 696 PINMUX_IPSR_GPSR(IP2_19_16, A5),
697 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 698 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 700 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
701 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
702 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 703
e01678e3
GU		 704 PINMUX_IPSR_GPSR(IP2_23_20, A6),
705 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 706 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
707 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 708 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
709 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
710 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 711
e01678e3
GU		 712 PINMUX_IPSR_GPSR(IP2_27_24, A7),
713 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 714 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
715 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 716 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
717 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
718 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 719
e01678e3 720 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 721 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
722 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
723 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
724 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
725 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
726 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
727
728 /* IPSR3 */
e01678e3 729 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 730 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
731 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 732 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 733
e01678e3 734 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 735 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
736 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 737 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 738
e01678e3 739 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 740 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
741 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
744 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 745 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
746 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
747 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
748
e01678e3
GU		 749 PINMUX_IPSR_GPSR(IP3_15_12, A12),
750 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 751 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
752 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 753 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
754 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 755
e01678e3
GU		 756 PINMUX_IPSR_GPSR(IP3_19_16, A13),
757 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 758 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
759 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 760 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
761 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 762
e01678e3
GU		 763 PINMUX_IPSR_GPSR(IP3_23_20, A14),
764 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 765 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 766 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
767 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
768 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 769
e01678e3
GU		 770 PINMUX_IPSR_GPSR(IP3_27_24, A15),
771 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 772 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 773 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
774 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
775 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 776
e01678e3
GU		 777 PINMUX_IPSR_GPSR(IP3_31_28, A16),
778 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
779 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
780 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 781
782 /* IPSR4 */
e01678e3
GU		 783 PINMUX_IPSR_GPSR(IP4_3_0, A17),
784 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
785 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
786 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
787
788 PINMUX_IPSR_GPSR(IP4_7_4, A18),
789 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
790 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
791 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
792
793 PINMUX_IPSR_GPSR(IP4_11_8, A19),
794 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
795 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
796 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
797
798 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
799 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
800
801 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
802 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 803 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
804
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
806 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 807 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 808 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
809 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
810 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
811 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 812 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
813
e01678e3 814 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 815 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
816 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
817 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
818 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
819 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
820
e01678e3 821 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 822 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
823 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
824 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
825 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
826 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
827
828 /* IPSR5 */
e01678e3 829 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 830 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 831 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
832 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 833 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 834 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 835 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
836
e01678e3 837 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 838 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 839 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
840 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 841 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 842 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
843 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 844 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
845
846 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 847 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
848 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
849 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 850
e01678e3 851 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 852 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
853 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 854 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
855 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 856
e01678e3 857 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 858 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
859 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 860 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
861 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 862
e01678e3 863 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 864 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 865 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
866 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 867
e01678e3 868 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 869 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 870 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
871 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 872
e01678e3 873 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 874 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 875 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
876 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 877
878 /* IPSR6 */
e01678e3 879 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 880 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 881 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
882 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 883
e01678e3 884 PINMUX_IPSR_GPSR(IP6_7_4, D6),
0b0ffc96 885 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
e01678e3
GU		 886 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
887 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
0b0ffc96 888
e01678e3 889 PINMUX_IPSR_GPSR(IP6_11_8, D7),
0b0ffc96 890 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
e01678e3
GU		 891 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
892 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
0b0ffc96 893
e01678e3
GU		 894 PINMUX_IPSR_GPSR(IP6_15_12, D8),
895 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
0b0ffc96
TK		 896 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
897 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
898 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
e01678e3 899 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
0b0ffc96 900
e01678e3
GU		 901 PINMUX_IPSR_GPSR(IP6_19_16, D9),
902 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
0b0ffc96
TK		 903 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
904 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
e01678e3 905 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
0b0ffc96 906
e01678e3
GU		 907 PINMUX_IPSR_GPSR(IP6_23_20, D10),
908 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
0b0ffc96
TK		 909 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
910 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
911 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
912 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
e01678e3 913 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
0b0ffc96 914
e01678e3
GU		 915 PINMUX_IPSR_GPSR(IP6_27_24, D11),
916 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
0b0ffc96
TK		 917 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
918 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
919 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
920 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
e01678e3 921 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
0b0ffc96 922
e01678e3
GU		 923 PINMUX_IPSR_GPSR(IP6_31_28, D12),
924 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
0b0ffc96
TK		 925 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
926 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
927 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
e01678e3 928 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
0b0ffc96
TK		 929
930 /* IPSR7 */
e01678e3
GU		 931 PINMUX_IPSR_GPSR(IP7_3_0, D13),
932 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
0b0ffc96
TK		 933 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
934 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
935 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
e01678e3 936 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
0b0ffc96 937
e01678e3
GU		 938 PINMUX_IPSR_GPSR(IP7_7_4, D14),
939 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
0b0ffc96
TK		 940 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
941 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
942 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
e01678e3 943 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
0b0ffc96
TK		 944 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
945
e01678e3
GU		 946 PINMUX_IPSR_GPSR(IP7_11_8, D15),
947 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
0b0ffc96
TK		 948 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
949 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
950 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
e01678e3 951 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
0b0ffc96
TK		 952 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
953
e01678e3 954 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
0b0ffc96 955
e01678e3 956 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
0b0ffc96
TK		 957 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
958 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
959
e01678e3 960 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
0b0ffc96
TK		 961 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
962 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
963
e01678e3 964 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
0b0ffc96
TK		 965 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
966 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
967 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
968
e01678e3 969 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
0b0ffc96
TK		 970 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
971 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
972 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
973
974 /* IPSR8 */
e01678e3 975 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
0b0ffc96
TK		 976 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
977 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
978 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
979
e01678e3 980 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
0b0ffc96
TK		 981 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
982 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
983 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
984
e01678e3 985 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
0b0ffc96
TK		 986 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
987 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
988
e01678e3 989 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
0b0ffc96
TK		 990 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
991 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
992 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
993
e01678e3
GU		 994 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
995 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
0b0ffc96
TK		 996 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
997 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
998 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
999
e01678e3
GU		 1000 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1001 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
0b0ffc96
TK		 1002 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1003 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1004 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1005
e01678e3
GU		 1006 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1007 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
0b0ffc96
TK		 1008 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1009 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1010 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1011
e01678e3
GU		 1012 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1013 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
0b0ffc96
TK		 1014 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1015 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1016 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1017
1018 /* IPSR9 */
e01678e3 1019 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
0b0ffc96 1020
e01678e3 1021 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
0b0ffc96 1022
e01678e3 1023 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
0b0ffc96 1024
e01678e3 1025 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
0b0ffc96 1026
e01678e3 1027 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
0b0ffc96 1028
e01678e3 1029 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
fd1aa743 1030 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
0b0ffc96 1031
e01678e3 1032 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
0b0ffc96
TK		 1033 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1034
e01678e3 1035 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
0b0ffc96
TK		 1036 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1037
1038 /* IPSR10 */
e01678e3
GU		 1039 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1040 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
0b0ffc96 1041
e01678e3
GU		 1042 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1043 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
0b0ffc96 1044
e01678e3 1045 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
0b0ffc96
TK		 1046 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1047 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1048
e01678e3 1049 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
0b0ffc96
TK		 1050 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1051
e01678e3 1052 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
0b0ffc96
TK		 1053 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1054
e01678e3 1055 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
0b0ffc96
TK		 1056 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1057
e01678e3 1058 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
0b0ffc96
TK		 1059 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1060 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1061 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1062 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1063 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1064 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1065 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
e01678e3 1066 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
0b0ffc96 1067
e01678e3 1068 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
0b0ffc96
TK		 1069 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1070 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1071 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1072 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1073
1074 /* IPSR11 */
e01678e3 1075 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
0b0ffc96
TK		 1076 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1077 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1078 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1079 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1080
e01678e3 1081 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
0b0ffc96
TK		 1082 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1083 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1084 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1085 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1086 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1087 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
e01678e3 1088 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
0b0ffc96 1089
e01678e3 1090 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
0b0ffc96
TK		 1091 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1092 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1093 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1094 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1095 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1096 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
e01678e3 1097 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
0b0ffc96
TK		 1098
1099 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1100 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1101 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1102 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1103 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1104
1105 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1106 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1107 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1108 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1109 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1110
e01678e3 1111 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
0b0ffc96
TK		 1112 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1113 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1114 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1115 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1116 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
e01678e3 1117 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
0b0ffc96 1118
e01678e3 1119 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
0b0ffc96
TK		 1120 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1121 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1122 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1123 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1124 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
e01678e3 1125 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
0b0ffc96 1126
e01678e3 1127 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
0b0ffc96
TK		 1128 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1129 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1130 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1131 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1132 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
e01678e3 1133 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
0b0ffc96
TK		 1134
1135 /* IPSR12 */
1136 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1137 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1138 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1139 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1140 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1141 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1142
1143 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1144 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1145 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1146 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1147 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1148 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1149
e01678e3 1150 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
0b0ffc96
TK		 1151 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1152 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1153 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1154 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1155 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1156 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1157
e01678e3 1158 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
0b0ffc96
TK		 1159 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1160 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1161 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1162 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1163 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1164
e01678e3 1165 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
0b0ffc96
TK		 1166 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1167 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1168 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1169 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1170 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1171
e01678e3 1172 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
0b0ffc96
TK		 1173 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1174 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1175 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1176 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1177 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1178 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1179 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1180
e01678e3 1181 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
0b0ffc96
TK		 1182 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1183 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1184 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1185 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1186 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1187 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1188
e01678e3 1189 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
0b0ffc96
TK		 1190 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1191
1192 /* IPSR13 */
e01678e3
GU		 1193 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1194 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
0b0ffc96
TK		 1195 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1196 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1197 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1198 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1199 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1200
e01678e3
GU		 1201 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1202 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
0b0ffc96
TK		 1203 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1204 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1205 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1206 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1207 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1208 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1209
e01678e3 1210 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
0b0ffc96
TK		 1211 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1212 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1213
e01678e3 1214 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
0b0ffc96
TK		 1215 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1216 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1217 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1218
e01678e3 1219 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
0b0ffc96
TK		 1220 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1221 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1222
00edf542 1223 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
0b0ffc96
TK		 1224 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1225
00edf542 1226 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
0b0ffc96
TK		 1227 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1228
e01678e3 1229 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
0b0ffc96
TK		 1230 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1231
1232 /* IPSR14 */
1233 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1234
1235 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1236 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1237
e01678e3 1238 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
0b0ffc96
TK		 1239 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1240 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1241
e01678e3 1242 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
0b0ffc96
TK		 1243 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1244 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1245 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1246
e01678e3 1247 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
0b0ffc96
TK		 1248 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1249 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1250 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1251 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1252 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1253 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1254
e01678e3 1255 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
0b0ffc96
TK		 1256 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1257 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1258 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1259 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1260 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1261 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1262
e01678e3 1263 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
0b0ffc96
TK		 1264 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1265 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1266 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1267 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1268 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1269 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1270
e01678e3 1271 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
0b0ffc96
TK		 1272 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1273 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1274 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1275 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1276 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1277 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1278
1279 /* IPSR15 */
e01678e3
GU		 1280 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1281 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
0b0ffc96
TK		 1282 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1283
e01678e3
GU		 1284 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1285 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
0b0ffc96
TK		 1286 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1287
e01678e3 1288 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
0b0ffc96 1289 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
fd1aa743 1290 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
0b0ffc96 1291
e01678e3 1292 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
0b0ffc96
TK		 1293 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1294 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1295 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1296 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1297 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1298 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1299
e01678e3 1300 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
0b0ffc96
TK		 1301 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1302 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1303 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1304 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1305 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1306 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1307
e01678e3 1308 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
0b0ffc96
TK		 1309 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1310 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1311 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1312 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1313 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1314 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1315 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1316
e01678e3 1317 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
0b0ffc96
TK		 1318 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1319 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1320 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1321 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1322 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1323 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1324
1325 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1326 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1327 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1328 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1329 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
e01678e3 1330 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
0b0ffc96 1331 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
e01678e3 1332 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
0b0ffc96
TK		 1333
1334 /* IPSR16 */
1335 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
e01678e3 1336 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
0b0ffc96
TK		 1337
1338 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1339 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1340 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1341 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1342 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1343
e01678e3 1344 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
0b0ffc96
TK		 1345 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1346 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1347 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1348 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1349 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1350
e01678e3 1351 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
0b0ffc96
TK		 1352 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1353 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1354 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1355 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1356
e01678e3 1357 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
0b0ffc96
TK		 1358 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1359 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1360 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1361 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1362 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1363 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1364 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1365
e01678e3 1366 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
0b0ffc96
TK		 1367 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1368 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1369 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1370 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1371 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1372 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1373 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1374
e01678e3 1375 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
0b0ffc96
TK		 1376 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1377 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1378 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1379 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1380 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1381 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1382 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
e01678e3 1383 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
0b0ffc96 1384
e01678e3 1385 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
0b0ffc96
TK		 1386 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1387 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1388 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1389 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1390 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1391 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1392 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
e01678e3 1393 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
0b0ffc96
TK		 1394
1395 /* IPSR17 */
e01678e3 1396 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
0b0ffc96
TK		 1397 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1398 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1399 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1400 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1401 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
e01678e3 1402 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
0b0ffc96 1403
e01678e3 1404 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
0b0ffc96
TK		 1405 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1406 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1407 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1408 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1409 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
e01678e3 1410 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
0b0ffc96
TK		 1411};
1412
1413static const struct sh_pfc_pin pinmux_pins[] = {
1414 PINMUX_GPIO_GP_ALL(),
1415};
1416
c33a7fe3
KM		 1417/* - AUDIO CLOCK ------------------------------------------------------------ */
1418static const unsigned int audio_clk_a_a_pins[] = {
1419 /* CLK A */
1420 RCAR_GP_PIN(6, 22),
1421};
1422static const unsigned int audio_clk_a_a_mux[] = {
1423 AUDIO_CLKA_A_MARK,
1424};
1425static const unsigned int audio_clk_a_b_pins[] = {
1426 /* CLK A */
1427 RCAR_GP_PIN(5, 4),
1428};
1429static const unsigned int audio_clk_a_b_mux[] = {
1430 AUDIO_CLKA_B_MARK,
1431};
1432static const unsigned int audio_clk_a_c_pins[] = {
1433 /* CLK A */
1434 RCAR_GP_PIN(5, 19),
1435};
1436static const unsigned int audio_clk_a_c_mux[] = {
1437 AUDIO_CLKA_C_MARK,
1438};
1439static const unsigned int audio_clk_b_a_pins[] = {
1440 /* CLK B */
1441 RCAR_GP_PIN(5, 12),
1442};
1443static const unsigned int audio_clk_b_a_mux[] = {
1444 AUDIO_CLKB_A_MARK,
1445};
1446static const unsigned int audio_clk_b_b_pins[] = {
1447 /* CLK B */
1448 RCAR_GP_PIN(6, 23),
1449};
1450static const unsigned int audio_clk_b_b_mux[] = {
1451 AUDIO_CLKB_B_MARK,
1452};
1453static const unsigned int audio_clk_c_a_pins[] = {
1454 /* CLK C */
1455 RCAR_GP_PIN(5, 21),
1456};
1457static const unsigned int audio_clk_c_a_mux[] = {
1458 AUDIO_CLKC_A_MARK,
1459};
1460static const unsigned int audio_clk_c_b_pins[] = {
1461 /* CLK C */
1462 RCAR_GP_PIN(5, 0),
1463};
1464static const unsigned int audio_clk_c_b_mux[] = {
1465 AUDIO_CLKC_B_MARK,
1466};
1467static const unsigned int audio_clkout_a_pins[] = {
1468 /* CLKOUT */
1469 RCAR_GP_PIN(5, 18),
1470};
1471static const unsigned int audio_clkout_a_mux[] = {
1472 AUDIO_CLKOUT_A_MARK,
1473};
1474static const unsigned int audio_clkout_b_pins[] = {
1475 /* CLKOUT */
1476 RCAR_GP_PIN(6, 28),
1477};
1478static const unsigned int audio_clkout_b_mux[] = {
1479 AUDIO_CLKOUT_B_MARK,
1480};
1481static const unsigned int audio_clkout_c_pins[] = {
1482 /* CLKOUT */
1483 RCAR_GP_PIN(5, 3),
1484};
1485static const unsigned int audio_clkout_c_mux[] = {
1486 AUDIO_CLKOUT_C_MARK,
1487};
1488static const unsigned int audio_clkout_d_pins[] = {
1489 /* CLKOUT */
1490 RCAR_GP_PIN(5, 21),
1491};
1492static const unsigned int audio_clkout_d_mux[] = {
1493 AUDIO_CLKOUT_D_MARK,
1494};
1495static const unsigned int audio_clkout1_a_pins[] = {
1496 /* CLKOUT1 */
1497 RCAR_GP_PIN(5, 15),
1498};
1499static const unsigned int audio_clkout1_a_mux[] = {
1500 AUDIO_CLKOUT1_A_MARK,
1501};
1502static const unsigned int audio_clkout1_b_pins[] = {
1503 /* CLKOUT1 */
1504 RCAR_GP_PIN(6, 29),
1505};
1506static const unsigned int audio_clkout1_b_mux[] = {
1507 AUDIO_CLKOUT1_B_MARK,
1508};
1509static const unsigned int audio_clkout2_a_pins[] = {
1510 /* CLKOUT2 */
1511 RCAR_GP_PIN(5, 16),
1512};
1513static const unsigned int audio_clkout2_a_mux[] = {
1514 AUDIO_CLKOUT2_A_MARK,
1515};
1516static const unsigned int audio_clkout2_b_pins[] = {
1517 /* CLKOUT2 */
1518 RCAR_GP_PIN(6, 30),
1519};
1520static const unsigned int audio_clkout2_b_mux[] = {
1521 AUDIO_CLKOUT2_B_MARK,
1522};
1523
1524static const unsigned int audio_clkout3_a_pins[] = {
1525 /* CLKOUT3 */
1526 RCAR_GP_PIN(5, 19),
1527};
1528static const unsigned int audio_clkout3_a_mux[] = {
1529 AUDIO_CLKOUT3_A_MARK,
1530};
1531static const unsigned int audio_clkout3_b_pins[] = {
1532 /* CLKOUT3 */
1533 RCAR_GP_PIN(6, 31),
1534};
1535static const unsigned int audio_clkout3_b_mux[] = {
1536 AUDIO_CLKOUT3_B_MARK,
1537};
1538
819fd4bf
TK		 1539/* - EtherAVB --------------------------------------------------------------- */
1540static const unsigned int avb_link_pins[] = {
1541 /* AVB_LINK */
1542 RCAR_GP_PIN(2, 12),
1543};
1544static const unsigned int avb_link_mux[] = {
1545 AVB_LINK_MARK,
1546};
1547static const unsigned int avb_magic_pins[] = {
1548 /* AVB_MAGIC_ */
1549 RCAR_GP_PIN(2, 10),
1550};
1551static const unsigned int avb_magic_mux[] = {
1552 AVB_MAGIC_MARK,
1553};
1554static const unsigned int avb_phy_int_pins[] = {
1555 /* AVB_PHY_INT */
1556 RCAR_GP_PIN(2, 11),
1557};
1558static const unsigned int avb_phy_int_mux[] = {
1559 AVB_PHY_INT_MARK,
1560};
1561static const unsigned int avb_mdc_pins[] = {
1562 /* AVB_MDC */
1563 RCAR_GP_PIN(2, 9),
1564};
1565static const unsigned int avb_mdc_mux[] = {
1566 AVB_MDC_MARK,
1567};
1568static const unsigned int avb_avtp_pps_pins[] = {
1569 /* AVB_AVTP_PPS */
1570 RCAR_GP_PIN(2, 6),
1571};
1572static const unsigned int avb_avtp_pps_mux[] = {
1573 AVB_AVTP_PPS_MARK,
1574};
1575static const unsigned int avb_avtp_match_a_pins[] = {
1576 /* AVB_AVTP_MATCH_A */
1577 RCAR_GP_PIN(2, 13),
1578};
1579static const unsigned int avb_avtp_match_a_mux[] = {
1580 AVB_AVTP_MATCH_A_MARK,
1581};
1582static const unsigned int avb_avtp_capture_a_pins[] = {
1583 /* AVB_AVTP_CAPTURE_A */
1584 RCAR_GP_PIN(2, 14),
1585};
1586static const unsigned int avb_avtp_capture_a_mux[] = {
1587 AVB_AVTP_CAPTURE_A_MARK,
1588};
1589static const unsigned int avb_avtp_match_b_pins[] = {
1590 /* AVB_AVTP_MATCH_B */
1591 RCAR_GP_PIN(1, 8),
1592};
1593static const unsigned int avb_avtp_match_b_mux[] = {
1594 AVB_AVTP_MATCH_B_MARK,
1595};
1596static const unsigned int avb_avtp_capture_b_pins[] = {
1597 /* AVB_AVTP_CAPTURE_B */
1598 RCAR_GP_PIN(1, 11),
1599};
1600static const unsigned int avb_avtp_capture_b_mux[] = {
1601 AVB_AVTP_CAPTURE_B_MARK,
1602};
1603
a4d9791f
RS		 1604/* - CAN ------------------------------------------------------------------ */
1605static const unsigned int can0_data_a_pins[] = {
1606 /* TX, RX */
1607 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1608};
1609static const unsigned int can0_data_a_mux[] = {
1610 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1611};
1612static const unsigned int can0_data_b_pins[] = {
1613 /* TX, RX */
1614 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1615};
1616static const unsigned int can0_data_b_mux[] = {
1617 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1618};
1619static const unsigned int can1_data_pins[] = {
1620 /* TX, RX */
1621 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1622};
1623static const unsigned int can1_data_mux[] = {
1624 CAN1_TX_MARK, CAN1_RX_MARK,
1625};
1626
1627/* - CAN Clock -------------------------------------------------------------- */
1628static const unsigned int can_clk_pins[] = {
1629 /* CLK */
1630 RCAR_GP_PIN(1, 25),
1631};
1632static const unsigned int can_clk_mux[] = {
1633 CAN_CLK_MARK,
1634};
1635
4412bb5d
RS		 1636/* - CAN FD --------------------------------------------------------------- */
1637static const unsigned int canfd0_data_a_pins[] = {
1638 /* TX, RX */
1639 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1640};
1641static const unsigned int canfd0_data_a_mux[] = {
1642 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1643};
1644static const unsigned int canfd0_data_b_pins[] = {
1645 /* TX, RX */
1646 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1647};
1648static const unsigned int canfd0_data_b_mux[] = {
1649 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1650};
1651static const unsigned int canfd1_data_pins[] = {
1652 /* TX, RX */
1653 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1654};
1655static const unsigned int canfd1_data_mux[] = {
1656 CANFD1_TX_MARK, CANFD1_RX_MARK,
1657};
1658
a56069c4
GU		 1659/* - HSCIF0 ----------------------------------------------------------------- */
1660static const unsigned int hscif0_data_pins[] = {
1661 /* RX, TX */
1662 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1663};
1664static const unsigned int hscif0_data_mux[] = {
1665 HRX0_MARK, HTX0_MARK,
1666};
1667static const unsigned int hscif0_clk_pins[] = {
1668 /* SCK */
1669 RCAR_GP_PIN(5, 12),
1670};
1671static const unsigned int hscif0_clk_mux[] = {
1672 HSCK0_MARK,
1673};
1674static const unsigned int hscif0_ctrl_pins[] = {
1675 /* RTS, CTS */
1676 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1677};
1678static const unsigned int hscif0_ctrl_mux[] = {
1679 HRTS0_N_MARK, HCTS0_N_MARK,
1680};
1681/* - HSCIF1 ----------------------------------------------------------------- */
1682static const unsigned int hscif1_data_a_pins[] = {
1683 /* RX, TX */
1684 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1685};
1686static const unsigned int hscif1_data_a_mux[] = {
1687 HRX1_A_MARK, HTX1_A_MARK,
1688};
1689static const unsigned int hscif1_clk_a_pins[] = {
1690 /* SCK */
1691 RCAR_GP_PIN(6, 21),
1692};
1693static const unsigned int hscif1_clk_a_mux[] = {
1694 HSCK1_A_MARK,
1695};
1696static const unsigned int hscif1_ctrl_a_pins[] = {
1697 /* RTS, CTS */
1698 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1699};
1700static const unsigned int hscif1_ctrl_a_mux[] = {
1701 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1702};
1703
1704static const unsigned int hscif1_data_b_pins[] = {
1705 /* RX, TX */
1706 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1707};
1708static const unsigned int hscif1_data_b_mux[] = {
1709 HRX1_B_MARK, HTX1_B_MARK,
1710};
1711static const unsigned int hscif1_clk_b_pins[] = {
1712 /* SCK */
1713 RCAR_GP_PIN(5, 0),
1714};
1715static const unsigned int hscif1_clk_b_mux[] = {
1716 HSCK1_B_MARK,
1717};
1718static const unsigned int hscif1_ctrl_b_pins[] = {
1719 /* RTS, CTS */
1720 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1721};
1722static const unsigned int hscif1_ctrl_b_mux[] = {
1723 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1724};
1725/* - HSCIF2 ----------------------------------------------------------------- */
1726static const unsigned int hscif2_data_a_pins[] = {
1727 /* RX, TX */
1728 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1729};
1730static const unsigned int hscif2_data_a_mux[] = {
1731 HRX2_A_MARK, HTX2_A_MARK,
1732};
1733static const unsigned int hscif2_clk_a_pins[] = {
1734 /* SCK */
1735 RCAR_GP_PIN(6, 10),
1736};
1737static const unsigned int hscif2_clk_a_mux[] = {
1738 HSCK2_A_MARK,
1739};
1740static const unsigned int hscif2_ctrl_a_pins[] = {
1741 /* RTS, CTS */
1742 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1743};
1744static const unsigned int hscif2_ctrl_a_mux[] = {
1745 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1746};
1747
1748static const unsigned int hscif2_data_b_pins[] = {
1749 /* RX, TX */
1750 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1751};
1752static const unsigned int hscif2_data_b_mux[] = {
1753 HRX2_B_MARK, HTX2_B_MARK,
1754};
1755static const unsigned int hscif2_clk_b_pins[] = {
1756 /* SCK */
1757 RCAR_GP_PIN(6, 21),
1758};
1759static const unsigned int hscif2_clk_b_mux[] = {
1760 HSCK1_B_MARK,
1761};
1762static const unsigned int hscif2_ctrl_b_pins[] = {
1763 /* RTS, CTS */
1764 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1765};
1766static const unsigned int hscif2_ctrl_b_mux[] = {
1767 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1768};
1769/* - HSCIF3 ----------------------------------------------------------------- */
1770static const unsigned int hscif3_data_a_pins[] = {
1771 /* RX, TX */
1772 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1773};
1774static const unsigned int hscif3_data_a_mux[] = {
1775 HRX3_A_MARK, HTX3_A_MARK,
1776};
1777static const unsigned int hscif3_clk_pins[] = {
1778 /* SCK */
1779 RCAR_GP_PIN(1, 22),
1780};
1781static const unsigned int hscif3_clk_mux[] = {
1782 HSCK3_MARK,
1783};
1784static const unsigned int hscif3_ctrl_pins[] = {
1785 /* RTS, CTS */
1786 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1787};
1788static const unsigned int hscif3_ctrl_mux[] = {
1789 HRTS3_N_MARK, HCTS3_N_MARK,
1790};
1791
1792static const unsigned int hscif3_data_b_pins[] = {
1793 /* RX, TX */
1794 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1795};
1796static const unsigned int hscif3_data_b_mux[] = {
1797 HRX3_B_MARK, HTX3_B_MARK,
1798};
1799static const unsigned int hscif3_data_c_pins[] = {
1800 /* RX, TX */
1801 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1802};
1803static const unsigned int hscif3_data_c_mux[] = {
1804 HRX3_C_MARK, HTX3_C_MARK,
1805};
1806static const unsigned int hscif3_data_d_pins[] = {
1807 /* RX, TX */
1808 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1809};
1810static const unsigned int hscif3_data_d_mux[] = {
1811 HRX3_D_MARK, HTX3_D_MARK,
1812};
1813/* - HSCIF4 ----------------------------------------------------------------- */
1814static const unsigned int hscif4_data_a_pins[] = {
1815 /* RX, TX */
1816 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
1817};
1818static const unsigned int hscif4_data_a_mux[] = {
1819 HRX4_A_MARK, HTX4_A_MARK,
1820};
1821static const unsigned int hscif4_clk_pins[] = {
1822 /* SCK */
1823 RCAR_GP_PIN(1, 11),
1824};
1825static const unsigned int hscif4_clk_mux[] = {
1826 HSCK4_MARK,
1827};
1828static const unsigned int hscif4_ctrl_pins[] = {
1829 /* RTS, CTS */
1830 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1831};
1832static const unsigned int hscif4_ctrl_mux[] = {
1833 HRTS4_N_MARK, HCTS3_N_MARK,
1834};
1835
1836static const unsigned int hscif4_data_b_pins[] = {
1837 /* RX, TX */
1838 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1839};
1840static const unsigned int hscif4_data_b_mux[] = {
1841 HRX4_B_MARK, HTX4_B_MARK,
1842};
1843
2544ef72
KM		 1844/* - I2C -------------------------------------------------------------------- */
1845static const unsigned int i2c1_a_pins[] = {
1846 /* SDA, SCL */
1847 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1848};
1849static const unsigned int i2c1_a_mux[] = {
1850 SDA1_A_MARK, SCL1_A_MARK,
1851};
1852static const unsigned int i2c1_b_pins[] = {
1853 /* SDA, SCL */
1854 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1855};
1856static const unsigned int i2c1_b_mux[] = {
1857 SDA1_B_MARK, SCL1_B_MARK,
1858};
1859static const unsigned int i2c2_a_pins[] = {
1860 /* SDA, SCL */
1861 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1862};
1863static const unsigned int i2c2_a_mux[] = {
1864 SDA2_A_MARK, SCL2_A_MARK,
1865};
1866static const unsigned int i2c2_b_pins[] = {
1867 /* SDA, SCL */
1868 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1869};
1870static const unsigned int i2c2_b_mux[] = {
1871 SDA2_B_MARK, SCL2_B_MARK,
1872};
1873static const unsigned int i2c6_a_pins[] = {
1874 /* SDA, SCL */
1875 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1876};
1877static const unsigned int i2c6_a_mux[] = {
1878 SDA6_A_MARK, SCL6_A_MARK,
1879};
1880static const unsigned int i2c6_b_pins[] = {
1881 /* SDA, SCL */
1882 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1883};
1884static const unsigned int i2c6_b_mux[] = {
1885 SDA6_B_MARK, SCL6_B_MARK,
1886};
1887static const unsigned int i2c6_c_pins[] = {
1888 /* SDA, SCL */
1889 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1890};
1891static const unsigned int i2c6_c_mux[] = {
1892 SDA6_C_MARK, SCL6_C_MARK,
1893};
1894
bb46f6f3
MD		 1895/* - INTC-EX ---------------------------------------------------------------- */
1896static const unsigned int intc_ex_irq0_pins[] = {
1897 /* IRQ0 */
1898 RCAR_GP_PIN(2, 0),
1899};
1900static const unsigned int intc_ex_irq0_mux[] = {
1901 IRQ0_MARK,
1902};
1903static const unsigned int intc_ex_irq1_pins[] = {
1904 /* IRQ1 */
1905 RCAR_GP_PIN(2, 1),
1906};
1907static const unsigned int intc_ex_irq1_mux[] = {
1908 IRQ1_MARK,
1909};
1910static const unsigned int intc_ex_irq2_pins[] = {
1911 /* IRQ2 */
1912 RCAR_GP_PIN(2, 2),
1913};
1914static const unsigned int intc_ex_irq2_mux[] = {
1915 IRQ2_MARK,
1916};
1917static const unsigned int intc_ex_irq3_pins[] = {
1918 /* IRQ3 */
1919 RCAR_GP_PIN(2, 3),
1920};
1921static const unsigned int intc_ex_irq3_mux[] = {
1922 IRQ3_MARK,
1923};
1924static const unsigned int intc_ex_irq4_pins[] = {
1925 /* IRQ4 */
1926 RCAR_GP_PIN(2, 4),
1927};
1928static const unsigned int intc_ex_irq4_mux[] = {
1929 IRQ4_MARK,
1930};
1931static const unsigned int intc_ex_irq5_pins[] = {
1932 /* IRQ5 */
1933 RCAR_GP_PIN(2, 5),
1934};
1935static const unsigned int intc_ex_irq5_mux[] = {
1936 IRQ5_MARK,
1937};
1938
e7419b81
GU		 1939/* - MSIOF0 ----------------------------------------------------------------- */
1940static const unsigned int msiof0_clk_pins[] = {
1941 /* SCK */
1942 RCAR_GP_PIN(5, 17),
1943};
1944static const unsigned int msiof0_clk_mux[] = {
1945 MSIOF0_SCK_MARK,
1946};
1947static const unsigned int msiof0_sync_pins[] = {
1948 /* SYNC */
1949 RCAR_GP_PIN(5, 18),
1950};
1951static const unsigned int msiof0_sync_mux[] = {
1952 MSIOF0_SYNC_MARK,
1953};
1954static const unsigned int msiof0_ss1_pins[] = {
1955 /* SS1 */
1956 RCAR_GP_PIN(5, 19),
1957};
1958static const unsigned int msiof0_ss1_mux[] = {
1959 MSIOF0_SS1_MARK,
1960};
1961static const unsigned int msiof0_ss2_pins[] = {
1962 /* SS2 */
1963 RCAR_GP_PIN(5, 21),
1964};
1965static const unsigned int msiof0_ss2_mux[] = {
1966 MSIOF0_SS2_MARK,
1967};
1968static const unsigned int msiof0_txd_pins[] = {
1969 /* TXD */
1970 RCAR_GP_PIN(5, 20),
1971};
1972static const unsigned int msiof0_txd_mux[] = {
1973 MSIOF0_TXD_MARK,
1974};
1975static const unsigned int msiof0_rxd_pins[] = {
1976 /* RXD */
1977 RCAR_GP_PIN(5, 22),
1978};
1979static const unsigned int msiof0_rxd_mux[] = {
1980 MSIOF0_RXD_MARK,
1981};
1982/* - MSIOF1 ----------------------------------------------------------------- */
1983static const unsigned int msiof1_clk_a_pins[] = {
1984 /* SCK */
1985 RCAR_GP_PIN(6, 8),
1986};
1987static const unsigned int msiof1_clk_a_mux[] = {
1988 MSIOF1_SCK_A_MARK,
1989};
1990static const unsigned int msiof1_sync_a_pins[] = {
1991 /* SYNC */
1992 RCAR_GP_PIN(6, 9),
1993};
1994static const unsigned int msiof1_sync_a_mux[] = {
1995 MSIOF1_SYNC_A_MARK,
1996};
1997static const unsigned int msiof1_ss1_a_pins[] = {
1998 /* SS1 */
1999 RCAR_GP_PIN(6, 5),
2000};
2001static const unsigned int msiof1_ss1_a_mux[] = {
2002 MSIOF1_SS1_A_MARK,
2003};
2004static const unsigned int msiof1_ss2_a_pins[] = {
2005 /* SS2 */
2006 RCAR_GP_PIN(6, 6),
2007};
2008static const unsigned int msiof1_ss2_a_mux[] = {
2009 MSIOF1_SS2_A_MARK,
2010};
2011static const unsigned int msiof1_txd_a_pins[] = {
2012 /* TXD */
2013 RCAR_GP_PIN(6, 7),
2014};
2015static const unsigned int msiof1_txd_a_mux[] = {
2016 MSIOF1_TXD_A_MARK,
2017};
2018static const unsigned int msiof1_rxd_a_pins[] = {
2019 /* RXD */
2020 RCAR_GP_PIN(6, 10),
2021};
2022static const unsigned int msiof1_rxd_a_mux[] = {
2023 MSIOF1_RXD_A_MARK,
2024};
2025static const unsigned int msiof1_clk_b_pins[] = {
2026 /* SCK */
2027 RCAR_GP_PIN(5, 9),
2028};
2029static const unsigned int msiof1_clk_b_mux[] = {
2030 MSIOF1_SCK_B_MARK,
2031};
2032static const unsigned int msiof1_sync_b_pins[] = {
2033 /* SYNC */
2034 RCAR_GP_PIN(5, 3),
2035};
2036static const unsigned int msiof1_sync_b_mux[] = {
2037 MSIOF1_SYNC_B_MARK,
2038};
2039static const unsigned int msiof1_ss1_b_pins[] = {
2040 /* SS1 */
2041 RCAR_GP_PIN(5, 4),
2042};
2043static const unsigned int msiof1_ss1_b_mux[] = {
2044 MSIOF1_SS1_B_MARK,
2045};
2046static const unsigned int msiof1_ss2_b_pins[] = {
2047 /* SS2 */
2048 RCAR_GP_PIN(5, 0),
2049};
2050static const unsigned int msiof1_ss2_b_mux[] = {
2051 MSIOF1_SS2_B_MARK,
2052};
2053static const unsigned int msiof1_txd_b_pins[] = {
2054 /* TXD */
2055 RCAR_GP_PIN(5, 8),
2056};
2057static const unsigned int msiof1_txd_b_mux[] = {
2058 MSIOF1_TXD_B_MARK,
2059};
2060static const unsigned int msiof1_rxd_b_pins[] = {
2061 /* RXD */
2062 RCAR_GP_PIN(5, 7),
2063};
2064static const unsigned int msiof1_rxd_b_mux[] = {
2065 MSIOF1_RXD_B_MARK,
2066};
2067static const unsigned int msiof1_clk_c_pins[] = {
2068 /* SCK */
2069 RCAR_GP_PIN(6, 17),
2070};
2071static const unsigned int msiof1_clk_c_mux[] = {
2072 MSIOF1_SCK_C_MARK,
2073};
2074static const unsigned int msiof1_sync_c_pins[] = {
2075 /* SYNC */
2076 RCAR_GP_PIN(6, 18),
2077};
2078static const unsigned int msiof1_sync_c_mux[] = {
2079 MSIOF1_SYNC_C_MARK,
2080};
2081static const unsigned int msiof1_ss1_c_pins[] = {
2082 /* SS1 */
2083 RCAR_GP_PIN(6, 21),
2084};
2085static const unsigned int msiof1_ss1_c_mux[] = {
2086 MSIOF1_SS1_C_MARK,
2087};
2088static const unsigned int msiof1_ss2_c_pins[] = {
2089 /* SS2 */
2090 RCAR_GP_PIN(6, 27),
2091};
2092static const unsigned int msiof1_ss2_c_mux[] = {
2093 MSIOF1_SS2_C_MARK,
2094};
2095static const unsigned int msiof1_txd_c_pins[] = {
2096 /* TXD */
2097 RCAR_GP_PIN(6, 20),
2098};
2099static const unsigned int msiof1_txd_c_mux[] = {
2100 MSIOF1_TXD_C_MARK,
2101};
2102static const unsigned int msiof1_rxd_c_pins[] = {
2103 /* RXD */
2104 RCAR_GP_PIN(6, 19),
2105};
2106static const unsigned int msiof1_rxd_c_mux[] = {
2107 MSIOF1_RXD_C_MARK,
2108};
2109static const unsigned int msiof1_clk_d_pins[] = {
2110 /* SCK */
2111 RCAR_GP_PIN(5, 12),
2112};
2113static const unsigned int msiof1_clk_d_mux[] = {
2114 MSIOF1_SCK_D_MARK,
2115};
2116static const unsigned int msiof1_sync_d_pins[] = {
2117 /* SYNC */
2118 RCAR_GP_PIN(5, 15),
2119};
2120static const unsigned int msiof1_sync_d_mux[] = {
2121 MSIOF1_SYNC_D_MARK,
2122};
2123static const unsigned int msiof1_ss1_d_pins[] = {
2124 /* SS1 */
2125 RCAR_GP_PIN(5, 16),
2126};
2127static const unsigned int msiof1_ss1_d_mux[] = {
2128 MSIOF1_SS1_D_MARK,
2129};
2130static const unsigned int msiof1_ss2_d_pins[] = {
2131 /* SS2 */
2132 RCAR_GP_PIN(5, 21),
2133};
2134static const unsigned int msiof1_ss2_d_mux[] = {
2135 MSIOF1_SS2_D_MARK,
2136};
2137static const unsigned int msiof1_txd_d_pins[] = {
2138 /* TXD */
2139 RCAR_GP_PIN(5, 14),
2140};
2141static const unsigned int msiof1_txd_d_mux[] = {
2142 MSIOF1_TXD_D_MARK,
2143};
2144static const unsigned int msiof1_rxd_d_pins[] = {
2145 /* RXD */
2146 RCAR_GP_PIN(5, 13),
2147};
2148static const unsigned int msiof1_rxd_d_mux[] = {
2149 MSIOF1_RXD_D_MARK,
2150};
2151static const unsigned int msiof1_clk_e_pins[] = {
2152 /* SCK */
2153 RCAR_GP_PIN(3, 0),
2154};
2155static const unsigned int msiof1_clk_e_mux[] = {
2156 MSIOF1_SCK_E_MARK,
2157};
2158static const unsigned int msiof1_sync_e_pins[] = {
2159 /* SYNC */
2160 RCAR_GP_PIN(3, 1),
2161};
2162static const unsigned int msiof1_sync_e_mux[] = {
2163 MSIOF1_SYNC_E_MARK,
2164};
2165static const unsigned int msiof1_ss1_e_pins[] = {
2166 /* SS1 */
2167 RCAR_GP_PIN(3, 4),
2168};
2169static const unsigned int msiof1_ss1_e_mux[] = {
2170 MSIOF1_SS1_E_MARK,
2171};
2172static const unsigned int msiof1_ss2_e_pins[] = {
2173 /* SS2 */
2174 RCAR_GP_PIN(3, 5),
2175};
2176static const unsigned int msiof1_ss2_e_mux[] = {
2177 MSIOF1_SS2_E_MARK,
2178};
2179static const unsigned int msiof1_txd_e_pins[] = {
2180 /* TXD */
2181 RCAR_GP_PIN(3, 3),
2182};
2183static const unsigned int msiof1_txd_e_mux[] = {
2184 MSIOF1_TXD_E_MARK,
2185};
2186static const unsigned int msiof1_rxd_e_pins[] = {
2187 /* RXD */
2188 RCAR_GP_PIN(3, 2),
2189};
2190static const unsigned int msiof1_rxd_e_mux[] = {
2191 MSIOF1_RXD_E_MARK,
2192};
2193static const unsigned int msiof1_clk_f_pins[] = {
2194 /* SCK */
2195 RCAR_GP_PIN(5, 23),
2196};
2197static const unsigned int msiof1_clk_f_mux[] = {
2198 MSIOF1_SCK_F_MARK,
2199};
2200static const unsigned int msiof1_sync_f_pins[] = {
2201 /* SYNC */
2202 RCAR_GP_PIN(5, 24),
2203};
2204static const unsigned int msiof1_sync_f_mux[] = {
2205 MSIOF1_SYNC_F_MARK,
2206};
2207static const unsigned int msiof1_ss1_f_pins[] = {
2208 /* SS1 */
2209 RCAR_GP_PIN(6, 1),
2210};
2211static const unsigned int msiof1_ss1_f_mux[] = {
2212 MSIOF1_SS1_F_MARK,
2213};
2214static const unsigned int msiof1_ss2_f_pins[] = {
2215 /* SS2 */
2216 RCAR_GP_PIN(6, 2),
2217};
2218static const unsigned int msiof1_ss2_f_mux[] = {
2219 MSIOF1_SS2_F_MARK,
2220};
2221static const unsigned int msiof1_txd_f_pins[] = {
2222 /* TXD */
2223 RCAR_GP_PIN(6, 0),
2224};
2225static const unsigned int msiof1_txd_f_mux[] = {
2226 MSIOF1_TXD_F_MARK,
2227};
2228static const unsigned int msiof1_rxd_f_pins[] = {
2229 /* RXD */
2230 RCAR_GP_PIN(5, 25),
2231};
2232static const unsigned int msiof1_rxd_f_mux[] = {
2233 MSIOF1_RXD_F_MARK,
2234};
2235static const unsigned int msiof1_clk_g_pins[] = {
2236 /* SCK */
2237 RCAR_GP_PIN(3, 6),
2238};
2239static const unsigned int msiof1_clk_g_mux[] = {
2240 MSIOF1_SCK_G_MARK,
2241};
2242static const unsigned int msiof1_sync_g_pins[] = {
2243 /* SYNC */
2244 RCAR_GP_PIN(3, 7),
2245};
2246static const unsigned int msiof1_sync_g_mux[] = {
2247 MSIOF1_SYNC_G_MARK,
2248};
2249static const unsigned int msiof1_ss1_g_pins[] = {
2250 /* SS1 */
2251 RCAR_GP_PIN(3, 10),
2252};
2253static const unsigned int msiof1_ss1_g_mux[] = {
2254 MSIOF1_SS1_G_MARK,
2255};
2256static const unsigned int msiof1_ss2_g_pins[] = {
2257 /* SS2 */
2258 RCAR_GP_PIN(3, 11),
2259};
2260static const unsigned int msiof1_ss2_g_mux[] = {
2261 MSIOF1_SS2_G_MARK,
2262};
2263static const unsigned int msiof1_txd_g_pins[] = {
2264 /* TXD */
2265 RCAR_GP_PIN(3, 9),
2266};
2267static const unsigned int msiof1_txd_g_mux[] = {
2268 MSIOF1_TXD_G_MARK,
2269};
2270static const unsigned int msiof1_rxd_g_pins[] = {
2271 /* RXD */
2272 RCAR_GP_PIN(3, 8),
2273};
2274static const unsigned int msiof1_rxd_g_mux[] = {
2275 MSIOF1_RXD_G_MARK,
2276};
2277/* - MSIOF2 ----------------------------------------------------------------- */
2278static const unsigned int msiof2_clk_a_pins[] = {
2279 /* SCK */
2280 RCAR_GP_PIN(1, 9),
2281};
2282static const unsigned int msiof2_clk_a_mux[] = {
2283 MSIOF2_SCK_A_MARK,
2284};
2285static const unsigned int msiof2_sync_a_pins[] = {
2286 /* SYNC */
2287 RCAR_GP_PIN(1, 8),
2288};
2289static const unsigned int msiof2_sync_a_mux[] = {
2290 MSIOF2_SYNC_A_MARK,
2291};
2292static const unsigned int msiof2_ss1_a_pins[] = {
2293 /* SS1 */
2294 RCAR_GP_PIN(1, 6),
2295};
2296static const unsigned int msiof2_ss1_a_mux[] = {
2297 MSIOF2_SS1_A_MARK,
2298};
2299static const unsigned int msiof2_ss2_a_pins[] = {
2300 /* SS2 */
2301 RCAR_GP_PIN(1, 7),
2302};
2303static const unsigned int msiof2_ss2_a_mux[] = {
2304 MSIOF2_SS2_A_MARK,
2305};
2306static const unsigned int msiof2_txd_a_pins[] = {
2307 /* TXD */
2308 RCAR_GP_PIN(1, 11),
2309};
2310static const unsigned int msiof2_txd_a_mux[] = {
2311 MSIOF2_TXD_A_MARK,
2312};
2313static const unsigned int msiof2_rxd_a_pins[] = {
2314 /* RXD */
2315 RCAR_GP_PIN(1, 10),
2316};
2317static const unsigned int msiof2_rxd_a_mux[] = {
2318 MSIOF2_RXD_A_MARK,
2319};
2320static const unsigned int msiof2_clk_b_pins[] = {
2321 /* SCK */
2322 RCAR_GP_PIN(0, 4),
2323};
2324static const unsigned int msiof2_clk_b_mux[] = {
2325 MSIOF2_SCK_B_MARK,
2326};
2327static const unsigned int msiof2_sync_b_pins[] = {
2328 /* SYNC */
2329 RCAR_GP_PIN(0, 5),
2330};
2331static const unsigned int msiof2_sync_b_mux[] = {
2332 MSIOF2_SYNC_B_MARK,
2333};
2334static const unsigned int msiof2_ss1_b_pins[] = {
2335 /* SS1 */
2336 RCAR_GP_PIN(0, 0),
2337};
2338static const unsigned int msiof2_ss1_b_mux[] = {
2339 MSIOF2_SS1_B_MARK,
2340};
2341static const unsigned int msiof2_ss2_b_pins[] = {
2342 /* SS2 */
2343 RCAR_GP_PIN(0, 1),
2344};
2345static const unsigned int msiof2_ss2_b_mux[] = {
2346 MSIOF2_SS2_B_MARK,
2347};
2348static const unsigned int msiof2_txd_b_pins[] = {
2349 /* TXD */
2350 RCAR_GP_PIN(0, 7),
2351};
2352static const unsigned int msiof2_txd_b_mux[] = {
2353 MSIOF2_TXD_B_MARK,
2354};
2355static const unsigned int msiof2_rxd_b_pins[] = {
2356 /* RXD */
2357 RCAR_GP_PIN(0, 6),
2358};
2359static const unsigned int msiof2_rxd_b_mux[] = {
2360 MSIOF2_RXD_B_MARK,
2361};
2362static const unsigned int msiof2_clk_c_pins[] = {
2363 /* SCK */
2364 RCAR_GP_PIN(2, 12),
2365};
2366static const unsigned int msiof2_clk_c_mux[] = {
2367 MSIOF2_SCK_C_MARK,
2368};
2369static const unsigned int msiof2_sync_c_pins[] = {
2370 /* SYNC */
2371 RCAR_GP_PIN(2, 11),
2372};
2373static const unsigned int msiof2_sync_c_mux[] = {
2374 MSIOF2_SYNC_C_MARK,
2375};
2376static const unsigned int msiof2_ss1_c_pins[] = {
2377 /* SS1 */
2378 RCAR_GP_PIN(2, 10),
2379};
2380static const unsigned int msiof2_ss1_c_mux[] = {
2381 MSIOF2_SS1_C_MARK,
2382};
2383static const unsigned int msiof2_ss2_c_pins[] = {
2384 /* SS2 */
2385 RCAR_GP_PIN(2, 9),
2386};
2387static const unsigned int msiof2_ss2_c_mux[] = {
2388 MSIOF2_SS2_C_MARK,
2389};
2390static const unsigned int msiof2_txd_c_pins[] = {
2391 /* TXD */
2392 RCAR_GP_PIN(2, 14),
2393};
2394static const unsigned int msiof2_txd_c_mux[] = {
2395 MSIOF2_TXD_C_MARK,
2396};
2397static const unsigned int msiof2_rxd_c_pins[] = {
2398 /* RXD */
2399 RCAR_GP_PIN(2, 13),
2400};
2401static const unsigned int msiof2_rxd_c_mux[] = {
2402 MSIOF2_RXD_C_MARK,
2403};
2404static const unsigned int msiof2_clk_d_pins[] = {
2405 /* SCK */
2406 RCAR_GP_PIN(0, 8),
2407};
2408static const unsigned int msiof2_clk_d_mux[] = {
2409 MSIOF2_SCK_D_MARK,
2410};
2411static const unsigned int msiof2_sync_d_pins[] = {
2412 /* SYNC */
2413 RCAR_GP_PIN(0, 9),
2414};
2415static const unsigned int msiof2_sync_d_mux[] = {
2416 MSIOF2_SYNC_D_MARK,
2417};
2418static const unsigned int msiof2_ss1_d_pins[] = {
2419 /* SS1 */
2420 RCAR_GP_PIN(0, 12),
2421};
2422static const unsigned int msiof2_ss1_d_mux[] = {
2423 MSIOF2_SS1_D_MARK,
2424};
2425static const unsigned int msiof2_ss2_d_pins[] = {
2426 /* SS2 */
2427 RCAR_GP_PIN(0, 13),
2428};
2429static const unsigned int msiof2_ss2_d_mux[] = {
2430 MSIOF2_SS2_D_MARK,
2431};
2432static const unsigned int msiof2_txd_d_pins[] = {
2433 /* TXD */
2434 RCAR_GP_PIN(0, 11),
2435};
2436static const unsigned int msiof2_txd_d_mux[] = {
2437 MSIOF2_TXD_D_MARK,
2438};
2439static const unsigned int msiof2_rxd_d_pins[] = {
2440 /* RXD */
2441 RCAR_GP_PIN(0, 10),
2442};
2443static const unsigned int msiof2_rxd_d_mux[] = {
2444 MSIOF2_RXD_D_MARK,
2445};
2446/* - MSIOF3 ----------------------------------------------------------------- */
2447static const unsigned int msiof3_clk_a_pins[] = {
2448 /* SCK */
2449 RCAR_GP_PIN(0, 0),
2450};
2451static const unsigned int msiof3_clk_a_mux[] = {
2452 MSIOF3_SCK_A_MARK,
2453};
2454static const unsigned int msiof3_sync_a_pins[] = {
2455 /* SYNC */
2456 RCAR_GP_PIN(0, 1),
2457};
2458static const unsigned int msiof3_sync_a_mux[] = {
2459 MSIOF3_SYNC_A_MARK,
2460};
2461static const unsigned int msiof3_ss1_a_pins[] = {
2462 /* SS1 */
2463 RCAR_GP_PIN(0, 14),
2464};
2465static const unsigned int msiof3_ss1_a_mux[] = {
2466 MSIOF3_SS1_A_MARK,
2467};
2468static const unsigned int msiof3_ss2_a_pins[] = {
2469 /* SS2 */
2470 RCAR_GP_PIN(0, 15),
2471};
2472static const unsigned int msiof3_ss2_a_mux[] = {
2473 MSIOF3_SS2_A_MARK,
2474};
2475static const unsigned int msiof3_txd_a_pins[] = {
2476 /* TXD */
2477 RCAR_GP_PIN(0, 3),
2478};
2479static const unsigned int msiof3_txd_a_mux[] = {
2480 MSIOF3_TXD_A_MARK,
2481};
2482static const unsigned int msiof3_rxd_a_pins[] = {
2483 /* RXD */
2484 RCAR_GP_PIN(0, 2),
2485};
2486static const unsigned int msiof3_rxd_a_mux[] = {
2487 MSIOF3_RXD_A_MARK,
2488};
2489static const unsigned int msiof3_clk_b_pins[] = {
2490 /* SCK */
2491 RCAR_GP_PIN(1, 2),
2492};
2493static const unsigned int msiof3_clk_b_mux[] = {
2494 MSIOF3_SCK_B_MARK,
2495};
2496static const unsigned int msiof3_sync_b_pins[] = {
2497 /* SYNC */
2498 RCAR_GP_PIN(1, 0),
2499};
2500static const unsigned int msiof3_sync_b_mux[] = {
2501 MSIOF3_SYNC_B_MARK,
2502};
2503static const unsigned int msiof3_ss1_b_pins[] = {
2504 /* SS1 */
2505 RCAR_GP_PIN(1, 4),
2506};
2507static const unsigned int msiof3_ss1_b_mux[] = {
2508 MSIOF3_SS1_B_MARK,
2509};
2510static const unsigned int msiof3_ss2_b_pins[] = {
2511 /* SS2 */
2512 RCAR_GP_PIN(1, 5),
2513};
2514static const unsigned int msiof3_ss2_b_mux[] = {
2515 MSIOF3_SS2_B_MARK,
2516};
2517static const unsigned int msiof3_txd_b_pins[] = {
2518 /* TXD */
2519 RCAR_GP_PIN(1, 1),
2520};
2521static const unsigned int msiof3_txd_b_mux[] = {
2522 MSIOF3_TXD_B_MARK,
2523};
2524static const unsigned int msiof3_rxd_b_pins[] = {
2525 /* RXD */
2526 RCAR_GP_PIN(1, 3),
2527};
2528static const unsigned int msiof3_rxd_b_mux[] = {
2529 MSIOF3_RXD_B_MARK,
2530};
2531static const unsigned int msiof3_clk_c_pins[] = {
2532 /* SCK */
2533 RCAR_GP_PIN(1, 12),
2534};
2535static const unsigned int msiof3_clk_c_mux[] = {
2536 MSIOF3_SCK_C_MARK,
2537};
2538static const unsigned int msiof3_sync_c_pins[] = {
2539 /* SYNC */
2540 RCAR_GP_PIN(1, 13),
2541};
2542static const unsigned int msiof3_sync_c_mux[] = {
2543 MSIOF3_SYNC_C_MARK,
2544};
2545static const unsigned int msiof3_txd_c_pins[] = {
2546 /* TXD */
2547 RCAR_GP_PIN(1, 15),
2548};
2549static const unsigned int msiof3_txd_c_mux[] = {
2550 MSIOF3_TXD_C_MARK,
2551};
2552static const unsigned int msiof3_rxd_c_pins[] = {
2553 /* RXD */
2554 RCAR_GP_PIN(1, 14),
2555};
2556static const unsigned int msiof3_rxd_c_mux[] = {
2557 MSIOF3_RXD_C_MARK,
2558};
2559static const unsigned int msiof3_clk_d_pins[] = {
2560 /* SCK */
2561 RCAR_GP_PIN(1, 22),
2562};
2563static const unsigned int msiof3_clk_d_mux[] = {
2564 MSIOF3_SCK_D_MARK,
2565};
2566static const unsigned int msiof3_sync_d_pins[] = {
2567 /* SYNC */
2568 RCAR_GP_PIN(1, 23),
2569};
2570static const unsigned int msiof3_sync_d_mux[] = {
2571 MSIOF3_SYNC_D_MARK,
2572};
2573static const unsigned int msiof3_ss1_d_pins[] = {
2574 /* SS1 */
2575 RCAR_GP_PIN(1, 26),
2576};
2577static const unsigned int msiof3_ss1_d_mux[] = {
2578 MSIOF3_SS1_D_MARK,
2579};
2580static const unsigned int msiof3_txd_d_pins[] = {
2581 /* TXD */
2582 RCAR_GP_PIN(1, 25),
2583};
2584static const unsigned int msiof3_txd_d_mux[] = {
2585 MSIOF3_TXD_D_MARK,
2586};
2587static const unsigned int msiof3_rxd_d_pins[] = {
2588 /* RXD */
2589 RCAR_GP_PIN(1, 24),
2590};
2591static const unsigned int msiof3_rxd_d_mux[] = {
2592 MSIOF3_RXD_D_MARK,
2593};
2594
4ca88cf6
TK		 2595/* - PWM0 --------------------------------------------------------------------*/
2596static const unsigned int pwm0_pins[] = {
2597 /* PWM */
2598 RCAR_GP_PIN(2, 6),
2599};
2600static const unsigned int pwm0_mux[] = {
2601 PWM0_MARK,
2602};
2603/* - PWM1 --------------------------------------------------------------------*/
2604static const unsigned int pwm1_a_pins[] = {
2605 /* PWM */
2606 RCAR_GP_PIN(2, 7),
2607};
2608static const unsigned int pwm1_a_mux[] = {
2609 PWM1_A_MARK,
2610};
2611static const unsigned int pwm1_b_pins[] = {
2612 /* PWM */
2613 RCAR_GP_PIN(1, 8),
2614};
2615static const unsigned int pwm1_b_mux[] = {
2616 PWM1_B_MARK,
2617};
2618/* - PWM2 --------------------------------------------------------------------*/
2619static const unsigned int pwm2_a_pins[] = {
2620 /* PWM */
2621 RCAR_GP_PIN(2, 8),
2622};
2623static const unsigned int pwm2_a_mux[] = {
2624 PWM2_A_MARK,
2625};
2626static const unsigned int pwm2_b_pins[] = {
2627 /* PWM */
2628 RCAR_GP_PIN(1, 11),
2629};
2630static const unsigned int pwm2_b_mux[] = {
2631 PWM2_B_MARK,
2632};
2633/* - PWM3 --------------------------------------------------------------------*/
2634static const unsigned int pwm3_a_pins[] = {
2635 /* PWM */
2636 RCAR_GP_PIN(1, 0),
2637};
2638static const unsigned int pwm3_a_mux[] = {
2639 PWM3_A_MARK,
2640};
2641static const unsigned int pwm3_b_pins[] = {
2642 /* PWM */
2643 RCAR_GP_PIN(2, 2),
2644};
2645static const unsigned int pwm3_b_mux[] = {
2646 PWM3_B_MARK,
2647};
2648/* - PWM4 --------------------------------------------------------------------*/
2649static const unsigned int pwm4_a_pins[] = {
2650 /* PWM */
2651 RCAR_GP_PIN(1, 1),
2652};
2653static const unsigned int pwm4_a_mux[] = {
2654 PWM4_A_MARK,
2655};
2656static const unsigned int pwm4_b_pins[] = {
2657 /* PWM */
2658 RCAR_GP_PIN(2, 3),
2659};
2660static const unsigned int pwm4_b_mux[] = {
2661 PWM4_B_MARK,
2662};
2663/* - PWM5 --------------------------------------------------------------------*/
2664static const unsigned int pwm5_a_pins[] = {
2665 /* PWM */
2666 RCAR_GP_PIN(1, 2),
2667};
2668static const unsigned int pwm5_a_mux[] = {
2669 PWM5_A_MARK,
2670};
2671static const unsigned int pwm5_b_pins[] = {
2672 /* PWM */
2673 RCAR_GP_PIN(2, 4),
2674};
2675static const unsigned int pwm5_b_mux[] = {
2676 PWM5_B_MARK,
2677};
2678/* - PWM6 --------------------------------------------------------------------*/
2679static const unsigned int pwm6_a_pins[] = {
2680 /* PWM */
2681 RCAR_GP_PIN(1, 3),
2682};
2683static const unsigned int pwm6_a_mux[] = {
2684 PWM6_A_MARK,
2685};
2686static const unsigned int pwm6_b_pins[] = {
2687 /* PWM */
2688 RCAR_GP_PIN(2, 5),
2689};
2690static const unsigned int pwm6_b_mux[] = {
2691 PWM6_B_MARK,
2692};
2693
34dc4e16
TK		 2694/* - SATA --------------------------------------------------------------------*/
2695static const unsigned int sata0_devslp_a_pins[] = {
2696 /* DEVSLP */
2697 RCAR_GP_PIN(6, 16),
2698};
2699static const unsigned int sata0_devslp_a_mux[] = {
2700 SATA_DEVSLP_A_MARK,
2701};
2702static const unsigned int sata0_devslp_b_pins[] = {
2703 /* DEVSLP */
2704 RCAR_GP_PIN(4, 6),
2705};
2706static const unsigned int sata0_devslp_b_mux[] = {
2707 SATA_DEVSLP_B_MARK,
2708};
2709
ff8459a5
GU		 2710/* - SCIF0 ------------------------------------------------------------------ */
2711static const unsigned int scif0_data_pins[] = {
2712 /* RX, TX */
2713 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2714};
2715static const unsigned int scif0_data_mux[] = {
2716 RX0_MARK, TX0_MARK,
2717};
2718static const unsigned int scif0_clk_pins[] = {
2719 /* SCK */
2720 RCAR_GP_PIN(5, 0),
2721};
2722static const unsigned int scif0_clk_mux[] = {
2723 SCK0_MARK,
2724};
2725static const unsigned int scif0_ctrl_pins[] = {
2726 /* RTS, CTS */
2727 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2728};
2729static const unsigned int scif0_ctrl_mux[] = {
2730 RTS0_N_TANS_MARK, CTS0_N_MARK,
2731};
2732/* - SCIF1 ------------------------------------------------------------------ */
2733static const unsigned int scif1_data_a_pins[] = {
2734 /* RX, TX */
2735 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2736};
2737static const unsigned int scif1_data_a_mux[] = {
2738 RX1_A_MARK, TX1_A_MARK,
2739};
2740static const unsigned int scif1_clk_pins[] = {
2741 /* SCK */
2742 RCAR_GP_PIN(6, 21),
2743};
2744static const unsigned int scif1_clk_mux[] = {
2745 SCK1_MARK,
2746};
2747static const unsigned int scif1_ctrl_pins[] = {
2748 /* RTS, CTS */
2749 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2750};
2751static const unsigned int scif1_ctrl_mux[] = {
2752 RTS1_N_TANS_MARK, CTS1_N_MARK,
2753};
2754
2755static const unsigned int scif1_data_b_pins[] = {
2756 /* RX, TX */
2757 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2758};
2759static const unsigned int scif1_data_b_mux[] = {
2760 RX1_B_MARK, TX1_B_MARK,
2761};
2762/* - SCIF2 ------------------------------------------------------------------ */
2763static const unsigned int scif2_data_a_pins[] = {
2764 /* RX, TX */
2765 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2766};
2767static const unsigned int scif2_data_a_mux[] = {
2768 RX2_A_MARK, TX2_A_MARK,
2769};
2770static const unsigned int scif2_clk_pins[] = {
2771 /* SCK */
2772 RCAR_GP_PIN(5, 9),
2773};
2774static const unsigned int scif2_clk_mux[] = {
2775 SCK2_MARK,
2776};
2777static const unsigned int scif2_data_b_pins[] = {
2778 /* RX, TX */
2779 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2780};
2781static const unsigned int scif2_data_b_mux[] = {
2782 RX2_B_MARK, TX2_B_MARK,
2783};
2784/* - SCIF3 ------------------------------------------------------------------ */
2785static const unsigned int scif3_data_a_pins[] = {
2786 /* RX, TX */
2787 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2788};
2789static const unsigned int scif3_data_a_mux[] = {
2790 RX3_A_MARK, TX3_A_MARK,
2791};
2792static const unsigned int scif3_clk_pins[] = {
2793 /* SCK */
2794 RCAR_GP_PIN(1, 22),
2795};
2796static const unsigned int scif3_clk_mux[] = {
2797 SCK3_MARK,
2798};
2799static const unsigned int scif3_ctrl_pins[] = {
2800 /* RTS, CTS */
2801 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2802};
2803static const unsigned int scif3_ctrl_mux[] = {
2804 RTS3_N_TANS_MARK, CTS3_N_MARK,
2805};
2806static const unsigned int scif3_data_b_pins[] = {
2807 /* RX, TX */
2808 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2809};
2810static const unsigned int scif3_data_b_mux[] = {
2811 RX3_B_MARK, TX3_B_MARK,
2812};
2813/* - SCIF4 ------------------------------------------------------------------ */
2814static const unsigned int scif4_data_a_pins[] = {
2815 /* RX, TX */
2816 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2817};
2818static const unsigned int scif4_data_a_mux[] = {
2819 RX4_A_MARK, TX4_A_MARK,
2820};
2821static const unsigned int scif4_clk_a_pins[] = {
2822 /* SCK */
2823 RCAR_GP_PIN(2, 10),
2824};
2825static const unsigned int scif4_clk_a_mux[] = {
2826 SCK4_A_MARK,
2827};
2828static const unsigned int scif4_ctrl_a_pins[] = {
2829 /* RTS, CTS */
2830 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2831};
2832static const unsigned int scif4_ctrl_a_mux[] = {
2833 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2834};
2835static const unsigned int scif4_data_b_pins[] = {
2836 /* RX, TX */
2837 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2838};
2839static const unsigned int scif4_data_b_mux[] = {
2840 RX4_B_MARK, TX4_B_MARK,
2841};
2842static const unsigned int scif4_clk_b_pins[] = {
2843 /* SCK */
2844 RCAR_GP_PIN(1, 5),
2845};
2846static const unsigned int scif4_clk_b_mux[] = {
2847 SCK4_B_MARK,
2848};
2849static const unsigned int scif4_ctrl_b_pins[] = {
2850 /* RTS, CTS */
2851 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2852};
2853static const unsigned int scif4_ctrl_b_mux[] = {
2854 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2855};
2856static const unsigned int scif4_data_c_pins[] = {
2857 /* RX, TX */
2858 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2859};
2860static const unsigned int scif4_data_c_mux[] = {
2861 RX4_C_MARK, TX4_C_MARK,
2862};
2863static const unsigned int scif4_clk_c_pins[] = {
2864 /* SCK */
2865 RCAR_GP_PIN(0, 8),
2866};
2867static const unsigned int scif4_clk_c_mux[] = {
2868 SCK4_C_MARK,
2869};
2870static const unsigned int scif4_ctrl_c_pins[] = {
2871 /* RTS, CTS */
2872 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2873};
2874static const unsigned int scif4_ctrl_c_mux[] = {
2875 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2876};
2877/* - SCIF5 ------------------------------------------------------------------ */
2878static const unsigned int scif5_data_pins[] = {
2879 /* RX, TX */
2880 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2881};
2882static const unsigned int scif5_data_mux[] = {
2883 RX5_MARK, TX5_MARK,
2884};
2885static const unsigned int scif5_clk_pins[] = {
2886 /* SCK */
2887 RCAR_GP_PIN(6, 21),
2888};
2889static const unsigned int scif5_clk_mux[] = {
2890 SCK5_MARK,
2891};
20cacae1
TK		 2892/* - SDHI0 ------------------------------------------------------------------ */
2893static const unsigned int sdhi0_data1_pins[] = {
2894 /* D0 */
2895 RCAR_GP_PIN(3, 2),
2896};
2897static const unsigned int sdhi0_data1_mux[] = {
2898 SD0_DAT0_MARK,
2899};
2900static const unsigned int sdhi0_data4_pins[] = {
2901 /* D[0:3] */
2902 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2903 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2904};
2905static const unsigned int sdhi0_data4_mux[] = {
2906 SD0_DAT0_MARK, SD0_DAT1_MARK,
2907 SD0_DAT2_MARK, SD0_DAT3_MARK,
2908};
2909static const unsigned int sdhi0_ctrl_pins[] = {
2910 /* CLK, CMD */
2911 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2912};
2913static const unsigned int sdhi0_ctrl_mux[] = {
2914 SD0_CLK_MARK, SD0_CMD_MARK,
2915};
2916static const unsigned int sdhi0_cd_pins[] = {
2917 /* CD */
2918 RCAR_GP_PIN(3, 12),
2919};
2920static const unsigned int sdhi0_cd_mux[] = {
2921 SD0_CD_MARK,
2922};
2923static const unsigned int sdhi0_wp_pins[] = {
2924 /* WP */
2925 RCAR_GP_PIN(3, 13),
2926};
2927static const unsigned int sdhi0_wp_mux[] = {
2928 SD0_WP_MARK,
2929};
2930/* - SDHI1 ------------------------------------------------------------------ */
2931static const unsigned int sdhi1_data1_pins[] = {
2932 /* D0 */
2933 RCAR_GP_PIN(3, 8),
2934};
2935static const unsigned int sdhi1_data1_mux[] = {
2936 SD1_DAT0_MARK,
2937};
2938static const unsigned int sdhi1_data4_pins[] = {
2939 /* D[0:3] */
2940 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2941 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2942};
2943static const unsigned int sdhi1_data4_mux[] = {
2944 SD1_DAT0_MARK, SD1_DAT1_MARK,
2945 SD1_DAT2_MARK, SD1_DAT3_MARK,
2946};
2947static const unsigned int sdhi1_ctrl_pins[] = {
2948 /* CLK, CMD */
2949 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2950};
2951static const unsigned int sdhi1_ctrl_mux[] = {
2952 SD1_CLK_MARK, SD1_CMD_MARK,
2953};
2954static const unsigned int sdhi1_cd_pins[] = {
2955 /* CD */
2956 RCAR_GP_PIN(3, 14),
2957};
2958static const unsigned int sdhi1_cd_mux[] = {
2959 SD1_CD_MARK,
2960};
2961static const unsigned int sdhi1_wp_pins[] = {
2962 /* WP */
2963 RCAR_GP_PIN(3, 15),
2964};
2965static const unsigned int sdhi1_wp_mux[] = {
2966 SD1_WP_MARK,
2967};
2968/* - SDHI2 ------------------------------------------------------------------ */
2969static const unsigned int sdhi2_data1_pins[] = {
2970 /* D0 */
2971 RCAR_GP_PIN(4, 2),
2972};
2973static const unsigned int sdhi2_data1_mux[] = {
2974 SD2_DAT0_MARK,
2975};
2976static const unsigned int sdhi2_data4_pins[] = {
2977 /* D[0:3] */
2978 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2979 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2980};
2981static const unsigned int sdhi2_data4_mux[] = {
2982 SD2_DAT0_MARK, SD2_DAT1_MARK,
2983 SD2_DAT2_MARK, SD2_DAT3_MARK,
2984};
2985static const unsigned int sdhi2_data8_pins[] = {
2986 /* D[0:7] */
2987 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2988 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2989 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2990 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2991};
2992static const unsigned int sdhi2_data8_mux[] = {
2993 SD2_DAT0_MARK, SD2_DAT1_MARK,
2994 SD2_DAT2_MARK, SD2_DAT3_MARK,
2995 SD2_DAT4_MARK, SD2_DAT5_MARK,
2996 SD2_DAT6_MARK, SD2_DAT7_MARK,
2997};
2998static const unsigned int sdhi2_ctrl_pins[] = {
2999 /* CLK, CMD */
3000 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3001};
3002static const unsigned int sdhi2_ctrl_mux[] = {
3003 SD2_CLK_MARK, SD2_CMD_MARK,
3004};
3005static const unsigned int sdhi2_cd_a_pins[] = {
3006 /* CD */
3007 RCAR_GP_PIN(4, 13),
3008};
3009static const unsigned int sdhi2_cd_a_mux[] = {
3010 SD2_CD_A_MARK,
3011};
3012static const unsigned int sdhi2_cd_b_pins[] = {
3013 /* CD */
3014 RCAR_GP_PIN(5, 10),
3015};
3016static const unsigned int sdhi2_cd_b_mux[] = {
3017 SD2_CD_B_MARK,
3018};
3019static const unsigned int sdhi2_wp_a_pins[] = {
3020 /* WP */
3021 RCAR_GP_PIN(4, 14),
3022};
3023static const unsigned int sdhi2_wp_a_mux[] = {
3024 SD2_WP_A_MARK,
3025};
3026static const unsigned int sdhi2_wp_b_pins[] = {
3027 /* WP */
3028 RCAR_GP_PIN(5, 11),
3029};
3030static const unsigned int sdhi2_wp_b_mux[] = {
3031 SD2_WP_B_MARK,
3032};
3033static const unsigned int sdhi2_ds_pins[] = {
3034 /* DS */
3035 RCAR_GP_PIN(4, 6),
3036};
3037static const unsigned int sdhi2_ds_mux[] = {
3038 SD2_DS_MARK,
3039};
3040/* - SDHI3 ------------------------------------------------------------------ */
3041static const unsigned int sdhi3_data1_pins[] = {
3042 /* D0 */
3043 RCAR_GP_PIN(4, 9),
3044};
3045static const unsigned int sdhi3_data1_mux[] = {
3046 SD3_DAT0_MARK,
3047};
3048static const unsigned int sdhi3_data4_pins[] = {
3049 /* D[0:3] */
3050 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3051 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3052};
3053static const unsigned int sdhi3_data4_mux[] = {
3054 SD3_DAT0_MARK, SD3_DAT1_MARK,
3055 SD3_DAT2_MARK, SD3_DAT3_MARK,
3056};
3057static const unsigned int sdhi3_data8_pins[] = {
3058 /* D[0:7] */
3059 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3060 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3061 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3062 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3063};
3064static const unsigned int sdhi3_data8_mux[] = {
3065 SD3_DAT0_MARK, SD3_DAT1_MARK,
3066 SD3_DAT2_MARK, SD3_DAT3_MARK,
3067 SD3_DAT4_MARK, SD3_DAT5_MARK,
3068 SD3_DAT6_MARK, SD3_DAT7_MARK,
3069};
3070static const unsigned int sdhi3_ctrl_pins[] = {
3071 /* CLK, CMD */
3072 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3073};
3074static const unsigned int sdhi3_ctrl_mux[] = {
3075 SD3_CLK_MARK, SD3_CMD_MARK,
3076};
3077static const unsigned int sdhi3_cd_pins[] = {
3078 /* CD */
3079 RCAR_GP_PIN(4, 15),
3080};
3081static const unsigned int sdhi3_cd_mux[] = {
3082 SD3_CD_MARK,
3083};
3084static const unsigned int sdhi3_wp_pins[] = {
3085 /* WP */
3086 RCAR_GP_PIN(4, 16),
3087};
3088static const unsigned int sdhi3_wp_mux[] = {
3089 SD3_WP_MARK,
3090};
3091static const unsigned int sdhi3_ds_pins[] = {
3092 /* DS */
3093 RCAR_GP_PIN(4, 17),
3094};
3095static const unsigned int sdhi3_ds_mux[] = {
3096 SD3_DS_MARK,
3097};
ff8459a5 3098
f27200f9
GU		 3099/* - SCIF Clock ------------------------------------------------------------- */
3100static const unsigned int scif_clk_a_pins[] = {
3101 /* SCIF_CLK */
3102 RCAR_GP_PIN(6, 23),
3103};
3104static const unsigned int scif_clk_a_mux[] = {
3105 SCIF_CLK_A_MARK,
3106};
3107static const unsigned int scif_clk_b_pins[] = {
3108 /* SCIF_CLK */
3109 RCAR_GP_PIN(5, 9),
3110};
3111static const unsigned int scif_clk_b_mux[] = {
3112 SCIF_CLK_B_MARK,
3113};
3114
9b132ba3
KM		 3115/* - SSI -------------------------------------------------------------------- */
3116static const unsigned int ssi0_data_pins[] = {
3117 /* SDATA */
3118 RCAR_GP_PIN(6, 2),
3119};
3120static const unsigned int ssi0_data_mux[] = {
3121 SSI_SDATA0_MARK,
3122};
3123static const unsigned int ssi01239_ctrl_pins[] = {
3124 /* SCK, WS */
3125 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3126};
3127static const unsigned int ssi01239_ctrl_mux[] = {
00edf542 3128 SSI_SCK01239_MARK, SSI_WS01239_MARK,
9b132ba3
KM		 3129};
3130static const unsigned int ssi1_data_a_pins[] = {
3131 /* SDATA */
3132 RCAR_GP_PIN(6, 3),
3133};
3134static const unsigned int ssi1_data_a_mux[] = {
3135 SSI_SDATA1_A_MARK,
3136};
3137static const unsigned int ssi1_data_b_pins[] = {
3138 /* SDATA */
3139 RCAR_GP_PIN(5, 12),
3140};
3141static const unsigned int ssi1_data_b_mux[] = {
3142 SSI_SDATA1_B_MARK,
3143};
3144static const unsigned int ssi1_ctrl_a_pins[] = {
3145 /* SCK, WS */
3146 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3147};
3148static const unsigned int ssi1_ctrl_a_mux[] = {
3149 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3150};
3151static const unsigned int ssi1_ctrl_b_pins[] = {
3152 /* SCK, WS */
3153 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3154};
3155static const unsigned int ssi1_ctrl_b_mux[] = {
3156 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3157};
3158static const unsigned int ssi2_data_a_pins[] = {
3159 /* SDATA */
3160 RCAR_GP_PIN(6, 4),
3161};
3162static const unsigned int ssi2_data_a_mux[] = {
3163 SSI_SDATA2_A_MARK,
3164};
3165static const unsigned int ssi2_data_b_pins[] = {
3166 /* SDATA */
3167 RCAR_GP_PIN(5, 13),
3168};
3169static const unsigned int ssi2_data_b_mux[] = {
3170 SSI_SDATA2_B_MARK,
3171};
3172static const unsigned int ssi2_ctrl_a_pins[] = {
3173 /* SCK, WS */
3174 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3175};
3176static const unsigned int ssi2_ctrl_a_mux[] = {
3177 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3178};
3179static const unsigned int ssi2_ctrl_b_pins[] = {
3180 /* SCK, WS */
3181 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3182};
3183static const unsigned int ssi2_ctrl_b_mux[] = {
3184 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3185};
3186static const unsigned int ssi3_data_pins[] = {
3187 /* SDATA */
3188 RCAR_GP_PIN(6, 7),
3189};
3190static const unsigned int ssi3_data_mux[] = {
3191 SSI_SDATA3_MARK,
3192};
3193static const unsigned int ssi34_ctrl_pins[] = {
3194 /* SCK, WS */
3195 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3196};
3197static const unsigned int ssi34_ctrl_mux[] = {
3198 SSI_SCK34_MARK, SSI_WS34_MARK,
3199};
3200static const unsigned int ssi4_data_pins[] = {
3201 /* SDATA */
3202 RCAR_GP_PIN(6, 10),
3203};
3204static const unsigned int ssi4_data_mux[] = {
3205 SSI_SDATA4_MARK,
3206};
3207static const unsigned int ssi4_ctrl_pins[] = {
3208 /* SCK, WS */
3209 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3210};
3211static const unsigned int ssi4_ctrl_mux[] = {
3212 SSI_SCK4_MARK, SSI_WS4_MARK,
3213};
3214static const unsigned int ssi5_data_pins[] = {
3215 /* SDATA */
3216 RCAR_GP_PIN(6, 13),
3217};
3218static const unsigned int ssi5_data_mux[] = {
3219 SSI_SDATA5_MARK,
3220};
3221static const unsigned int ssi5_ctrl_pins[] = {
3222 /* SCK, WS */
3223 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3224};
3225static const unsigned int ssi5_ctrl_mux[] = {
3226 SSI_SCK5_MARK, SSI_WS5_MARK,
3227};
3228static const unsigned int ssi6_data_pins[] = {
3229 /* SDATA */
3230 RCAR_GP_PIN(6, 16),
3231};
3232static const unsigned int ssi6_data_mux[] = {
3233 SSI_SDATA6_MARK,
3234};
3235static const unsigned int ssi6_ctrl_pins[] = {
3236 /* SCK, WS */
3237 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3238};
3239static const unsigned int ssi6_ctrl_mux[] = {
3240 SSI_SCK6_MARK, SSI_WS6_MARK,
3241};
3242static const unsigned int ssi7_data_pins[] = {
3243 /* SDATA */
3244 RCAR_GP_PIN(6, 19),
3245};
3246static const unsigned int ssi7_data_mux[] = {
3247 SSI_SDATA7_MARK,
3248};
3249static const unsigned int ssi78_ctrl_pins[] = {
3250 /* SCK, WS */
3251 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3252};
3253static const unsigned int ssi78_ctrl_mux[] = {
3254 SSI_SCK78_MARK, SSI_WS78_MARK,
3255};
3256static const unsigned int ssi8_data_pins[] = {
3257 /* SDATA */
3258 RCAR_GP_PIN(6, 20),
3259};
3260static const unsigned int ssi8_data_mux[] = {
3261 SSI_SDATA8_MARK,
3262};
3263static const unsigned int ssi9_data_a_pins[] = {
3264 /* SDATA */
3265 RCAR_GP_PIN(6, 21),
3266};
3267static const unsigned int ssi9_data_a_mux[] = {
3268 SSI_SDATA9_A_MARK,
3269};
3270static const unsigned int ssi9_data_b_pins[] = {
3271 /* SDATA */
3272 RCAR_GP_PIN(5, 14),
3273};
3274static const unsigned int ssi9_data_b_mux[] = {
3275 SSI_SDATA9_B_MARK,
3276};
3277static const unsigned int ssi9_ctrl_a_pins[] = {
3278 /* SCK, WS */
3279 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3280};
3281static const unsigned int ssi9_ctrl_a_mux[] = {
3282 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3283};
3284static const unsigned int ssi9_ctrl_b_pins[] = {
3285 /* SCK, WS */
3286 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3287};
3288static const unsigned int ssi9_ctrl_b_mux[] = {
3289 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3290};
3291
76250a6c
TK		 3292/* - USB0 ------------------------------------------------------------------- */
3293static const unsigned int usb0_pins[] = {
3294 /* PWEN, OVC */
3295 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3296};
3297static const unsigned int usb0_mux[] = {
3298 USB0_PWEN_MARK, USB0_OVC_MARK,
3299};
3300/* - USB1 ------------------------------------------------------------------- */
3301static const unsigned int usb1_pins[] = {
3302 /* PWEN, OVC */
3303 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3304};
3305static const unsigned int usb1_mux[] = {
3306 USB1_PWEN_MARK, USB1_OVC_MARK,
3307};
3308/* - USB2 ------------------------------------------------------------------- */
3309static const unsigned int usb2_pins[] = {
3310 /* PWEN, OVC */
3311 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3312};
3313static const unsigned int usb2_mux[] = {
3314 USB2_PWEN_MARK, USB2_OVC_MARK,
3315};
3316
0b0ffc96 3317static const struct sh_pfc_pin_group pinmux_groups[] = {
c33a7fe3
KM		 3318 SH_PFC_PIN_GROUP(audio_clk_a_a),
3319 SH_PFC_PIN_GROUP(audio_clk_a_b),
3320 SH_PFC_PIN_GROUP(audio_clk_a_c),
3321 SH_PFC_PIN_GROUP(audio_clk_b_a),
3322 SH_PFC_PIN_GROUP(audio_clk_b_b),
3323 SH_PFC_PIN_GROUP(audio_clk_c_a),
3324 SH_PFC_PIN_GROUP(audio_clk_c_b),
3325 SH_PFC_PIN_GROUP(audio_clkout_a),
3326 SH_PFC_PIN_GROUP(audio_clkout_b),
3327 SH_PFC_PIN_GROUP(audio_clkout_c),
3328 SH_PFC_PIN_GROUP(audio_clkout_d),
3329 SH_PFC_PIN_GROUP(audio_clkout1_a),
3330 SH_PFC_PIN_GROUP(audio_clkout1_b),
3331 SH_PFC_PIN_GROUP(audio_clkout2_a),
3332 SH_PFC_PIN_GROUP(audio_clkout2_b),
3333 SH_PFC_PIN_GROUP(audio_clkout3_a),
3334 SH_PFC_PIN_GROUP(audio_clkout3_b),
819fd4bf
TK		 3335 SH_PFC_PIN_GROUP(avb_link),
3336 SH_PFC_PIN_GROUP(avb_magic),
3337 SH_PFC_PIN_GROUP(avb_phy_int),
3338 SH_PFC_PIN_GROUP(avb_mdc),
3339 SH_PFC_PIN_GROUP(avb_avtp_pps),
3340 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3341 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3342 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3343 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a4d9791f
RS		 3344 SH_PFC_PIN_GROUP(can0_data_a),
3345 SH_PFC_PIN_GROUP(can0_data_b),
3346 SH_PFC_PIN_GROUP(can1_data),
3347 SH_PFC_PIN_GROUP(can_clk),
4412bb5d
RS		 3348 SH_PFC_PIN_GROUP(canfd0_data_a),
3349 SH_PFC_PIN_GROUP(canfd0_data_b),
3350 SH_PFC_PIN_GROUP(canfd1_data),
a56069c4
GU		 3351 SH_PFC_PIN_GROUP(hscif0_data),
3352 SH_PFC_PIN_GROUP(hscif0_clk),
3353 SH_PFC_PIN_GROUP(hscif0_ctrl),
3354 SH_PFC_PIN_GROUP(hscif1_data_a),
3355 SH_PFC_PIN_GROUP(hscif1_clk_a),
3356 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3357 SH_PFC_PIN_GROUP(hscif1_data_b),
3358 SH_PFC_PIN_GROUP(hscif1_clk_b),
3359 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3360 SH_PFC_PIN_GROUP(hscif2_data_a),
3361 SH_PFC_PIN_GROUP(hscif2_clk_a),
3362 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3363 SH_PFC_PIN_GROUP(hscif2_data_b),
3364 SH_PFC_PIN_GROUP(hscif2_clk_b),
3365 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3366 SH_PFC_PIN_GROUP(hscif3_data_a),
3367 SH_PFC_PIN_GROUP(hscif3_clk),
3368 SH_PFC_PIN_GROUP(hscif3_ctrl),
3369 SH_PFC_PIN_GROUP(hscif3_data_b),
3370 SH_PFC_PIN_GROUP(hscif3_data_c),
3371 SH_PFC_PIN_GROUP(hscif3_data_d),
3372 SH_PFC_PIN_GROUP(hscif4_data_a),
3373 SH_PFC_PIN_GROUP(hscif4_clk),
3374 SH_PFC_PIN_GROUP(hscif4_ctrl),
3375 SH_PFC_PIN_GROUP(hscif4_data_b),
2544ef72
KM		 3376 SH_PFC_PIN_GROUP(i2c1_a),
3377 SH_PFC_PIN_GROUP(i2c1_b),
3378 SH_PFC_PIN_GROUP(i2c2_a),
3379 SH_PFC_PIN_GROUP(i2c2_b),
3380 SH_PFC_PIN_GROUP(i2c6_a),
3381 SH_PFC_PIN_GROUP(i2c6_b),
3382 SH_PFC_PIN_GROUP(i2c6_c),
bb46f6f3
MD		 3383 SH_PFC_PIN_GROUP(intc_ex_irq0),
3384 SH_PFC_PIN_GROUP(intc_ex_irq1),
3385 SH_PFC_PIN_GROUP(intc_ex_irq2),
3386 SH_PFC_PIN_GROUP(intc_ex_irq3),
3387 SH_PFC_PIN_GROUP(intc_ex_irq4),
3388 SH_PFC_PIN_GROUP(intc_ex_irq5),
e7419b81
GU		 3389 SH_PFC_PIN_GROUP(msiof0_clk),
3390 SH_PFC_PIN_GROUP(msiof0_sync),
3391 SH_PFC_PIN_GROUP(msiof0_ss1),
3392 SH_PFC_PIN_GROUP(msiof0_ss2),
3393 SH_PFC_PIN_GROUP(msiof0_txd),
3394 SH_PFC_PIN_GROUP(msiof0_rxd),
3395 SH_PFC_PIN_GROUP(msiof1_clk_a),
3396 SH_PFC_PIN_GROUP(msiof1_sync_a),
3397 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3398 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3399 SH_PFC_PIN_GROUP(msiof1_txd_a),
3400 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3401 SH_PFC_PIN_GROUP(msiof1_clk_b),
3402 SH_PFC_PIN_GROUP(msiof1_sync_b),
3403 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3404 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3405 SH_PFC_PIN_GROUP(msiof1_txd_b),
3406 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3407 SH_PFC_PIN_GROUP(msiof1_clk_c),
3408 SH_PFC_PIN_GROUP(msiof1_sync_c),
3409 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3410 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3411 SH_PFC_PIN_GROUP(msiof1_txd_c),
3412 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3413 SH_PFC_PIN_GROUP(msiof1_clk_d),
3414 SH_PFC_PIN_GROUP(msiof1_sync_d),
3415 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3416 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3417 SH_PFC_PIN_GROUP(msiof1_txd_d),
3418 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3419 SH_PFC_PIN_GROUP(msiof1_clk_e),
3420 SH_PFC_PIN_GROUP(msiof1_sync_e),
3421 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3422 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3423 SH_PFC_PIN_GROUP(msiof1_txd_e),
3424 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3425 SH_PFC_PIN_GROUP(msiof1_clk_f),
3426 SH_PFC_PIN_GROUP(msiof1_sync_f),
3427 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3428 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3429 SH_PFC_PIN_GROUP(msiof1_txd_f),
3430 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3431 SH_PFC_PIN_GROUP(msiof1_clk_g),
3432 SH_PFC_PIN_GROUP(msiof1_sync_g),
3433 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3434 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3435 SH_PFC_PIN_GROUP(msiof1_txd_g),
3436 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3437 SH_PFC_PIN_GROUP(msiof2_clk_a),
3438 SH_PFC_PIN_GROUP(msiof2_sync_a),
3439 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3440 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3441 SH_PFC_PIN_GROUP(msiof2_txd_a),
3442 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3443 SH_PFC_PIN_GROUP(msiof2_clk_b),
3444 SH_PFC_PIN_GROUP(msiof2_sync_b),
3445 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3446 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3447 SH_PFC_PIN_GROUP(msiof2_txd_b),
3448 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3449 SH_PFC_PIN_GROUP(msiof2_clk_c),
3450 SH_PFC_PIN_GROUP(msiof2_sync_c),
3451 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3452 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3453 SH_PFC_PIN_GROUP(msiof2_txd_c),
3454 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3455 SH_PFC_PIN_GROUP(msiof2_clk_d),
3456 SH_PFC_PIN_GROUP(msiof2_sync_d),
3457 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3458 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3459 SH_PFC_PIN_GROUP(msiof2_txd_d),
3460 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3461 SH_PFC_PIN_GROUP(msiof3_clk_a),
3462 SH_PFC_PIN_GROUP(msiof3_sync_a),
3463 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3464 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3465 SH_PFC_PIN_GROUP(msiof3_txd_a),
3466 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3467 SH_PFC_PIN_GROUP(msiof3_clk_b),
3468 SH_PFC_PIN_GROUP(msiof3_sync_b),
3469 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3470 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3471 SH_PFC_PIN_GROUP(msiof3_txd_b),
3472 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3473 SH_PFC_PIN_GROUP(msiof3_clk_c),
3474 SH_PFC_PIN_GROUP(msiof3_sync_c),
3475 SH_PFC_PIN_GROUP(msiof3_txd_c),
3476 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3477 SH_PFC_PIN_GROUP(msiof3_clk_d),
3478 SH_PFC_PIN_GROUP(msiof3_sync_d),
3479 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3480 SH_PFC_PIN_GROUP(msiof3_txd_d),
3481 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4ca88cf6
TK		 3482 SH_PFC_PIN_GROUP(pwm0),
3483 SH_PFC_PIN_GROUP(pwm1_a),
3484 SH_PFC_PIN_GROUP(pwm1_b),
3485 SH_PFC_PIN_GROUP(pwm2_a),
3486 SH_PFC_PIN_GROUP(pwm2_b),
3487 SH_PFC_PIN_GROUP(pwm3_a),
3488 SH_PFC_PIN_GROUP(pwm3_b),
3489 SH_PFC_PIN_GROUP(pwm4_a),
3490 SH_PFC_PIN_GROUP(pwm4_b),
3491 SH_PFC_PIN_GROUP(pwm5_a),
3492 SH_PFC_PIN_GROUP(pwm5_b),
3493 SH_PFC_PIN_GROUP(pwm6_a),
3494 SH_PFC_PIN_GROUP(pwm6_b),
34dc4e16
TK		 3495 SH_PFC_PIN_GROUP(sata0_devslp_a),
3496 SH_PFC_PIN_GROUP(sata0_devslp_b),
ff8459a5
GU		 3497 SH_PFC_PIN_GROUP(scif0_data),
3498 SH_PFC_PIN_GROUP(scif0_clk),
3499 SH_PFC_PIN_GROUP(scif0_ctrl),
3500 SH_PFC_PIN_GROUP(scif1_data_a),
3501 SH_PFC_PIN_GROUP(scif1_clk),
3502 SH_PFC_PIN_GROUP(scif1_ctrl),
3503 SH_PFC_PIN_GROUP(scif1_data_b),
3504 SH_PFC_PIN_GROUP(scif2_data_a),
3505 SH_PFC_PIN_GROUP(scif2_clk),
3506 SH_PFC_PIN_GROUP(scif2_data_b),
3507 SH_PFC_PIN_GROUP(scif3_data_a),
3508 SH_PFC_PIN_GROUP(scif3_clk),
3509 SH_PFC_PIN_GROUP(scif3_ctrl),
3510 SH_PFC_PIN_GROUP(scif3_data_b),
3511 SH_PFC_PIN_GROUP(scif4_data_a),
3512 SH_PFC_PIN_GROUP(scif4_clk_a),
3513 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3514 SH_PFC_PIN_GROUP(scif4_data_b),
3515 SH_PFC_PIN_GROUP(scif4_clk_b),
3516 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3517 SH_PFC_PIN_GROUP(scif4_data_c),
3518 SH_PFC_PIN_GROUP(scif4_clk_c),
3519 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3520 SH_PFC_PIN_GROUP(scif5_data),
3521 SH_PFC_PIN_GROUP(scif5_clk),
f27200f9
GU		 3522 SH_PFC_PIN_GROUP(scif_clk_a),
3523 SH_PFC_PIN_GROUP(scif_clk_b),
20cacae1
TK		 3524 SH_PFC_PIN_GROUP(sdhi0_data1),
3525 SH_PFC_PIN_GROUP(sdhi0_data4),
3526 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3527 SH_PFC_PIN_GROUP(sdhi0_cd),
3528 SH_PFC_PIN_GROUP(sdhi0_wp),
3529 SH_PFC_PIN_GROUP(sdhi1_data1),
3530 SH_PFC_PIN_GROUP(sdhi1_data4),
3531 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3532 SH_PFC_PIN_GROUP(sdhi1_cd),
3533 SH_PFC_PIN_GROUP(sdhi1_wp),
3534 SH_PFC_PIN_GROUP(sdhi2_data1),
3535 SH_PFC_PIN_GROUP(sdhi2_data4),
3536 SH_PFC_PIN_GROUP(sdhi2_data8),
3537 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3538 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3539 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3540 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3541 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3542 SH_PFC_PIN_GROUP(sdhi2_ds),
3543 SH_PFC_PIN_GROUP(sdhi3_data1),
3544 SH_PFC_PIN_GROUP(sdhi3_data4),
3545 SH_PFC_PIN_GROUP(sdhi3_data8),
3546 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3547 SH_PFC_PIN_GROUP(sdhi3_cd),
3548 SH_PFC_PIN_GROUP(sdhi3_wp),
3549 SH_PFC_PIN_GROUP(sdhi3_ds),
9b132ba3
KM		 3550 SH_PFC_PIN_GROUP(ssi0_data),
3551 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3552 SH_PFC_PIN_GROUP(ssi1_data_a),
3553 SH_PFC_PIN_GROUP(ssi1_data_b),
3554 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3555 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3556 SH_PFC_PIN_GROUP(ssi2_data_a),
3557 SH_PFC_PIN_GROUP(ssi2_data_b),
3558 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3559 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3560 SH_PFC_PIN_GROUP(ssi3_data),
3561 SH_PFC_PIN_GROUP(ssi34_ctrl),
3562 SH_PFC_PIN_GROUP(ssi4_data),
3563 SH_PFC_PIN_GROUP(ssi4_ctrl),
3564 SH_PFC_PIN_GROUP(ssi5_data),
3565 SH_PFC_PIN_GROUP(ssi5_ctrl),
3566 SH_PFC_PIN_GROUP(ssi6_data),
3567 SH_PFC_PIN_GROUP(ssi6_ctrl),
3568 SH_PFC_PIN_GROUP(ssi7_data),
3569 SH_PFC_PIN_GROUP(ssi78_ctrl),
3570 SH_PFC_PIN_GROUP(ssi8_data),
3571 SH_PFC_PIN_GROUP(ssi9_data_a),
3572 SH_PFC_PIN_GROUP(ssi9_data_b),
3573 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3574 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
76250a6c
TK		 3575 SH_PFC_PIN_GROUP(usb0),
3576 SH_PFC_PIN_GROUP(usb1),
3577 SH_PFC_PIN_GROUP(usb2),
ff8459a5
GU		 3578};
3579
c33a7fe3
KM		 3580static const char * const audio_clk_groups[] = {
3581 "audio_clk_a_a",
3582 "audio_clk_a_b",
3583 "audio_clk_a_c",
3584 "audio_clk_b_a",
3585 "audio_clk_b_b",
3586 "audio_clk_c_a",
3587 "audio_clk_c_b",
3588 "audio_clkout_a",
3589 "audio_clkout_b",
3590 "audio_clkout_c",
3591 "audio_clkout_d",
3592 "audio_clkout1_a",
3593 "audio_clkout1_b",
3594 "audio_clkout2_a",
3595 "audio_clkout2_b",
3596 "audio_clkout3_a",
3597 "audio_clkout3_b",
3598};
3599
819fd4bf
TK		 3600static const char * const avb_groups[] = {
3601 "avb_link",
3602 "avb_magic",
3603 "avb_phy_int",
3604 "avb_mdc",
3605 "avb_avtp_pps",
3606 "avb_avtp_match_a",
3607 "avb_avtp_capture_a",
3608 "avb_avtp_match_b",
3609 "avb_avtp_capture_b",
3610};
3611
a4d9791f
RS		 3612static const char * const can0_groups[] = {
3613 "can0_data_a",
3614 "can0_data_b",
3615};
3616
3617static const char * const can1_groups[] = {
3618 "can1_data",
3619};
3620
3621static const char * const can_clk_groups[] = {
3622 "can_clk",
3623};
3624
4412bb5d
RS		 3625static const char * const canfd0_groups[] = {
3626 "canfd0_data_a",
3627 "canfd0_data_b",
3628};
3629
3630static const char * const canfd1_groups[] = {
3631 "canfd1_data",
3632};
3633
a56069c4
GU		 3634static const char * const hscif0_groups[] = {
3635 "hscif0_data",
3636 "hscif0_clk",
3637 "hscif0_ctrl",
3638};
3639
3640static const char * const hscif1_groups[] = {
3641 "hscif1_data_a",
3642 "hscif1_clk_a",
3643 "hscif1_ctrl_a",
3644 "hscif1_data_b",
3645 "hscif1_clk_b",
3646 "hscif1_ctrl_b",
3647};
3648
3649static const char * const hscif2_groups[] = {
3650 "hscif2_data_a",
3651 "hscif2_clk_a",
3652 "hscif2_ctrl_a",
3653 "hscif2_data_b",
3654 "hscif2_clk_b",
3655 "hscif2_ctrl_b",
3656};
3657
3658static const char * const hscif3_groups[] = {
3659 "hscif3_data_a",
3660 "hscif3_clk",
3661 "hscif3_ctrl",
3662 "hscif3_data_b",
3663 "hscif3_data_c",
3664 "hscif3_data_d",
3665};
3666
3667static const char * const hscif4_groups[] = {
3668 "hscif4_data_a",
3669 "hscif4_clk",
3670 "hscif4_ctrl",
3671 "hscif4_data_b",
3672};
3673
2544ef72
KM		 3674static const char * const i2c1_groups[] = {
3675 "i2c1_a",
3676 "i2c1_b",
3677};
3678
3679static const char * const i2c2_groups[] = {
3680 "i2c2_a",
3681 "i2c2_b",
3682};
3683
3684static const char * const i2c6_groups[] = {
3685 "i2c6_a",
3686 "i2c6_b",
3687 "i2c6_c",
3688};
3689
bb46f6f3
MD		 3690static const char * const intc_ex_groups[] = {
3691 "intc_ex_irq0",
3692 "intc_ex_irq1",
3693 "intc_ex_irq2",
3694 "intc_ex_irq3",
3695 "intc_ex_irq4",
3696 "intc_ex_irq5",
3697};
3698
e7419b81
GU		 3699static const char * const msiof0_groups[] = {
3700 "msiof0_clk",
3701 "msiof0_sync",
3702 "msiof0_ss1",
3703 "msiof0_ss2",
3704 "msiof0_txd",
3705 "msiof0_rxd",
3706};
3707
3708static const char * const msiof1_groups[] = {
3709 "msiof1_clk_a",
3710 "msiof1_sync_a",
3711 "msiof1_ss1_a",
3712 "msiof1_ss2_a",
3713 "msiof1_txd_a",
3714 "msiof1_rxd_a",
3715 "msiof1_clk_b",
3716 "msiof1_sync_b",
3717 "msiof1_ss1_b",
3718 "msiof1_ss2_b",
3719 "msiof1_txd_b",
3720 "msiof1_rxd_b",
3721 "msiof1_clk_c",
3722 "msiof1_sync_c",
3723 "msiof1_ss1_c",
3724 "msiof1_ss2_c",
3725 "msiof1_txd_c",
3726 "msiof1_rxd_c",
3727 "msiof1_clk_d",
3728 "msiof1_sync_d",
3729 "msiof1_ss1_d",
3730 "msiof1_ss2_d",
3731 "msiof1_txd_d",
3732 "msiof1_rxd_d",
3733 "msiof1_clk_e",
3734 "msiof1_sync_e",
3735 "msiof1_ss1_e",
3736 "msiof1_ss2_e",
3737 "msiof1_txd_e",
3738 "msiof1_rxd_e",
3739 "msiof1_clk_f",
3740 "msiof1_sync_f",
3741 "msiof1_ss1_f",
3742 "msiof1_ss2_f",
3743 "msiof1_txd_f",
3744 "msiof1_rxd_f",
3745 "msiof1_clk_g",
3746 "msiof1_sync_g",
3747 "msiof1_ss1_g",
3748 "msiof1_ss2_g",
3749 "msiof1_txd_g",
3750 "msiof1_rxd_g",
3751};
3752
3753static const char * const msiof2_groups[] = {
3754 "msiof2_clk_a",
3755 "msiof2_sync_a",
3756 "msiof2_ss1_a",
3757 "msiof2_ss2_a",
3758 "msiof2_txd_a",
3759 "msiof2_rxd_a",
3760 "msiof2_clk_b",
3761 "msiof2_sync_b",
3762 "msiof2_ss1_b",
3763 "msiof2_ss2_b",
3764 "msiof2_txd_b",
3765 "msiof2_rxd_b",
3766 "msiof2_clk_c",
3767 "msiof2_sync_c",
3768 "msiof2_ss1_c",
3769 "msiof2_ss2_c",
3770 "msiof2_txd_c",
3771 "msiof2_rxd_c",
3772 "msiof2_clk_d",
3773 "msiof2_sync_d",
3774 "msiof2_ss1_d",
3775 "msiof2_ss2_d",
3776 "msiof2_txd_d",
3777 "msiof2_rxd_d",
3778};
3779
3780static const char * const msiof3_groups[] = {
3781 "msiof3_clk_a",
3782 "msiof3_sync_a",
3783 "msiof3_ss1_a",
3784 "msiof3_ss2_a",
3785 "msiof3_txd_a",
3786 "msiof3_rxd_a",
3787 "msiof3_clk_b",
3788 "msiof3_sync_b",
3789 "msiof3_ss1_b",
3790 "msiof3_ss2_b",
3791 "msiof3_txd_b",
3792 "msiof3_rxd_b",
3793 "msiof3_clk_c",
3794 "msiof3_sync_c",
3795 "msiof3_txd_c",
3796 "msiof3_rxd_c",
3797 "msiof3_clk_d",
3798 "msiof3_sync_d",
3799 "msiof3_ss1_d",
3800 "msiof3_txd_d",
3801 "msiof3_rxd_d",
3802};
3803
4ca88cf6
TK		 3804static const char * const pwm0_groups[] = {
3805 "pwm0",
3806};
3807
3808static const char * const pwm1_groups[] = {
3809 "pwm1_a",
3810 "pwm1_b",
3811};
3812
3813static const char * const pwm2_groups[] = {
3814 "pwm2_a",
3815 "pwm2_b",
3816};
3817
3818static const char * const pwm3_groups[] = {
3819 "pwm3_a",
3820 "pwm3_b",
3821};
3822
3823static const char * const pwm4_groups[] = {
3824 "pwm4_a",
3825 "pwm4_b",
3826};
3827
3828static const char * const pwm5_groups[] = {
3829 "pwm5_a",
3830 "pwm5_b",
3831};
3832
3833static const char * const pwm6_groups[] = {
3834 "pwm6_a",
3835 "pwm6_b",
3836};
3837
34dc4e16
TK		 3838static const char * const sata0_groups[] = {
3839 "sata0_devslp_a",
3840 "sata0_devslp_b",
3841};
3842
ff8459a5
GU		 3843static const char * const scif0_groups[] = {
3844 "scif0_data",
3845 "scif0_clk",
3846 "scif0_ctrl",
3847};
3848
3849static const char * const scif1_groups[] = {
3850 "scif1_data_a",
3851 "scif1_clk",
3852 "scif1_ctrl",
3853 "scif1_data_b",
3854};
3855
3856static const char * const scif2_groups[] = {
3857 "scif2_data_a",
3858 "scif2_clk",
3859 "scif2_data_b",
3860};
3861
3862static const char * const scif3_groups[] = {
3863 "scif3_data_a",
3864 "scif3_clk",
3865 "scif3_ctrl",
3866 "scif3_data_b",
3867};
3868
3869static const char * const scif4_groups[] = {
3870 "scif4_data_a",
3871 "scif4_clk_a",
3872 "scif4_ctrl_a",
3873 "scif4_data_b",
3874 "scif4_clk_b",
3875 "scif4_ctrl_b",
3876 "scif4_data_c",
3877 "scif4_clk_c",
3878 "scif4_ctrl_c",
3879};
3880
3881static const char * const scif5_groups[] = {
3882 "scif5_data",
3883 "scif5_clk",
0b0ffc96
TK		 3884};
3885
f27200f9
GU		 3886static const char * const scif_clk_groups[] = {
3887 "scif_clk_a",
3888 "scif_clk_b",
3889};
3890
20cacae1
TK		 3891static const char * const sdhi0_groups[] = {
3892 "sdhi0_data1",
3893 "sdhi0_data4",
3894 "sdhi0_ctrl",
3895 "sdhi0_cd",
3896 "sdhi0_wp",
3897};
3898
3899static const char * const sdhi1_groups[] = {
3900 "sdhi1_data1",
3901 "sdhi1_data4",
3902 "sdhi1_ctrl",
3903 "sdhi1_cd",
3904 "sdhi1_wp",
3905};
3906
3907static const char * const sdhi2_groups[] = {
3908 "sdhi2_data1",
3909 "sdhi2_data4",
3910 "sdhi2_data8",
3911 "sdhi2_ctrl",
3912 "sdhi2_cd_a",
3913 "sdhi2_wp_a",
3914 "sdhi2_cd_b",
3915 "sdhi2_wp_b",
3916 "sdhi2_ds",
3917};
3918
3919static const char * const sdhi3_groups[] = {
3920 "sdhi3_data1",
3921 "sdhi3_data4",
3922 "sdhi3_data8",
3923 "sdhi3_ctrl",
3924 "sdhi3_cd",
3925 "sdhi3_wp",
3926 "sdhi3_ds",
3927};
3928
9b132ba3
KM		 3929static const char * const ssi_groups[] = {
3930 "ssi0_data",
3931 "ssi01239_ctrl",
3932 "ssi1_data_a",
3933 "ssi1_data_b",
3934 "ssi1_ctrl_a",
3935 "ssi1_ctrl_b",
3936 "ssi2_data_a",
3937 "ssi2_data_b",
3938 "ssi2_ctrl_a",
3939 "ssi2_ctrl_b",
3940 "ssi3_data",
3941 "ssi34_ctrl",
3942 "ssi4_data",
3943 "ssi4_ctrl",
3944 "ssi5_data",
3945 "ssi5_ctrl",
3946 "ssi6_data",
3947 "ssi6_ctrl",
3948 "ssi7_data",
3949 "ssi78_ctrl",
3950 "ssi8_data",
3951 "ssi9_data_a",
3952 "ssi9_data_b",
3953 "ssi9_ctrl_a",
3954 "ssi9_ctrl_b",
3955};
3956
76250a6c
TK		 3957static const char * const usb0_groups[] = {
3958 "usb0",
3959};
3960
3961static const char * const usb1_groups[] = {
3962 "usb1",
3963};
3964
3965static const char * const usb2_groups[] = {
3966 "usb2",
3967};
3968
0b0ffc96 3969static const struct sh_pfc_function pinmux_functions[] = {
c33a7fe3 3970 SH_PFC_FUNCTION(audio_clk),
819fd4bf 3971 SH_PFC_FUNCTION(avb),
a4d9791f
RS		 3972 SH_PFC_FUNCTION(can0),
3973 SH_PFC_FUNCTION(can1),
3974 SH_PFC_FUNCTION(can_clk),
4412bb5d
RS		 3975 SH_PFC_FUNCTION(canfd0),
3976 SH_PFC_FUNCTION(canfd1),
a56069c4
GU		 3977 SH_PFC_FUNCTION(hscif0),
3978 SH_PFC_FUNCTION(hscif1),
3979 SH_PFC_FUNCTION(hscif2),
3980 SH_PFC_FUNCTION(hscif3),
3981 SH_PFC_FUNCTION(hscif4),
2544ef72
KM		 3982 SH_PFC_FUNCTION(i2c1),
3983 SH_PFC_FUNCTION(i2c2),
3984 SH_PFC_FUNCTION(i2c6),
bb46f6f3 3985 SH_PFC_FUNCTION(intc_ex),
e7419b81
GU		 3986 SH_PFC_FUNCTION(msiof0),
3987 SH_PFC_FUNCTION(msiof1),
3988 SH_PFC_FUNCTION(msiof2),
3989 SH_PFC_FUNCTION(msiof3),
4ca88cf6
TK		 3990 SH_PFC_FUNCTION(pwm0),
3991 SH_PFC_FUNCTION(pwm1),
3992 SH_PFC_FUNCTION(pwm2),
3993 SH_PFC_FUNCTION(pwm3),
3994 SH_PFC_FUNCTION(pwm4),
3995 SH_PFC_FUNCTION(pwm5),
3996 SH_PFC_FUNCTION(pwm6),
34dc4e16 3997 SH_PFC_FUNCTION(sata0),
ff8459a5
GU		 3998 SH_PFC_FUNCTION(scif0),
3999 SH_PFC_FUNCTION(scif1),
4000 SH_PFC_FUNCTION(scif2),
4001 SH_PFC_FUNCTION(scif3),
4002 SH_PFC_FUNCTION(scif4),
4003 SH_PFC_FUNCTION(scif5),
f27200f9 4004 SH_PFC_FUNCTION(scif_clk),
20cacae1
TK		 4005 SH_PFC_FUNCTION(sdhi0),
4006 SH_PFC_FUNCTION(sdhi1),
4007 SH_PFC_FUNCTION(sdhi2),
4008 SH_PFC_FUNCTION(sdhi3),
9b132ba3 4009 SH_PFC_FUNCTION(ssi),
76250a6c
TK		 4010 SH_PFC_FUNCTION(usb0),
4011 SH_PFC_FUNCTION(usb1),
4012 SH_PFC_FUNCTION(usb2),
0b0ffc96
TK		 4013};
4014
4015static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4016#define F_(x, y) FN_##y
4017#define FM(x) FN_##x
4018 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4019 0, 0,
4020 0, 0,
4021 0, 0,
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 0, 0,
4028 0, 0,
4029 0, 0,
4030 0, 0,
4031 0, 0,
4032 0, 0,
4033 0, 0,
4034 0, 0,
4035 GP_0_15_FN, GPSR0_15,
4036 GP_0_14_FN, GPSR0_14,
4037 GP_0_13_FN, GPSR0_13,
4038 GP_0_12_FN, GPSR0_12,
4039 GP_0_11_FN, GPSR0_11,
4040 GP_0_10_FN, GPSR0_10,
4041 GP_0_9_FN, GPSR0_9,
4042 GP_0_8_FN, GPSR0_8,
4043 GP_0_7_FN, GPSR0_7,
4044 GP_0_6_FN, GPSR0_6,
4045 GP_0_5_FN, GPSR0_5,
4046 GP_0_4_FN, GPSR0_4,
4047 GP_0_3_FN, GPSR0_3,
4048 GP_0_2_FN, GPSR0_2,
4049 GP_0_1_FN, GPSR0_1,
4050 GP_0_0_FN, GPSR0_0, }
4051 },
4052 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4053 0, 0,
4054 0, 0,
4055 0, 0,
4056 0, 0,
4057 GP_1_27_FN, GPSR1_27,
4058 GP_1_26_FN, GPSR1_26,
4059 GP_1_25_FN, GPSR1_25,
4060 GP_1_24_FN, GPSR1_24,
4061 GP_1_23_FN, GPSR1_23,
4062 GP_1_22_FN, GPSR1_22,
4063 GP_1_21_FN, GPSR1_21,
4064 GP_1_20_FN, GPSR1_20,
4065 GP_1_19_FN, GPSR1_19,
4066 GP_1_18_FN, GPSR1_18,
4067 GP_1_17_FN, GPSR1_17,
4068 GP_1_16_FN, GPSR1_16,
4069 GP_1_15_FN, GPSR1_15,
4070 GP_1_14_FN, GPSR1_14,
4071 GP_1_13_FN, GPSR1_13,
4072 GP_1_12_FN, GPSR1_12,
4073 GP_1_11_FN, GPSR1_11,
4074 GP_1_10_FN, GPSR1_10,
4075 GP_1_9_FN, GPSR1_9,
4076 GP_1_8_FN, GPSR1_8,
4077 GP_1_7_FN, GPSR1_7,
4078 GP_1_6_FN, GPSR1_6,
4079 GP_1_5_FN, GPSR1_5,
4080 GP_1_4_FN, GPSR1_4,
4081 GP_1_3_FN, GPSR1_3,
4082 GP_1_2_FN, GPSR1_2,
4083 GP_1_1_FN, GPSR1_1,
4084 GP_1_0_FN, GPSR1_0, }
4085 },
4086 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4087 0, 0,
4088 0, 0,
4089 0, 0,
4090 0, 0,
4091 0, 0,
4092 0, 0,
4093 0, 0,
4094 0, 0,
4095 0, 0,
4096 0, 0,
4097 0, 0,
4098 0, 0,
4099 0, 0,
4100 0, 0,
4101 0, 0,
4102 0, 0,
4103 0, 0,
4104 GP_2_14_FN, GPSR2_14,
4105 GP_2_13_FN, GPSR2_13,
4106 GP_2_12_FN, GPSR2_12,
4107 GP_2_11_FN, GPSR2_11,
4108 GP_2_10_FN, GPSR2_10,
4109 GP_2_9_FN, GPSR2_9,
4110 GP_2_8_FN, GPSR2_8,
4111 GP_2_7_FN, GPSR2_7,
4112 GP_2_6_FN, GPSR2_6,
4113 GP_2_5_FN, GPSR2_5,
4114 GP_2_4_FN, GPSR2_4,
4115 GP_2_3_FN, GPSR2_3,
4116 GP_2_2_FN, GPSR2_2,
4117 GP_2_1_FN, GPSR2_1,
4118 GP_2_0_FN, GPSR2_0, }
4119 },
4120 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4121 0, 0,
4122 0, 0,
4123 0, 0,
4124 0, 0,
4125 0, 0,
4126 0, 0,
4127 0, 0,
4128 0, 0,
4129 0, 0,
4130 0, 0,
4131 0, 0,
4132 0, 0,
4133 0, 0,
4134 0, 0,
4135 0, 0,
4136 0, 0,
4137 GP_3_15_FN, GPSR3_15,
4138 GP_3_14_FN, GPSR3_14,
4139 GP_3_13_FN, GPSR3_13,
4140 GP_3_12_FN, GPSR3_12,
4141 GP_3_11_FN, GPSR3_11,
4142 GP_3_10_FN, GPSR3_10,
4143 GP_3_9_FN, GPSR3_9,
4144 GP_3_8_FN, GPSR3_8,
4145 GP_3_7_FN, GPSR3_7,
4146 GP_3_6_FN, GPSR3_6,
4147 GP_3_5_FN, GPSR3_5,
4148 GP_3_4_FN, GPSR3_4,
4149 GP_3_3_FN, GPSR3_3,
4150 GP_3_2_FN, GPSR3_2,
4151 GP_3_1_FN, GPSR3_1,
4152 GP_3_0_FN, GPSR3_0, }
4153 },
4154 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4155 0, 0,
4156 0, 0,
4157 0, 0,
4158 0, 0,
4159 0, 0,
4160 0, 0,
4161 0, 0,
4162 0, 0,
4163 0, 0,
4164 0, 0,
4165 0, 0,
4166 0, 0,
4167 0, 0,
4168 0, 0,
4169 GP_4_17_FN, GPSR4_17,
4170 GP_4_16_FN, GPSR4_16,
4171 GP_4_15_FN, GPSR4_15,
4172 GP_4_14_FN, GPSR4_14,
4173 GP_4_13_FN, GPSR4_13,
4174 GP_4_12_FN, GPSR4_12,
4175 GP_4_11_FN, GPSR4_11,
4176 GP_4_10_FN, GPSR4_10,
4177 GP_4_9_FN, GPSR4_9,
4178 GP_4_8_FN, GPSR4_8,
4179 GP_4_7_FN, GPSR4_7,
4180 GP_4_6_FN, GPSR4_6,
4181 GP_4_5_FN, GPSR4_5,
4182 GP_4_4_FN, GPSR4_4,
4183 GP_4_3_FN, GPSR4_3,
4184 GP_4_2_FN, GPSR4_2,
4185 GP_4_1_FN, GPSR4_1,
4186 GP_4_0_FN, GPSR4_0, }
4187 },
4188 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4189 0, 0,
4190 0, 0,
4191 0, 0,
4192 0, 0,
4193 0, 0,
4194 0, 0,
4195 GP_5_25_FN, GPSR5_25,
4196 GP_5_24_FN, GPSR5_24,
4197 GP_5_23_FN, GPSR5_23,
4198 GP_5_22_FN, GPSR5_22,
4199 GP_5_21_FN, GPSR5_21,
4200 GP_5_20_FN, GPSR5_20,
4201 GP_5_19_FN, GPSR5_19,
4202 GP_5_18_FN, GPSR5_18,
4203 GP_5_17_FN, GPSR5_17,
4204 GP_5_16_FN, GPSR5_16,
4205 GP_5_15_FN, GPSR5_15,
4206 GP_5_14_FN, GPSR5_14,
4207 GP_5_13_FN, GPSR5_13,
4208 GP_5_12_FN, GPSR5_12,
4209 GP_5_11_FN, GPSR5_11,
4210 GP_5_10_FN, GPSR5_10,
4211 GP_5_9_FN, GPSR5_9,
4212 GP_5_8_FN, GPSR5_8,
4213 GP_5_7_FN, GPSR5_7,
4214 GP_5_6_FN, GPSR5_6,
4215 GP_5_5_FN, GPSR5_5,
4216 GP_5_4_FN, GPSR5_4,
4217 GP_5_3_FN, GPSR5_3,
4218 GP_5_2_FN, GPSR5_2,
4219 GP_5_1_FN, GPSR5_1,
4220 GP_5_0_FN, GPSR5_0, }
4221 },
4222 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4223 GP_6_31_FN, GPSR6_31,
4224 GP_6_30_FN, GPSR6_30,
4225 GP_6_29_FN, GPSR6_29,
4226 GP_6_28_FN, GPSR6_28,
4227 GP_6_27_FN, GPSR6_27,
4228 GP_6_26_FN, GPSR6_26,
4229 GP_6_25_FN, GPSR6_25,
4230 GP_6_24_FN, GPSR6_24,
4231 GP_6_23_FN, GPSR6_23,
4232 GP_6_22_FN, GPSR6_22,
4233 GP_6_21_FN, GPSR6_21,
4234 GP_6_20_FN, GPSR6_20,
4235 GP_6_19_FN, GPSR6_19,
4236 GP_6_18_FN, GPSR6_18,
4237 GP_6_17_FN, GPSR6_17,
4238 GP_6_16_FN, GPSR6_16,
4239 GP_6_15_FN, GPSR6_15,
4240 GP_6_14_FN, GPSR6_14,
4241 GP_6_13_FN, GPSR6_13,
4242 GP_6_12_FN, GPSR6_12,
4243 GP_6_11_FN, GPSR6_11,
4244 GP_6_10_FN, GPSR6_10,
4245 GP_6_9_FN, GPSR6_9,
4246 GP_6_8_FN, GPSR6_8,
4247 GP_6_7_FN, GPSR6_7,
4248 GP_6_6_FN, GPSR6_6,
4249 GP_6_5_FN, GPSR6_5,
4250 GP_6_4_FN, GPSR6_4,
4251 GP_6_3_FN, GPSR6_3,
4252 GP_6_2_FN, GPSR6_2,
4253 GP_6_1_FN, GPSR6_1,
4254 GP_6_0_FN, GPSR6_0, }
4255 },
4256 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4257 0, 0,
4258 0, 0,
4259 0, 0,
4260 0, 0,
4261 0, 0,
4262 0, 0,
4263 0, 0,
4264 0, 0,
4265 0, 0,
4266 0, 0,
4267 0, 0,
4268 0, 0,
4269 0, 0,
4270 0, 0,
4271 0, 0,
4272 0, 0,
4273 0, 0,
4274 0, 0,
4275 0, 0,
4276 0, 0,
4277 0, 0,
4278 0, 0,
4279 0, 0,
4280 0, 0,
4281 0, 0,
4282 0, 0,
4283 0, 0,
4284 0, 0,
4285 GP_7_3_FN, GPSR7_3,
4286 GP_7_2_FN, GPSR7_2,
4287 GP_7_1_FN, GPSR7_1,
4288 GP_7_0_FN, GPSR7_0, }
4289 },
4290#undef F_
4291#undef FM
4292
4293#define F_(x, y) x,
4294#define FM(x) FN_##x,
4295 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4296 IP0_31_28
4297 IP0_27_24
4298 IP0_23_20
4299 IP0_19_16
4300 IP0_15_12
4301 IP0_11_8
4302 IP0_7_4
4303 IP0_3_0 }
4304 },
4305 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4306 IP1_31_28
4307 IP1_27_24
4308 IP1_23_20
4309 IP1_19_16
4310 IP1_15_12
4311 IP1_11_8
4312 IP1_7_4
4313 IP1_3_0 }
4314 },
4315 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4316 IP2_31_28
4317 IP2_27_24
4318 IP2_23_20
4319 IP2_19_16
4320 IP2_15_12
4321 IP2_11_8
4322 IP2_7_4
4323 IP2_3_0 }
4324 },
4325 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4326 IP3_31_28
4327 IP3_27_24
4328 IP3_23_20
4329 IP3_19_16
4330 IP3_15_12
4331 IP3_11_8
4332 IP3_7_4
4333 IP3_3_0 }
4334 },
4335 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4336 IP4_31_28
4337 IP4_27_24
4338 IP4_23_20
4339 IP4_19_16
4340 IP4_15_12
4341 IP4_11_8
4342 IP4_7_4
4343 IP4_3_0 }
4344 },
4345 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4346 IP5_31_28
4347 IP5_27_24
4348 IP5_23_20
4349 IP5_19_16
4350 IP5_15_12
4351 IP5_11_8
4352 IP5_7_4
4353 IP5_3_0 }
4354 },
4355 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4356 IP6_31_28
4357 IP6_27_24
4358 IP6_23_20
4359 IP6_19_16
4360 IP6_15_12
4361 IP6_11_8
4362 IP6_7_4
4363 IP6_3_0 }
4364 },
4365 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4366 IP7_31_28
4367 IP7_27_24
4368 IP7_23_20
4369 IP7_19_16
4370 IP7_15_12
4371 IP7_11_8
4372 IP7_7_4
4373 IP7_3_0 }
4374 },
4375 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4376 IP8_31_28
4377 IP8_27_24
4378 IP8_23_20
4379 IP8_19_16
4380 IP8_15_12
4381 IP8_11_8
4382 IP8_7_4
4383 IP8_3_0 }
4384 },
4385 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4386 IP9_31_28
4387 IP9_27_24
4388 IP9_23_20
4389 IP9_19_16
4390 IP9_15_12
4391 IP9_11_8
4392 IP9_7_4
4393 IP9_3_0 }
4394 },
4395 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4396 IP10_31_28
4397 IP10_27_24
4398 IP10_23_20
4399 IP10_19_16
4400 IP10_15_12
4401 IP10_11_8
4402 IP10_7_4
4403 IP10_3_0 }
4404 },
4405 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4406 IP11_31_28
4407 IP11_27_24
4408 IP11_23_20
4409 IP11_19_16
4410 IP11_15_12
4411 IP11_11_8
4412 IP11_7_4
4413 IP11_3_0 }
4414 },
4415 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4416 IP12_31_28
4417 IP12_27_24
4418 IP12_23_20
4419 IP12_19_16
4420 IP12_15_12
4421 IP12_11_8
4422 IP12_7_4
4423 IP12_3_0 }
4424 },
4425 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4426 IP13_31_28
4427 IP13_27_24
4428 IP13_23_20
4429 IP13_19_16
4430 IP13_15_12
4431 IP13_11_8
4432 IP13_7_4
4433 IP13_3_0 }
4434 },
4435 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4436 IP14_31_28
4437 IP14_27_24
4438 IP14_23_20
4439 IP14_19_16
4440 IP14_15_12
4441 IP14_11_8
4442 IP14_7_4
4443 IP14_3_0 }
4444 },
4445 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4446 IP15_31_28
4447 IP15_27_24
4448 IP15_23_20
4449 IP15_19_16
4450 IP15_15_12
4451 IP15_11_8
4452 IP15_7_4
4453 IP15_3_0 }
4454 },
4455 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4456 IP16_31_28
4457 IP16_27_24
4458 IP16_23_20
4459 IP16_19_16
4460 IP16_15_12
4461 IP16_11_8
4462 IP16_7_4
4463 IP16_3_0 }
4464 },
4465 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4466 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4467 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4468 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4469 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4470 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4471 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4472 IP17_7_4
4473 IP17_3_0 }
4474 },
4475#undef F_
4476#undef FM
4477
4478#define F_(x, y) x,
4479#define FM(x) FN_##x,
4480 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4481 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4482 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4483 0, 0, /* RESERVED 31 */
4484 MOD_SEL0_30_29
4485 MOD_SEL0_28_27
4486 MOD_SEL0_26_25_24
4487 MOD_SEL0_23
4488 MOD_SEL0_22
4489 MOD_SEL0_21_20
4490 MOD_SEL0_19
4491 MOD_SEL0_18
4492 MOD_SEL0_17
4493 MOD_SEL0_16_15
4494 MOD_SEL0_14
4495 MOD_SEL0_13
4496 MOD_SEL0_12
4497 MOD_SEL0_11
4498 MOD_SEL0_10
4499 MOD_SEL0_9
4500 MOD_SEL0_8
4501 MOD_SEL0_7_6
4502 MOD_SEL0_5_4
4503 MOD_SEL0_3
4504 MOD_SEL0_2_1
4505 0, 0, /* RESERVED 0 */ }
4506 },
4507 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4508 2, 3, 1, 2, 3, 1, 1, 2, 1,
4509 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4510 MOD_SEL1_31_30
4511 MOD_SEL1_29_28_27
4512 MOD_SEL1_26
4513 MOD_SEL1_25_24
4514 MOD_SEL1_23_22_21
4515 MOD_SEL1_20
4516 MOD_SEL1_19
4517 MOD_SEL1_18_17
4518 MOD_SEL1_16
4519 MOD_SEL1_15_14
4520 MOD_SEL1_13
4521 MOD_SEL1_12
4522 MOD_SEL1_11
4523 MOD_SEL1_10
4524 MOD_SEL1_9
4525 0, 0, 0, 0, /* RESERVED 8, 7 */
4526 MOD_SEL1_6
4527 MOD_SEL1_5
4528 MOD_SEL1_4
4529 MOD_SEL1_3
4530 MOD_SEL1_2
4531 MOD_SEL1_1
4532 MOD_SEL1_0 }
4533 },
4534 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4535 1, 1, 1, 1, 4, 4, 4,
4536 4, 4, 4, 1, 2, 1) {
4537 MOD_SEL2_31
4538 MOD_SEL2_30
4539 MOD_SEL2_29
4540 /* RESERVED 28 */
4541 0, 0,
4542 /* RESERVED 27, 26, 25, 24 */
4543 0, 0, 0, 0, 0, 0, 0, 0,
4544 0, 0, 0, 0, 0, 0, 0, 0,
4545 /* RESERVED 23, 22, 21, 20 */
4546 0, 0, 0, 0, 0, 0, 0, 0,
4547 0, 0, 0, 0, 0, 0, 0, 0,
4548 /* RESERVED 19, 18, 17, 16 */
4549 0, 0, 0, 0, 0, 0, 0, 0,
4550 0, 0, 0, 0, 0, 0, 0, 0,
4551 /* RESERVED 15, 14, 13, 12 */
4552 0, 0, 0, 0, 0, 0, 0, 0,
4553 0, 0, 0, 0, 0, 0, 0, 0,
4554 /* RESERVED 11, 10, 9, 8 */
4555 0, 0, 0, 0, 0, 0, 0, 0,
4556 0, 0, 0, 0, 0, 0, 0, 0,
4557 /* RESERVED 7, 6, 5, 4 */
4558 0, 0, 0, 0, 0, 0, 0, 0,
4559 0, 0, 0, 0, 0, 0, 0, 0,
4560 /* RESERVED 3 */
4561 0, 0,
a5d2dade
GU		 4562 /* RESERVED 2, 1 */
4563 0, 0, 0, 0,
0b0ffc96
TK		 4564 MOD_SEL2_0 }
4565 },
4566 { },
4567};
4568
92e6d9a2
LP		 4569static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4570 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4571 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4572 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4573 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4574 } },
4575 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4576 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4577 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4578 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4579 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4580 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4581 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4582 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4583 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4584 } },
4585 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4586 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4587 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4588 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4589 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4590 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4591 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4592 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4593 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4594 } },
4595 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4596 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4597 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4598 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4599 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4600 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4601 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4602 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4603 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4604 } },
4605 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4606 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4607 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4608 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4609 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4610 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4611 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4612 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4613 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4614 } },
4615 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4616 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4617 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4618 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4619 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4620 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4621 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4622 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4623 } },
4624 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4625 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4626 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4627 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4628 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4629 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4630 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4631 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4632 } },
4633 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4634 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4635 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4636 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4637 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4638 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4639 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4640 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4641 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4642 } },
4643 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4644 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4645 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4646 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4647 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4648 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4649 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4650 } },
4651 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4652 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4653 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4654 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4655 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4656 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4657 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4658 } },
4659 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4660 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4661 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4662 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4663 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4664 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4665 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4666 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4667 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4668 } },
4669 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4670 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4671 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4672 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4673 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4674 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4675 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4676 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4677 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4678 } },
4679 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4680 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4681 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4682 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4683 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4684 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4685 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4686 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4687 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4688 } },
4689 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4690 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4691 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4692 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4693 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4694 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4695 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4696 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4697 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4698 } },
4699 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4700 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4701 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4702 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4703 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4704 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4705 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4706 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4707 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4708 } },
4709 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4710 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4711 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4712 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4713 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4714 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4715 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4716 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4717 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4718 } },
4719 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4720 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4721 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4722 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4723 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4724 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4725 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4726 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4727 } },
4728 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4729 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4730 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4731 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4732 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4733 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
4734 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
4735 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4736 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4737 } },
4738 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4739 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4740 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4741 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4742 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4743 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4744 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4745 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4746 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4747 } },
4748 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4749 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4750 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4751 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4752 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4753 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4754 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4755 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4756 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4757 } },
4758 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4759 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4760 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4761 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4762 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4763 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4764 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
4765 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
4766 } },
4767 { },
4768};
4769
e9eace32
WS		 4770static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4771{
4772 int bit = -EINVAL;
4773
4774 *pocctrl = 0xe6060380;
4775
4776 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4777 bit = pin & 0x1f;
4778
4779 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4780 bit = (pin & 0x1f) + 12;
4781
4782 return bit;
4783}
4784
4785static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
4786 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
4787};
4788
0b0ffc96
TK		 4789const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4790 .name = "r8a77950_pfc",
e9eace32 4791 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 4792 .unlock_reg = 0xe6060000, /* PMMR */
4793
4794 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4795
4796 .pins = pinmux_pins,
4797 .nr_pins = ARRAY_SIZE(pinmux_pins),
4798 .groups = pinmux_groups,
4799 .nr_groups = ARRAY_SIZE(pinmux_groups),
4800 .functions = pinmux_functions,
4801 .nr_functions = ARRAY_SIZE(pinmux_functions),
4802
4803 .cfg_regs = pinmux_config_regs,
92e6d9a2 4804 .drive_regs = pinmux_drive_regs,
0b0ffc96 4805
b8b47d67
GU		 4806 .pinmux_data = pinmux_data,
4807 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 4808};
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