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UBUNTU: Ubuntu-4.13.0-45.50
[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
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0b0ffc96 1/*
b205914c 2 * R8A7795 ES2.0+ processor support - PFC hardware block.
0b0ffc96 3 *
b205914c 4 * Copyright (C) 2015-2016 Renesas Electronics Corporation
0b0ffc96
TK		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/kernel.h>
b205914c 12#include <linux/sys_soc.h>
0b0ffc96
TK		 13
14#include "core.h"
15#include "sh_pfc.h"
16
56065524
UH		 17#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
18 SH_PFC_PIN_CFG_PULL_UP | \
19 SH_PFC_PIN_CFG_PULL_DOWN)
20
0b0ffc96 21#define CPU_ALL_PORT(fn, sfx) \
56065524
UH		 22 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
23 PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
25 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
26 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
0b0ffc96
TK		 34/*
35 * F_() : just information
36 * FM() : macro for FN_xxx / xxx_MARK
37 */
38
39/* GPSR0 */
40#define GPSR0_15 F_(D15, IP7_11_8)
41#define GPSR0_14 F_(D14, IP7_7_4)
42#define GPSR0_13 F_(D13, IP7_3_0)
43#define GPSR0_12 F_(D12, IP6_31_28)
44#define GPSR0_11 F_(D11, IP6_27_24)
45#define GPSR0_10 F_(D10, IP6_23_20)
46#define GPSR0_9 F_(D9, IP6_19_16)
47#define GPSR0_8 F_(D8, IP6_15_12)
48#define GPSR0_7 F_(D7, IP6_11_8)
49#define GPSR0_6 F_(D6, IP6_7_4)
50#define GPSR0_5 F_(D5, IP6_3_0)
51#define GPSR0_4 F_(D4, IP5_31_28)
52#define GPSR0_3 F_(D3, IP5_27_24)
53#define GPSR0_2 F_(D2, IP5_23_20)
54#define GPSR0_1 F_(D1, IP5_19_16)
55#define GPSR0_0 F_(D0, IP5_15_12)
56
57/* GPSR1 */
58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
b205914c
GU		 105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
0b0ffc96
TK		 109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
b205914c
GU		 123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
0b0ffc96
TK		 140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
b205914c
GU		 143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
0b0ffc96 146#define GPSR5_22 FM(MSIOF0_RXD)
b205914c 147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
0b0ffc96 148#define GPSR5_20 FM(MSIOF0_TXD)
b205914c
GU		 149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
0b0ffc96 151#define GPSR5_17 FM(MSIOF0_SCK)
b205914c
GU		 152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
160#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
164#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
0b0ffc96
TK		 169
170/* GPSR6 */
b205914c
GU		 171#define GPSR6_31 F_(USB3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
0b0ffc96
TK		 189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
b205914c
GU		 192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
68e63892
KM		 196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
b205914c
GU		 198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
0b0ffc96
TK		 203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c 216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96 217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
b205914c
GU		 218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275
276/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
277#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 283#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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TK		 307
308/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
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GU		 309#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
330#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337
338/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
339#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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KM		 342#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
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GU		 344#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
359#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
360#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
361#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
363#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP18_3_0 FM(USB3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
365#define IP18_7_4 FM(USB3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
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TK		 366
367#define PINMUX_GPSR \
368\
369 GPSR6_31 \
370 GPSR6_30 \
371 GPSR6_29 \
372 GPSR6_28 \
373 GPSR1_27 GPSR6_27 \
374 GPSR1_26 GPSR6_26 \
375 GPSR1_25 GPSR5_25 GPSR6_25 \
376 GPSR1_24 GPSR5_24 GPSR6_24 \
377 GPSR1_23 GPSR5_23 GPSR6_23 \
378 GPSR1_22 GPSR5_22 GPSR6_22 \
379 GPSR1_21 GPSR5_21 GPSR6_21 \
380 GPSR1_20 GPSR5_20 GPSR6_20 \
381 GPSR1_19 GPSR5_19 GPSR6_19 \
382 GPSR1_18 GPSR5_18 GPSR6_18 \
383 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
384 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
385GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
386GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
387GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
388GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
389GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
390GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
391GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
392GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
393GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
394GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
395GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
396GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
397GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
398GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
399GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
400GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
401
402#define PINMUX_IPSR \
403\
404FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
405FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
406FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
407FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
408FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
409FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
410FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
411FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
412\
413FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
414FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
415FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
416FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
417FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
418FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
419FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
420FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
421\
422FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
423FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
424FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
425FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
426FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
427FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
428FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
429FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
430\
431FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
432FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
433FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
434FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
435FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
436FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
437FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
438FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
439\
b205914c
GU		 440FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
441FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
442FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
443FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
444FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
445FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
446FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
447FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
0b0ffc96
TK		 448
449/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
b205914c 450#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
0b0ffc96
TK		 451#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
452#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
453#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
454#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
b205914c
GU		 455#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
456#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
457#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
458#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
459#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
460#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
461#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
462#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
463#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
464#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
465#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
466#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
467#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
0b0ffc96
TK		 468
469/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
470#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
471#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
472#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
473#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
474#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
475#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
476#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
477#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
478#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
479#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
480#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
481#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
482#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
fd1aa743 483#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
0b0ffc96
TK		 484#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
485#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
486#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
487#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
488#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
489#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
490#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
491#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
492
493/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
494#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
495#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
496#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
b205914c
GU		 497#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
498#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
499#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
500#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
501#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
502#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
503#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
504#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
505#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
0b0ffc96
TK		 506#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
507
b205914c 508#define PINMUX_MOD_SELS \
0b0ffc96 509\
b205914c
GU		 510MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
511 MOD_SEL2_30 \
0b0ffc96 512 MOD_SEL1_29_28_27 MOD_SEL2_29 \
b205914c
GU		 513MOD_SEL0_28_27 MOD_SEL2_28_27 \
514MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
515 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
0b0ffc96 516MOD_SEL0_23 MOD_SEL1_23_22_21 \
b205914c
GU		 517MOD_SEL0_22 MOD_SEL2_22 \
518MOD_SEL0_21 MOD_SEL2_21 \
519MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
520MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
521MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
522 MOD_SEL2_17 \
523MOD_SEL0_16 MOD_SEL1_16 \
0b0ffc96 524 MOD_SEL1_15_14 \
b205914c
GU		 525MOD_SEL0_14_13 \
526 MOD_SEL1_13 \
0b0ffc96
TK		 527MOD_SEL0_12 MOD_SEL1_12 \
528MOD_SEL0_11 MOD_SEL1_11 \
529MOD_SEL0_10 MOD_SEL1_10 \
b205914c 530MOD_SEL0_9_8 MOD_SEL1_9 \
0b0ffc96
TK		 531MOD_SEL0_7_6 \
532 MOD_SEL1_6 \
b205914c
GU		 533MOD_SEL0_5 MOD_SEL1_5 \
534MOD_SEL0_4_3 MOD_SEL1_4 \
535 MOD_SEL1_3 \
536 MOD_SEL1_2 \
0b0ffc96
TK		 537 MOD_SEL1_1 \
538 MOD_SEL1_0 MOD_SEL2_0
539
ea9c7405
NS		 540/*
541 * These pins are not able to be muxed but have other properties
542 * that can be set, such as drive-strength or pull-up/pull-down enable.
543 */
544#define PINMUX_STATIC \
545 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
546 FM(QSPI0_IO2) FM(QSPI0_IO3) \
547 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
548 FM(QSPI1_IO2) FM(QSPI1_IO3) \
549 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
550 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
551 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
552 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
553 FM(CLKOUT) FM(PRESETOUT) \
554 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
4c2fb44d 555 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
0b0ffc96
TK		 556
557enum {
558 PINMUX_RESERVED = 0,
559
560 PINMUX_DATA_BEGIN,
561 GP_ALL(DATA),
562 PINMUX_DATA_END,
563
564#define F_(x, y)
565#define FM(x) FN_##x,
566 PINMUX_FUNCTION_BEGIN,
567 GP_ALL(FN),
568 PINMUX_GPSR
569 PINMUX_IPSR
570 PINMUX_MOD_SELS
571 PINMUX_FUNCTION_END,
572#undef F_
573#undef FM
574
575#define F_(x, y)
576#define FM(x) x##_MARK,
577 PINMUX_MARK_BEGIN,
578 PINMUX_GPSR
579 PINMUX_IPSR
580 PINMUX_MOD_SELS
ea9c7405 581 PINMUX_STATIC
0b0ffc96
TK		 582 PINMUX_MARK_END,
583#undef F_
584#undef FM
585};
586
587static const u16 pinmux_data[] = {
588 PINMUX_DATA_GP_ALL(),
589
8d4df573
GU		 590 PINMUX_SINGLE(AVS1),
591 PINMUX_SINGLE(AVS2),
592 PINMUX_SINGLE(HDMI0_CEC),
593 PINMUX_SINGLE(HDMI1_CEC),
d07640f5
KM		 594 PINMUX_SINGLE(I2C_SEL_0_1),
595 PINMUX_SINGLE(I2C_SEL_3_1),
596 PINMUX_SINGLE(I2C_SEL_5_1),
8d4df573
GU		 597 PINMUX_SINGLE(MSIOF0_RXD),
598 PINMUX_SINGLE(MSIOF0_SCK),
599 PINMUX_SINGLE(MSIOF0_TXD),
8d4df573
GU		 600 PINMUX_SINGLE(SSI_SCK5),
601 PINMUX_SINGLE(SSI_SDATA5),
602 PINMUX_SINGLE(SSI_WS5),
603
0b0ffc96 604 /* IPSR0 */
e01678e3 605 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
0b0ffc96
TK		 606 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
607
e01678e3 608 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
0b0ffc96
TK		 609 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
610 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
611
e01678e3 612 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
0b0ffc96
TK		 613 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
614 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
615
e01678e3 616 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
0b0ffc96
TK		 617 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
618 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
619
620 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
621 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
622 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
b205914c 623 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
0b0ffc96
TK		 624
625 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
626 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
627 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
628
e01678e3
GU		 629 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
630 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
631 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
0b0ffc96
TK		 632 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
b205914c 635 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
0b0ffc96 636
e01678e3
GU		 637 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
638 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
639 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
0b0ffc96
TK		 640 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
b205914c 643 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
0b0ffc96
TK		 644
645 /* IPSR1 */
e01678e3
GU		 646 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
647 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
648 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
0b0ffc96
TK		 649 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
b205914c 651 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
0b0ffc96 652
e01678e3
GU		 653 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
654 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
655 PINMUX_IPSR_GPSR(IP1_7_4, A25),
656 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
0b0ffc96
TK		 657 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
658 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
b205914c 659 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
0b0ffc96 660
e01678e3
GU		 661 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
662 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
663 PINMUX_IPSR_GPSR(IP1_11_8, A24),
664 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
0b0ffc96
TK		 665 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
666 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
b205914c 667 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
0b0ffc96 668
e01678e3
GU		 669 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
670 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
671 PINMUX_IPSR_GPSR(IP1_15_12, A23),
672 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
0b0ffc96
TK		 673 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
674 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
b205914c
GU		 675 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
676 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
0b0ffc96 677
e01678e3
GU		 678 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
679 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
680 PINMUX_IPSR_GPSR(IP1_19_16, A22),
0b0ffc96
TK		 681 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
e01678e3 685 PINMUX_IPSR_GPSR(IP1_23_20, A21),
0b0ffc96
TK		 686 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
687 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
688 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
689
690 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
e01678e3 691 PINMUX_IPSR_GPSR(IP1_27_24, A20),
0b0ffc96
TK		 692 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
693 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
694
e01678e3
GU		 695 PINMUX_IPSR_GPSR(IP1_31_28, A0),
696 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
0b0ffc96 697 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
e01678e3
GU		 698 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
699 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
0b0ffc96
TK		 700 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
701
702 /* IPSR2 */
e01678e3
GU		 703 PINMUX_IPSR_GPSR(IP2_3_0, A1),
704 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
0b0ffc96 705 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
e01678e3
GU		 706 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
707 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
0b0ffc96
TK		 708 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
709
e01678e3
GU		 710 PINMUX_IPSR_GPSR(IP2_7_4, A2),
711 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
0b0ffc96 712 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
e01678e3
GU		 713 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
714 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
0b0ffc96
TK		 715 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
716
e01678e3
GU		 717 PINMUX_IPSR_GPSR(IP2_11_8, A3),
718 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
0b0ffc96 719 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
e01678e3
GU		 720 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
721 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
0b0ffc96
TK		 722 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
723
e01678e3
GU		 724 PINMUX_IPSR_GPSR(IP2_15_12, A4),
725 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
0b0ffc96 726 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
e01678e3
GU		 727 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
728 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
729 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
0b0ffc96 730
e01678e3
GU		 731 PINMUX_IPSR_GPSR(IP2_19_16, A5),
732 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
0b0ffc96
TK		 733 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
734 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
e01678e3
GU		 735 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
736 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
737 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
0b0ffc96 738
e01678e3
GU		 739 PINMUX_IPSR_GPSR(IP2_23_20, A6),
740 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
0b0ffc96
TK		 741 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
742 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
e01678e3
GU		 743 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
744 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
745 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
0b0ffc96 746
e01678e3
GU		 747 PINMUX_IPSR_GPSR(IP2_27_24, A7),
748 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
0b0ffc96
TK		 749 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
750 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
e01678e3
GU		 751 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
752 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
753 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
0b0ffc96 754
e01678e3 755 PINMUX_IPSR_GPSR(IP2_31_28, A8),
0b0ffc96
TK		 756 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
757 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
758 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
759 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
760 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
762
763 /* IPSR3 */
e01678e3 764 PINMUX_IPSR_GPSR(IP3_3_0, A9),
0b0ffc96
TK		 765 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
766 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
e01678e3 767 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
0b0ffc96 768
e01678e3 769 PINMUX_IPSR_GPSR(IP3_7_4, A10),
0b0ffc96
TK		 770 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
771 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
e01678e3 772 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
0b0ffc96 773
e01678e3 774 PINMUX_IPSR_GPSR(IP3_11_8, A11),
0b0ffc96
TK		 775 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
776 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
777 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
e01678e3
GU		 778 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
779 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
0b0ffc96
TK		 780 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
782 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
783
e01678e3
GU		 784 PINMUX_IPSR_GPSR(IP3_15_12, A12),
785 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
0b0ffc96
TK		 786 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
e01678e3
GU		 788 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
789 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
0b0ffc96 790
e01678e3
GU		 791 PINMUX_IPSR_GPSR(IP3_19_16, A13),
792 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
0b0ffc96
TK		 793 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
e01678e3
GU		 795 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
796 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
0b0ffc96 797
e01678e3
GU		 798 PINMUX_IPSR_GPSR(IP3_23_20, A14),
799 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
0b0ffc96 800 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
e01678e3
GU		 801 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
802 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
803 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
0b0ffc96 804
e01678e3
GU		 805 PINMUX_IPSR_GPSR(IP3_27_24, A15),
806 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
0b0ffc96 807 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
e01678e3
GU		 808 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
809 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
810 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
0b0ffc96 811
e01678e3
GU		 812 PINMUX_IPSR_GPSR(IP3_31_28, A16),
813 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
814 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
815 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
0b0ffc96
TK		 816
817 /* IPSR4 */
e01678e3
GU		 818 PINMUX_IPSR_GPSR(IP4_3_0, A17),
819 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
820 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
821 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
822
823 PINMUX_IPSR_GPSR(IP4_7_4, A18),
824 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
825 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
826 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
827
828 PINMUX_IPSR_GPSR(IP4_11_8, A19),
829 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
830 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
831 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
832
833 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
834 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
835
836 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
837 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
0b0ffc96
TK		 838 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
839
e01678e3
GU		 840 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
841 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
0b0ffc96 842 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
e01678e3
GU		 843 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
844 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
845 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
846 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
0b0ffc96
TK		 847 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
848
e01678e3 849 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
0b0ffc96
TK		 850 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
855
e01678e3 856 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
0b0ffc96
TK		 857 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
858 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
859 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
860 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
861 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
862
863 /* IPSR5 */
e01678e3 864 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
0b0ffc96 865 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
e01678e3
GU		 866 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
867 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
0b0ffc96 868 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
e01678e3 869 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
0b0ffc96
TK		 870 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
871
e01678e3 872 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
0b0ffc96 873 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
e01678e3
GU		 874 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
875 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
0b0ffc96 876 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
e01678e3
GU		 877 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
878 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
0b0ffc96
TK		 879 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
880
881 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
e01678e3
GU		 882 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
883 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
884 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
0b0ffc96 885
e01678e3 886 PINMUX_IPSR_GPSR(IP5_15_12, D0),
0b0ffc96
TK		 887 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
888 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
e01678e3
GU		 889 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
890 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
0b0ffc96 891
e01678e3 892 PINMUX_IPSR_GPSR(IP5_19_16, D1),
0b0ffc96
TK		 893 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
894 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
e01678e3
GU		 895 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
896 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
0b0ffc96 897
e01678e3 898 PINMUX_IPSR_GPSR(IP5_23_20, D2),
0b0ffc96 899 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
e01678e3
GU		 900 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
901 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
0b0ffc96 902
e01678e3 903 PINMUX_IPSR_GPSR(IP5_27_24, D3),
0b0ffc96 904 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
e01678e3
GU		 905 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
906 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
0b0ffc96 907
e01678e3 908 PINMUX_IPSR_GPSR(IP5_31_28, D4),
0b0ffc96 909 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
e01678e3
GU		 910 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
911 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
0b0ffc96
TK		 912
913 /* IPSR6 */
e01678e3 914 PINMUX_IPSR_GPSR(IP6_3_0, D5),
0b0ffc96 915 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
e01678e3
GU		 916 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
917 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
0b0ffc96 918
b205914c
GU		 919 PINMUX_IPSR_GPSR(IP6_7_4, D6),
920 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
921 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
922 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
c33a7fe3 923
b205914c
GU		 924 PINMUX_IPSR_GPSR(IP6_11_8, D7),
925 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
926 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
927 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
819fd4bf 928
b205914c
GU		 929 PINMUX_IPSR_GPSR(IP6_15_12, D8),
930 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
931 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
933 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
934 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
a4d9791f 935
b205914c
GU		 936 PINMUX_IPSR_GPSR(IP6_19_16, D9),
937 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
938 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
939 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
940 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
a4d9791f 941
b205914c
GU		 942 PINMUX_IPSR_GPSR(IP6_23_20, D10),
943 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
944 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
945 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
946 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
947 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
948 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
a4d9791f 949
b205914c
GU		 950 PINMUX_IPSR_GPSR(IP6_27_24, D11),
951 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
952 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
953 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
954 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
955 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
956 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
4412bb5d 957
b205914c
GU		 958 PINMUX_IPSR_GPSR(IP6_31_28, D12),
959 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
960 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
961 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
962 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
963 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
4412bb5d 964
b205914c
GU		 965 /* IPSR7 */
966 PINMUX_IPSR_GPSR(IP7_3_0, D13),
967 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
968 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
969 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
970 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
2d775831 972
b205914c
GU		 973 PINMUX_IPSR_GPSR(IP7_7_4, D14),
974 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
975 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
976 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
977 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
978 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
979 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
2d775831 980
b205914c
GU		 981 PINMUX_IPSR_GPSR(IP7_11_8, D15),
982 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
983 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
984 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
985 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
986 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
987 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
2d775831 988
b205914c 989 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
2d775831 990
b205914c
GU		 991 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
992 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
993 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
7955dac1 994
b205914c
GU		 995 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
996 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
a56069c4 998
b205914c
GU		 999 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1000 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1002 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
a56069c4 1003
b205914c
GU		 1004 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1005 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1006 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1007 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
a56069c4 1008
b205914c
GU		 1009 /* IPSR8 */
1010 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1011 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1012 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1013 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
a56069c4 1014
b205914c
GU		 1015 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1016 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1017 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1018 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
a56069c4 1019
b205914c
GU		 1020 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1021 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1022 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
2544ef72 1023
b205914c
GU		 1024 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1025 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1027 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1028 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
2544ef72 1029
b205914c
GU		 1030 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1031 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1032 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1033 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1034 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1035 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
2544ef72 1036
b205914c
GU		 1037 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1038 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1039 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1040 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1041 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1042 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
bb46f6f3 1043
b205914c
GU		 1044 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1045 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1046 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1047 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1048 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1049 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
e7419b81 1050
b205914c
GU		 1051 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1052 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1053 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1054 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1055 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1056 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
e7419b81 1057
b205914c
GU		 1058 /* IPSR9 */
1059 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1060 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
e7419b81 1061
b205914c
GU		 1062 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1063 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
e7419b81 1064
b205914c
GU		 1065 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1066 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
4ca88cf6 1067
b205914c
GU		 1068 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1069 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
4ca88cf6 1070
b205914c
GU		 1071 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1072 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
4ca88cf6 1073
b205914c
GU		 1074 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1075 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
4ca88cf6 1076
b205914c
GU		 1077 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1078 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1079 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
4ca88cf6 1080
b205914c
GU		 1081 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1082 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
4ca88cf6 1083
b205914c
GU		 1084 /* IPSR10 */
1085 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1086 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
4ca88cf6 1087
b205914c
GU		 1088 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1089 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
b332da51 1090
b205914c
GU		 1091 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1092 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
b332da51 1093
b205914c
GU		 1094 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1095 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
34dc4e16 1096
b205914c
GU		 1097 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1098 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
ff8459a5 1099
b205914c
GU		 1100 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1101 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1102 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
ff8459a5 1103
b205914c
GU		 1104 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1105 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1106 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
ff8459a5 1107
b205914c
GU		 1108 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1109 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1110 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
ff8459a5 1111
b205914c
GU		 1112 /* IPSR11 */
1113 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1114 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1115 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1116
1117 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1118 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1119
1120 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1121 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1122 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1123
1124 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1125 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1126
1127 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1128 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1131 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1132
1133 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1134 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1135 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1136 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1137 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1138 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1140 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1141 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1142 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1143
1144 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1145 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1146 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1147 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1148 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
ff8459a5 1149
b205914c
GU		 1150 /* IPSR12 */
1151 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1152 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1153 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1154 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1155 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1156
1157 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1158 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1161 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1162 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1163 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1164 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1165
1166 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1167 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1168 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1169 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1170 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1171 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1172 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1173 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1174
1175 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1176 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1177 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1178 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1179 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1180
1181 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1182 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1183 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1184 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1185 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1186
1187 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1188 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1189 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1190 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1191 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1192 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1193 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1194
1195 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1196 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1197 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1198 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1199 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1200 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1201 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1202
1203 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1204 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1205 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1206 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1207 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1209 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
0b0ffc96 1210
b205914c
GU		 1211 /* IPSR13 */
1212 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1213 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1214 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1215 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1216 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1217 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1218
1219 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1220 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1221 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1222 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1223 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1224 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1225
1226 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1227 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1228 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1229 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1230 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1231 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1233 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1234
1235 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1236 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1237 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1238 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1239 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1240 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1241
1242 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1243 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1244 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1245 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1246 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1247 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1248
1249 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1252 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1253 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1254 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1255 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1256 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1257
1258 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1259 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1260 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1261 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1262 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1263 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1264 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1265
1266 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1267 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1268 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1269 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
f27200f9 1270
b205914c
GU		 1271 /* IPSR14 */
1272 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1273 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1275 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1276 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1277 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1278 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1279 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1280
1281 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1282 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1283 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1284 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1285 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1286 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1287 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1288 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1291 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1292 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1293
1294 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1295 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1296 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1297 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1298
1299 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1300 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1301 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1302
1303 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1304 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1305
1306 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1307 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1308
1309 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1310 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
20cacae1 1311
b205914c
GU		 1312 /* IPSR15 */
1313 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1314
1315 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1316 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1317
68e63892 1318 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
b205914c
GU		 1319 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1320 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1321
68e63892 1322 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
b205914c
GU		 1323 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1324 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1325 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1326
1327 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1328 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1329 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1330 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1331 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1332 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1334
1335 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1336 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1337 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1338 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1339 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1340 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1342
1343 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1344 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1345 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1346 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1347 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1348 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1350
1351 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1352 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1353 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1354 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1355 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1356 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
20cacae1 1358
b205914c
GU		 1359 /* IPSR16 */
1360 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1361 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1362 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1363
1364 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1365 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1366 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1367
1368 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1369 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1370 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1371
1372 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1373 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1374 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1375 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1376 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1379
1380 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1381 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1382 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1383 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1384 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1387
1388 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1389 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1396
1397 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1398 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1399 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1400 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1401 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1404
1405 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1406 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1407 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1408 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1409 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1410 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1411 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1412 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
20cacae1 1413
b205914c
GU		 1414 /* IPSR17 */
1415 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1416 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1417
1418 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1419 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1420 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1421 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1422 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1423
1424 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1425 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1426 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1427 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1429 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1431
1432 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1433 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1434 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1435 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1437 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1438
1439 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1440 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1442 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1443 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1445 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1447 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1448
1449 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1450 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1451 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1452 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1453 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1455 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1458
1459 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1460 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1461 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1462 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1463 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1465 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1466 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1467 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1468 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1469 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1470
1471 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1472 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1473 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1474 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1475 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1477 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1478 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1479 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1480
1481 /* IPSR18 */
1482 PINMUX_IPSR_GPSR(IP18_3_0, USB3_PWEN),
1483 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1484 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1485 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1486 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1488 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1489 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1491
1492 PINMUX_IPSR_GPSR(IP18_7_4, USB3_OVC),
1493 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1494 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1495 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1496 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1497 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1498 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1499 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1500 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
20cacae1 1501
b205914c
GU		 1502/*
1503 * Static pins can not be muxed between different functions but
1504 * still needs a mark entry in the pinmux list. Add each static
1505 * pin to the list without an associated function. The sh-pfc
1506 * core will do the right thing and skip trying to mux then pin
1507 * while still applying configuration to it
1508 */
1509#define FM(x) PINMUX_DATA(x##_MARK, 0),
1510 PINMUX_STATIC
1511#undef FM
9b132ba3
KM		 1512};
1513
b205914c
GU		 1514/*
1515 * R8A7795 has 8 banks with 32 PGIOS in each => 256 GPIOs.
1516 * Physical layout rows: A - AW, cols: 1 - 39.
1517 */
1518#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1519#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1520#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1521
1522static const struct sh_pfc_pin pinmux_pins[] = {
1523 PINMUX_GPIO_GP_ALL(),
76250a6c 1524
b205914c
GU		 1525 /*
1526 * Pins not associated with a GPIO port.
1527 *
1528 * The pin positions are different between different r8a7795
1529 * packages, all that is needed for the pfc driver is a unique
1530 * number for each pin. To this end use the pin layout from
1531 * R-Car H3SiP to calculate a unique number for each pin.
1532 */
1533 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1540 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('F', 1, CLKOUT, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
76250a6c
TK		 1577};
1578
30c078de
GU		 1579/* - EtherAVB --------------------------------------------------------------- */
1580static const unsigned int avb_link_pins[] = {
1581 /* AVB_LINK */
1582 RCAR_GP_PIN(2, 12),
1583};
1584static const unsigned int avb_link_mux[] = {
1585 AVB_LINK_MARK,
1586};
1587static const unsigned int avb_magic_pins[] = {
1588 /* AVB_MAGIC_ */
1589 RCAR_GP_PIN(2, 10),
1590};
1591static const unsigned int avb_magic_mux[] = {
1592 AVB_MAGIC_MARK,
1593};
1594static const unsigned int avb_phy_int_pins[] = {
1595 /* AVB_PHY_INT */
1596 RCAR_GP_PIN(2, 11),
1597};
1598static const unsigned int avb_phy_int_mux[] = {
1599 AVB_PHY_INT_MARK,
1600};
1601static const unsigned int avb_mdc_pins[] = {
1602 /* AVB_MDC, AVB_MDIO */
1603 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1604};
1605static const unsigned int avb_mdc_mux[] = {
1606 AVB_MDC_MARK, AVB_MDIO_MARK,
1607};
1608static const unsigned int avb_mii_pins[] = {
1609 /*
1610 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1611 * AVB_TD1, AVB_TD2, AVB_TD3,
1612 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1613 * AVB_RD1, AVB_RD2, AVB_RD3,
1614 * AVB_TXCREFCLK
1615 */
1616 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1617 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1618 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1619 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1620 PIN_NUMBER('A', 12),
1621
1622};
1623static const unsigned int avb_mii_mux[] = {
1624 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1625 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1626 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1627 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1628 AVB_TXCREFCLK_MARK,
1629};
1630static const unsigned int avb_avtp_pps_pins[] = {
1631 /* AVB_AVTP_PPS */
1632 RCAR_GP_PIN(2, 6),
1633};
1634static const unsigned int avb_avtp_pps_mux[] = {
1635 AVB_AVTP_PPS_MARK,
1636};
1637static const unsigned int avb_avtp_match_a_pins[] = {
1638 /* AVB_AVTP_MATCH_A */
1639 RCAR_GP_PIN(2, 13),
1640};
1641static const unsigned int avb_avtp_match_a_mux[] = {
1642 AVB_AVTP_MATCH_A_MARK,
1643};
1644static const unsigned int avb_avtp_capture_a_pins[] = {
1645 /* AVB_AVTP_CAPTURE_A */
1646 RCAR_GP_PIN(2, 14),
1647};
1648static const unsigned int avb_avtp_capture_a_mux[] = {
1649 AVB_AVTP_CAPTURE_A_MARK,
1650};
1651static const unsigned int avb_avtp_match_b_pins[] = {
1652 /* AVB_AVTP_MATCH_B */
1653 RCAR_GP_PIN(1, 8),
1654};
1655static const unsigned int avb_avtp_match_b_mux[] = {
1656 AVB_AVTP_MATCH_B_MARK,
1657};
1658static const unsigned int avb_avtp_capture_b_pins[] = {
1659 /* AVB_AVTP_CAPTURE_B */
1660 RCAR_GP_PIN(1, 11),
1661};
1662static const unsigned int avb_avtp_capture_b_mux[] = {
1663 AVB_AVTP_CAPTURE_B_MARK,
1664};
1665
a20a6585
LP		 1666/* - DU --------------------------------------------------------------------- */
1667static const unsigned int du_rgb666_pins[] = {
1668 /* R[7:2], G[7:2], B[7:2] */
1669 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1670 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1671 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1672 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1673 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1674 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1675};
1676static const unsigned int du_rgb666_mux[] = {
1677 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1678 DU_DR3_MARK, DU_DR2_MARK,
1679 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1680 DU_DG3_MARK, DU_DG2_MARK,
1681 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1682 DU_DB3_MARK, DU_DB2_MARK,
1683};
1684static const unsigned int du_rgb888_pins[] = {
1685 /* R[7:0], G[7:0], B[7:0] */
1686 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1687 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1688 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1689 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1690 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1691 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1692 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1693 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1694 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1695};
1696static const unsigned int du_rgb888_mux[] = {
1697 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1698 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1699 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1700 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1701 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1702 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1703};
1704static const unsigned int du_clk_out_0_pins[] = {
1705 /* CLKOUT */
1706 RCAR_GP_PIN(1, 27),
1707};
1708static const unsigned int du_clk_out_0_mux[] = {
1709 DU_DOTCLKOUT0_MARK
1710};
1711static const unsigned int du_clk_out_1_pins[] = {
1712 /* CLKOUT */
1713 RCAR_GP_PIN(2, 3),
1714};
1715static const unsigned int du_clk_out_1_mux[] = {
1716 DU_DOTCLKOUT1_MARK
1717};
1718static const unsigned int du_sync_pins[] = {
1719 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1720 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1721};
1722static const unsigned int du_sync_mux[] = {
1723 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1724};
1725static const unsigned int du_oddf_pins[] = {
1726 /* EXDISP/EXODDF/EXCDE */
1727 RCAR_GP_PIN(2, 2),
1728};
1729static const unsigned int du_oddf_mux[] = {
1730 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1731};
1732static const unsigned int du_cde_pins[] = {
1733 /* CDE */
1734 RCAR_GP_PIN(2, 0),
1735};
1736static const unsigned int du_cde_mux[] = {
1737 DU_CDE_MARK,
1738};
1739static const unsigned int du_disp_pins[] = {
1740 /* DISP */
1741 RCAR_GP_PIN(2, 1),
1742};
1743static const unsigned int du_disp_mux[] = {
1744 DU_DISP_MARK,
1745};
1746
c03a133b
LP		 1747/* - PWM0 --------------------------------------------------------------------*/
1748static const unsigned int pwm0_pins[] = {
1749 /* PWM */
1750 RCAR_GP_PIN(2, 6),
1751};
1752static const unsigned int pwm0_mux[] = {
1753 PWM0_MARK,
1754};
1755/* - PWM1 --------------------------------------------------------------------*/
1756static const unsigned int pwm1_a_pins[] = {
1757 /* PWM */
1758 RCAR_GP_PIN(2, 7),
1759};
1760static const unsigned int pwm1_a_mux[] = {
1761 PWM1_A_MARK,
1762};
1763static const unsigned int pwm1_b_pins[] = {
1764 /* PWM */
1765 RCAR_GP_PIN(1, 8),
1766};
1767static const unsigned int pwm1_b_mux[] = {
1768 PWM1_B_MARK,
1769};
1770/* - PWM2 --------------------------------------------------------------------*/
1771static const unsigned int pwm2_a_pins[] = {
1772 /* PWM */
1773 RCAR_GP_PIN(2, 8),
1774};
1775static const unsigned int pwm2_a_mux[] = {
1776 PWM2_A_MARK,
1777};
1778static const unsigned int pwm2_b_pins[] = {
1779 /* PWM */
1780 RCAR_GP_PIN(1, 11),
1781};
1782static const unsigned int pwm2_b_mux[] = {
1783 PWM2_B_MARK,
1784};
1785/* - PWM3 --------------------------------------------------------------------*/
1786static const unsigned int pwm3_a_pins[] = {
1787 /* PWM */
1788 RCAR_GP_PIN(1, 0),
1789};
1790static const unsigned int pwm3_a_mux[] = {
1791 PWM3_A_MARK,
1792};
1793static const unsigned int pwm3_b_pins[] = {
1794 /* PWM */
1795 RCAR_GP_PIN(2, 2),
1796};
1797static const unsigned int pwm3_b_mux[] = {
1798 PWM3_B_MARK,
1799};
1800/* - PWM4 --------------------------------------------------------------------*/
1801static const unsigned int pwm4_a_pins[] = {
1802 /* PWM */
1803 RCAR_GP_PIN(1, 1),
1804};
1805static const unsigned int pwm4_a_mux[] = {
1806 PWM4_A_MARK,
1807};
1808static const unsigned int pwm4_b_pins[] = {
1809 /* PWM */
1810 RCAR_GP_PIN(2, 3),
1811};
1812static const unsigned int pwm4_b_mux[] = {
1813 PWM4_B_MARK,
1814};
1815/* - PWM5 --------------------------------------------------------------------*/
1816static const unsigned int pwm5_a_pins[] = {
1817 /* PWM */
1818 RCAR_GP_PIN(1, 2),
1819};
1820static const unsigned int pwm5_a_mux[] = {
1821 PWM5_A_MARK,
1822};
1823static const unsigned int pwm5_b_pins[] = {
1824 /* PWM */
1825 RCAR_GP_PIN(2, 4),
1826};
1827static const unsigned int pwm5_b_mux[] = {
1828 PWM5_B_MARK,
1829};
1830/* - PWM6 --------------------------------------------------------------------*/
1831static const unsigned int pwm6_a_pins[] = {
1832 /* PWM */
1833 RCAR_GP_PIN(1, 3),
1834};
1835static const unsigned int pwm6_a_mux[] = {
1836 PWM6_A_MARK,
1837};
1838static const unsigned int pwm6_b_pins[] = {
1839 /* PWM */
1840 RCAR_GP_PIN(2, 5),
1841};
1842static const unsigned int pwm6_b_mux[] = {
1843 PWM6_B_MARK,
1844};
1845
e7ad4d3c
GU		 1846/* - SCIF0 ------------------------------------------------------------------ */
1847static const unsigned int scif0_data_pins[] = {
1848 /* RX, TX */
1849 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1850};
1851static const unsigned int scif0_data_mux[] = {
1852 RX0_MARK, TX0_MARK,
1853};
1854static const unsigned int scif0_clk_pins[] = {
1855 /* SCK */
1856 RCAR_GP_PIN(5, 0),
1857};
1858static const unsigned int scif0_clk_mux[] = {
1859 SCK0_MARK,
1860};
1861static const unsigned int scif0_ctrl_pins[] = {
1862 /* RTS, CTS */
1863 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1864};
1865static const unsigned int scif0_ctrl_mux[] = {
1866 RTS0_N_TANS_MARK, CTS0_N_MARK,
1867};
1868/* - SCIF1 ------------------------------------------------------------------ */
1869static const unsigned int scif1_data_a_pins[] = {
1870 /* RX, TX */
1871 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1872};
1873static const unsigned int scif1_data_a_mux[] = {
1874 RX1_A_MARK, TX1_A_MARK,
1875};
1876static const unsigned int scif1_clk_pins[] = {
1877 /* SCK */
1878 RCAR_GP_PIN(6, 21),
1879};
1880static const unsigned int scif1_clk_mux[] = {
1881 SCK1_MARK,
1882};
1883static const unsigned int scif1_ctrl_pins[] = {
1884 /* RTS, CTS */
1885 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1886};
1887static const unsigned int scif1_ctrl_mux[] = {
1888 RTS1_N_TANS_MARK, CTS1_N_MARK,
1889};
1890
1891static const unsigned int scif1_data_b_pins[] = {
1892 /* RX, TX */
1893 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
1894};
1895static const unsigned int scif1_data_b_mux[] = {
1896 RX1_B_MARK, TX1_B_MARK,
1897};
1898/* - SCIF2 ------------------------------------------------------------------ */
1899static const unsigned int scif2_data_a_pins[] = {
1900 /* RX, TX */
1901 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1902};
1903static const unsigned int scif2_data_a_mux[] = {
1904 RX2_A_MARK, TX2_A_MARK,
1905};
1906static const unsigned int scif2_clk_pins[] = {
1907 /* SCK */
1908 RCAR_GP_PIN(5, 9),
1909};
1910static const unsigned int scif2_clk_mux[] = {
1911 SCK2_MARK,
1912};
1913static const unsigned int scif2_data_b_pins[] = {
1914 /* RX, TX */
1915 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1916};
1917static const unsigned int scif2_data_b_mux[] = {
1918 RX2_B_MARK, TX2_B_MARK,
1919};
1920/* - SCIF3 ------------------------------------------------------------------ */
1921static const unsigned int scif3_data_a_pins[] = {
1922 /* RX, TX */
1923 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1924};
1925static const unsigned int scif3_data_a_mux[] = {
1926 RX3_A_MARK, TX3_A_MARK,
1927};
1928static const unsigned int scif3_clk_pins[] = {
1929 /* SCK */
1930 RCAR_GP_PIN(1, 22),
1931};
1932static const unsigned int scif3_clk_mux[] = {
1933 SCK3_MARK,
1934};
1935static const unsigned int scif3_ctrl_pins[] = {
1936 /* RTS, CTS */
1937 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1938};
1939static const unsigned int scif3_ctrl_mux[] = {
1940 RTS3_N_TANS_MARK, CTS3_N_MARK,
1941};
1942static const unsigned int scif3_data_b_pins[] = {
1943 /* RX, TX */
1944 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1945};
1946static const unsigned int scif3_data_b_mux[] = {
1947 RX3_B_MARK, TX3_B_MARK,
1948};
1949/* - SCIF4 ------------------------------------------------------------------ */
1950static const unsigned int scif4_data_a_pins[] = {
1951 /* RX, TX */
1952 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1953};
1954static const unsigned int scif4_data_a_mux[] = {
1955 RX4_A_MARK, TX4_A_MARK,
1956};
1957static const unsigned int scif4_clk_a_pins[] = {
1958 /* SCK */
1959 RCAR_GP_PIN(2, 10),
1960};
1961static const unsigned int scif4_clk_a_mux[] = {
1962 SCK4_A_MARK,
1963};
1964static const unsigned int scif4_ctrl_a_pins[] = {
1965 /* RTS, CTS */
1966 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
1967};
1968static const unsigned int scif4_ctrl_a_mux[] = {
1969 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
1970};
1971static const unsigned int scif4_data_b_pins[] = {
1972 /* RX, TX */
1973 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
1974};
1975static const unsigned int scif4_data_b_mux[] = {
1976 RX4_B_MARK, TX4_B_MARK,
1977};
1978static const unsigned int scif4_clk_b_pins[] = {
1979 /* SCK */
1980 RCAR_GP_PIN(1, 5),
1981};
1982static const unsigned int scif4_clk_b_mux[] = {
1983 SCK4_B_MARK,
1984};
1985static const unsigned int scif4_ctrl_b_pins[] = {
1986 /* RTS, CTS */
1987 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
1988};
1989static const unsigned int scif4_ctrl_b_mux[] = {
1990 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
1991};
1992static const unsigned int scif4_data_c_pins[] = {
1993 /* RX, TX */
1994 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1995};
1996static const unsigned int scif4_data_c_mux[] = {
1997 RX4_C_MARK, TX4_C_MARK,
1998};
1999static const unsigned int scif4_clk_c_pins[] = {
2000 /* SCK */
2001 RCAR_GP_PIN(0, 8),
2002};
2003static const unsigned int scif4_clk_c_mux[] = {
2004 SCK4_C_MARK,
2005};
2006static const unsigned int scif4_ctrl_c_pins[] = {
2007 /* RTS, CTS */
2008 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2009};
2010static const unsigned int scif4_ctrl_c_mux[] = {
2011 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2012};
2013/* - SCIF5 ------------------------------------------------------------------ */
2014static const unsigned int scif5_data_a_pins[] = {
2015 /* RX, TX */
2016 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2017};
2018static const unsigned int scif5_data_a_mux[] = {
2019 RX5_A_MARK, TX5_A_MARK,
2020};
2021static const unsigned int scif5_clk_a_pins[] = {
2022 /* SCK */
2023 RCAR_GP_PIN(6, 21),
2024};
2025static const unsigned int scif5_clk_a_mux[] = {
2026 SCK5_A_MARK,
2027};
2028static const unsigned int scif5_data_b_pins[] = {
2029 /* RX, TX */
2030 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
2031};
2032static const unsigned int scif5_data_b_mux[] = {
2033 RX5_B_MARK, TX5_B_MARK,
2034};
2035static const unsigned int scif5_clk_b_pins[] = {
2036 /* SCK */
2037 RCAR_GP_PIN(5, 0),
2038};
2039static const unsigned int scif5_clk_b_mux[] = {
2040 SCK5_B_MARK,
2041};
2042
d14a39ed
GU		 2043/* - SCIF Clock ------------------------------------------------------------- */
2044static const unsigned int scif_clk_a_pins[] = {
2045 /* SCIF_CLK */
2046 RCAR_GP_PIN(6, 23),
2047};
2048static const unsigned int scif_clk_a_mux[] = {
2049 SCIF_CLK_A_MARK,
2050};
2051static const unsigned int scif_clk_b_pins[] = {
2052 /* SCIF_CLK */
2053 RCAR_GP_PIN(5, 9),
2054};
2055static const unsigned int scif_clk_b_mux[] = {
2056 SCIF_CLK_B_MARK,
2057};
2058
b205914c 2059static const struct sh_pfc_pin_group pinmux_groups[] = {
30c078de
GU		 2060 SH_PFC_PIN_GROUP(avb_link),
2061 SH_PFC_PIN_GROUP(avb_magic),
2062 SH_PFC_PIN_GROUP(avb_phy_int),
2063 SH_PFC_PIN_GROUP(avb_mdc),
2064 SH_PFC_PIN_GROUP(avb_mii),
2065 SH_PFC_PIN_GROUP(avb_avtp_pps),
2066 SH_PFC_PIN_GROUP(avb_avtp_match_a),
2067 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
2068 SH_PFC_PIN_GROUP(avb_avtp_match_b),
2069 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
a20a6585
LP		 2070 SH_PFC_PIN_GROUP(du_rgb666),
2071 SH_PFC_PIN_GROUP(du_rgb888),
2072 SH_PFC_PIN_GROUP(du_clk_out_0),
2073 SH_PFC_PIN_GROUP(du_clk_out_1),
2074 SH_PFC_PIN_GROUP(du_sync),
2075 SH_PFC_PIN_GROUP(du_oddf),
2076 SH_PFC_PIN_GROUP(du_cde),
2077 SH_PFC_PIN_GROUP(du_disp),
c03a133b
LP		 2078 SH_PFC_PIN_GROUP(pwm0),
2079 SH_PFC_PIN_GROUP(pwm1_a),
2080 SH_PFC_PIN_GROUP(pwm1_b),
2081 SH_PFC_PIN_GROUP(pwm2_a),
2082 SH_PFC_PIN_GROUP(pwm2_b),
2083 SH_PFC_PIN_GROUP(pwm3_a),
2084 SH_PFC_PIN_GROUP(pwm3_b),
2085 SH_PFC_PIN_GROUP(pwm4_a),
2086 SH_PFC_PIN_GROUP(pwm4_b),
2087 SH_PFC_PIN_GROUP(pwm5_a),
2088 SH_PFC_PIN_GROUP(pwm5_b),
2089 SH_PFC_PIN_GROUP(pwm6_a),
2090 SH_PFC_PIN_GROUP(pwm6_b),
e7ad4d3c
GU		 2091 SH_PFC_PIN_GROUP(scif0_data),
2092 SH_PFC_PIN_GROUP(scif0_clk),
2093 SH_PFC_PIN_GROUP(scif0_ctrl),
2094 SH_PFC_PIN_GROUP(scif1_data_a),
2095 SH_PFC_PIN_GROUP(scif1_clk),
2096 SH_PFC_PIN_GROUP(scif1_ctrl),
2097 SH_PFC_PIN_GROUP(scif1_data_b),
2098 SH_PFC_PIN_GROUP(scif2_data_a),
2099 SH_PFC_PIN_GROUP(scif2_clk),
2100 SH_PFC_PIN_GROUP(scif2_data_b),
2101 SH_PFC_PIN_GROUP(scif3_data_a),
2102 SH_PFC_PIN_GROUP(scif3_clk),
2103 SH_PFC_PIN_GROUP(scif3_ctrl),
2104 SH_PFC_PIN_GROUP(scif3_data_b),
2105 SH_PFC_PIN_GROUP(scif4_data_a),
2106 SH_PFC_PIN_GROUP(scif4_clk_a),
2107 SH_PFC_PIN_GROUP(scif4_ctrl_a),
2108 SH_PFC_PIN_GROUP(scif4_data_b),
2109 SH_PFC_PIN_GROUP(scif4_clk_b),
2110 SH_PFC_PIN_GROUP(scif4_ctrl_b),
2111 SH_PFC_PIN_GROUP(scif4_data_c),
2112 SH_PFC_PIN_GROUP(scif4_clk_c),
2113 SH_PFC_PIN_GROUP(scif4_ctrl_c),
2114 SH_PFC_PIN_GROUP(scif5_data_a),
2115 SH_PFC_PIN_GROUP(scif5_clk_a),
2116 SH_PFC_PIN_GROUP(scif5_data_b),
2117 SH_PFC_PIN_GROUP(scif5_clk_b),
d14a39ed
GU		 2118 SH_PFC_PIN_GROUP(scif_clk_a),
2119 SH_PFC_PIN_GROUP(scif_clk_b),
e7ad4d3c
GU		 2120};
2121
30c078de
GU		 2122static const char * const avb_groups[] = {
2123 "avb_link",
2124 "avb_magic",
2125 "avb_phy_int",
2126 "avb_mdc",
2127 "avb_mii",
2128 "avb_avtp_pps",
2129 "avb_avtp_match_a",
2130 "avb_avtp_capture_a",
2131 "avb_avtp_match_b",
2132 "avb_avtp_capture_b",
2133};
2134
a20a6585
LP		 2135static const char * const du_groups[] = {
2136 "du_rgb666",
2137 "du_rgb888",
2138 "du_clk_out_0",
2139 "du_clk_out_1",
2140 "du_sync",
2141 "du_oddf",
2142 "du_cde",
2143 "du_disp",
2144};
2145
c03a133b
LP		 2146static const char * const pwm0_groups[] = {
2147 "pwm0",
2148};
2149
2150static const char * const pwm1_groups[] = {
2151 "pwm1_a",
2152 "pwm1_b",
2153};
2154
2155static const char * const pwm2_groups[] = {
2156 "pwm2_a",
2157 "pwm2_b",
2158};
2159
2160static const char * const pwm3_groups[] = {
2161 "pwm3_a",
2162 "pwm3_b",
2163};
2164
2165static const char * const pwm4_groups[] = {
2166 "pwm4_a",
2167 "pwm4_b",
2168};
2169
2170static const char * const pwm5_groups[] = {
2171 "pwm5_a",
2172 "pwm5_b",
2173};
2174
2175static const char * const pwm6_groups[] = {
2176 "pwm6_a",
2177 "pwm6_b",
2178};
2179
e7ad4d3c
GU		 2180static const char * const scif0_groups[] = {
2181 "scif0_data",
2182 "scif0_clk",
2183 "scif0_ctrl",
2184};
2185
2186static const char * const scif1_groups[] = {
2187 "scif1_data_a",
2188 "scif1_clk",
2189 "scif1_ctrl",
2190 "scif1_data_b",
2191};
2192
2193static const char * const scif2_groups[] = {
2194 "scif2_data_a",
2195 "scif2_clk",
2196 "scif2_data_b",
2197};
2198
2199static const char * const scif3_groups[] = {
2200 "scif3_data_a",
2201 "scif3_clk",
2202 "scif3_ctrl",
2203 "scif3_data_b",
2204};
2205
2206static const char * const scif4_groups[] = {
2207 "scif4_data_a",
2208 "scif4_clk_a",
2209 "scif4_ctrl_a",
2210 "scif4_data_b",
2211 "scif4_clk_b",
2212 "scif4_ctrl_b",
2213 "scif4_data_c",
2214 "scif4_clk_c",
2215 "scif4_ctrl_c",
2216};
2217
2218static const char * const scif5_groups[] = {
2219 "scif5_data_a",
2220 "scif5_clk_a",
2221 "scif5_data_b",
2222 "scif5_clk_b",
76250a6c
TK		 2223};
2224
d14a39ed
GU		 2225static const char * const scif_clk_groups[] = {
2226 "scif_clk_a",
2227 "scif_clk_b",
2228};
2229
0b0ffc96 2230static const struct sh_pfc_function pinmux_functions[] = {
30c078de 2231 SH_PFC_FUNCTION(avb),
a20a6585 2232 SH_PFC_FUNCTION(du),
c03a133b
LP		 2233 SH_PFC_FUNCTION(pwm0),
2234 SH_PFC_FUNCTION(pwm1),
2235 SH_PFC_FUNCTION(pwm2),
2236 SH_PFC_FUNCTION(pwm3),
2237 SH_PFC_FUNCTION(pwm4),
2238 SH_PFC_FUNCTION(pwm5),
2239 SH_PFC_FUNCTION(pwm6),
e7ad4d3c
GU		 2240 SH_PFC_FUNCTION(scif0),
2241 SH_PFC_FUNCTION(scif1),
2242 SH_PFC_FUNCTION(scif2),
2243 SH_PFC_FUNCTION(scif3),
2244 SH_PFC_FUNCTION(scif4),
2245 SH_PFC_FUNCTION(scif5),
d14a39ed 2246 SH_PFC_FUNCTION(scif_clk),
0b0ffc96
TK		 2247};
2248
2249static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2250#define F_(x, y) FN_##y
2251#define FM(x) FN_##x
2252 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
2253 0, 0,
2254 0, 0,
2255 0, 0,
2256 0, 0,
2257 0, 0,
2258 0, 0,
2259 0, 0,
2260 0, 0,
2261 0, 0,
2262 0, 0,
2263 0, 0,
2264 0, 0,
2265 0, 0,
2266 0, 0,
2267 0, 0,
2268 0, 0,
2269 GP_0_15_FN, GPSR0_15,
2270 GP_0_14_FN, GPSR0_14,
2271 GP_0_13_FN, GPSR0_13,
2272 GP_0_12_FN, GPSR0_12,
2273 GP_0_11_FN, GPSR0_11,
2274 GP_0_10_FN, GPSR0_10,
2275 GP_0_9_FN, GPSR0_9,
2276 GP_0_8_FN, GPSR0_8,
2277 GP_0_7_FN, GPSR0_7,
2278 GP_0_6_FN, GPSR0_6,
2279 GP_0_5_FN, GPSR0_5,
2280 GP_0_4_FN, GPSR0_4,
2281 GP_0_3_FN, GPSR0_3,
2282 GP_0_2_FN, GPSR0_2,
2283 GP_0_1_FN, GPSR0_1,
2284 GP_0_0_FN, GPSR0_0, }
2285 },
2286 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 GP_1_27_FN, GPSR1_27,
2292 GP_1_26_FN, GPSR1_26,
2293 GP_1_25_FN, GPSR1_25,
2294 GP_1_24_FN, GPSR1_24,
2295 GP_1_23_FN, GPSR1_23,
2296 GP_1_22_FN, GPSR1_22,
2297 GP_1_21_FN, GPSR1_21,
2298 GP_1_20_FN, GPSR1_20,
2299 GP_1_19_FN, GPSR1_19,
2300 GP_1_18_FN, GPSR1_18,
2301 GP_1_17_FN, GPSR1_17,
2302 GP_1_16_FN, GPSR1_16,
2303 GP_1_15_FN, GPSR1_15,
2304 GP_1_14_FN, GPSR1_14,
2305 GP_1_13_FN, GPSR1_13,
2306 GP_1_12_FN, GPSR1_12,
2307 GP_1_11_FN, GPSR1_11,
2308 GP_1_10_FN, GPSR1_10,
2309 GP_1_9_FN, GPSR1_9,
2310 GP_1_8_FN, GPSR1_8,
2311 GP_1_7_FN, GPSR1_7,
2312 GP_1_6_FN, GPSR1_6,
2313 GP_1_5_FN, GPSR1_5,
2314 GP_1_4_FN, GPSR1_4,
2315 GP_1_3_FN, GPSR1_3,
2316 GP_1_2_FN, GPSR1_2,
2317 GP_1_1_FN, GPSR1_1,
2318 GP_1_0_FN, GPSR1_0, }
2319 },
2320 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
2321 0, 0,
2322 0, 0,
2323 0, 0,
2324 0, 0,
2325 0, 0,
2326 0, 0,
2327 0, 0,
2328 0, 0,
2329 0, 0,
2330 0, 0,
2331 0, 0,
2332 0, 0,
2333 0, 0,
2334 0, 0,
2335 0, 0,
2336 0, 0,
2337 0, 0,
2338 GP_2_14_FN, GPSR2_14,
2339 GP_2_13_FN, GPSR2_13,
2340 GP_2_12_FN, GPSR2_12,
2341 GP_2_11_FN, GPSR2_11,
2342 GP_2_10_FN, GPSR2_10,
2343 GP_2_9_FN, GPSR2_9,
2344 GP_2_8_FN, GPSR2_8,
2345 GP_2_7_FN, GPSR2_7,
2346 GP_2_6_FN, GPSR2_6,
2347 GP_2_5_FN, GPSR2_5,
2348 GP_2_4_FN, GPSR2_4,
2349 GP_2_3_FN, GPSR2_3,
2350 GP_2_2_FN, GPSR2_2,
2351 GP_2_1_FN, GPSR2_1,
2352 GP_2_0_FN, GPSR2_0, }
2353 },
2354 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
2355 0, 0,
2356 0, 0,
2357 0, 0,
2358 0, 0,
2359 0, 0,
2360 0, 0,
2361 0, 0,
2362 0, 0,
2363 0, 0,
2364 0, 0,
2365 0, 0,
2366 0, 0,
2367 0, 0,
2368 0, 0,
2369 0, 0,
2370 0, 0,
2371 GP_3_15_FN, GPSR3_15,
2372 GP_3_14_FN, GPSR3_14,
2373 GP_3_13_FN, GPSR3_13,
2374 GP_3_12_FN, GPSR3_12,
2375 GP_3_11_FN, GPSR3_11,
2376 GP_3_10_FN, GPSR3_10,
2377 GP_3_9_FN, GPSR3_9,
2378 GP_3_8_FN, GPSR3_8,
2379 GP_3_7_FN, GPSR3_7,
2380 GP_3_6_FN, GPSR3_6,
2381 GP_3_5_FN, GPSR3_5,
2382 GP_3_4_FN, GPSR3_4,
2383 GP_3_3_FN, GPSR3_3,
2384 GP_3_2_FN, GPSR3_2,
2385 GP_3_1_FN, GPSR3_1,
2386 GP_3_0_FN, GPSR3_0, }
2387 },
2388 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
2389 0, 0,
2390 0, 0,
2391 0, 0,
2392 0, 0,
2393 0, 0,
2394 0, 0,
2395 0, 0,
2396 0, 0,
2397 0, 0,
2398 0, 0,
2399 0, 0,
2400 0, 0,
2401 0, 0,
2402 0, 0,
2403 GP_4_17_FN, GPSR4_17,
2404 GP_4_16_FN, GPSR4_16,
2405 GP_4_15_FN, GPSR4_15,
2406 GP_4_14_FN, GPSR4_14,
2407 GP_4_13_FN, GPSR4_13,
2408 GP_4_12_FN, GPSR4_12,
2409 GP_4_11_FN, GPSR4_11,
2410 GP_4_10_FN, GPSR4_10,
2411 GP_4_9_FN, GPSR4_9,
2412 GP_4_8_FN, GPSR4_8,
2413 GP_4_7_FN, GPSR4_7,
2414 GP_4_6_FN, GPSR4_6,
2415 GP_4_5_FN, GPSR4_5,
2416 GP_4_4_FN, GPSR4_4,
2417 GP_4_3_FN, GPSR4_3,
2418 GP_4_2_FN, GPSR4_2,
2419 GP_4_1_FN, GPSR4_1,
2420 GP_4_0_FN, GPSR4_0, }
2421 },
2422 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
2423 0, 0,
2424 0, 0,
2425 0, 0,
2426 0, 0,
2427 0, 0,
2428 0, 0,
2429 GP_5_25_FN, GPSR5_25,
2430 GP_5_24_FN, GPSR5_24,
2431 GP_5_23_FN, GPSR5_23,
2432 GP_5_22_FN, GPSR5_22,
2433 GP_5_21_FN, GPSR5_21,
2434 GP_5_20_FN, GPSR5_20,
2435 GP_5_19_FN, GPSR5_19,
2436 GP_5_18_FN, GPSR5_18,
2437 GP_5_17_FN, GPSR5_17,
2438 GP_5_16_FN, GPSR5_16,
2439 GP_5_15_FN, GPSR5_15,
2440 GP_5_14_FN, GPSR5_14,
2441 GP_5_13_FN, GPSR5_13,
2442 GP_5_12_FN, GPSR5_12,
2443 GP_5_11_FN, GPSR5_11,
2444 GP_5_10_FN, GPSR5_10,
2445 GP_5_9_FN, GPSR5_9,
2446 GP_5_8_FN, GPSR5_8,
2447 GP_5_7_FN, GPSR5_7,
2448 GP_5_6_FN, GPSR5_6,
2449 GP_5_5_FN, GPSR5_5,
2450 GP_5_4_FN, GPSR5_4,
2451 GP_5_3_FN, GPSR5_3,
2452 GP_5_2_FN, GPSR5_2,
2453 GP_5_1_FN, GPSR5_1,
2454 GP_5_0_FN, GPSR5_0, }
2455 },
2456 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
2457 GP_6_31_FN, GPSR6_31,
2458 GP_6_30_FN, GPSR6_30,
2459 GP_6_29_FN, GPSR6_29,
2460 GP_6_28_FN, GPSR6_28,
2461 GP_6_27_FN, GPSR6_27,
2462 GP_6_26_FN, GPSR6_26,
2463 GP_6_25_FN, GPSR6_25,
2464 GP_6_24_FN, GPSR6_24,
2465 GP_6_23_FN, GPSR6_23,
2466 GP_6_22_FN, GPSR6_22,
2467 GP_6_21_FN, GPSR6_21,
2468 GP_6_20_FN, GPSR6_20,
2469 GP_6_19_FN, GPSR6_19,
2470 GP_6_18_FN, GPSR6_18,
2471 GP_6_17_FN, GPSR6_17,
2472 GP_6_16_FN, GPSR6_16,
2473 GP_6_15_FN, GPSR6_15,
2474 GP_6_14_FN, GPSR6_14,
2475 GP_6_13_FN, GPSR6_13,
2476 GP_6_12_FN, GPSR6_12,
2477 GP_6_11_FN, GPSR6_11,
2478 GP_6_10_FN, GPSR6_10,
2479 GP_6_9_FN, GPSR6_9,
2480 GP_6_8_FN, GPSR6_8,
2481 GP_6_7_FN, GPSR6_7,
2482 GP_6_6_FN, GPSR6_6,
2483 GP_6_5_FN, GPSR6_5,
2484 GP_6_4_FN, GPSR6_4,
2485 GP_6_3_FN, GPSR6_3,
2486 GP_6_2_FN, GPSR6_2,
2487 GP_6_1_FN, GPSR6_1,
2488 GP_6_0_FN, GPSR6_0, }
2489 },
2490 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
2491 0, 0,
2492 0, 0,
2493 0, 0,
2494 0, 0,
2495 0, 0,
2496 0, 0,
2497 0, 0,
2498 0, 0,
2499 0, 0,
2500 0, 0,
2501 0, 0,
2502 0, 0,
2503 0, 0,
2504 0, 0,
2505 0, 0,
2506 0, 0,
2507 0, 0,
2508 0, 0,
2509 0, 0,
2510 0, 0,
2511 0, 0,
2512 0, 0,
2513 0, 0,
2514 0, 0,
2515 0, 0,
2516 0, 0,
2517 0, 0,
2518 0, 0,
2519 GP_7_3_FN, GPSR7_3,
2520 GP_7_2_FN, GPSR7_2,
2521 GP_7_1_FN, GPSR7_1,
2522 GP_7_0_FN, GPSR7_0, }
2523 },
2524#undef F_
2525#undef FM
2526
2527#define F_(x, y) x,
2528#define FM(x) FN_##x,
2529 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
2530 IP0_31_28
2531 IP0_27_24
2532 IP0_23_20
2533 IP0_19_16
2534 IP0_15_12
2535 IP0_11_8
2536 IP0_7_4
2537 IP0_3_0 }
2538 },
2539 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
2540 IP1_31_28
2541 IP1_27_24
2542 IP1_23_20
2543 IP1_19_16
2544 IP1_15_12
2545 IP1_11_8
2546 IP1_7_4
2547 IP1_3_0 }
2548 },
2549 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
2550 IP2_31_28
2551 IP2_27_24
2552 IP2_23_20
2553 IP2_19_16
2554 IP2_15_12
2555 IP2_11_8
2556 IP2_7_4
2557 IP2_3_0 }
2558 },
2559 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
2560 IP3_31_28
2561 IP3_27_24
2562 IP3_23_20
2563 IP3_19_16
2564 IP3_15_12
2565 IP3_11_8
2566 IP3_7_4
2567 IP3_3_0 }
2568 },
2569 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
2570 IP4_31_28
2571 IP4_27_24
2572 IP4_23_20
2573 IP4_19_16
2574 IP4_15_12
2575 IP4_11_8
2576 IP4_7_4
2577 IP4_3_0 }
2578 },
2579 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
2580 IP5_31_28
2581 IP5_27_24
2582 IP5_23_20
2583 IP5_19_16
2584 IP5_15_12
2585 IP5_11_8
2586 IP5_7_4
2587 IP5_3_0 }
2588 },
2589 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
2590 IP6_31_28
2591 IP6_27_24
2592 IP6_23_20
2593 IP6_19_16
2594 IP6_15_12
2595 IP6_11_8
2596 IP6_7_4
2597 IP6_3_0 }
2598 },
2599 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
2600 IP7_31_28
2601 IP7_27_24
2602 IP7_23_20
2603 IP7_19_16
2604 IP7_15_12
2605 IP7_11_8
2606 IP7_7_4
2607 IP7_3_0 }
2608 },
2609 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
2610 IP8_31_28
2611 IP8_27_24
2612 IP8_23_20
2613 IP8_19_16
2614 IP8_15_12
2615 IP8_11_8
2616 IP8_7_4
2617 IP8_3_0 }
2618 },
2619 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
2620 IP9_31_28
2621 IP9_27_24
2622 IP9_23_20
2623 IP9_19_16
2624 IP9_15_12
2625 IP9_11_8
2626 IP9_7_4
2627 IP9_3_0 }
2628 },
2629 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
2630 IP10_31_28
2631 IP10_27_24
2632 IP10_23_20
2633 IP10_19_16
2634 IP10_15_12
2635 IP10_11_8
2636 IP10_7_4
2637 IP10_3_0 }
2638 },
2639 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
2640 IP11_31_28
2641 IP11_27_24
2642 IP11_23_20
2643 IP11_19_16
2644 IP11_15_12
2645 IP11_11_8
2646 IP11_7_4
2647 IP11_3_0 }
2648 },
2649 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
2650 IP12_31_28
2651 IP12_27_24
2652 IP12_23_20
2653 IP12_19_16
2654 IP12_15_12
2655 IP12_11_8
2656 IP12_7_4
2657 IP12_3_0 }
2658 },
2659 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
2660 IP13_31_28
2661 IP13_27_24
2662 IP13_23_20
2663 IP13_19_16
2664 IP13_15_12
2665 IP13_11_8
2666 IP13_7_4
2667 IP13_3_0 }
2668 },
2669 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
2670 IP14_31_28
2671 IP14_27_24
2672 IP14_23_20
2673 IP14_19_16
2674 IP14_15_12
2675 IP14_11_8
2676 IP14_7_4
2677 IP14_3_0 }
2678 },
2679 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
2680 IP15_31_28
2681 IP15_27_24
2682 IP15_23_20
2683 IP15_19_16
2684 IP15_15_12
2685 IP15_11_8
2686 IP15_7_4
2687 IP15_3_0 }
2688 },
2689 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
2690 IP16_31_28
2691 IP16_27_24
2692 IP16_23_20
2693 IP16_19_16
2694 IP16_15_12
2695 IP16_11_8
2696 IP16_7_4
2697 IP16_3_0 }
2698 },
2699 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
b205914c
GU		 2700 IP17_31_28
2701 IP17_27_24
2702 IP17_23_20
2703 IP17_19_16
2704 IP17_15_12
2705 IP17_11_8
0b0ffc96
TK		 2706 IP17_7_4
2707 IP17_3_0 }
2708 },
b205914c
GU		 2709 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
2710 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2711 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2712 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2713 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2714 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2715 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2716 IP18_7_4
2717 IP18_3_0 }
2718 },
0b0ffc96
TK		 2719#undef F_
2720#undef FM
2721
2722#define F_(x, y) x,
2723#define FM(x) FN_##x,
2724 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
b205914c
GU		 2725 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
2726 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
2727 MOD_SEL0_31_30_29
0b0ffc96
TK		 2728 MOD_SEL0_28_27
2729 MOD_SEL0_26_25_24
2730 MOD_SEL0_23
2731 MOD_SEL0_22
b205914c
GU		 2732 MOD_SEL0_21
2733 MOD_SEL0_20
0b0ffc96 2734 MOD_SEL0_19
b205914c
GU		 2735 MOD_SEL0_18_17
2736 MOD_SEL0_16
2737 0, 0, /* RESERVED 15 */
2738 MOD_SEL0_14_13
0b0ffc96
TK		 2739 MOD_SEL0_12
2740 MOD_SEL0_11
2741 MOD_SEL0_10
b205914c 2742 MOD_SEL0_9_8
0b0ffc96 2743 MOD_SEL0_7_6
b205914c
GU		 2744 MOD_SEL0_5
2745 MOD_SEL0_4_3
2746 /* RESERVED 2, 1, 0 */
2747 0, 0, 0, 0, 0, 0, 0, 0 }
0b0ffc96
TK		 2748 },
2749 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
2750 2, 3, 1, 2, 3, 1, 1, 2, 1,
2751 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
2752 MOD_SEL1_31_30
2753 MOD_SEL1_29_28_27
2754 MOD_SEL1_26
2755 MOD_SEL1_25_24
2756 MOD_SEL1_23_22_21
2757 MOD_SEL1_20
2758 MOD_SEL1_19
2759 MOD_SEL1_18_17
2760 MOD_SEL1_16
2761 MOD_SEL1_15_14
2762 MOD_SEL1_13
2763 MOD_SEL1_12
2764 MOD_SEL1_11
2765 MOD_SEL1_10
2766 MOD_SEL1_9
2767 0, 0, 0, 0, /* RESERVED 8, 7 */
2768 MOD_SEL1_6
2769 MOD_SEL1_5
2770 MOD_SEL1_4
2771 MOD_SEL1_3
2772 MOD_SEL1_2
2773 MOD_SEL1_1
2774 MOD_SEL1_0 }
2775 },
2776 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
b205914c
GU		 2777 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
2778 4, 4, 4, 3, 1) {
0b0ffc96
TK		 2779 MOD_SEL2_31
2780 MOD_SEL2_30
2781 MOD_SEL2_29
b205914c
GU		 2782 MOD_SEL2_28_27
2783 MOD_SEL2_26
2784 MOD_SEL2_25_24_23
2785 MOD_SEL2_22
2786 MOD_SEL2_21
2787 MOD_SEL2_20
2788 MOD_SEL2_19
2789 MOD_SEL2_18
2790 MOD_SEL2_17
2791 /* RESERVED 16 */
0b0ffc96 2792 0, 0,
0b0ffc96
TK		 2793 /* RESERVED 15, 14, 13, 12 */
2794 0, 0, 0, 0, 0, 0, 0, 0,
2795 0, 0, 0, 0, 0, 0, 0, 0,
2796 /* RESERVED 11, 10, 9, 8 */
2797 0, 0, 0, 0, 0, 0, 0, 0,
2798 0, 0, 0, 0, 0, 0, 0, 0,
2799 /* RESERVED 7, 6, 5, 4 */
2800 0, 0, 0, 0, 0, 0, 0, 0,
2801 0, 0, 0, 0, 0, 0, 0, 0,
b205914c
GU		 2802 /* RESERVED 3, 2, 1 */
2803 0, 0, 0, 0, 0, 0, 0, 0,
0b0ffc96
TK		 2804 MOD_SEL2_0 }
2805 },
2806 { },
2807};
2808
92e6d9a2 2809static const struct pinmux_drive_reg pinmux_drive_regs[] = {
ea9c7405
NS		 2810 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
2811 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
2812 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
2813 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
2814 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
2815 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
2816 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
2817 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
2818 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
2819 } },
2820 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
2821 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
2822 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
2823 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
2824 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
2825 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
2826 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
2827 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
2828 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
2829 } },
2830 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
2831 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
2832 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
2833 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
2834 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
2835 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
2836 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
2837 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
2838 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
2839 } },
92e6d9a2 2840 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
ea9c7405
NS		 2841 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
2842 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
2843 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
2844 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
2845 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
2846 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
2847 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
2848 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
92e6d9a2
LP		 2849 } },
2850 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
2851 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
2852 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
2853 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
2854 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
2855 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
2856 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
2857 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
2858 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
2859 } },
2860 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
2861 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
2862 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
2863 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
2864 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
2865 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
2866 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
2867 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
2868 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
2869 } },
2870 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
2871 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
2872 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
2873 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
2874 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
2875 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
2876 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
2877 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
2878 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
2879 } },
2880 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
2881 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
2882 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
2883 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
2884 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
2885 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
2886 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
2887 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
2888 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
2889 } },
2890 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
ea9c7405 2891 { PIN_NUMBER('F', 1), 28, 3 }, /* CLKOUT */
92e6d9a2
LP		 2892 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
2893 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
2894 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
2895 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
2896 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
2897 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
2898 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
2899 } },
2900 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
2901 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
ea9c7405 2902 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
92e6d9a2
LP		 2903 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
2904 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
2905 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
2906 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
2907 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
2908 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
2909 } },
2910 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
2911 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
2912 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
2913 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
2914 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
2915 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
2916 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
2917 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
2918 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
2919 } },
2920 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
ea9c7405
NS		 2921 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
2922 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
2923 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
2924 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
2925 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
2926 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
2927 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
2928 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
2929 } },
2930 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
2931 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
2932 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
2933 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
2934 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
92e6d9a2
LP		 2935 } },
2936 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
ea9c7405
NS		 2937 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
2938 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
2939 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
2940 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
2941 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
2942 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
2943 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
2944 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
92e6d9a2
LP		 2945 } },
2946 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
2947 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
2948 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
2949 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
2950 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
2951 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
2952 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
2953 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
2954 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
2955 } },
2956 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
2957 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
2958 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
2959 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
2960 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
2961 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
2962 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
2963 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
2964 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
2965 } },
2966 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
2967 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
2968 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
2969 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
2970 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
2971 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
2972 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
2973 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
2974 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
2975 } },
2976 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
2977 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
2978 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
2979 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
2980 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
2981 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
2982 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
2983 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
2984 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
2985 } },
2986 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
2987 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
2988 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
2989 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
2990 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
2991 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
2992 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
2993 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
2994 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
2995 } },
2996 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
2997 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
2998 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
2999 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
3000 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
3001 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
3002 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
3003 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
3004 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
3005 } },
3006 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
3007 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
3008 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
3009 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
3010 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
3011 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
3012 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
ea9c7405 3013 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
92e6d9a2
LP		 3014 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
3015 } },
3016 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
3017 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
3018 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
3019 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
3020 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
68e63892
KM		 3021 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
3022 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
92e6d9a2
LP		 3023 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
3024 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
3025 } },
3026 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
3027 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
3028 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
3029 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
3030 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
3031 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
3032 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
3033 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
3034 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
3035 } },
3036 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
3037 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
3038 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
3039 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
3040 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
3041 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
3042 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
3043 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
3044 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
3045 } },
3046 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
3047 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
3048 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
3049 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
3050 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
3051 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
b205914c
GU		 3052 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB3_PWEN */
3053 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB3_OVC */
92e6d9a2
LP		 3054 } },
3055 { },
3056};
3057
e9eace32
WS		 3058static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
3059{
3060 int bit = -EINVAL;
3061
3062 *pocctrl = 0xe6060380;
3063
3064 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
3065 bit = pin & 0x1f;
3066
3067 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
3068 bit = (pin & 0x1f) + 12;
3069
3070 return bit;
3071}
3072
56065524
UH		 3073#define PUEN 0xe6060400
3074#define PUD 0xe6060440
3075
3076#define PU0 0x00
3077#define PU1 0x04
3078#define PU2 0x08
3079#define PU3 0x0c
3080#define PU4 0x10
3081#define PU5 0x14
3082#define PU6 0x18
3083
d3b861bc 3084static const struct sh_pfc_bias_info bias_info[] = {
4c2fb44d
NS		 3085 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
3086 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
3087 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
3088 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
3089 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
3090 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
3091 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
3092 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
3093 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
3094 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
3095 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
3096 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
3097 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
3098 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
3099 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
3100 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
3101 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
3102 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
3103 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
3104 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
3105 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
3106 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
3107 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
3108 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
3109 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
3110 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
3111 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
3112 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
3113 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
3114 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
3115 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
3116 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
3117
3118 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
3119 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
3120 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
3121 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
3122 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
3123 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
3124 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
3125 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
3126 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
3127 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
3128 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
3129 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
3130 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
3131 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
3132 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
3133 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
3134 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
3135 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
3136 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
3137 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
3138 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
3139 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
3140 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
3141 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
3142 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
3143 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
3144 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
3145 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
3146 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
3147 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
3148 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
3149 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
3150
3151 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
3152 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
3153 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* HDMI1_CEC */
3154 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
3155 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
3156 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
3157 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
3158 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
3159 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
3160 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
3161 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
3162 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
3163 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
3164 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
3165 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
3166 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
3167 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
3168 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
3169 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
3170 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
3171 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
3172 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
3173 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
3174 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
3175 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
3176 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
3177 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
3178 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
3179 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
3180 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
3181 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
3182 { PIN_NUMBER('F', 1), PU2, 0 }, /* CLKOUT */
3183
3184 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
3185 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
3186 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
3187 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
3188 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
3189 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
3190 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
3191 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
3192 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
3193 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
3194 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
3195 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
3196 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
3197 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
3198 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
3199 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
3200 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
3201 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
3202 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
3203 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
3204 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
3205 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
3206 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
3207 /* bit 8 n/a */
3208 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
3209 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
3210 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
3211 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
3212 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
3213 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST# */
3214 { PIN_A_NUMBER('R', 8), PU3, 1 }, /* DU_DOTCLKIN3 */
3215 { PIN_A_NUMBER('R', 7), PU3, 0 }, /* DU_DOTCLKIN2 */
3216
3217 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
3218 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
3219 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
3220 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
3221 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
3222 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
3223 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
3224 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
3225 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
3226 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
3227 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
3228 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
3229 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
3230 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
3231 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
3232 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
3233 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
3234 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
3235 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
3236 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
3237 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
3238 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
3239 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
3240 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
3241 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
3242 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
3243 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
3244 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
3245 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
3246 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
3247 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
3248 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
3249
3250 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
3251 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
3252 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
3253 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
3254 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
3255 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
3256 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
3257 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
3258 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
3259 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
3260 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
3261 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
3262 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
3263 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
3264 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
3265 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
3266 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
3267 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
68e63892
KM		 3268 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS349 */
3269 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK349 */
4c2fb44d
NS		 3270 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
3271 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
3272 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
3273 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
3274 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
3275 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
3276 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
3277 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
3278 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
3279 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
3280 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
3281 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
3282
b205914c
GU		 3283 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* USB3_OVC */
3284 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* USB3_PWEN */
4c2fb44d
NS		 3285 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
3286 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
3287 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
3288 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
3289 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
56065524
UH		 3290};
3291
3292static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
3293 unsigned int pin)
3294{
d3b861bc 3295 const struct sh_pfc_bias_info *info;
56065524
UH		 3296 u32 reg;
3297 u32 bit;
3298
d3b861bc
NS		 3299 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3300 if (!info)
56065524
UH		 3301 return PIN_CONFIG_BIAS_DISABLE;
3302
d3b861bc
NS		 3303 reg = info->reg;
3304 bit = BIT(info->bit);
56065524 3305
42831cf9 3306 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
56065524 3307 return PIN_CONFIG_BIAS_DISABLE;
42831cf9
NS		 3308 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
3309 return PIN_CONFIG_BIAS_PULL_UP;
3310 else
3311 return PIN_CONFIG_BIAS_PULL_DOWN;
56065524
UH		 3312}
3313
3314static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3315 unsigned int bias)
3316{
d3b861bc 3317 const struct sh_pfc_bias_info *info;
56065524
UH		 3318 u32 enable, updown;
3319 u32 reg;
3320 u32 bit;
3321
d3b861bc
NS		 3322 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
3323 if (!info)
56065524
UH		 3324 return;
3325
d3b861bc
NS		 3326 reg = info->reg;
3327 bit = BIT(info->bit);
56065524
UH		 3328
3329 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
3330 if (bias != PIN_CONFIG_BIAS_DISABLE)
3331 enable |= bit;
3332
3333 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
3334 if (bias == PIN_CONFIG_BIAS_PULL_UP)
3335 updown |= bit;
3336
3337 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
3338 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
3339}
3340
b205914c
GU		 3341static const struct soc_device_attribute r8a7795es1[] = {
3342 { .soc_id = "r8a7795", .revision = "ES1.*" },
3343 { /* sentinel */ }
3344};
3345
3346static int r8a7795_pinmux_init(struct sh_pfc *pfc)
3347{
3348 if (soc_device_match(r8a7795es1))
3349 pfc->info = &r8a7795es1_pinmux_info;
3350
3351 return 0;
3352}
3353
e9eace32 3354static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
b205914c 3355 .init = r8a7795_pinmux_init,
e9eace32 3356 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
56065524
UH		 3357 .get_bias = r8a7795_pinmux_get_bias,
3358 .set_bias = r8a7795_pinmux_set_bias,
e9eace32
WS		 3359};
3360
0b0ffc96 3361const struct sh_pfc_soc_info r8a7795_pinmux_info = {
b205914c 3362 .name = "r8a77951_pfc",
e9eace32 3363 .ops = &r8a7795_pinmux_ops,
0b0ffc96
TK		 3364 .unlock_reg = 0xe6060000, /* PMMR */
3365
3366 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3367
3368 .pins = pinmux_pins,
3369 .nr_pins = ARRAY_SIZE(pinmux_pins),
3370 .groups = pinmux_groups,
3371 .nr_groups = ARRAY_SIZE(pinmux_groups),
3372 .functions = pinmux_functions,
3373 .nr_functions = ARRAY_SIZE(pinmux_functions),
3374
3375 .cfg_regs = pinmux_config_regs,
92e6d9a2 3376 .drive_regs = pinmux_drive_regs,
0b0ffc96 3377
b8b47d67
GU		 3378 .pinmux_data = pinmux_data,
3379 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
0b0ffc96 3380};
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