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[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pfc-r8a7796.c
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f9aece73
TK		 1/*
2 * R8A7796 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2016 Renesas Electronics Corp.
5 *
6 * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c
7 *
8 * R-Car Gen3 processor support - PFC hardware block.
9 *
10 * Copyright (C) 2015 Renesas Electronics Corporation
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; version 2 of the License.
15 */
16
17#include <linux/kernel.h>
18
19#include "core.h"
20#include "sh_pfc.h"
21
2d40bd24
NS		 22#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
23 SH_PFC_PIN_CFG_PULL_UP | \
24 SH_PFC_PIN_CFG_PULL_DOWN)
9e35d6fa 25
f9aece73 26#define CPU_ALL_PORT(fn, sfx) \
9e35d6fa
NS		 27 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
30 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
31 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
33 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
34 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
35 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
36 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
37 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
38 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
f9aece73
TK		 39/*
40 * F_() : just information
41 * FM() : macro for FN_xxx / xxx_MARK
42 */
43
44/* GPSR0 */
45#define GPSR0_15 F_(D15, IP7_11_8)
46#define GPSR0_14 F_(D14, IP7_7_4)
47#define GPSR0_13 F_(D13, IP7_3_0)
48#define GPSR0_12 F_(D12, IP6_31_28)
49#define GPSR0_11 F_(D11, IP6_27_24)
50#define GPSR0_10 F_(D10, IP6_23_20)
51#define GPSR0_9 F_(D9, IP6_19_16)
52#define GPSR0_8 F_(D8, IP6_15_12)
53#define GPSR0_7 F_(D7, IP6_11_8)
54#define GPSR0_6 F_(D6, IP6_7_4)
55#define GPSR0_5 F_(D5, IP6_3_0)
56#define GPSR0_4 F_(D4, IP5_31_28)
57#define GPSR0_3 F_(D3, IP5_27_24)
58#define GPSR0_2 F_(D2, IP5_23_20)
59#define GPSR0_1 F_(D1, IP5_19_16)
60#define GPSR0_0 F_(D0, IP5_15_12)
61
62/* GPSR1 */
63#define GPSR1_28 FM(CLKOUT)
64#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
65#define GPSR1_26 F_(WE1_N, IP5_7_4)
66#define GPSR1_25 F_(WE0_N, IP5_3_0)
67#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
68#define GPSR1_23 F_(RD_N, IP4_27_24)
69#define GPSR1_22 F_(BS_N, IP4_23_20)
70#define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
71#define GPSR1_20 F_(CS0_N, IP4_15_12)
72#define GPSR1_19 F_(A19, IP4_11_8)
73#define GPSR1_18 F_(A18, IP4_7_4)
74#define GPSR1_17 F_(A17, IP4_3_0)
75#define GPSR1_16 F_(A16, IP3_31_28)
76#define GPSR1_15 F_(A15, IP3_27_24)
77#define GPSR1_14 F_(A14, IP3_23_20)
78#define GPSR1_13 F_(A13, IP3_19_16)
79#define GPSR1_12 F_(A12, IP3_15_12)
80#define GPSR1_11 F_(A11, IP3_11_8)
81#define GPSR1_10 F_(A10, IP3_7_4)
82#define GPSR1_9 F_(A9, IP3_3_0)
83#define GPSR1_8 F_(A8, IP2_31_28)
84#define GPSR1_7 F_(A7, IP2_27_24)
85#define GPSR1_6 F_(A6, IP2_23_20)
86#define GPSR1_5 F_(A5, IP2_19_16)
87#define GPSR1_4 F_(A4, IP2_15_12)
88#define GPSR1_3 F_(A3, IP2_11_8)
89#define GPSR1_2 F_(A2, IP2_7_4)
90#define GPSR1_1 F_(A1, IP2_3_0)
91#define GPSR1_0 F_(A0, IP1_31_28)
92
93/* GPSR2 */
94#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
95#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
96#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
97#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
98#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
99#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
100#define GPSR2_8 F_(PWM2_A, IP1_27_24)
101#define GPSR2_7 F_(PWM1_A, IP1_23_20)
102#define GPSR2_6 F_(PWM0, IP1_19_16)
103#define GPSR2_5 F_(IRQ5, IP1_15_12)
104#define GPSR2_4 F_(IRQ4, IP1_11_8)
105#define GPSR2_3 F_(IRQ3, IP1_7_4)
106#define GPSR2_2 F_(IRQ2, IP1_3_0)
107#define GPSR2_1 F_(IRQ1, IP0_31_28)
108#define GPSR2_0 F_(IRQ0, IP0_27_24)
109
110/* GPSR3 */
111#define GPSR3_15 F_(SD1_WP, IP11_23_20)
112#define GPSR3_14 F_(SD1_CD, IP11_19_16)
113#define GPSR3_13 F_(SD0_WP, IP11_15_12)
114#define GPSR3_12 F_(SD0_CD, IP11_11_8)
115#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
116#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
117#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
118#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
119#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
120#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
121#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
122#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
123#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
124#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
125#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
126#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
127
128/* GPSR4 */
0f866a96
GU		 129#define GPSR4_17 F_(SD3_DS, IP11_7_4)
130#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
131#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
132#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
133#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
f9aece73
TK		 134#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
135#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
136#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
137#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
138#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
139#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
0f866a96
GU		 140#define GPSR4_6 F_(SD2_DS, IP9_27_24)
141#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
142#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
143#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
144#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
f9aece73
TK		 145#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
146#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
147
148/* GPSR5 */
149#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
150#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
151#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
152#define GPSR5_22 FM(MSIOF0_RXD)
153#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
154#define GPSR5_20 FM(MSIOF0_TXD)
155#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
156#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
157#define GPSR5_17 FM(MSIOF0_SCK)
158#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
159#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
160#define GPSR5_14 F_(HTX0, IP13_19_16)
161#define GPSR5_13 F_(HRX0, IP13_15_12)
162#define GPSR5_12 F_(HSCK0, IP13_11_8)
163#define GPSR5_11 F_(RX2_A, IP13_7_4)
164#define GPSR5_10 F_(TX2_A, IP13_3_0)
165#define GPSR5_9 F_(SCK2, IP12_31_28)
166#define GPSR5_8 F_(RTS1_N_TANS, IP12_27_24)
167#define GPSR5_7 F_(CTS1_N, IP12_23_20)
168#define GPSR5_6 F_(TX1_A, IP12_19_16)
169#define GPSR5_5 F_(RX1_A, IP12_15_12)
170#define GPSR5_4 F_(RTS0_N_TANS, IP12_11_8)
171#define GPSR5_3 F_(CTS0_N, IP12_7_4)
172#define GPSR5_2 F_(TX0, IP12_3_0)
173#define GPSR5_1 F_(RX0, IP11_31_28)
174#define GPSR5_0 F_(SCK0, IP11_27_24)
175
176/* GPSR6 */
177#define GPSR6_31 F_(GP6_31, IP18_7_4)
178#define GPSR6_30 F_(GP6_30, IP18_3_0)
179#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
180#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
181#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
182#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
183#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
184#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
185#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
186#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
187#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
188#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
189#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
190#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
191#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
192#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
193#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
194#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
195#define GPSR6_13 FM(SSI_SDATA5)
196#define GPSR6_12 FM(SSI_WS5)
197#define GPSR6_11 FM(SSI_SCK5)
198#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
199#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
200#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
201#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
202#define GPSR6_6 F_(SSI_WS34, IP15_15_12)
203#define GPSR6_5 F_(SSI_SCK34, IP15_11_8)
204#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
205#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
206#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
207#define GPSR6_1 F_(SSI_WS0129, IP14_27_24)
208#define GPSR6_0 F_(SSI_SCK0129, IP14_23_20)
209
210/* GPSR7 */
211#define GPSR7_3 FM(GP7_03)
212#define GPSR7_2 FM(HDMI0_CEC)
213#define GPSR7_1 FM(AVS2)
214#define GPSR7_0 FM(AVS1)
215
216
217/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
218#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231#define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232#define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245
246/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
247#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256#define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
268#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276
277/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
278#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP9_7_4 FM(SD2_CMD) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP9_27_24 FM(SD2_DS) F_(0, 0) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP9_31_28 FM(SD3_CLK) F_(0, 0) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_3_0 FM(SD3_CMD) F_(0, 0) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_7_4 FM(SD3_DS) F_(0, 0) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313
314/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
315#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP12_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) FM(FSO_TOE_A) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP12_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
336#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP14_23_20 FM(SSI_SCK0129) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP14_27_24 FM(SSI_WS0129) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343
344/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
345#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP15_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP15_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_3_0 FM(SSI_SCK6) F_(0, 0) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP16_7_4 FM(SSI_WS6) F_(0, 0) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
358#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
359#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
360#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
361#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
362#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
364#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
365#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
366#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
367#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
368#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
369#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
370#define IP18_3_0 FM(GP6_30) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) FM(FSO_CFE_0_A) FM(TPU0TO2) F_(0, 0) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0)
371#define IP18_7_4 FM(GP6_31) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) FM(FSO_CFE_1_A) FM(TPU0TO3) F_(0, 0) FM(FMIN_C) FM(FMIN_D) F_(0, 0)
372
373#define PINMUX_GPSR \
374\
375 GPSR6_31 \
376 GPSR6_30 \
377 GPSR6_29 \
378 GPSR1_28 GPSR6_28 \
379 GPSR1_27 GPSR6_27 \
380 GPSR1_26 GPSR6_26 \
381 GPSR1_25 GPSR5_25 GPSR6_25 \
382 GPSR1_24 GPSR5_24 GPSR6_24 \
383 GPSR1_23 GPSR5_23 GPSR6_23 \
384 GPSR1_22 GPSR5_22 GPSR6_22 \
385 GPSR1_21 GPSR5_21 GPSR6_21 \
386 GPSR1_20 GPSR5_20 GPSR6_20 \
387 GPSR1_19 GPSR5_19 GPSR6_19 \
388 GPSR1_18 GPSR5_18 GPSR6_18 \
389 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
390 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
391GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
392GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
393GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
394GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
395GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
396GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
397GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
398GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
399GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
400GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
401GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
402GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
403GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
404GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
405GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
406GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
407
408#define PINMUX_IPSR \
409\
410FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
411FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
412FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
413FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
414FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
415FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
416FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
417FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
418\
419FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
420FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
421FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
422FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
423FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
424FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
425FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
426FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
427\
428FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
429FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
430FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
431FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
432FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
433FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
434FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
435FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
436\
437FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
438FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
439FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
440FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
441FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
442FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
443FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
444FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
445\
446FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
447FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
448FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
449FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
450FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
451FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
452FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
453FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
454
455/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
456#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
457#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
458#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
459#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
460#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
461#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
462#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
463#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
464#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
465#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
466#define MOD_SEL0_15 FM(SEL_FSO_0) FM(SEL_FSO_1)
467#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
468#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
469#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
470#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
471#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
472#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
473#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
474#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
475#define MOD_SEL0_2 FM(SEL_5LINE_0) FM(SEL_5LINE_1)
476
477/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
478#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
479#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
480#define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
481#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
482#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
483#define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
484#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
485#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
486#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
487#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
488#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
489#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
490#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
491#define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
492#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
493#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
494#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
495#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
496#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
497#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
498#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
499#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
500
501/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
502#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
503#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
504#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
505#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
506#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
507#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
508#define MOD_SEL2_22 FM(SEL_NDF_0) FM(SEL_NDF_1)
509#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
510#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
511#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
512#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
513#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
514#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
515
516#define PINMUX_MOD_SELS \
517\
518MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
519 MOD_SEL2_30 \
520 MOD_SEL1_29_28_27 MOD_SEL2_29 \
521MOD_SEL0_28_27 MOD_SEL2_28_27 \
522MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
523 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
524MOD_SEL0_23 MOD_SEL1_23_22_21 \
525MOD_SEL0_22 MOD_SEL2_22 \
526MOD_SEL0_21 MOD_SEL2_21 \
527MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
528MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
529MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
530 MOD_SEL2_17 \
531MOD_SEL0_16 MOD_SEL1_16 \
532MOD_SEL0_15 MOD_SEL1_15_14 \
533MOD_SEL0_14_13 \
534 MOD_SEL1_13 \
535MOD_SEL0_12 MOD_SEL1_12 \
536MOD_SEL0_11 MOD_SEL1_11 \
537MOD_SEL0_10 MOD_SEL1_10 \
538MOD_SEL0_9_8 MOD_SEL1_9 \
539MOD_SEL0_7_6 \
540 MOD_SEL1_6 \
541MOD_SEL0_5 MOD_SEL1_5 \
542MOD_SEL0_4_3 MOD_SEL1_4 \
543 MOD_SEL1_3 \
544MOD_SEL0_2 MOD_SEL1_2 \
545 MOD_SEL1_1 \
546 MOD_SEL1_0 MOD_SEL2_0
547
9e35d6fa
NS		 548/*
549 * These pins are not able to be muxed but have other properties
550 * that can be set, such as drive-strength or pull-up/pull-down enable.
551 */
552#define PINMUX_STATIC \
553 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
554 FM(QSPI0_IO2) FM(QSPI0_IO3) \
555 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
556 FM(QSPI1_IO2) FM(QSPI1_IO3) \
557 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
558 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
559 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
560 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
561 FM(PRESETOUT) \
562 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) \
2d40bd24 563 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
9e35d6fa 564
f9aece73
TK		 565enum {
566 PINMUX_RESERVED = 0,
567
568 PINMUX_DATA_BEGIN,
569 GP_ALL(DATA),
570 PINMUX_DATA_END,
571
572#define F_(x, y)
573#define FM(x) FN_##x,
574 PINMUX_FUNCTION_BEGIN,
575 GP_ALL(FN),
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
579 PINMUX_FUNCTION_END,
580#undef F_
581#undef FM
582
583#define F_(x, y)
584#define FM(x) x##_MARK,
585 PINMUX_MARK_BEGIN,
586 PINMUX_GPSR
587 PINMUX_IPSR
588 PINMUX_MOD_SELS
9e35d6fa 589 PINMUX_STATIC
f9aece73
TK		 590 PINMUX_MARK_END,
591#undef F_
592#undef FM
593};
594
595static const u16 pinmux_data[] = {
596 PINMUX_DATA_GP_ALL(),
597
598 PINMUX_SINGLE(AVS1),
599 PINMUX_SINGLE(AVS2),
600 PINMUX_SINGLE(CLKOUT),
601 PINMUX_SINGLE(GP7_03),
602 PINMUX_SINGLE(HDMI0_CEC),
603 PINMUX_SINGLE(MSIOF0_RXD),
604 PINMUX_SINGLE(MSIOF0_SCK),
605 PINMUX_SINGLE(MSIOF0_TXD),
606 PINMUX_SINGLE(SSI_SCK5),
607 PINMUX_SINGLE(SSI_SDATA5),
608 PINMUX_SINGLE(SSI_WS5),
609
610 /* IPSR0 */
611 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
612 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
613
614 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
615 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
616 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
617
618 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
619 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
620 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
621
622 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
623 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
624 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
625
626 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
627 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
628 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
629
630 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
631 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
632 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
633
634 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
635 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
636 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
637 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
638 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
639 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
640 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
641
642 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
643 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
644 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
645 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
646 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
647 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
648 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS1_E, SEL_MSIOF3_4),
649
650 /* IPSR1 */
651 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
652 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
653 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
654 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
655 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
656 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
657
658 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
659 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
660 PINMUX_IPSR_GPSR(IP1_7_4, A25),
661 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
662 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
663 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
664 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
665
666 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
667 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
668 PINMUX_IPSR_GPSR(IP1_11_8, A24),
669 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
670 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
671 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
672 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
673
674 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
675 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
676 PINMUX_IPSR_GPSR(IP1_15_12, A23),
677 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
678 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
679 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
680 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
681
682 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
683 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
684 PINMUX_IPSR_GPSR(IP1_19_16, A22),
685 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
686 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
689 PINMUX_IPSR_GPSR(IP1_23_20, A21),
690 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
691 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
692 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
693
694 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
695 PINMUX_IPSR_GPSR(IP1_27_24, A20),
696 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
697 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
698
699 PINMUX_IPSR_GPSR(IP1_31_28, A0),
700 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
701 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
702 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
703 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
704 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
705
706 /* IPSR2 */
707 PINMUX_IPSR_GPSR(IP2_3_0, A1),
708 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
709 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
710 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
711 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
712 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
713
714 PINMUX_IPSR_GPSR(IP2_7_4, A2),
715 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
716 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
717 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
718 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
719 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
720
721 PINMUX_IPSR_GPSR(IP2_11_8, A3),
722 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
723 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
724 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
725 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
726 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
727
728 PINMUX_IPSR_GPSR(IP2_15_12, A4),
729 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
730 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
731 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
732 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
733 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
734
735 PINMUX_IPSR_GPSR(IP2_19_16, A5),
736 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
737 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
738 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
739 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
740 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
741 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
742
743 PINMUX_IPSR_GPSR(IP2_23_20, A6),
744 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
745 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
746 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
747 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
748 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
749 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
750
751 PINMUX_IPSR_GPSR(IP2_27_24, A7),
752 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
753 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
754 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
755 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
756 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
757 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
758
759 PINMUX_IPSR_GPSR(IP2_31_28, A8),
760 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
761 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
762 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
763 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
764 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
765 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
766
767 /* IPSR3 */
768 PINMUX_IPSR_GPSR(IP3_3_0, A9),
769 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
770 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
771 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
772
773 PINMUX_IPSR_GPSR(IP3_7_4, A10),
774 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
775 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
776 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
777
778 PINMUX_IPSR_GPSR(IP3_11_8, A11),
779 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
780 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
781 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
782 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
783 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
784 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
785 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
786 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
787
788 PINMUX_IPSR_GPSR(IP3_15_12, A12),
789 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
790 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
791 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
792 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
793 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
794
795 PINMUX_IPSR_GPSR(IP3_19_16, A13),
796 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
797 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
798 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
799 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
800 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
801
802 PINMUX_IPSR_GPSR(IP3_23_20, A14),
803 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
804 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
805 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
806 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
807 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
808
809 PINMUX_IPSR_GPSR(IP3_27_24, A15),
810 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
811 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
812 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
813 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
814 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
815
816 PINMUX_IPSR_GPSR(IP3_31_28, A16),
817 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
818 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
819 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
820
821 /* IPSR4 */
822 PINMUX_IPSR_GPSR(IP4_3_0, A17),
823 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
824 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
825 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
826
827 PINMUX_IPSR_GPSR(IP4_7_4, A18),
828 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
829 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
830 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
831
832 PINMUX_IPSR_GPSR(IP4_11_8, A19),
833 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
834 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
835 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
836
837 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
838 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
839
840 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
841 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
842 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
843
844 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
845 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
846 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
847 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
848 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
849 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
850 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
851 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
852
853 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
854 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
855 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
856 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
857 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
858 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
859
860 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
861 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
862 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
863 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
864 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
865 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
866
867 /* IPSR5 */
868 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
869 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
870 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
871 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
872 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
873 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
874 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
875
876 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
877 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
878 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
879 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
880 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
881 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
882 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
883 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
884
885 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
886 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
887 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
888 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
889
890 PINMUX_IPSR_GPSR(IP5_15_12, D0),
891 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
892 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
894 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
895
896 PINMUX_IPSR_GPSR(IP5_19_16, D1),
897 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
898 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
899 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
900 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
901
902 PINMUX_IPSR_GPSR(IP5_23_20, D2),
903 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
904 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
905 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
906
907 PINMUX_IPSR_GPSR(IP5_27_24, D3),
908 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
909 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
910 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
911
912 PINMUX_IPSR_GPSR(IP5_31_28, D4),
913 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
915 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
916
917 /* IPSR6 */
918 PINMUX_IPSR_GPSR(IP6_3_0, D5),
919 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
920 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
921 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
922
923 PINMUX_IPSR_GPSR(IP6_7_4, D6),
924 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
925 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
926 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
927
928 PINMUX_IPSR_GPSR(IP6_11_8, D7),
929 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
930 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
931 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
932
933 PINMUX_IPSR_GPSR(IP6_15_12, D8),
934 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
935 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
936 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
937 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
938 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
939
940 PINMUX_IPSR_GPSR(IP6_19_16, D9),
941 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
942 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
943 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
944 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
945
946 PINMUX_IPSR_GPSR(IP6_23_20, D10),
947 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
948 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
949 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
950 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
951 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
952 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
953
954 PINMUX_IPSR_GPSR(IP6_27_24, D11),
955 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
956 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
957 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
958 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
959 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
960 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
961
962 PINMUX_IPSR_GPSR(IP6_31_28, D12),
963 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
964 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
965 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
966 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
967 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
968
969 /* IPSR7 */
970 PINMUX_IPSR_GPSR(IP7_3_0, D13),
971 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
972 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
973 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
974 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
975 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
976
977 PINMUX_IPSR_GPSR(IP7_7_4, D14),
978 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
979 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
980 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
981 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
982 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
983 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
984
985 PINMUX_IPSR_GPSR(IP7_11_8, D15),
986 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
987 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
988 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
989 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
990 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
991 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
992
993 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
994
995 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
996 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
998
999 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
1000 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
1001 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
1002
1003 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
1004 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
1005 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
1006 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
1007
1008 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
1009 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
1010 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
1011 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
1012
1013 /* IPSR8 */
1014 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1015 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1016 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1017 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1018
1019 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1020 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1021 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1022 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1023
1024 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1025 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1026 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1027
1028 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1029 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1030 PINMUX_IPSR_MSEL(IP8_15_12, NFCE_N_B, SEL_NDF_1),
1031 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1032 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1033
1034 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1035 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1036 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1037 PINMUX_IPSR_MSEL(IP8_19_16, NFWP_N_B, SEL_NDF_1),
1038 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1039 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1040
1041 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1042 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1043 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1044 PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
1045 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1046 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1047
1048 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1049 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1050 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1051 PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
1052 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1053 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1054
1055 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1056 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1057 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1058 PINMUX_IPSR_MSEL(IP8_31_28, NFRB_N_B, SEL_NDF_1),
1059 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1060 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1061
1062 /* IPSR9 */
1063 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1064 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1065
1066 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1067 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1068
1069 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1070 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1071
1072 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1073 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1074
1075 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1076 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1077
1078 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1079 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1080
1081 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1082 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1083
1084 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1085 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1086
1087 /* IPSR10 */
1088 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1089 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1090
1091 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1092 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1093
1094 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1095 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1096
1097 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1098 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1099
1100 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1101 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1102
1103 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1104 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1105 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1106
1107 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1108 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1109 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1110
1111 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1112 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1113 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1114
1115 /* IPSR11 */
1116 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1117 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1118 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1119
1120 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1121 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1122
1123 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1124 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1125 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1126
1127 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1128 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1129
1130 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1131 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1132
1133 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1134 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1135
1136 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1137 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1138 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1139 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1140 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1141 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1142 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1143 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1144 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1145 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1146
1147 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1148 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1149 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1150 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1151 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1152
1153 /* IPSR12 */
1154 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1155 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1156 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1157 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1158 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1159
1160 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1161 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1162 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1163 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1164 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1165 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1166 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1167 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1168
1169 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N_TANS),
1170 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1171 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1172 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1173 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1174 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1175 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1176 PINMUX_IPSR_MSEL(IP12_11_8, FSO_TOE_A, SEL_FSO_0),
1177 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1178
1179 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1181 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1182 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1183 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1184
1185 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1186 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1187 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1188 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1189 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1190
1191 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1192 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1193 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1194 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1195 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1196 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1197 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1198
1199 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N_TANS),
1200 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1201 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1202 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1203 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1204 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1205 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1206
1207 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1208 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1209 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1210 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1211 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1212 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1213 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1214
1215 /* IPSR13 */
1216 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1217 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1218 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1219 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1220 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1221 PINMUX_IPSR_MSEL(IP13_3_0, FSO_CFE_0_B, SEL_FSO_1),
1222
1223 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1224 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1225 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1226 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1227 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1228 PINMUX_IPSR_MSEL(IP13_7_4, FSO_CFE_1_B, SEL_FSO_1),
1229
1230 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1231 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1232 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
1233 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI_1),
1234 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1235 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1236 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1237 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1238
1239 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1240 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1241 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI_1),
1242 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1243 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1244 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1245
1246 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1247 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1248 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI_1),
1249 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1250 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1251 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1252
1253 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1254 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1255 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1256 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI_0),
1257 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1258 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1259 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1260 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1261
1262 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1263 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1264 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1265 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI_0),
1266 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1267 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1268 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1269
1270 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1271 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1272 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1273 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1274
1275 /* IPSR14 */
1276 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1277 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1278 PINMUX_IPSR_MSEL(IP14_3_0, NFWP_N_A, SEL_NDF_0),
1279 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
1280 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI_0),
1281 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1282 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1283 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1284
1285 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1286 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1287 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1288 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
1289 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI_0),
1290 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1291 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1292 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1293
1294 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1295 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1296 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1297
1298 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1299 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1300 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1301 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1302
1303 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1304 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1305 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1306
1307 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK0129),
1308 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1309
1310 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS0129),
1311 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1312
1313 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1314 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1315
1316 /* IPSR15 */
1317 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI_0),
1318
1319 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI_0),
1320 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI_1),
1321
1322 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK34),
1323 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1324 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1325
1326 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS34),
1327 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1330
1331 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1332 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1333 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1334 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1335 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1336 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1337 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1338
1339 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1340 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1341 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1342 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1343 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1344 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1345 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1346
1347 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1348 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1349 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1350 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1351 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1352 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1353 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1354
1355 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1356 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1357 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1358 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1359 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1360 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1361 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1362
1363 /* IPSR16 */
1364 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1365 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1366
1367 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1368 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1369
1370 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1371 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1372
1373 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1374 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1375 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1376 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1378 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1379 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1380
1381 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1382 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1383 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1384 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1386 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1387 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1388
1389 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1390 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1391 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1392 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1393 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1394 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1395 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1396 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1397
1398 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1399 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1400 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1401 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1402 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1403 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1404 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1405
1406 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI_0),
1407 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1408 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1409 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
1410 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI_1),
1411 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1412 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1413 PINMUX_IPSR_GPSR(IP16_31_28, SCK5_A),
1414
1415 /* IPSR17 */
1416 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1417 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1418
1419 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1420 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1421 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1422 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1423 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1424
1425 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1426 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1427 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1428 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1429 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1430 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1431 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1432
1433 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1434 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1435 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1436 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1437 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1438 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1439
1440 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1441 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1442 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI_0),
1443 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1444 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1445 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1446 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1447 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1448 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1449
1450 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1451 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1452 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI_0),
1453 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1454 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1455 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1456 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1457 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1458 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1459
1460 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1461 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
1462 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI_1),
1463 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1464 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1465 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1466 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1467 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1468 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1469 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1470 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1471
1472 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1473 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
1474 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI_1),
1475 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1476 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1477 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1479 PINMUX_IPSR_MSEL(IP17_31_28, FSO_TOE_B, SEL_FSO_1),
1480 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1481
1482 /* IPSR18 */
1483 PINMUX_IPSR_GPSR(IP18_3_0, GP6_30),
1484 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
1485 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI_1),
1486 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1487 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1490 PINMUX_IPSR_MSEL(IP18_3_0, FSO_CFE_0_A, SEL_FSO_0),
1491 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1492 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1493
1494 PINMUX_IPSR_GPSR(IP18_7_4, GP6_31),
1495 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
1496 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI_1),
1497 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1498 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1499 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1500 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1501 PINMUX_IPSR_MSEL(IP18_7_4, FSO_CFE_1_A, SEL_FSO_0),
1502 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1503 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1504
1505 /* I2C */
1506 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1507 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1508 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
9e35d6fa
NS		 1509
1510/*
1511 * Static pins can not be muxed between different functions but
1512 * still needs a mark entry in the pinmux list. Add each static
1513 * pin to the list without an associated function. The sh-pfc
1514 * core will do the right thing and skip trying to mux then pin
1515 * while still applying configuration to it
1516 */
1517#define FM(x) PINMUX_DATA(x##_MARK, 0),
1518 PINMUX_STATIC
1519#undef FM
f9aece73
TK		 1520};
1521
9e35d6fa
NS		 1522/*
1523 * R8A7796 has 8 banks with 32 GPIOs in each => 256 GPIOs.
1524 * Physical layout rows: A - AW, cols: 1 - 39.
1525 */
1526#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1527#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1528#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1529
f9aece73
TK		 1530static const struct sh_pfc_pin pinmux_pins[] = {
1531 PINMUX_GPIO_GP_ALL(),
9e35d6fa
NS		 1532
1533 /*
1534 * Pins not associated with a GPIO port.
1535 *
1536 * The pin positions are different between different r8a7796
1537 * packages, all that is needed for the pfc driver is a unique
1538 * number for each pin. To this end use the pin layout from
1539 * R-Car M3SiP to calculate a unique number for each pin.
1540 */
2d40bd24
NS		 1541 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
1556 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1563 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1564 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1568 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1569 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1570 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST, CFG_FLAGS),
1571 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1572 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1573 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1574 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1575 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1576 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN2, CFG_FLAGS),
1577 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1578 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1579 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1580 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
9e35d6fa 1581 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
2d40bd24 1582 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
f9aece73
TK		 1583};
1584
9c99a63e
TK		 1585/* - EtherAVB --------------------------------------------------------------- */
1586static const unsigned int avb_link_pins[] = {
1587 /* AVB_LINK */
1588 RCAR_GP_PIN(2, 12),
1589};
1590static const unsigned int avb_link_mux[] = {
1591 AVB_LINK_MARK,
1592};
1593static const unsigned int avb_magic_pins[] = {
1594 /* AVB_MAGIC_ */
1595 RCAR_GP_PIN(2, 10),
1596};
1597static const unsigned int avb_magic_mux[] = {
1598 AVB_MAGIC_MARK,
1599};
1600static const unsigned int avb_phy_int_pins[] = {
1601 /* AVB_PHY_INT */
1602 RCAR_GP_PIN(2, 11),
1603};
1604static const unsigned int avb_phy_int_mux[] = {
1605 AVB_PHY_INT_MARK,
1606};
1607static const unsigned int avb_mdc_pins[] = {
1608 /* AVB_MDC */
1609 RCAR_GP_PIN(2, 9),
1610};
1611static const unsigned int avb_mdc_mux[] = {
1612 AVB_MDC_MARK,
1613};
1614static const unsigned int avb_avtp_pps_pins[] = {
1615 /* AVB_AVTP_PPS */
1616 RCAR_GP_PIN(2, 6),
1617};
1618static const unsigned int avb_avtp_pps_mux[] = {
1619 AVB_AVTP_PPS_MARK,
1620};
1621static const unsigned int avb_avtp_match_a_pins[] = {
1622 /* AVB_AVTP_MATCH_A */
1623 RCAR_GP_PIN(2, 13),
1624};
1625static const unsigned int avb_avtp_match_a_mux[] = {
1626 AVB_AVTP_MATCH_A_MARK,
1627};
1628static const unsigned int avb_avtp_capture_a_pins[] = {
1629 /* AVB_AVTP_CAPTURE_A */
1630 RCAR_GP_PIN(2, 14),
1631};
1632static const unsigned int avb_avtp_capture_a_mux[] = {
1633 AVB_AVTP_CAPTURE_A_MARK,
1634};
1635static const unsigned int avb_avtp_match_b_pins[] = {
1636 /* AVB_AVTP_MATCH_B */
1637 RCAR_GP_PIN(1, 8),
1638};
1639static const unsigned int avb_avtp_match_b_mux[] = {
1640 AVB_AVTP_MATCH_B_MARK,
1641};
1642static const unsigned int avb_avtp_capture_b_pins[] = {
1643 /* AVB_AVTP_CAPTURE_B */
1644 RCAR_GP_PIN(1, 11),
1645};
1646static const unsigned int avb_avtp_capture_b_mux[] = {
1647 AVB_AVTP_CAPTURE_B_MARK,
1648};
1649
cf75341a
CP		 1650/* - CAN ------------------------------------------------------------------ */
1651static const unsigned int can0_data_a_pins[] = {
1652 /* TX, RX */
1653 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1654};
1655static const unsigned int can0_data_a_mux[] = {
1656 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1657};
1658static const unsigned int can0_data_b_pins[] = {
1659 /* TX, RX */
1660 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1661};
1662static const unsigned int can0_data_b_mux[] = {
1663 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1664};
1665static const unsigned int can1_data_pins[] = {
1666 /* TX, RX */
1667 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1668};
1669static const unsigned int can1_data_mux[] = {
1670 CAN1_TX_MARK, CAN1_RX_MARK,
1671};
1672
1673/* - CAN Clock -------------------------------------------------------------- */
1674static const unsigned int can_clk_pins[] = {
1675 /* CLK */
1676 RCAR_GP_PIN(1, 25),
1677};
1678static const unsigned int can_clk_mux[] = {
1679 CAN_CLK_MARK,
1680};
1681
3dc93dce
CP		 1682/* - CAN FD --------------------------------------------------------------- */
1683static const unsigned int canfd0_data_a_pins[] = {
1684 /* TX, RX */
1685 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1686};
1687static const unsigned int canfd0_data_a_mux[] = {
1688 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1689};
1690static const unsigned int canfd0_data_b_pins[] = {
1691 /* TX, RX */
1692 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1693};
1694static const unsigned int canfd0_data_b_mux[] = {
1695 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1696};
1697static const unsigned int canfd1_data_pins[] = {
1698 /* TX, RX */
1699 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1700};
1701static const unsigned int canfd1_data_mux[] = {
1702 CANFD1_TX_MARK, CANFD1_RX_MARK,
1703};
1704
fb082831
RS		 1705/* - DRIF0 --------------------------------------------------------------- */
1706static const unsigned int drif0_ctrl_a_pins[] = {
1707 /* CLK, SYNC */
1708 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1709};
1710static const unsigned int drif0_ctrl_a_mux[] = {
1711 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1712};
1713static const unsigned int drif0_data0_a_pins[] = {
1714 /* D0 */
1715 RCAR_GP_PIN(6, 10),
1716};
1717static const unsigned int drif0_data0_a_mux[] = {
1718 RIF0_D0_A_MARK,
1719};
1720static const unsigned int drif0_data1_a_pins[] = {
1721 /* D1 */
1722 RCAR_GP_PIN(6, 7),
1723};
1724static const unsigned int drif0_data1_a_mux[] = {
1725 RIF0_D1_A_MARK,
1726};
1727static const unsigned int drif0_ctrl_b_pins[] = {
1728 /* CLK, SYNC */
1729 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1730};
1731static const unsigned int drif0_ctrl_b_mux[] = {
1732 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1733};
1734static const unsigned int drif0_data0_b_pins[] = {
1735 /* D0 */
1736 RCAR_GP_PIN(5, 1),
1737};
1738static const unsigned int drif0_data0_b_mux[] = {
1739 RIF0_D0_B_MARK,
1740};
1741static const unsigned int drif0_data1_b_pins[] = {
1742 /* D1 */
1743 RCAR_GP_PIN(5, 2),
1744};
1745static const unsigned int drif0_data1_b_mux[] = {
1746 RIF0_D1_B_MARK,
1747};
1748static const unsigned int drif0_ctrl_c_pins[] = {
1749 /* CLK, SYNC */
1750 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1751};
1752static const unsigned int drif0_ctrl_c_mux[] = {
1753 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1754};
1755static const unsigned int drif0_data0_c_pins[] = {
1756 /* D0 */
1757 RCAR_GP_PIN(5, 13),
1758};
1759static const unsigned int drif0_data0_c_mux[] = {
1760 RIF0_D0_C_MARK,
1761};
1762static const unsigned int drif0_data1_c_pins[] = {
1763 /* D1 */
1764 RCAR_GP_PIN(5, 14),
1765};
1766static const unsigned int drif0_data1_c_mux[] = {
1767 RIF0_D1_C_MARK,
1768};
1769/* - DRIF1 --------------------------------------------------------------- */
1770static const unsigned int drif1_ctrl_a_pins[] = {
1771 /* CLK, SYNC */
1772 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1773};
1774static const unsigned int drif1_ctrl_a_mux[] = {
1775 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1776};
1777static const unsigned int drif1_data0_a_pins[] = {
1778 /* D0 */
1779 RCAR_GP_PIN(6, 19),
1780};
1781static const unsigned int drif1_data0_a_mux[] = {
1782 RIF1_D0_A_MARK,
1783};
1784static const unsigned int drif1_data1_a_pins[] = {
1785 /* D1 */
1786 RCAR_GP_PIN(6, 20),
1787};
1788static const unsigned int drif1_data1_a_mux[] = {
1789 RIF1_D1_A_MARK,
1790};
1791static const unsigned int drif1_ctrl_b_pins[] = {
1792 /* CLK, SYNC */
1793 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1794};
1795static const unsigned int drif1_ctrl_b_mux[] = {
1796 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1797};
1798static const unsigned int drif1_data0_b_pins[] = {
1799 /* D0 */
1800 RCAR_GP_PIN(5, 7),
1801};
1802static const unsigned int drif1_data0_b_mux[] = {
1803 RIF1_D0_B_MARK,
1804};
1805static const unsigned int drif1_data1_b_pins[] = {
1806 /* D1 */
1807 RCAR_GP_PIN(5, 8),
1808};
1809static const unsigned int drif1_data1_b_mux[] = {
1810 RIF1_D1_B_MARK,
1811};
1812static const unsigned int drif1_ctrl_c_pins[] = {
1813 /* CLK, SYNC */
1814 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1815};
1816static const unsigned int drif1_ctrl_c_mux[] = {
1817 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1818};
1819static const unsigned int drif1_data0_c_pins[] = {
1820 /* D0 */
1821 RCAR_GP_PIN(5, 6),
1822};
1823static const unsigned int drif1_data0_c_mux[] = {
1824 RIF1_D0_C_MARK,
1825};
1826static const unsigned int drif1_data1_c_pins[] = {
1827 /* D1 */
1828 RCAR_GP_PIN(5, 10),
1829};
1830static const unsigned int drif1_data1_c_mux[] = {
1831 RIF1_D1_C_MARK,
1832};
1833/* - DRIF2 --------------------------------------------------------------- */
1834static const unsigned int drif2_ctrl_a_pins[] = {
1835 /* CLK, SYNC */
1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1837};
1838static const unsigned int drif2_ctrl_a_mux[] = {
1839 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1840};
1841static const unsigned int drif2_data0_a_pins[] = {
1842 /* D0 */
1843 RCAR_GP_PIN(6, 7),
1844};
1845static const unsigned int drif2_data0_a_mux[] = {
1846 RIF2_D0_A_MARK,
1847};
1848static const unsigned int drif2_data1_a_pins[] = {
1849 /* D1 */
1850 RCAR_GP_PIN(6, 10),
1851};
1852static const unsigned int drif2_data1_a_mux[] = {
1853 RIF2_D1_A_MARK,
1854};
1855static const unsigned int drif2_ctrl_b_pins[] = {
1856 /* CLK, SYNC */
1857 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1858};
1859static const unsigned int drif2_ctrl_b_mux[] = {
1860 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1861};
1862static const unsigned int drif2_data0_b_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(6, 30),
1865};
1866static const unsigned int drif2_data0_b_mux[] = {
1867 RIF2_D0_B_MARK,
1868};
1869static const unsigned int drif2_data1_b_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(6, 31),
1872};
1873static const unsigned int drif2_data1_b_mux[] = {
1874 RIF2_D1_B_MARK,
1875};
1876/* - DRIF3 --------------------------------------------------------------- */
1877static const unsigned int drif3_ctrl_a_pins[] = {
1878 /* CLK, SYNC */
1879 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1880};
1881static const unsigned int drif3_ctrl_a_mux[] = {
1882 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
1883};
1884static const unsigned int drif3_data0_a_pins[] = {
1885 /* D0 */
1886 RCAR_GP_PIN(6, 19),
1887};
1888static const unsigned int drif3_data0_a_mux[] = {
1889 RIF3_D0_A_MARK,
1890};
1891static const unsigned int drif3_data1_a_pins[] = {
1892 /* D1 */
1893 RCAR_GP_PIN(6, 20),
1894};
1895static const unsigned int drif3_data1_a_mux[] = {
1896 RIF3_D1_A_MARK,
1897};
1898static const unsigned int drif3_ctrl_b_pins[] = {
1899 /* CLK, SYNC */
1900 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1901};
1902static const unsigned int drif3_ctrl_b_mux[] = {
1903 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
1904};
1905static const unsigned int drif3_data0_b_pins[] = {
1906 /* D0 */
1907 RCAR_GP_PIN(6, 28),
1908};
1909static const unsigned int drif3_data0_b_mux[] = {
1910 RIF3_D0_B_MARK,
1911};
1912static const unsigned int drif3_data1_b_pins[] = {
1913 /* D1 */
1914 RCAR_GP_PIN(6, 29),
1915};
1916static const unsigned int drif3_data1_b_mux[] = {
1917 RIF3_D1_B_MARK,
1918};
1919
cccc618a
NS		 1920/* - DU --------------------------------------------------------------------- */
1921static const unsigned int du_rgb666_pins[] = {
1922 /* R[7:2], G[7:2], B[7:2] */
1923 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1924 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1925 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1926 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1927 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1928 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1929};
1930static const unsigned int du_rgb666_mux[] = {
1931 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1932 DU_DR3_MARK, DU_DR2_MARK,
1933 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1934 DU_DG3_MARK, DU_DG2_MARK,
1935 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1936 DU_DB3_MARK, DU_DB2_MARK,
1937};
1938static const unsigned int du_rgb888_pins[] = {
1939 /* R[7:0], G[7:0], B[7:0] */
1940 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
1941 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
1942 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
1943 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
1944 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
1945 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
1946 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
1947 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
1948 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
1949};
1950static const unsigned int du_rgb888_mux[] = {
1951 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
1952 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
1953 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
1954 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
1955 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
1956 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
1957};
1958static const unsigned int du_clk_out_0_pins[] = {
1959 /* CLKOUT */
1960 RCAR_GP_PIN(1, 27),
1961};
1962static const unsigned int du_clk_out_0_mux[] = {
1963 DU_DOTCLKOUT0_MARK
1964};
1965static const unsigned int du_clk_out_1_pins[] = {
1966 /* CLKOUT */
1967 RCAR_GP_PIN(2, 3),
1968};
1969static const unsigned int du_clk_out_1_mux[] = {
1970 DU_DOTCLKOUT1_MARK
1971};
1972static const unsigned int du_sync_pins[] = {
1973 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
1974 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
1975};
1976static const unsigned int du_sync_mux[] = {
1977 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
1978};
1979static const unsigned int du_oddf_pins[] = {
1980 /* EXDISP/EXODDF/EXCDE */
1981 RCAR_GP_PIN(2, 2),
1982};
1983static const unsigned int du_oddf_mux[] = {
1984 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
1985};
1986static const unsigned int du_cde_pins[] = {
1987 /* CDE */
1988 RCAR_GP_PIN(2, 0),
1989};
1990static const unsigned int du_cde_mux[] = {
1991 DU_CDE_MARK,
1992};
1993static const unsigned int du_disp_pins[] = {
1994 /* DISP */
1995 RCAR_GP_PIN(2, 1),
1996};
1997static const unsigned int du_disp_mux[] = {
1998 DU_DISP_MARK,
1999};
2000
0e4e4999
UH		 2001/* - HSCIF0 ----------------------------------------------------------------- */
2002static const unsigned int hscif0_data_pins[] = {
2003 /* RX, TX */
2004 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2005};
2006static const unsigned int hscif0_data_mux[] = {
2007 HRX0_MARK, HTX0_MARK,
2008};
2009static const unsigned int hscif0_clk_pins[] = {
2010 /* SCK */
2011 RCAR_GP_PIN(5, 12),
2012};
2013static const unsigned int hscif0_clk_mux[] = {
2014 HSCK0_MARK,
2015};
2016static const unsigned int hscif0_ctrl_pins[] = {
2017 /* RTS, CTS */
2018 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2019};
2020static const unsigned int hscif0_ctrl_mux[] = {
2021 HRTS0_N_MARK, HCTS0_N_MARK,
2022};
2023/* - HSCIF1 ----------------------------------------------------------------- */
2024static const unsigned int hscif1_data_a_pins[] = {
2025 /* RX, TX */
2026 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2027};
2028static const unsigned int hscif1_data_a_mux[] = {
2029 HRX1_A_MARK, HTX1_A_MARK,
2030};
2031static const unsigned int hscif1_clk_a_pins[] = {
2032 /* SCK */
2033 RCAR_GP_PIN(6, 21),
2034};
2035static const unsigned int hscif1_clk_a_mux[] = {
2036 HSCK1_A_MARK,
2037};
2038static const unsigned int hscif1_ctrl_a_pins[] = {
2039 /* RTS, CTS */
2040 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2041};
2042static const unsigned int hscif1_ctrl_a_mux[] = {
2043 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2044};
2045
2046static const unsigned int hscif1_data_b_pins[] = {
2047 /* RX, TX */
2048 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2049};
2050static const unsigned int hscif1_data_b_mux[] = {
2051 HRX1_B_MARK, HTX1_B_MARK,
2052};
2053static const unsigned int hscif1_clk_b_pins[] = {
2054 /* SCK */
2055 RCAR_GP_PIN(5, 0),
2056};
2057static const unsigned int hscif1_clk_b_mux[] = {
2058 HSCK1_B_MARK,
2059};
2060static const unsigned int hscif1_ctrl_b_pins[] = {
2061 /* RTS, CTS */
2062 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2063};
2064static const unsigned int hscif1_ctrl_b_mux[] = {
2065 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2066};
2067/* - HSCIF2 ----------------------------------------------------------------- */
2068static const unsigned int hscif2_data_a_pins[] = {
2069 /* RX, TX */
2070 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2071};
2072static const unsigned int hscif2_data_a_mux[] = {
2073 HRX2_A_MARK, HTX2_A_MARK,
2074};
2075static const unsigned int hscif2_clk_a_pins[] = {
2076 /* SCK */
2077 RCAR_GP_PIN(6, 10),
2078};
2079static const unsigned int hscif2_clk_a_mux[] = {
2080 HSCK2_A_MARK,
2081};
2082static const unsigned int hscif2_ctrl_a_pins[] = {
2083 /* RTS, CTS */
2084 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2085};
2086static const unsigned int hscif2_ctrl_a_mux[] = {
2087 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2088};
2089
2090static const unsigned int hscif2_data_b_pins[] = {
2091 /* RX, TX */
2092 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2093};
2094static const unsigned int hscif2_data_b_mux[] = {
2095 HRX2_B_MARK, HTX2_B_MARK,
2096};
2097static const unsigned int hscif2_clk_b_pins[] = {
2098 /* SCK */
2099 RCAR_GP_PIN(6, 21),
2100};
2101static const unsigned int hscif2_clk_b_mux[] = {
2102 HSCK2_B_MARK,
2103};
2104static const unsigned int hscif2_ctrl_b_pins[] = {
2105 /* RTS, CTS */
2106 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2107};
2108static const unsigned int hscif2_ctrl_b_mux[] = {
2109 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2110};
2111
2112static const unsigned int hscif2_data_c_pins[] = {
2113 /* RX, TX */
2114 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2115};
2116static const unsigned int hscif2_data_c_mux[] = {
2117 HRX2_C_MARK, HTX2_C_MARK,
2118};
2119static const unsigned int hscif2_clk_c_pins[] = {
2120 /* SCK */
2121 RCAR_GP_PIN(6, 24),
2122};
2123static const unsigned int hscif2_clk_c_mux[] = {
2124 HSCK2_C_MARK,
2125};
2126static const unsigned int hscif2_ctrl_c_pins[] = {
2127 /* RTS, CTS */
2128 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2129};
2130static const unsigned int hscif2_ctrl_c_mux[] = {
2131 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2132};
2133/* - HSCIF3 ----------------------------------------------------------------- */
2134static const unsigned int hscif3_data_a_pins[] = {
2135 /* RX, TX */
2136 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2137};
2138static const unsigned int hscif3_data_a_mux[] = {
2139 HRX3_A_MARK, HTX3_A_MARK,
2140};
2141static const unsigned int hscif3_clk_pins[] = {
2142 /* SCK */
2143 RCAR_GP_PIN(1, 22),
2144};
2145static const unsigned int hscif3_clk_mux[] = {
2146 HSCK3_MARK,
2147};
2148static const unsigned int hscif3_ctrl_pins[] = {
2149 /* RTS, CTS */
2150 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2151};
2152static const unsigned int hscif3_ctrl_mux[] = {
2153 HRTS3_N_MARK, HCTS3_N_MARK,
2154};
2155
2156static const unsigned int hscif3_data_b_pins[] = {
2157 /* RX, TX */
2158 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2159};
2160static const unsigned int hscif3_data_b_mux[] = {
2161 HRX3_B_MARK, HTX3_B_MARK,
2162};
2163static const unsigned int hscif3_data_c_pins[] = {
2164 /* RX, TX */
2165 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2166};
2167static const unsigned int hscif3_data_c_mux[] = {
2168 HRX3_C_MARK, HTX3_C_MARK,
2169};
2170static const unsigned int hscif3_data_d_pins[] = {
2171 /* RX, TX */
2172 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2173};
2174static const unsigned int hscif3_data_d_mux[] = {
2175 HRX3_D_MARK, HTX3_D_MARK,
2176};
2177/* - HSCIF4 ----------------------------------------------------------------- */
2178static const unsigned int hscif4_data_a_pins[] = {
2179 /* RX, TX */
2180 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2181};
2182static const unsigned int hscif4_data_a_mux[] = {
2183 HRX4_A_MARK, HTX4_A_MARK,
2184};
2185static const unsigned int hscif4_clk_pins[] = {
2186 /* SCK */
2187 RCAR_GP_PIN(1, 11),
2188};
2189static const unsigned int hscif4_clk_mux[] = {
2190 HSCK4_MARK,
2191};
2192static const unsigned int hscif4_ctrl_pins[] = {
2193 /* RTS, CTS */
2194 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2195};
2196static const unsigned int hscif4_ctrl_mux[] = {
2197 HRTS4_N_MARK, HCTS4_N_MARK,
2198};
2199
2200static const unsigned int hscif4_data_b_pins[] = {
2201 /* RX, TX */
2202 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2203};
2204static const unsigned int hscif4_data_b_mux[] = {
2205 HRX4_B_MARK, HTX4_B_MARK,
2206};
2207
02609a23
UH		 2208/* - I2C -------------------------------------------------------------------- */
2209static const unsigned int i2c1_a_pins[] = {
2210 /* SDA, SCL */
2211 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2212};
2213static const unsigned int i2c1_a_mux[] = {
2214 SDA1_A_MARK, SCL1_A_MARK,
2215};
2216static const unsigned int i2c1_b_pins[] = {
2217 /* SDA, SCL */
2218 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2219};
2220static const unsigned int i2c1_b_mux[] = {
2221 SDA1_B_MARK, SCL1_B_MARK,
2222};
2223static const unsigned int i2c2_a_pins[] = {
2224 /* SDA, SCL */
2225 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2226};
2227static const unsigned int i2c2_a_mux[] = {
2228 SDA2_A_MARK, SCL2_A_MARK,
2229};
2230static const unsigned int i2c2_b_pins[] = {
2231 /* SDA, SCL */
2232 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2233};
2234static const unsigned int i2c2_b_mux[] = {
2235 SDA2_B_MARK, SCL2_B_MARK,
2236};
2237static const unsigned int i2c6_a_pins[] = {
2238 /* SDA, SCL */
2239 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2240};
2241static const unsigned int i2c6_a_mux[] = {
2242 SDA6_A_MARK, SCL6_A_MARK,
2243};
2244static const unsigned int i2c6_b_pins[] = {
2245 /* SDA, SCL */
2246 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2247};
2248static const unsigned int i2c6_b_mux[] = {
2249 SDA6_B_MARK, SCL6_B_MARK,
2250};
2251static const unsigned int i2c6_c_pins[] = {
2252 /* SDA, SCL */
2253 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2254};
2255static const unsigned int i2c6_c_mux[] = {
2256 SDA6_C_MARK, SCL6_C_MARK,
2257};
2258
4753231c
TK		 2259/* - MSIOF0 ----------------------------------------------------------------- */
2260static const unsigned int msiof0_clk_pins[] = {
2261 /* SCK */
2262 RCAR_GP_PIN(5, 17),
2263};
2264static const unsigned int msiof0_clk_mux[] = {
2265 MSIOF0_SCK_MARK,
2266};
2267static const unsigned int msiof0_sync_pins[] = {
2268 /* SYNC */
2269 RCAR_GP_PIN(5, 18),
2270};
2271static const unsigned int msiof0_sync_mux[] = {
2272 MSIOF0_SYNC_MARK,
2273};
2274static const unsigned int msiof0_ss1_pins[] = {
2275 /* SS1 */
2276 RCAR_GP_PIN(5, 19),
2277};
2278static const unsigned int msiof0_ss1_mux[] = {
2279 MSIOF0_SS1_MARK,
2280};
2281static const unsigned int msiof0_ss2_pins[] = {
2282 /* SS2 */
2283 RCAR_GP_PIN(5, 21),
2284};
2285static const unsigned int msiof0_ss2_mux[] = {
2286 MSIOF0_SS2_MARK,
2287};
2288static const unsigned int msiof0_txd_pins[] = {
2289 /* TXD */
2290 RCAR_GP_PIN(5, 20),
2291};
2292static const unsigned int msiof0_txd_mux[] = {
2293 MSIOF0_TXD_MARK,
2294};
2295static const unsigned int msiof0_rxd_pins[] = {
2296 /* RXD */
2297 RCAR_GP_PIN(5, 22),
2298};
2299static const unsigned int msiof0_rxd_mux[] = {
2300 MSIOF0_RXD_MARK,
2301};
2302/* - MSIOF1 ----------------------------------------------------------------- */
2303static const unsigned int msiof1_clk_a_pins[] = {
2304 /* SCK */
2305 RCAR_GP_PIN(6, 8),
2306};
2307static const unsigned int msiof1_clk_a_mux[] = {
2308 MSIOF1_SCK_A_MARK,
2309};
2310static const unsigned int msiof1_sync_a_pins[] = {
2311 /* SYNC */
2312 RCAR_GP_PIN(6, 9),
2313};
2314static const unsigned int msiof1_sync_a_mux[] = {
2315 MSIOF1_SYNC_A_MARK,
2316};
2317static const unsigned int msiof1_ss1_a_pins[] = {
2318 /* SS1 */
2319 RCAR_GP_PIN(6, 5),
2320};
2321static const unsigned int msiof1_ss1_a_mux[] = {
2322 MSIOF1_SS1_A_MARK,
2323};
2324static const unsigned int msiof1_ss2_a_pins[] = {
2325 /* SS2 */
2326 RCAR_GP_PIN(6, 6),
2327};
2328static const unsigned int msiof1_ss2_a_mux[] = {
2329 MSIOF1_SS2_A_MARK,
2330};
2331static const unsigned int msiof1_txd_a_pins[] = {
2332 /* TXD */
2333 RCAR_GP_PIN(6, 7),
2334};
2335static const unsigned int msiof1_txd_a_mux[] = {
2336 MSIOF1_TXD_A_MARK,
2337};
2338static const unsigned int msiof1_rxd_a_pins[] = {
2339 /* RXD */
2340 RCAR_GP_PIN(6, 10),
2341};
2342static const unsigned int msiof1_rxd_a_mux[] = {
2343 MSIOF1_RXD_A_MARK,
2344};
2345static const unsigned int msiof1_clk_b_pins[] = {
2346 /* SCK */
2347 RCAR_GP_PIN(5, 9),
2348};
2349static const unsigned int msiof1_clk_b_mux[] = {
2350 MSIOF1_SCK_B_MARK,
2351};
2352static const unsigned int msiof1_sync_b_pins[] = {
2353 /* SYNC */
2354 RCAR_GP_PIN(5, 3),
2355};
2356static const unsigned int msiof1_sync_b_mux[] = {
2357 MSIOF1_SYNC_B_MARK,
2358};
2359static const unsigned int msiof1_ss1_b_pins[] = {
2360 /* SS1 */
2361 RCAR_GP_PIN(5, 4),
2362};
2363static const unsigned int msiof1_ss1_b_mux[] = {
2364 MSIOF1_SS1_B_MARK,
2365};
2366static const unsigned int msiof1_ss2_b_pins[] = {
2367 /* SS2 */
2368 RCAR_GP_PIN(5, 0),
2369};
2370static const unsigned int msiof1_ss2_b_mux[] = {
2371 MSIOF1_SS2_B_MARK,
2372};
2373static const unsigned int msiof1_txd_b_pins[] = {
2374 /* TXD */
2375 RCAR_GP_PIN(5, 8),
2376};
2377static const unsigned int msiof1_txd_b_mux[] = {
2378 MSIOF1_TXD_B_MARK,
2379};
2380static const unsigned int msiof1_rxd_b_pins[] = {
2381 /* RXD */
2382 RCAR_GP_PIN(5, 7),
2383};
2384static const unsigned int msiof1_rxd_b_mux[] = {
2385 MSIOF1_RXD_B_MARK,
2386};
2387static const unsigned int msiof1_clk_c_pins[] = {
2388 /* SCK */
2389 RCAR_GP_PIN(6, 17),
2390};
2391static const unsigned int msiof1_clk_c_mux[] = {
2392 MSIOF1_SCK_C_MARK,
2393};
2394static const unsigned int msiof1_sync_c_pins[] = {
2395 /* SYNC */
2396 RCAR_GP_PIN(6, 18),
2397};
2398static const unsigned int msiof1_sync_c_mux[] = {
2399 MSIOF1_SYNC_C_MARK,
2400};
2401static const unsigned int msiof1_ss1_c_pins[] = {
2402 /* SS1 */
2403 RCAR_GP_PIN(6, 21),
2404};
2405static const unsigned int msiof1_ss1_c_mux[] = {
2406 MSIOF1_SS1_C_MARK,
2407};
2408static const unsigned int msiof1_ss2_c_pins[] = {
2409 /* SS2 */
2410 RCAR_GP_PIN(6, 27),
2411};
2412static const unsigned int msiof1_ss2_c_mux[] = {
2413 MSIOF1_SS2_C_MARK,
2414};
2415static const unsigned int msiof1_txd_c_pins[] = {
2416 /* TXD */
2417 RCAR_GP_PIN(6, 20),
2418};
2419static const unsigned int msiof1_txd_c_mux[] = {
2420 MSIOF1_TXD_C_MARK,
2421};
2422static const unsigned int msiof1_rxd_c_pins[] = {
2423 /* RXD */
2424 RCAR_GP_PIN(6, 19),
2425};
2426static const unsigned int msiof1_rxd_c_mux[] = {
2427 MSIOF1_RXD_C_MARK,
2428};
2429static const unsigned int msiof1_clk_d_pins[] = {
2430 /* SCK */
2431 RCAR_GP_PIN(5, 12),
2432};
2433static const unsigned int msiof1_clk_d_mux[] = {
2434 MSIOF1_SCK_D_MARK,
2435};
2436static const unsigned int msiof1_sync_d_pins[] = {
2437 /* SYNC */
2438 RCAR_GP_PIN(5, 15),
2439};
2440static const unsigned int msiof1_sync_d_mux[] = {
2441 MSIOF1_SYNC_D_MARK,
2442};
2443static const unsigned int msiof1_ss1_d_pins[] = {
2444 /* SS1 */
2445 RCAR_GP_PIN(5, 16),
2446};
2447static const unsigned int msiof1_ss1_d_mux[] = {
2448 MSIOF1_SS1_D_MARK,
2449};
2450static const unsigned int msiof1_ss2_d_pins[] = {
2451 /* SS2 */
2452 RCAR_GP_PIN(5, 21),
2453};
2454static const unsigned int msiof1_ss2_d_mux[] = {
2455 MSIOF1_SS2_D_MARK,
2456};
2457static const unsigned int msiof1_txd_d_pins[] = {
2458 /* TXD */
2459 RCAR_GP_PIN(5, 14),
2460};
2461static const unsigned int msiof1_txd_d_mux[] = {
2462 MSIOF1_TXD_D_MARK,
2463};
2464static const unsigned int msiof1_rxd_d_pins[] = {
2465 /* RXD */
2466 RCAR_GP_PIN(5, 13),
2467};
2468static const unsigned int msiof1_rxd_d_mux[] = {
2469 MSIOF1_RXD_D_MARK,
2470};
2471static const unsigned int msiof1_clk_e_pins[] = {
2472 /* SCK */
2473 RCAR_GP_PIN(3, 0),
2474};
2475static const unsigned int msiof1_clk_e_mux[] = {
2476 MSIOF1_SCK_E_MARK,
2477};
2478static const unsigned int msiof1_sync_e_pins[] = {
2479 /* SYNC */
2480 RCAR_GP_PIN(3, 1),
2481};
2482static const unsigned int msiof1_sync_e_mux[] = {
2483 MSIOF1_SYNC_E_MARK,
2484};
2485static const unsigned int msiof1_ss1_e_pins[] = {
2486 /* SS1 */
2487 RCAR_GP_PIN(3, 4),
2488};
2489static const unsigned int msiof1_ss1_e_mux[] = {
2490 MSIOF1_SS1_E_MARK,
2491};
2492static const unsigned int msiof1_ss2_e_pins[] = {
2493 /* SS2 */
2494 RCAR_GP_PIN(3, 5),
2495};
2496static const unsigned int msiof1_ss2_e_mux[] = {
2497 MSIOF1_SS2_E_MARK,
2498};
2499static const unsigned int msiof1_txd_e_pins[] = {
2500 /* TXD */
2501 RCAR_GP_PIN(3, 3),
2502};
2503static const unsigned int msiof1_txd_e_mux[] = {
2504 MSIOF1_TXD_E_MARK,
2505};
2506static const unsigned int msiof1_rxd_e_pins[] = {
2507 /* RXD */
2508 RCAR_GP_PIN(3, 2),
2509};
2510static const unsigned int msiof1_rxd_e_mux[] = {
2511 MSIOF1_RXD_E_MARK,
2512};
2513static const unsigned int msiof1_clk_f_pins[] = {
2514 /* SCK */
2515 RCAR_GP_PIN(5, 23),
2516};
2517static const unsigned int msiof1_clk_f_mux[] = {
2518 MSIOF1_SCK_F_MARK,
2519};
2520static const unsigned int msiof1_sync_f_pins[] = {
2521 /* SYNC */
2522 RCAR_GP_PIN(5, 24),
2523};
2524static const unsigned int msiof1_sync_f_mux[] = {
2525 MSIOF1_SYNC_F_MARK,
2526};
2527static const unsigned int msiof1_ss1_f_pins[] = {
2528 /* SS1 */
2529 RCAR_GP_PIN(6, 1),
2530};
2531static const unsigned int msiof1_ss1_f_mux[] = {
2532 MSIOF1_SS1_F_MARK,
2533};
2534static const unsigned int msiof1_ss2_f_pins[] = {
2535 /* SS2 */
2536 RCAR_GP_PIN(6, 2),
2537};
2538static const unsigned int msiof1_ss2_f_mux[] = {
2539 MSIOF1_SS2_F_MARK,
2540};
2541static const unsigned int msiof1_txd_f_pins[] = {
2542 /* TXD */
2543 RCAR_GP_PIN(6, 0),
2544};
2545static const unsigned int msiof1_txd_f_mux[] = {
2546 MSIOF1_TXD_F_MARK,
2547};
2548static const unsigned int msiof1_rxd_f_pins[] = {
2549 /* RXD */
2550 RCAR_GP_PIN(5, 25),
2551};
2552static const unsigned int msiof1_rxd_f_mux[] = {
2553 MSIOF1_RXD_F_MARK,
2554};
2555static const unsigned int msiof1_clk_g_pins[] = {
2556 /* SCK */
2557 RCAR_GP_PIN(3, 6),
2558};
2559static const unsigned int msiof1_clk_g_mux[] = {
2560 MSIOF1_SCK_G_MARK,
2561};
2562static const unsigned int msiof1_sync_g_pins[] = {
2563 /* SYNC */
2564 RCAR_GP_PIN(3, 7),
2565};
2566static const unsigned int msiof1_sync_g_mux[] = {
2567 MSIOF1_SYNC_G_MARK,
2568};
2569static const unsigned int msiof1_ss1_g_pins[] = {
2570 /* SS1 */
2571 RCAR_GP_PIN(3, 10),
2572};
2573static const unsigned int msiof1_ss1_g_mux[] = {
2574 MSIOF1_SS1_G_MARK,
2575};
2576static const unsigned int msiof1_ss2_g_pins[] = {
2577 /* SS2 */
2578 RCAR_GP_PIN(3, 11),
2579};
2580static const unsigned int msiof1_ss2_g_mux[] = {
2581 MSIOF1_SS2_G_MARK,
2582};
2583static const unsigned int msiof1_txd_g_pins[] = {
2584 /* TXD */
2585 RCAR_GP_PIN(3, 9),
2586};
2587static const unsigned int msiof1_txd_g_mux[] = {
2588 MSIOF1_TXD_G_MARK,
2589};
2590static const unsigned int msiof1_rxd_g_pins[] = {
2591 /* RXD */
2592 RCAR_GP_PIN(3, 8),
2593};
2594static const unsigned int msiof1_rxd_g_mux[] = {
2595 MSIOF1_RXD_G_MARK,
2596};
2597/* - MSIOF2 ----------------------------------------------------------------- */
2598static const unsigned int msiof2_clk_a_pins[] = {
2599 /* SCK */
2600 RCAR_GP_PIN(1, 9),
2601};
2602static const unsigned int msiof2_clk_a_mux[] = {
2603 MSIOF2_SCK_A_MARK,
2604};
2605static const unsigned int msiof2_sync_a_pins[] = {
2606 /* SYNC */
2607 RCAR_GP_PIN(1, 8),
2608};
2609static const unsigned int msiof2_sync_a_mux[] = {
2610 MSIOF2_SYNC_A_MARK,
2611};
2612static const unsigned int msiof2_ss1_a_pins[] = {
2613 /* SS1 */
2614 RCAR_GP_PIN(1, 6),
2615};
2616static const unsigned int msiof2_ss1_a_mux[] = {
2617 MSIOF2_SS1_A_MARK,
2618};
2619static const unsigned int msiof2_ss2_a_pins[] = {
2620 /* SS2 */
2621 RCAR_GP_PIN(1, 7),
2622};
2623static const unsigned int msiof2_ss2_a_mux[] = {
2624 MSIOF2_SS2_A_MARK,
2625};
2626static const unsigned int msiof2_txd_a_pins[] = {
2627 /* TXD */
2628 RCAR_GP_PIN(1, 11),
2629};
2630static const unsigned int msiof2_txd_a_mux[] = {
2631 MSIOF2_TXD_A_MARK,
2632};
2633static const unsigned int msiof2_rxd_a_pins[] = {
2634 /* RXD */
2635 RCAR_GP_PIN(1, 10),
2636};
2637static const unsigned int msiof2_rxd_a_mux[] = {
2638 MSIOF2_RXD_A_MARK,
2639};
2640static const unsigned int msiof2_clk_b_pins[] = {
2641 /* SCK */
2642 RCAR_GP_PIN(0, 4),
2643};
2644static const unsigned int msiof2_clk_b_mux[] = {
2645 MSIOF2_SCK_B_MARK,
2646};
2647static const unsigned int msiof2_sync_b_pins[] = {
2648 /* SYNC */
2649 RCAR_GP_PIN(0, 5),
2650};
2651static const unsigned int msiof2_sync_b_mux[] = {
2652 MSIOF2_SYNC_B_MARK,
2653};
2654static const unsigned int msiof2_ss1_b_pins[] = {
2655 /* SS1 */
2656 RCAR_GP_PIN(0, 0),
2657};
2658static const unsigned int msiof2_ss1_b_mux[] = {
2659 MSIOF2_SS1_B_MARK,
2660};
2661static const unsigned int msiof2_ss2_b_pins[] = {
2662 /* SS2 */
2663 RCAR_GP_PIN(0, 1),
2664};
2665static const unsigned int msiof2_ss2_b_mux[] = {
2666 MSIOF2_SS2_B_MARK,
2667};
2668static const unsigned int msiof2_txd_b_pins[] = {
2669 /* TXD */
2670 RCAR_GP_PIN(0, 7),
2671};
2672static const unsigned int msiof2_txd_b_mux[] = {
2673 MSIOF2_TXD_B_MARK,
2674};
2675static const unsigned int msiof2_rxd_b_pins[] = {
2676 /* RXD */
2677 RCAR_GP_PIN(0, 6),
2678};
2679static const unsigned int msiof2_rxd_b_mux[] = {
2680 MSIOF2_RXD_B_MARK,
2681};
2682static const unsigned int msiof2_clk_c_pins[] = {
2683 /* SCK */
2684 RCAR_GP_PIN(2, 12),
2685};
2686static const unsigned int msiof2_clk_c_mux[] = {
2687 MSIOF2_SCK_C_MARK,
2688};
2689static const unsigned int msiof2_sync_c_pins[] = {
2690 /* SYNC */
2691 RCAR_GP_PIN(2, 11),
2692};
2693static const unsigned int msiof2_sync_c_mux[] = {
2694 MSIOF2_SYNC_C_MARK,
2695};
2696static const unsigned int msiof2_ss1_c_pins[] = {
2697 /* SS1 */
2698 RCAR_GP_PIN(2, 10),
2699};
2700static const unsigned int msiof2_ss1_c_mux[] = {
2701 MSIOF2_SS1_C_MARK,
2702};
2703static const unsigned int msiof2_ss2_c_pins[] = {
2704 /* SS2 */
2705 RCAR_GP_PIN(2, 9),
2706};
2707static const unsigned int msiof2_ss2_c_mux[] = {
2708 MSIOF2_SS2_C_MARK,
2709};
2710static const unsigned int msiof2_txd_c_pins[] = {
2711 /* TXD */
2712 RCAR_GP_PIN(2, 14),
2713};
2714static const unsigned int msiof2_txd_c_mux[] = {
2715 MSIOF2_TXD_C_MARK,
2716};
2717static const unsigned int msiof2_rxd_c_pins[] = {
2718 /* RXD */
2719 RCAR_GP_PIN(2, 13),
2720};
2721static const unsigned int msiof2_rxd_c_mux[] = {
2722 MSIOF2_RXD_C_MARK,
2723};
2724static const unsigned int msiof2_clk_d_pins[] = {
2725 /* SCK */
2726 RCAR_GP_PIN(0, 8),
2727};
2728static const unsigned int msiof2_clk_d_mux[] = {
2729 MSIOF2_SCK_D_MARK,
2730};
2731static const unsigned int msiof2_sync_d_pins[] = {
2732 /* SYNC */
2733 RCAR_GP_PIN(0, 9),
2734};
2735static const unsigned int msiof2_sync_d_mux[] = {
2736 MSIOF2_SYNC_D_MARK,
2737};
2738static const unsigned int msiof2_ss1_d_pins[] = {
2739 /* SS1 */
2740 RCAR_GP_PIN(0, 12),
2741};
2742static const unsigned int msiof2_ss1_d_mux[] = {
2743 MSIOF2_SS1_D_MARK,
2744};
2745static const unsigned int msiof2_ss2_d_pins[] = {
2746 /* SS2 */
2747 RCAR_GP_PIN(0, 13),
2748};
2749static const unsigned int msiof2_ss2_d_mux[] = {
2750 MSIOF2_SS2_D_MARK,
2751};
2752static const unsigned int msiof2_txd_d_pins[] = {
2753 /* TXD */
2754 RCAR_GP_PIN(0, 11),
2755};
2756static const unsigned int msiof2_txd_d_mux[] = {
2757 MSIOF2_TXD_D_MARK,
2758};
2759static const unsigned int msiof2_rxd_d_pins[] = {
2760 /* RXD */
2761 RCAR_GP_PIN(0, 10),
2762};
2763static const unsigned int msiof2_rxd_d_mux[] = {
2764 MSIOF2_RXD_D_MARK,
2765};
2766/* - MSIOF3 ----------------------------------------------------------------- */
2767static const unsigned int msiof3_clk_a_pins[] = {
2768 /* SCK */
2769 RCAR_GP_PIN(0, 0),
2770};
2771static const unsigned int msiof3_clk_a_mux[] = {
2772 MSIOF3_SCK_A_MARK,
2773};
2774static const unsigned int msiof3_sync_a_pins[] = {
2775 /* SYNC */
2776 RCAR_GP_PIN(0, 1),
2777};
2778static const unsigned int msiof3_sync_a_mux[] = {
2779 MSIOF3_SYNC_A_MARK,
2780};
2781static const unsigned int msiof3_ss1_a_pins[] = {
2782 /* SS1 */
2783 RCAR_GP_PIN(0, 14),
2784};
2785static const unsigned int msiof3_ss1_a_mux[] = {
2786 MSIOF3_SS1_A_MARK,
2787};
2788static const unsigned int msiof3_ss2_a_pins[] = {
2789 /* SS2 */
2790 RCAR_GP_PIN(0, 15),
2791};
2792static const unsigned int msiof3_ss2_a_mux[] = {
2793 MSIOF3_SS2_A_MARK,
2794};
2795static const unsigned int msiof3_txd_a_pins[] = {
2796 /* TXD */
2797 RCAR_GP_PIN(0, 3),
2798};
2799static const unsigned int msiof3_txd_a_mux[] = {
2800 MSIOF3_TXD_A_MARK,
2801};
2802static const unsigned int msiof3_rxd_a_pins[] = {
2803 /* RXD */
2804 RCAR_GP_PIN(0, 2),
2805};
2806static const unsigned int msiof3_rxd_a_mux[] = {
2807 MSIOF3_RXD_A_MARK,
2808};
2809static const unsigned int msiof3_clk_b_pins[] = {
2810 /* SCK */
2811 RCAR_GP_PIN(1, 2),
2812};
2813static const unsigned int msiof3_clk_b_mux[] = {
2814 MSIOF3_SCK_B_MARK,
2815};
2816static const unsigned int msiof3_sync_b_pins[] = {
2817 /* SYNC */
2818 RCAR_GP_PIN(1, 0),
2819};
2820static const unsigned int msiof3_sync_b_mux[] = {
2821 MSIOF3_SYNC_B_MARK,
2822};
2823static const unsigned int msiof3_ss1_b_pins[] = {
2824 /* SS1 */
2825 RCAR_GP_PIN(1, 4),
2826};
2827static const unsigned int msiof3_ss1_b_mux[] = {
2828 MSIOF3_SS1_B_MARK,
2829};
2830static const unsigned int msiof3_ss2_b_pins[] = {
2831 /* SS2 */
2832 RCAR_GP_PIN(1, 5),
2833};
2834static const unsigned int msiof3_ss2_b_mux[] = {
2835 MSIOF3_SS2_B_MARK,
2836};
2837static const unsigned int msiof3_txd_b_pins[] = {
2838 /* TXD */
2839 RCAR_GP_PIN(1, 1),
2840};
2841static const unsigned int msiof3_txd_b_mux[] = {
2842 MSIOF3_TXD_B_MARK,
2843};
2844static const unsigned int msiof3_rxd_b_pins[] = {
2845 /* RXD */
2846 RCAR_GP_PIN(1, 3),
2847};
2848static const unsigned int msiof3_rxd_b_mux[] = {
2849 MSIOF3_RXD_B_MARK,
2850};
2851static const unsigned int msiof3_clk_c_pins[] = {
2852 /* SCK */
2853 RCAR_GP_PIN(1, 12),
2854};
2855static const unsigned int msiof3_clk_c_mux[] = {
2856 MSIOF3_SCK_C_MARK,
2857};
2858static const unsigned int msiof3_sync_c_pins[] = {
2859 /* SYNC */
2860 RCAR_GP_PIN(1, 13),
2861};
2862static const unsigned int msiof3_sync_c_mux[] = {
2863 MSIOF3_SYNC_C_MARK,
2864};
2865static const unsigned int msiof3_txd_c_pins[] = {
2866 /* TXD */
2867 RCAR_GP_PIN(1, 15),
2868};
2869static const unsigned int msiof3_txd_c_mux[] = {
2870 MSIOF3_TXD_C_MARK,
2871};
2872static const unsigned int msiof3_rxd_c_pins[] = {
2873 /* RXD */
2874 RCAR_GP_PIN(1, 14),
2875};
2876static const unsigned int msiof3_rxd_c_mux[] = {
2877 MSIOF3_RXD_C_MARK,
2878};
2879static const unsigned int msiof3_clk_d_pins[] = {
2880 /* SCK */
2881 RCAR_GP_PIN(1, 22),
2882};
2883static const unsigned int msiof3_clk_d_mux[] = {
2884 MSIOF3_SCK_D_MARK,
2885};
2886static const unsigned int msiof3_sync_d_pins[] = {
2887 /* SYNC */
2888 RCAR_GP_PIN(1, 23),
2889};
2890static const unsigned int msiof3_sync_d_mux[] = {
2891 MSIOF3_SYNC_D_MARK,
2892};
2893static const unsigned int msiof3_ss1_d_pins[] = {
2894 /* SS1 */
2895 RCAR_GP_PIN(1, 26),
2896};
2897static const unsigned int msiof3_ss1_d_mux[] = {
2898 MSIOF3_SS1_D_MARK,
2899};
2900static const unsigned int msiof3_txd_d_pins[] = {
2901 /* TXD */
2902 RCAR_GP_PIN(1, 25),
2903};
2904static const unsigned int msiof3_txd_d_mux[] = {
2905 MSIOF3_TXD_D_MARK,
2906};
2907static const unsigned int msiof3_rxd_d_pins[] = {
2908 /* RXD */
2909 RCAR_GP_PIN(1, 24),
2910};
2911static const unsigned int msiof3_rxd_d_mux[] = {
2912 MSIOF3_RXD_D_MARK,
2913};
2914
2915static const unsigned int msiof3_clk_e_pins[] = {
2916 /* SCK */
2917 RCAR_GP_PIN(2, 3),
2918};
2919static const unsigned int msiof3_clk_e_mux[] = {
2920 MSIOF3_SCK_E_MARK,
2921};
2922static const unsigned int msiof3_sync_e_pins[] = {
2923 /* SYNC */
2924 RCAR_GP_PIN(2, 2),
2925};
2926static const unsigned int msiof3_sync_e_mux[] = {
2927 MSIOF3_SYNC_E_MARK,
2928};
2929static const unsigned int msiof3_ss1_e_pins[] = {
2930 /* SS1 */
2931 RCAR_GP_PIN(2, 1),
2932};
2933static const unsigned int msiof3_ss1_e_mux[] = {
2934 MSIOF3_SS1_E_MARK,
2935};
2936static const unsigned int msiof3_ss2_e_pins[] = {
2937 /* SS1 */
2938 RCAR_GP_PIN(2, 0),
2939};
2940static const unsigned int msiof3_ss2_e_mux[] = {
2941 MSIOF3_SS1_E_MARK,
2942};
2943static const unsigned int msiof3_txd_e_pins[] = {
2944 /* TXD */
2945 RCAR_GP_PIN(2, 5),
2946};
2947static const unsigned int msiof3_txd_e_mux[] = {
2948 MSIOF3_TXD_E_MARK,
2949};
2950static const unsigned int msiof3_rxd_e_pins[] = {
2951 /* RXD */
2952 RCAR_GP_PIN(2, 4),
2953};
2954static const unsigned int msiof3_rxd_e_mux[] = {
2955 MSIOF3_RXD_E_MARK,
2956};
2957
fc43d8b2
TK		 2958/* - SCIF0 ------------------------------------------------------------------ */
2959static const unsigned int scif0_data_pins[] = {
2960 /* RX, TX */
2961 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2962};
2963static const unsigned int scif0_data_mux[] = {
2964 RX0_MARK, TX0_MARK,
2965};
2966static const unsigned int scif0_clk_pins[] = {
2967 /* SCK */
2968 RCAR_GP_PIN(5, 0),
2969};
2970static const unsigned int scif0_clk_mux[] = {
2971 SCK0_MARK,
2972};
2973static const unsigned int scif0_ctrl_pins[] = {
2974 /* RTS, CTS */
2975 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2976};
2977static const unsigned int scif0_ctrl_mux[] = {
2978 RTS0_N_TANS_MARK, CTS0_N_MARK,
2979};
2980/* - SCIF1 ------------------------------------------------------------------ */
2981static const unsigned int scif1_data_a_pins[] = {
2982 /* RX, TX */
2983 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2984};
2985static const unsigned int scif1_data_a_mux[] = {
2986 RX1_A_MARK, TX1_A_MARK,
2987};
2988static const unsigned int scif1_clk_pins[] = {
2989 /* SCK */
2990 RCAR_GP_PIN(6, 21),
2991};
2992static const unsigned int scif1_clk_mux[] = {
2993 SCK1_MARK,
2994};
2995static const unsigned int scif1_ctrl_pins[] = {
2996 /* RTS, CTS */
2997 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2998};
2999static const unsigned int scif1_ctrl_mux[] = {
3000 RTS1_N_TANS_MARK, CTS1_N_MARK,
3001};
3002
3003static const unsigned int scif1_data_b_pins[] = {
3004 /* RX, TX */
3005 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3006};
3007static const unsigned int scif1_data_b_mux[] = {
3008 RX1_B_MARK, TX1_B_MARK,
3009};
3010/* - SCIF2 ------------------------------------------------------------------ */
3011static const unsigned int scif2_data_a_pins[] = {
3012 /* RX, TX */
3013 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3014};
3015static const unsigned int scif2_data_a_mux[] = {
3016 RX2_A_MARK, TX2_A_MARK,
3017};
3018static const unsigned int scif2_clk_pins[] = {
3019 /* SCK */
3020 RCAR_GP_PIN(5, 9),
3021};
3022static const unsigned int scif2_clk_mux[] = {
3023 SCK2_MARK,
3024};
3025static const unsigned int scif2_data_b_pins[] = {
3026 /* RX, TX */
3027 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3028};
3029static const unsigned int scif2_data_b_mux[] = {
3030 RX2_B_MARK, TX2_B_MARK,
3031};
3032/* - SCIF3 ------------------------------------------------------------------ */
3033static const unsigned int scif3_data_a_pins[] = {
3034 /* RX, TX */
3035 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3036};
3037static const unsigned int scif3_data_a_mux[] = {
3038 RX3_A_MARK, TX3_A_MARK,
3039};
3040static const unsigned int scif3_clk_pins[] = {
3041 /* SCK */
3042 RCAR_GP_PIN(1, 22),
3043};
3044static const unsigned int scif3_clk_mux[] = {
3045 SCK3_MARK,
3046};
3047static const unsigned int scif3_ctrl_pins[] = {
3048 /* RTS, CTS */
3049 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3050};
3051static const unsigned int scif3_ctrl_mux[] = {
3052 RTS3_N_TANS_MARK, CTS3_N_MARK,
3053};
3054static const unsigned int scif3_data_b_pins[] = {
3055 /* RX, TX */
3056 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3057};
3058static const unsigned int scif3_data_b_mux[] = {
3059 RX3_B_MARK, TX3_B_MARK,
3060};
3061/* - SCIF4 ------------------------------------------------------------------ */
3062static const unsigned int scif4_data_a_pins[] = {
3063 /* RX, TX */
3064 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3065};
3066static const unsigned int scif4_data_a_mux[] = {
3067 RX4_A_MARK, TX4_A_MARK,
3068};
3069static const unsigned int scif4_clk_a_pins[] = {
3070 /* SCK */
3071 RCAR_GP_PIN(2, 10),
3072};
3073static const unsigned int scif4_clk_a_mux[] = {
3074 SCK4_A_MARK,
3075};
3076static const unsigned int scif4_ctrl_a_pins[] = {
3077 /* RTS, CTS */
3078 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3079};
3080static const unsigned int scif4_ctrl_a_mux[] = {
3081 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
3082};
3083static const unsigned int scif4_data_b_pins[] = {
3084 /* RX, TX */
3085 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3086};
3087static const unsigned int scif4_data_b_mux[] = {
3088 RX4_B_MARK, TX4_B_MARK,
3089};
3090static const unsigned int scif4_clk_b_pins[] = {
3091 /* SCK */
3092 RCAR_GP_PIN(1, 5),
3093};
3094static const unsigned int scif4_clk_b_mux[] = {
3095 SCK4_B_MARK,
3096};
3097static const unsigned int scif4_ctrl_b_pins[] = {
3098 /* RTS, CTS */
3099 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3100};
3101static const unsigned int scif4_ctrl_b_mux[] = {
3102 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
3103};
3104static const unsigned int scif4_data_c_pins[] = {
3105 /* RX, TX */
3106 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3107};
3108static const unsigned int scif4_data_c_mux[] = {
3109 RX4_C_MARK, TX4_C_MARK,
3110};
3111static const unsigned int scif4_clk_c_pins[] = {
3112 /* SCK */
3113 RCAR_GP_PIN(0, 8),
3114};
3115static const unsigned int scif4_clk_c_mux[] = {
3116 SCK4_C_MARK,
3117};
3118static const unsigned int scif4_ctrl_c_pins[] = {
3119 /* RTS, CTS */
3120 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3121};
3122static const unsigned int scif4_ctrl_c_mux[] = {
3123 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
3124};
3125/* - SCIF5 ------------------------------------------------------------------ */
3126static const unsigned int scif5_data_a_pins[] = {
3127 /* RX, TX */
3128 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3129};
3130static const unsigned int scif5_data_a_mux[] = {
3131 RX5_A_MARK, TX5_A_MARK,
3132};
3133static const unsigned int scif5_clk_a_pins[] = {
3134 /* SCK */
3135 RCAR_GP_PIN(6, 21),
3136};
3137static const unsigned int scif5_clk_a_mux[] = {
3138 SCK5_A_MARK,
3139};
3140
3141static const unsigned int scif5_data_b_pins[] = {
3142 /* RX, TX */
3143 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3144};
3145static const unsigned int scif5_data_b_mux[] = {
3146 RX5_B_MARK, TX5_B_MARK,
3147};
3148static const unsigned int scif5_clk_b_pins[] = {
3149 /* SCK */
3150 RCAR_GP_PIN(5, 0),
3151};
3152static const unsigned int scif5_clk_b_mux[] = {
3153 SCK5_B_MARK,
3154};
3155
3156/* - SCIF Clock ------------------------------------------------------------- */
3157static const unsigned int scif_clk_a_pins[] = {
3158 /* SCIF_CLK */
3159 RCAR_GP_PIN(6, 23),
3160};
3161static const unsigned int scif_clk_a_mux[] = {
3162 SCIF_CLK_A_MARK,
3163};
3164static const unsigned int scif_clk_b_pins[] = {
3165 /* SCIF_CLK */
3166 RCAR_GP_PIN(5, 9),
3167};
3168static const unsigned int scif_clk_b_mux[] = {
3169 SCIF_CLK_B_MARK,
3170};
3171
374cf699
TK		 3172/* - SDHI0 ------------------------------------------------------------------ */
3173static const unsigned int sdhi0_data1_pins[] = {
3174 /* D0 */
3175 RCAR_GP_PIN(3, 2),
3176};
3177static const unsigned int sdhi0_data1_mux[] = {
3178 SD0_DAT0_MARK,
3179};
3180static const unsigned int sdhi0_data4_pins[] = {
3181 /* D[0:3] */
3182 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3183 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3184};
3185static const unsigned int sdhi0_data4_mux[] = {
3186 SD0_DAT0_MARK, SD0_DAT1_MARK,
3187 SD0_DAT2_MARK, SD0_DAT3_MARK,
3188};
3189static const unsigned int sdhi0_ctrl_pins[] = {
3190 /* CLK, CMD */
3191 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3192};
3193static const unsigned int sdhi0_ctrl_mux[] = {
3194 SD0_CLK_MARK, SD0_CMD_MARK,
3195};
3196static const unsigned int sdhi0_cd_pins[] = {
3197 /* CD */
3198 RCAR_GP_PIN(3, 12),
3199};
3200static const unsigned int sdhi0_cd_mux[] = {
3201 SD0_CD_MARK,
3202};
3203static const unsigned int sdhi0_wp_pins[] = {
3204 /* WP */
3205 RCAR_GP_PIN(3, 13),
3206};
3207static const unsigned int sdhi0_wp_mux[] = {
3208 SD0_WP_MARK,
3209};
3210/* - SDHI1 ------------------------------------------------------------------ */
3211static const unsigned int sdhi1_data1_pins[] = {
3212 /* D0 */
3213 RCAR_GP_PIN(3, 8),
3214};
3215static const unsigned int sdhi1_data1_mux[] = {
3216 SD1_DAT0_MARK,
3217};
3218static const unsigned int sdhi1_data4_pins[] = {
3219 /* D[0:3] */
3220 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3221 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3222};
3223static const unsigned int sdhi1_data4_mux[] = {
3224 SD1_DAT0_MARK, SD1_DAT1_MARK,
3225 SD1_DAT2_MARK, SD1_DAT3_MARK,
3226};
3227static const unsigned int sdhi1_ctrl_pins[] = {
3228 /* CLK, CMD */
3229 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3230};
3231static const unsigned int sdhi1_ctrl_mux[] = {
3232 SD1_CLK_MARK, SD1_CMD_MARK,
3233};
3234static const unsigned int sdhi1_cd_pins[] = {
3235 /* CD */
3236 RCAR_GP_PIN(3, 14),
3237};
3238static const unsigned int sdhi1_cd_mux[] = {
3239 SD1_CD_MARK,
3240};
3241static const unsigned int sdhi1_wp_pins[] = {
3242 /* WP */
3243 RCAR_GP_PIN(3, 15),
3244};
3245static const unsigned int sdhi1_wp_mux[] = {
3246 SD1_WP_MARK,
3247};
3248/* - SDHI2 ------------------------------------------------------------------ */
3249static const unsigned int sdhi2_data1_pins[] = {
3250 /* D0 */
3251 RCAR_GP_PIN(4, 2),
3252};
3253static const unsigned int sdhi2_data1_mux[] = {
3254 SD2_DAT0_MARK,
3255};
3256static const unsigned int sdhi2_data4_pins[] = {
3257 /* D[0:3] */
3258 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3259 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3260};
3261static const unsigned int sdhi2_data4_mux[] = {
3262 SD2_DAT0_MARK, SD2_DAT1_MARK,
3263 SD2_DAT2_MARK, SD2_DAT3_MARK,
3264};
3265static const unsigned int sdhi2_data8_pins[] = {
3266 /* D[0:7] */
3267 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3268 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3269 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3270 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3271};
3272static const unsigned int sdhi2_data8_mux[] = {
3273 SD2_DAT0_MARK, SD2_DAT1_MARK,
3274 SD2_DAT2_MARK, SD2_DAT3_MARK,
3275 SD2_DAT4_MARK, SD2_DAT5_MARK,
3276 SD2_DAT6_MARK, SD2_DAT7_MARK,
3277};
3278static const unsigned int sdhi2_ctrl_pins[] = {
3279 /* CLK, CMD */
3280 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3281};
3282static const unsigned int sdhi2_ctrl_mux[] = {
3283 SD2_CLK_MARK, SD2_CMD_MARK,
3284};
3285static const unsigned int sdhi2_cd_a_pins[] = {
3286 /* CD */
3287 RCAR_GP_PIN(4, 13),
3288};
3289static const unsigned int sdhi2_cd_a_mux[] = {
3290 SD2_CD_A_MARK,
3291};
3292static const unsigned int sdhi2_cd_b_pins[] = {
3293 /* CD */
3294 RCAR_GP_PIN(5, 10),
3295};
3296static const unsigned int sdhi2_cd_b_mux[] = {
3297 SD2_CD_B_MARK,
3298};
3299static const unsigned int sdhi2_wp_a_pins[] = {
3300 /* WP */
3301 RCAR_GP_PIN(4, 14),
3302};
3303static const unsigned int sdhi2_wp_a_mux[] = {
3304 SD2_WP_A_MARK,
3305};
3306static const unsigned int sdhi2_wp_b_pins[] = {
3307 /* WP */
3308 RCAR_GP_PIN(5, 11),
3309};
3310static const unsigned int sdhi2_wp_b_mux[] = {
3311 SD2_WP_B_MARK,
3312};
3313static const unsigned int sdhi2_ds_pins[] = {
3314 /* DS */
3315 RCAR_GP_PIN(4, 6),
3316};
3317static const unsigned int sdhi2_ds_mux[] = {
3318 SD2_DS_MARK,
3319};
3320/* - SDHI3 ------------------------------------------------------------------ */
3321static const unsigned int sdhi3_data1_pins[] = {
3322 /* D0 */
3323 RCAR_GP_PIN(4, 9),
3324};
3325static const unsigned int sdhi3_data1_mux[] = {
3326 SD3_DAT0_MARK,
3327};
3328static const unsigned int sdhi3_data4_pins[] = {
3329 /* D[0:3] */
3330 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3331 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3332};
3333static const unsigned int sdhi3_data4_mux[] = {
3334 SD3_DAT0_MARK, SD3_DAT1_MARK,
3335 SD3_DAT2_MARK, SD3_DAT3_MARK,
3336};
3337static const unsigned int sdhi3_data8_pins[] = {
3338 /* D[0:7] */
3339 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3340 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3341 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3342 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3343};
3344static const unsigned int sdhi3_data8_mux[] = {
3345 SD3_DAT0_MARK, SD3_DAT1_MARK,
3346 SD3_DAT2_MARK, SD3_DAT3_MARK,
3347 SD3_DAT4_MARK, SD3_DAT5_MARK,
3348 SD3_DAT6_MARK, SD3_DAT7_MARK,
3349};
3350static const unsigned int sdhi3_ctrl_pins[] = {
3351 /* CLK, CMD */
3352 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3353};
3354static const unsigned int sdhi3_ctrl_mux[] = {
3355 SD3_CLK_MARK, SD3_CMD_MARK,
3356};
3357static const unsigned int sdhi3_cd_pins[] = {
3358 /* CD */
3359 RCAR_GP_PIN(4, 15),
3360};
3361static const unsigned int sdhi3_cd_mux[] = {
3362 SD3_CD_MARK,
3363};
3364static const unsigned int sdhi3_wp_pins[] = {
3365 /* WP */
3366 RCAR_GP_PIN(4, 16),
3367};
3368static const unsigned int sdhi3_wp_mux[] = {
3369 SD3_WP_MARK,
3370};
3371static const unsigned int sdhi3_ds_pins[] = {
3372 /* DS */
3373 RCAR_GP_PIN(4, 17),
3374};
3375static const unsigned int sdhi3_ds_mux[] = {
3376 SD3_DS_MARK,
3377};
3378
f9aece73 3379static const struct sh_pfc_pin_group pinmux_groups[] = {
9c99a63e
TK		 3380 SH_PFC_PIN_GROUP(avb_link),
3381 SH_PFC_PIN_GROUP(avb_magic),
3382 SH_PFC_PIN_GROUP(avb_phy_int),
3383 SH_PFC_PIN_GROUP(avb_mdc),
3384 SH_PFC_PIN_GROUP(avb_avtp_pps),
3385 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3386 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3387 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3388 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
cf75341a
CP		 3389 SH_PFC_PIN_GROUP(can0_data_a),
3390 SH_PFC_PIN_GROUP(can0_data_b),
3391 SH_PFC_PIN_GROUP(can1_data),
3392 SH_PFC_PIN_GROUP(can_clk),
3dc93dce
CP		 3393 SH_PFC_PIN_GROUP(canfd0_data_a),
3394 SH_PFC_PIN_GROUP(canfd0_data_b),
3395 SH_PFC_PIN_GROUP(canfd1_data),
fb082831
RS		 3396 SH_PFC_PIN_GROUP(drif0_ctrl_a),
3397 SH_PFC_PIN_GROUP(drif0_data0_a),
3398 SH_PFC_PIN_GROUP(drif0_data1_a),
3399 SH_PFC_PIN_GROUP(drif0_ctrl_b),
3400 SH_PFC_PIN_GROUP(drif0_data0_b),
3401 SH_PFC_PIN_GROUP(drif0_data1_b),
3402 SH_PFC_PIN_GROUP(drif0_ctrl_c),
3403 SH_PFC_PIN_GROUP(drif0_data0_c),
3404 SH_PFC_PIN_GROUP(drif0_data1_c),
3405 SH_PFC_PIN_GROUP(drif1_ctrl_a),
3406 SH_PFC_PIN_GROUP(drif1_data0_a),
3407 SH_PFC_PIN_GROUP(drif1_data1_a),
3408 SH_PFC_PIN_GROUP(drif1_ctrl_b),
3409 SH_PFC_PIN_GROUP(drif1_data0_b),
3410 SH_PFC_PIN_GROUP(drif1_data1_b),
3411 SH_PFC_PIN_GROUP(drif1_ctrl_c),
3412 SH_PFC_PIN_GROUP(drif1_data0_c),
3413 SH_PFC_PIN_GROUP(drif1_data1_c),
3414 SH_PFC_PIN_GROUP(drif2_ctrl_a),
3415 SH_PFC_PIN_GROUP(drif2_data0_a),
3416 SH_PFC_PIN_GROUP(drif2_data1_a),
3417 SH_PFC_PIN_GROUP(drif2_ctrl_b),
3418 SH_PFC_PIN_GROUP(drif2_data0_b),
3419 SH_PFC_PIN_GROUP(drif2_data1_b),
3420 SH_PFC_PIN_GROUP(drif3_ctrl_a),
3421 SH_PFC_PIN_GROUP(drif3_data0_a),
3422 SH_PFC_PIN_GROUP(drif3_data1_a),
3423 SH_PFC_PIN_GROUP(drif3_ctrl_b),
3424 SH_PFC_PIN_GROUP(drif3_data0_b),
3425 SH_PFC_PIN_GROUP(drif3_data1_b),
cccc618a
NS		 3426 SH_PFC_PIN_GROUP(du_rgb666),
3427 SH_PFC_PIN_GROUP(du_rgb888),
3428 SH_PFC_PIN_GROUP(du_clk_out_0),
3429 SH_PFC_PIN_GROUP(du_clk_out_1),
3430 SH_PFC_PIN_GROUP(du_sync),
3431 SH_PFC_PIN_GROUP(du_oddf),
3432 SH_PFC_PIN_GROUP(du_cde),
3433 SH_PFC_PIN_GROUP(du_disp),
0e4e4999
UH		 3434 SH_PFC_PIN_GROUP(hscif0_data),
3435 SH_PFC_PIN_GROUP(hscif0_clk),
3436 SH_PFC_PIN_GROUP(hscif0_ctrl),
3437 SH_PFC_PIN_GROUP(hscif1_data_a),
3438 SH_PFC_PIN_GROUP(hscif1_clk_a),
3439 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3440 SH_PFC_PIN_GROUP(hscif1_data_b),
3441 SH_PFC_PIN_GROUP(hscif1_clk_b),
3442 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3443 SH_PFC_PIN_GROUP(hscif2_data_a),
3444 SH_PFC_PIN_GROUP(hscif2_clk_a),
3445 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3446 SH_PFC_PIN_GROUP(hscif2_data_b),
3447 SH_PFC_PIN_GROUP(hscif2_clk_b),
3448 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3449 SH_PFC_PIN_GROUP(hscif2_data_c),
3450 SH_PFC_PIN_GROUP(hscif2_clk_c),
3451 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
3452 SH_PFC_PIN_GROUP(hscif3_data_a),
3453 SH_PFC_PIN_GROUP(hscif3_clk),
3454 SH_PFC_PIN_GROUP(hscif3_ctrl),
3455 SH_PFC_PIN_GROUP(hscif3_data_b),
3456 SH_PFC_PIN_GROUP(hscif3_data_c),
3457 SH_PFC_PIN_GROUP(hscif3_data_d),
3458 SH_PFC_PIN_GROUP(hscif4_data_a),
3459 SH_PFC_PIN_GROUP(hscif4_clk),
3460 SH_PFC_PIN_GROUP(hscif4_ctrl),
3461 SH_PFC_PIN_GROUP(hscif4_data_b),
02609a23
UH		 3462 SH_PFC_PIN_GROUP(i2c1_a),
3463 SH_PFC_PIN_GROUP(i2c1_b),
3464 SH_PFC_PIN_GROUP(i2c2_a),
3465 SH_PFC_PIN_GROUP(i2c2_b),
3466 SH_PFC_PIN_GROUP(i2c6_a),
3467 SH_PFC_PIN_GROUP(i2c6_b),
3468 SH_PFC_PIN_GROUP(i2c6_c),
4753231c
TK		 3469 SH_PFC_PIN_GROUP(msiof0_clk),
3470 SH_PFC_PIN_GROUP(msiof0_sync),
3471 SH_PFC_PIN_GROUP(msiof0_ss1),
3472 SH_PFC_PIN_GROUP(msiof0_ss2),
3473 SH_PFC_PIN_GROUP(msiof0_txd),
3474 SH_PFC_PIN_GROUP(msiof0_rxd),
3475 SH_PFC_PIN_GROUP(msiof1_clk_a),
3476 SH_PFC_PIN_GROUP(msiof1_sync_a),
3477 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3478 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3479 SH_PFC_PIN_GROUP(msiof1_txd_a),
3480 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3481 SH_PFC_PIN_GROUP(msiof1_clk_b),
3482 SH_PFC_PIN_GROUP(msiof1_sync_b),
3483 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3484 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3485 SH_PFC_PIN_GROUP(msiof1_txd_b),
3486 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3487 SH_PFC_PIN_GROUP(msiof1_clk_c),
3488 SH_PFC_PIN_GROUP(msiof1_sync_c),
3489 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3490 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3491 SH_PFC_PIN_GROUP(msiof1_txd_c),
3492 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3493 SH_PFC_PIN_GROUP(msiof1_clk_d),
3494 SH_PFC_PIN_GROUP(msiof1_sync_d),
3495 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3496 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3497 SH_PFC_PIN_GROUP(msiof1_txd_d),
3498 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3499 SH_PFC_PIN_GROUP(msiof1_clk_e),
3500 SH_PFC_PIN_GROUP(msiof1_sync_e),
3501 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3502 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3503 SH_PFC_PIN_GROUP(msiof1_txd_e),
3504 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3505 SH_PFC_PIN_GROUP(msiof1_clk_f),
3506 SH_PFC_PIN_GROUP(msiof1_sync_f),
3507 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3508 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3509 SH_PFC_PIN_GROUP(msiof1_txd_f),
3510 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3511 SH_PFC_PIN_GROUP(msiof1_clk_g),
3512 SH_PFC_PIN_GROUP(msiof1_sync_g),
3513 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3514 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3515 SH_PFC_PIN_GROUP(msiof1_txd_g),
3516 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3517 SH_PFC_PIN_GROUP(msiof2_clk_a),
3518 SH_PFC_PIN_GROUP(msiof2_sync_a),
3519 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3520 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3521 SH_PFC_PIN_GROUP(msiof2_txd_a),
3522 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3523 SH_PFC_PIN_GROUP(msiof2_clk_b),
3524 SH_PFC_PIN_GROUP(msiof2_sync_b),
3525 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3526 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3527 SH_PFC_PIN_GROUP(msiof2_txd_b),
3528 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3529 SH_PFC_PIN_GROUP(msiof2_clk_c),
3530 SH_PFC_PIN_GROUP(msiof2_sync_c),
3531 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3532 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3533 SH_PFC_PIN_GROUP(msiof2_txd_c),
3534 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3535 SH_PFC_PIN_GROUP(msiof2_clk_d),
3536 SH_PFC_PIN_GROUP(msiof2_sync_d),
3537 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3538 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3539 SH_PFC_PIN_GROUP(msiof2_txd_d),
3540 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3541 SH_PFC_PIN_GROUP(msiof3_clk_a),
3542 SH_PFC_PIN_GROUP(msiof3_sync_a),
3543 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3544 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3545 SH_PFC_PIN_GROUP(msiof3_txd_a),
3546 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3547 SH_PFC_PIN_GROUP(msiof3_clk_b),
3548 SH_PFC_PIN_GROUP(msiof3_sync_b),
3549 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3550 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3551 SH_PFC_PIN_GROUP(msiof3_txd_b),
3552 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3553 SH_PFC_PIN_GROUP(msiof3_clk_c),
3554 SH_PFC_PIN_GROUP(msiof3_sync_c),
3555 SH_PFC_PIN_GROUP(msiof3_txd_c),
3556 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3557 SH_PFC_PIN_GROUP(msiof3_clk_d),
3558 SH_PFC_PIN_GROUP(msiof3_sync_d),
3559 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3560 SH_PFC_PIN_GROUP(msiof3_txd_d),
3561 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3562 SH_PFC_PIN_GROUP(msiof3_clk_e),
3563 SH_PFC_PIN_GROUP(msiof3_sync_e),
3564 SH_PFC_PIN_GROUP(msiof3_ss1_e),
3565 SH_PFC_PIN_GROUP(msiof3_ss2_e),
3566 SH_PFC_PIN_GROUP(msiof3_txd_e),
3567 SH_PFC_PIN_GROUP(msiof3_rxd_e),
fc43d8b2
TK		 3568 SH_PFC_PIN_GROUP(scif0_data),
3569 SH_PFC_PIN_GROUP(scif0_clk),
3570 SH_PFC_PIN_GROUP(scif0_ctrl),
3571 SH_PFC_PIN_GROUP(scif1_data_a),
3572 SH_PFC_PIN_GROUP(scif1_clk),
3573 SH_PFC_PIN_GROUP(scif1_ctrl),
3574 SH_PFC_PIN_GROUP(scif1_data_b),
3575 SH_PFC_PIN_GROUP(scif2_data_a),
3576 SH_PFC_PIN_GROUP(scif2_clk),
3577 SH_PFC_PIN_GROUP(scif2_data_b),
3578 SH_PFC_PIN_GROUP(scif3_data_a),
3579 SH_PFC_PIN_GROUP(scif3_clk),
3580 SH_PFC_PIN_GROUP(scif3_ctrl),
3581 SH_PFC_PIN_GROUP(scif3_data_b),
3582 SH_PFC_PIN_GROUP(scif4_data_a),
3583 SH_PFC_PIN_GROUP(scif4_clk_a),
3584 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3585 SH_PFC_PIN_GROUP(scif4_data_b),
3586 SH_PFC_PIN_GROUP(scif4_clk_b),
3587 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3588 SH_PFC_PIN_GROUP(scif4_data_c),
3589 SH_PFC_PIN_GROUP(scif4_clk_c),
3590 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3591 SH_PFC_PIN_GROUP(scif5_data_a),
3592 SH_PFC_PIN_GROUP(scif5_clk_a),
3593 SH_PFC_PIN_GROUP(scif5_data_b),
3594 SH_PFC_PIN_GROUP(scif5_clk_b),
3595 SH_PFC_PIN_GROUP(scif_clk_a),
3596 SH_PFC_PIN_GROUP(scif_clk_b),
374cf699
TK		 3597 SH_PFC_PIN_GROUP(sdhi0_data1),
3598 SH_PFC_PIN_GROUP(sdhi0_data4),
3599 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3600 SH_PFC_PIN_GROUP(sdhi0_cd),
3601 SH_PFC_PIN_GROUP(sdhi0_wp),
3602 SH_PFC_PIN_GROUP(sdhi1_data1),
3603 SH_PFC_PIN_GROUP(sdhi1_data4),
3604 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3605 SH_PFC_PIN_GROUP(sdhi1_cd),
3606 SH_PFC_PIN_GROUP(sdhi1_wp),
3607 SH_PFC_PIN_GROUP(sdhi2_data1),
3608 SH_PFC_PIN_GROUP(sdhi2_data4),
3609 SH_PFC_PIN_GROUP(sdhi2_data8),
3610 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3611 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3612 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3613 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3614 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3615 SH_PFC_PIN_GROUP(sdhi2_ds),
3616 SH_PFC_PIN_GROUP(sdhi3_data1),
3617 SH_PFC_PIN_GROUP(sdhi3_data4),
3618 SH_PFC_PIN_GROUP(sdhi3_data8),
3619 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3620 SH_PFC_PIN_GROUP(sdhi3_cd),
3621 SH_PFC_PIN_GROUP(sdhi3_wp),
3622 SH_PFC_PIN_GROUP(sdhi3_ds),
fc43d8b2
TK		 3623};
3624
9c99a63e
TK		 3625static const char * const avb_groups[] = {
3626 "avb_link",
3627 "avb_magic",
3628 "avb_phy_int",
3629 "avb_mdc",
3630 "avb_avtp_pps",
3631 "avb_avtp_match_a",
3632 "avb_avtp_capture_a",
3633 "avb_avtp_match_b",
3634 "avb_avtp_capture_b",
3635};
3636
cf75341a
CP		 3637static const char * const can0_groups[] = {
3638 "can0_data_a",
3639 "can0_data_b",
3640};
3641
3642static const char * const can1_groups[] = {
3643 "can1_data",
3644};
3645
3646static const char * const can_clk_groups[] = {
3647 "can_clk",
3648};
3649
3dc93dce
CP		 3650static const char * const canfd0_groups[] = {
3651 "canfd0_data_a",
3652 "canfd0_data_b",
3653};
3654
3655static const char * const canfd1_groups[] = {
3656 "canfd1_data",
3657};
3658
fb082831
RS		 3659static const char * const drif0_groups[] = {
3660 "drif0_ctrl_a",
3661 "drif0_data0_a",
3662 "drif0_data1_a",
3663 "drif0_ctrl_b",
3664 "drif0_data0_b",
3665 "drif0_data1_b",
3666 "drif0_ctrl_c",
3667 "drif0_data0_c",
3668 "drif0_data1_c",
3669};
3670
3671static const char * const drif1_groups[] = {
3672 "drif1_ctrl_a",
3673 "drif1_data0_a",
3674 "drif1_data1_a",
3675 "drif1_ctrl_b",
3676 "drif1_data0_b",
3677 "drif1_data1_b",
3678 "drif1_ctrl_c",
3679 "drif1_data0_c",
3680 "drif1_data1_c",
3681};
3682
3683static const char * const drif2_groups[] = {
3684 "drif2_ctrl_a",
3685 "drif2_data0_a",
3686 "drif2_data1_a",
3687 "drif2_ctrl_b",
3688 "drif2_data0_b",
3689 "drif2_data1_b",
3690};
3691
3692static const char * const drif3_groups[] = {
3693 "drif3_ctrl_a",
3694 "drif3_data0_a",
3695 "drif3_data1_a",
3696 "drif3_ctrl_b",
3697 "drif3_data0_b",
3698 "drif3_data1_b",
3699};
3700
cccc618a
NS		 3701static const char * const du_groups[] = {
3702 "du_rgb666",
3703 "du_rgb888",
3704 "du_clk_out_0",
3705 "du_clk_out_1",
3706 "du_sync",
3707 "du_oddf",
3708 "du_cde",
3709 "du_disp",
3710};
3711
0e4e4999
UH		 3712static const char * const hscif0_groups[] = {
3713 "hscif0_data",
3714 "hscif0_clk",
3715 "hscif0_ctrl",
3716};
3717
3718static const char * const hscif1_groups[] = {
3719 "hscif1_data_a",
3720 "hscif1_clk_a",
3721 "hscif1_ctrl_a",
3722 "hscif1_data_b",
3723 "hscif1_clk_b",
3724 "hscif1_ctrl_b",
3725};
3726
3727static const char * const hscif2_groups[] = {
3728 "hscif2_data_a",
3729 "hscif2_clk_a",
3730 "hscif2_ctrl_a",
3731 "hscif2_data_b",
3732 "hscif2_clk_b",
3733 "hscif2_ctrl_b",
3734 "hscif2_data_c",
3735 "hscif2_clk_c",
3736 "hscif2_ctrl_c",
3737};
3738
3739static const char * const hscif3_groups[] = {
3740 "hscif3_data_a",
3741 "hscif3_clk",
3742 "hscif3_ctrl",
3743 "hscif3_data_b",
3744 "hscif3_data_c",
3745 "hscif3_data_d",
3746};
3747
3748static const char * const hscif4_groups[] = {
3749 "hscif4_data_a",
3750 "hscif4_clk",
3751 "hscif4_ctrl",
3752 "hscif4_data_b",
3753};
3754
02609a23
UH		 3755static const char * const i2c1_groups[] = {
3756 "i2c1_a",
3757 "i2c1_b",
3758};
3759
3760static const char * const i2c2_groups[] = {
3761 "i2c2_a",
3762 "i2c2_b",
3763};
3764
3765static const char * const i2c6_groups[] = {
3766 "i2c6_a",
3767 "i2c6_b",
3768 "i2c6_c",
3769};
3770
4753231c
TK		 3771static const char * const msiof0_groups[] = {
3772 "msiof0_clk",
3773 "msiof0_sync",
3774 "msiof0_ss1",
3775 "msiof0_ss2",
3776 "msiof0_txd",
3777 "msiof0_rxd",
3778};
3779
3780static const char * const msiof1_groups[] = {
3781 "msiof1_clk_a",
3782 "msiof1_sync_a",
3783 "msiof1_ss1_a",
3784 "msiof1_ss2_a",
3785 "msiof1_txd_a",
3786 "msiof1_rxd_a",
3787 "msiof1_clk_b",
3788 "msiof1_sync_b",
3789 "msiof1_ss1_b",
3790 "msiof1_ss2_b",
3791 "msiof1_txd_b",
3792 "msiof1_rxd_b",
3793 "msiof1_clk_c",
3794 "msiof1_sync_c",
3795 "msiof1_ss1_c",
3796 "msiof1_ss2_c",
3797 "msiof1_txd_c",
3798 "msiof1_rxd_c",
3799 "msiof1_clk_d",
3800 "msiof1_sync_d",
3801 "msiof1_ss1_d",
3802 "msiof1_ss2_d",
3803 "msiof1_txd_d",
3804 "msiof1_rxd_d",
3805 "msiof1_clk_e",
3806 "msiof1_sync_e",
3807 "msiof1_ss1_e",
3808 "msiof1_ss2_e",
3809 "msiof1_txd_e",
3810 "msiof1_rxd_e",
3811 "msiof1_clk_f",
3812 "msiof1_sync_f",
3813 "msiof1_ss1_f",
3814 "msiof1_ss2_f",
3815 "msiof1_txd_f",
3816 "msiof1_rxd_f",
3817 "msiof1_clk_g",
3818 "msiof1_sync_g",
3819 "msiof1_ss1_g",
3820 "msiof1_ss2_g",
3821 "msiof1_txd_g",
3822 "msiof1_rxd_g",
3823};
3824
3825static const char * const msiof2_groups[] = {
3826 "msiof2_clk_a",
3827 "msiof2_sync_a",
3828 "msiof2_ss1_a",
3829 "msiof2_ss2_a",
3830 "msiof2_txd_a",
3831 "msiof2_rxd_a",
3832 "msiof2_clk_b",
3833 "msiof2_sync_b",
3834 "msiof2_ss1_b",
3835 "msiof2_ss2_b",
3836 "msiof2_txd_b",
3837 "msiof2_rxd_b",
3838 "msiof2_clk_c",
3839 "msiof2_sync_c",
3840 "msiof2_ss1_c",
3841 "msiof2_ss2_c",
3842 "msiof2_txd_c",
3843 "msiof2_rxd_c",
3844 "msiof2_clk_d",
3845 "msiof2_sync_d",
3846 "msiof2_ss1_d",
3847 "msiof2_ss2_d",
3848 "msiof2_txd_d",
3849 "msiof2_rxd_d",
3850};
3851
3852static const char * const msiof3_groups[] = {
3853 "msiof3_clk_a",
3854 "msiof3_sync_a",
3855 "msiof3_ss1_a",
3856 "msiof3_ss2_a",
3857 "msiof3_txd_a",
3858 "msiof3_rxd_a",
3859 "msiof3_clk_b",
3860 "msiof3_sync_b",
3861 "msiof3_ss1_b",
3862 "msiof3_ss2_b",
3863 "msiof3_txd_b",
3864 "msiof3_rxd_b",
3865 "msiof3_clk_c",
3866 "msiof3_sync_c",
3867 "msiof3_txd_c",
3868 "msiof3_rxd_c",
3869 "msiof3_clk_d",
3870 "msiof3_sync_d",
3871 "msiof3_ss1_d",
3872 "msiof3_txd_d",
3873 "msiof3_rxd_d",
3874 "msiof3_clk_e",
3875 "msiof3_sync_e",
3876 "msiof3_ss1_e",
3877 "msiof3_ss2_e",
3878 "msiof3_txd_e",
3879 "msiof3_rxd_e",
3880};
3881
fc43d8b2
TK		 3882static const char * const scif0_groups[] = {
3883 "scif0_data",
3884 "scif0_clk",
3885 "scif0_ctrl",
3886};
3887
3888static const char * const scif1_groups[] = {
3889 "scif1_data_a",
3890 "scif1_clk",
3891 "scif1_ctrl",
3892 "scif1_data_b",
3893};
3894
3895static const char * const scif2_groups[] = {
3896 "scif2_data_a",
3897 "scif2_clk",
3898 "scif2_data_b",
3899};
3900
3901static const char * const scif3_groups[] = {
3902 "scif3_data_a",
3903 "scif3_clk",
3904 "scif3_ctrl",
3905 "scif3_data_b",
3906};
3907
3908static const char * const scif4_groups[] = {
3909 "scif4_data_a",
3910 "scif4_clk_a",
3911 "scif4_ctrl_a",
3912 "scif4_data_b",
3913 "scif4_clk_b",
3914 "scif4_ctrl_b",
3915 "scif4_data_c",
3916 "scif4_clk_c",
3917 "scif4_ctrl_c",
3918};
3919
3920static const char * const scif5_groups[] = {
3921 "scif5_data_a",
3922 "scif5_clk_a",
3923 "scif5_data_b",
3924 "scif5_clk_b",
3925};
3926
3927static const char * const scif_clk_groups[] = {
3928 "scif_clk_a",
3929 "scif_clk_b",
f9aece73
TK		 3930};
3931
374cf699
TK		 3932static const char * const sdhi0_groups[] = {
3933 "sdhi0_data1",
3934 "sdhi0_data4",
3935 "sdhi0_ctrl",
3936 "sdhi0_cd",
3937 "sdhi0_wp",
3938};
3939
3940static const char * const sdhi1_groups[] = {
3941 "sdhi1_data1",
3942 "sdhi1_data4",
3943 "sdhi1_ctrl",
3944 "sdhi1_cd",
3945 "sdhi1_wp",
3946};
3947
3948static const char * const sdhi2_groups[] = {
3949 "sdhi2_data1",
3950 "sdhi2_data4",
3951 "sdhi2_data8",
3952 "sdhi2_ctrl",
3953 "sdhi2_cd_a",
3954 "sdhi2_wp_a",
3955 "sdhi2_cd_b",
3956 "sdhi2_wp_b",
3957 "sdhi2_ds",
3958};
3959
3960static const char * const sdhi3_groups[] = {
3961 "sdhi3_data1",
3962 "sdhi3_data4",
3963 "sdhi3_data8",
3964 "sdhi3_ctrl",
3965 "sdhi3_cd",
3966 "sdhi3_wp",
3967 "sdhi3_ds",
3968};
3969
f9aece73 3970static const struct sh_pfc_function pinmux_functions[] = {
9c99a63e 3971 SH_PFC_FUNCTION(avb),
cf75341a
CP		 3972 SH_PFC_FUNCTION(can0),
3973 SH_PFC_FUNCTION(can1),
3974 SH_PFC_FUNCTION(can_clk),
3dc93dce
CP		 3975 SH_PFC_FUNCTION(canfd0),
3976 SH_PFC_FUNCTION(canfd1),
fb082831
RS		 3977 SH_PFC_FUNCTION(drif0),
3978 SH_PFC_FUNCTION(drif1),
3979 SH_PFC_FUNCTION(drif2),
3980 SH_PFC_FUNCTION(drif3),
cccc618a 3981 SH_PFC_FUNCTION(du),
0e4e4999
UH		 3982 SH_PFC_FUNCTION(hscif0),
3983 SH_PFC_FUNCTION(hscif1),
3984 SH_PFC_FUNCTION(hscif2),
3985 SH_PFC_FUNCTION(hscif3),
3986 SH_PFC_FUNCTION(hscif4),
02609a23
UH		 3987 SH_PFC_FUNCTION(i2c1),
3988 SH_PFC_FUNCTION(i2c2),
3989 SH_PFC_FUNCTION(i2c6),
4753231c
TK		 3990 SH_PFC_FUNCTION(msiof0),
3991 SH_PFC_FUNCTION(msiof1),
3992 SH_PFC_FUNCTION(msiof2),
3993 SH_PFC_FUNCTION(msiof3),
fc43d8b2
TK		 3994 SH_PFC_FUNCTION(scif0),
3995 SH_PFC_FUNCTION(scif1),
3996 SH_PFC_FUNCTION(scif2),
3997 SH_PFC_FUNCTION(scif3),
3998 SH_PFC_FUNCTION(scif4),
3999 SH_PFC_FUNCTION(scif5),
4000 SH_PFC_FUNCTION(scif_clk),
374cf699
TK		 4001 SH_PFC_FUNCTION(sdhi0),
4002 SH_PFC_FUNCTION(sdhi1),
4003 SH_PFC_FUNCTION(sdhi2),
4004 SH_PFC_FUNCTION(sdhi3),
f9aece73
TK		 4005};
4006
4007static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4008#define F_(x, y) FN_##y
4009#define FM(x) FN_##x
4010 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4011 0, 0,
4012 0, 0,
4013 0, 0,
4014 0, 0,
4015 0, 0,
4016 0, 0,
4017 0, 0,
4018 0, 0,
4019 0, 0,
4020 0, 0,
4021 0, 0,
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 GP_0_15_FN, GPSR0_15,
4028 GP_0_14_FN, GPSR0_14,
4029 GP_0_13_FN, GPSR0_13,
4030 GP_0_12_FN, GPSR0_12,
4031 GP_0_11_FN, GPSR0_11,
4032 GP_0_10_FN, GPSR0_10,
4033 GP_0_9_FN, GPSR0_9,
4034 GP_0_8_FN, GPSR0_8,
4035 GP_0_7_FN, GPSR0_7,
4036 GP_0_6_FN, GPSR0_6,
4037 GP_0_5_FN, GPSR0_5,
4038 GP_0_4_FN, GPSR0_4,
4039 GP_0_3_FN, GPSR0_3,
4040 GP_0_2_FN, GPSR0_2,
4041 GP_0_1_FN, GPSR0_1,
4042 GP_0_0_FN, GPSR0_0, }
4043 },
4044 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4045 0, 0,
4046 0, 0,
4047 0, 0,
4048 GP_1_28_FN, GPSR1_28,
4049 GP_1_27_FN, GPSR1_27,
4050 GP_1_26_FN, GPSR1_26,
4051 GP_1_25_FN, GPSR1_25,
4052 GP_1_24_FN, GPSR1_24,
4053 GP_1_23_FN, GPSR1_23,
4054 GP_1_22_FN, GPSR1_22,
4055 GP_1_21_FN, GPSR1_21,
4056 GP_1_20_FN, GPSR1_20,
4057 GP_1_19_FN, GPSR1_19,
4058 GP_1_18_FN, GPSR1_18,
4059 GP_1_17_FN, GPSR1_17,
4060 GP_1_16_FN, GPSR1_16,
4061 GP_1_15_FN, GPSR1_15,
4062 GP_1_14_FN, GPSR1_14,
4063 GP_1_13_FN, GPSR1_13,
4064 GP_1_12_FN, GPSR1_12,
4065 GP_1_11_FN, GPSR1_11,
4066 GP_1_10_FN, GPSR1_10,
4067 GP_1_9_FN, GPSR1_9,
4068 GP_1_8_FN, GPSR1_8,
4069 GP_1_7_FN, GPSR1_7,
4070 GP_1_6_FN, GPSR1_6,
4071 GP_1_5_FN, GPSR1_5,
4072 GP_1_4_FN, GPSR1_4,
4073 GP_1_3_FN, GPSR1_3,
4074 GP_1_2_FN, GPSR1_2,
4075 GP_1_1_FN, GPSR1_1,
4076 GP_1_0_FN, GPSR1_0, }
4077 },
4078 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4079 0, 0,
4080 0, 0,
4081 0, 0,
4082 0, 0,
4083 0, 0,
4084 0, 0,
4085 0, 0,
4086 0, 0,
4087 0, 0,
4088 0, 0,
4089 0, 0,
4090 0, 0,
4091 0, 0,
4092 0, 0,
4093 0, 0,
4094 0, 0,
4095 0, 0,
4096 GP_2_14_FN, GPSR2_14,
4097 GP_2_13_FN, GPSR2_13,
4098 GP_2_12_FN, GPSR2_12,
4099 GP_2_11_FN, GPSR2_11,
4100 GP_2_10_FN, GPSR2_10,
4101 GP_2_9_FN, GPSR2_9,
4102 GP_2_8_FN, GPSR2_8,
4103 GP_2_7_FN, GPSR2_7,
4104 GP_2_6_FN, GPSR2_6,
4105 GP_2_5_FN, GPSR2_5,
4106 GP_2_4_FN, GPSR2_4,
4107 GP_2_3_FN, GPSR2_3,
4108 GP_2_2_FN, GPSR2_2,
4109 GP_2_1_FN, GPSR2_1,
4110 GP_2_0_FN, GPSR2_0, }
4111 },
4112 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4113 0, 0,
4114 0, 0,
4115 0, 0,
4116 0, 0,
4117 0, 0,
4118 0, 0,
4119 0, 0,
4120 0, 0,
4121 0, 0,
4122 0, 0,
4123 0, 0,
4124 0, 0,
4125 0, 0,
4126 0, 0,
4127 0, 0,
4128 0, 0,
4129 GP_3_15_FN, GPSR3_15,
4130 GP_3_14_FN, GPSR3_14,
4131 GP_3_13_FN, GPSR3_13,
4132 GP_3_12_FN, GPSR3_12,
4133 GP_3_11_FN, GPSR3_11,
4134 GP_3_10_FN, GPSR3_10,
4135 GP_3_9_FN, GPSR3_9,
4136 GP_3_8_FN, GPSR3_8,
4137 GP_3_7_FN, GPSR3_7,
4138 GP_3_6_FN, GPSR3_6,
4139 GP_3_5_FN, GPSR3_5,
4140 GP_3_4_FN, GPSR3_4,
4141 GP_3_3_FN, GPSR3_3,
4142 GP_3_2_FN, GPSR3_2,
4143 GP_3_1_FN, GPSR3_1,
4144 GP_3_0_FN, GPSR3_0, }
4145 },
4146 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4147 0, 0,
4148 0, 0,
4149 0, 0,
4150 0, 0,
4151 0, 0,
4152 0, 0,
4153 0, 0,
4154 0, 0,
4155 0, 0,
4156 0, 0,
4157 0, 0,
4158 0, 0,
4159 0, 0,
4160 0, 0,
4161 GP_4_17_FN, GPSR4_17,
4162 GP_4_16_FN, GPSR4_16,
4163 GP_4_15_FN, GPSR4_15,
4164 GP_4_14_FN, GPSR4_14,
4165 GP_4_13_FN, GPSR4_13,
4166 GP_4_12_FN, GPSR4_12,
4167 GP_4_11_FN, GPSR4_11,
4168 GP_4_10_FN, GPSR4_10,
4169 GP_4_9_FN, GPSR4_9,
4170 GP_4_8_FN, GPSR4_8,
4171 GP_4_7_FN, GPSR4_7,
4172 GP_4_6_FN, GPSR4_6,
4173 GP_4_5_FN, GPSR4_5,
4174 GP_4_4_FN, GPSR4_4,
4175 GP_4_3_FN, GPSR4_3,
4176 GP_4_2_FN, GPSR4_2,
4177 GP_4_1_FN, GPSR4_1,
4178 GP_4_0_FN, GPSR4_0, }
4179 },
4180 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4181 0, 0,
4182 0, 0,
4183 0, 0,
4184 0, 0,
4185 0, 0,
4186 0, 0,
4187 GP_5_25_FN, GPSR5_25,
4188 GP_5_24_FN, GPSR5_24,
4189 GP_5_23_FN, GPSR5_23,
4190 GP_5_22_FN, GPSR5_22,
4191 GP_5_21_FN, GPSR5_21,
4192 GP_5_20_FN, GPSR5_20,
4193 GP_5_19_FN, GPSR5_19,
4194 GP_5_18_FN, GPSR5_18,
4195 GP_5_17_FN, GPSR5_17,
4196 GP_5_16_FN, GPSR5_16,
4197 GP_5_15_FN, GPSR5_15,
4198 GP_5_14_FN, GPSR5_14,
4199 GP_5_13_FN, GPSR5_13,
4200 GP_5_12_FN, GPSR5_12,
4201 GP_5_11_FN, GPSR5_11,
4202 GP_5_10_FN, GPSR5_10,
4203 GP_5_9_FN, GPSR5_9,
4204 GP_5_8_FN, GPSR5_8,
4205 GP_5_7_FN, GPSR5_7,
4206 GP_5_6_FN, GPSR5_6,
4207 GP_5_5_FN, GPSR5_5,
4208 GP_5_4_FN, GPSR5_4,
4209 GP_5_3_FN, GPSR5_3,
4210 GP_5_2_FN, GPSR5_2,
4211 GP_5_1_FN, GPSR5_1,
4212 GP_5_0_FN, GPSR5_0, }
4213 },
4214 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4215 GP_6_31_FN, GPSR6_31,
4216 GP_6_30_FN, GPSR6_30,
4217 GP_6_29_FN, GPSR6_29,
4218 GP_6_28_FN, GPSR6_28,
4219 GP_6_27_FN, GPSR6_27,
4220 GP_6_26_FN, GPSR6_26,
4221 GP_6_25_FN, GPSR6_25,
4222 GP_6_24_FN, GPSR6_24,
4223 GP_6_23_FN, GPSR6_23,
4224 GP_6_22_FN, GPSR6_22,
4225 GP_6_21_FN, GPSR6_21,
4226 GP_6_20_FN, GPSR6_20,
4227 GP_6_19_FN, GPSR6_19,
4228 GP_6_18_FN, GPSR6_18,
4229 GP_6_17_FN, GPSR6_17,
4230 GP_6_16_FN, GPSR6_16,
4231 GP_6_15_FN, GPSR6_15,
4232 GP_6_14_FN, GPSR6_14,
4233 GP_6_13_FN, GPSR6_13,
4234 GP_6_12_FN, GPSR6_12,
4235 GP_6_11_FN, GPSR6_11,
4236 GP_6_10_FN, GPSR6_10,
4237 GP_6_9_FN, GPSR6_9,
4238 GP_6_8_FN, GPSR6_8,
4239 GP_6_7_FN, GPSR6_7,
4240 GP_6_6_FN, GPSR6_6,
4241 GP_6_5_FN, GPSR6_5,
4242 GP_6_4_FN, GPSR6_4,
4243 GP_6_3_FN, GPSR6_3,
4244 GP_6_2_FN, GPSR6_2,
4245 GP_6_1_FN, GPSR6_1,
4246 GP_6_0_FN, GPSR6_0, }
4247 },
4248 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4249 0, 0,
4250 0, 0,
4251 0, 0,
4252 0, 0,
4253 0, 0,
4254 0, 0,
4255 0, 0,
4256 0, 0,
4257 0, 0,
4258 0, 0,
4259 0, 0,
4260 0, 0,
4261 0, 0,
4262 0, 0,
4263 0, 0,
4264 0, 0,
4265 0, 0,
4266 0, 0,
4267 0, 0,
4268 0, 0,
4269 0, 0,
4270 0, 0,
4271 0, 0,
4272 0, 0,
4273 0, 0,
4274 0, 0,
4275 0, 0,
4276 0, 0,
4277 GP_7_3_FN, GPSR7_3,
4278 GP_7_2_FN, GPSR7_2,
4279 GP_7_1_FN, GPSR7_1,
4280 GP_7_0_FN, GPSR7_0, }
4281 },
4282#undef F_
4283#undef FM
4284
4285#define F_(x, y) x,
4286#define FM(x) FN_##x,
4287 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4288 IP0_31_28
4289 IP0_27_24
4290 IP0_23_20
4291 IP0_19_16
4292 IP0_15_12
4293 IP0_11_8
4294 IP0_7_4
4295 IP0_3_0 }
4296 },
4297 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4298 IP1_31_28
4299 IP1_27_24
4300 IP1_23_20
4301 IP1_19_16
4302 IP1_15_12
4303 IP1_11_8
4304 IP1_7_4
4305 IP1_3_0 }
4306 },
4307 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4308 IP2_31_28
4309 IP2_27_24
4310 IP2_23_20
4311 IP2_19_16
4312 IP2_15_12
4313 IP2_11_8
4314 IP2_7_4
4315 IP2_3_0 }
4316 },
4317 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4318 IP3_31_28
4319 IP3_27_24
4320 IP3_23_20
4321 IP3_19_16
4322 IP3_15_12
4323 IP3_11_8
4324 IP3_7_4
4325 IP3_3_0 }
4326 },
4327 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4328 IP4_31_28
4329 IP4_27_24
4330 IP4_23_20
4331 IP4_19_16
4332 IP4_15_12
4333 IP4_11_8
4334 IP4_7_4
4335 IP4_3_0 }
4336 },
4337 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4338 IP5_31_28
4339 IP5_27_24
4340 IP5_23_20
4341 IP5_19_16
4342 IP5_15_12
4343 IP5_11_8
4344 IP5_7_4
4345 IP5_3_0 }
4346 },
4347 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4348 IP6_31_28
4349 IP6_27_24
4350 IP6_23_20
4351 IP6_19_16
4352 IP6_15_12
4353 IP6_11_8
4354 IP6_7_4
4355 IP6_3_0 }
4356 },
4357 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4358 IP7_31_28
4359 IP7_27_24
4360 IP7_23_20
4361 IP7_19_16
4362 IP7_15_12
4363 IP7_11_8
4364 IP7_7_4
4365 IP7_3_0 }
4366 },
4367 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4368 IP8_31_28
4369 IP8_27_24
4370 IP8_23_20
4371 IP8_19_16
4372 IP8_15_12
4373 IP8_11_8
4374 IP8_7_4
4375 IP8_3_0 }
4376 },
4377 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4378 IP9_31_28
4379 IP9_27_24
4380 IP9_23_20
4381 IP9_19_16
4382 IP9_15_12
4383 IP9_11_8
4384 IP9_7_4
4385 IP9_3_0 }
4386 },
4387 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4388 IP10_31_28
4389 IP10_27_24
4390 IP10_23_20
4391 IP10_19_16
4392 IP10_15_12
4393 IP10_11_8
4394 IP10_7_4
4395 IP10_3_0 }
4396 },
4397 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4398 IP11_31_28
4399 IP11_27_24
4400 IP11_23_20
4401 IP11_19_16
4402 IP11_15_12
4403 IP11_11_8
4404 IP11_7_4
4405 IP11_3_0 }
4406 },
4407 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4408 IP12_31_28
4409 IP12_27_24
4410 IP12_23_20
4411 IP12_19_16
4412 IP12_15_12
4413 IP12_11_8
4414 IP12_7_4
4415 IP12_3_0 }
4416 },
4417 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4418 IP13_31_28
4419 IP13_27_24
4420 IP13_23_20
4421 IP13_19_16
4422 IP13_15_12
4423 IP13_11_8
4424 IP13_7_4
4425 IP13_3_0 }
4426 },
4427 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4428 IP14_31_28
4429 IP14_27_24
4430 IP14_23_20
4431 IP14_19_16
4432 IP14_15_12
4433 IP14_11_8
4434 IP14_7_4
4435 IP14_3_0 }
4436 },
4437 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4438 IP15_31_28
4439 IP15_27_24
4440 IP15_23_20
4441 IP15_19_16
4442 IP15_15_12
4443 IP15_11_8
4444 IP15_7_4
4445 IP15_3_0 }
4446 },
4447 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4448 IP16_31_28
4449 IP16_27_24
4450 IP16_23_20
4451 IP16_19_16
4452 IP16_15_12
4453 IP16_11_8
4454 IP16_7_4
4455 IP16_3_0 }
4456 },
4457 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4458 IP17_31_28
4459 IP17_27_24
4460 IP17_23_20
4461 IP17_19_16
4462 IP17_15_12
4463 IP17_11_8
4464 IP17_7_4
4465 IP17_3_0 }
4466 },
4467 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
4468 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4469 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4470 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4471 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4472 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4473 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4474 IP18_7_4
4475 IP18_3_0 }
4476 },
4477#undef F_
4478#undef FM
4479
4480#define F_(x, y) x,
4481#define FM(x) FN_##x,
4482 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4483 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
4484 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
4485 MOD_SEL0_31_30_29
4486 MOD_SEL0_28_27
4487 MOD_SEL0_26_25_24
4488 MOD_SEL0_23
4489 MOD_SEL0_22
4490 MOD_SEL0_21
4491 MOD_SEL0_20
4492 MOD_SEL0_19
4493 MOD_SEL0_18_17
4494 MOD_SEL0_16
4495 MOD_SEL0_15
4496 MOD_SEL0_14_13
4497 MOD_SEL0_12
4498 MOD_SEL0_11
4499 MOD_SEL0_10
4500 MOD_SEL0_9_8
4501 MOD_SEL0_7_6
4502 MOD_SEL0_5
4503 MOD_SEL0_4_3
4504 /* RESERVED 2, 1, 0 */
4505 0, 0, 0, 0, 0, 0, 0, 0 }
4506 },
4507 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4508 2, 3, 1, 2, 3, 1, 1, 2, 1,
4509 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4510 MOD_SEL1_31_30
4511 MOD_SEL1_29_28_27
4512 MOD_SEL1_26
4513 MOD_SEL1_25_24
4514 MOD_SEL1_23_22_21
4515 MOD_SEL1_20
4516 MOD_SEL1_19
4517 MOD_SEL1_18_17
4518 MOD_SEL1_16
4519 MOD_SEL1_15_14
4520 MOD_SEL1_13
4521 MOD_SEL1_12
4522 MOD_SEL1_11
4523 MOD_SEL1_10
4524 MOD_SEL1_9
4525 0, 0, 0, 0, /* RESERVED 8, 7 */
4526 MOD_SEL1_6
4527 MOD_SEL1_5
4528 MOD_SEL1_4
4529 MOD_SEL1_3
4530 MOD_SEL1_2
4531 MOD_SEL1_1
4532 MOD_SEL1_0 }
4533 },
4534 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4535 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
4536 4, 4, 4, 3, 1) {
4537 MOD_SEL2_31
4538 MOD_SEL2_30
4539 MOD_SEL2_29
4540 MOD_SEL2_28_27
4541 MOD_SEL2_26
4542 MOD_SEL2_25_24_23
4543 MOD_SEL2_22
4544 MOD_SEL2_21
4545 MOD_SEL2_20
4546 MOD_SEL2_19
4547 MOD_SEL2_18
4548 MOD_SEL2_17
4549 /* RESERVED 16 */
4550 0, 0,
4551 /* RESERVED 15, 14, 13, 12 */
4552 0, 0, 0, 0, 0, 0, 0, 0,
4553 0, 0, 0, 0, 0, 0, 0, 0,
4554 /* RESERVED 11, 10, 9, 8 */
4555 0, 0, 0, 0, 0, 0, 0, 0,
4556 0, 0, 0, 0, 0, 0, 0, 0,
4557 /* RESERVED 7, 6, 5, 4 */
4558 0, 0, 0, 0, 0, 0, 0, 0,
4559 0, 0, 0, 0, 0, 0, 0, 0,
4560 /* RESERVED 3, 2, 1 */
4561 0, 0, 0, 0, 0, 0, 0, 0,
4562 MOD_SEL2_0 }
4563 },
4564 { },
4565};
4566
9e35d6fa
NS		 4567static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4568 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
4569 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
4570 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
4571 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
4572 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
4573 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
4574 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
4575 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
4576 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
4577 } },
4578 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
4579 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
4580 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
4581 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
4582 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
4583 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
4584 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
4585 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
4586 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
4587 } },
4588 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
4589 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
4590 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
4591 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
4592 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
4593 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
4594 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
4595 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
4596 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
4597 } },
4598 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4599 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
4600 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
4601 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
4602 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
4603 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
4604 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4605 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4606 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4607 } },
4608 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4609 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4610 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4611 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4612 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4613 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4614 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4615 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4616 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4617 } },
4618 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4619 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4620 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4621 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4622 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4623 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4624 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4625 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4626 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4627 } },
4628 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4629 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4630 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4631 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4632 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4633 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4634 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4635 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4636 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4637 } },
4638 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4639 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4640 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4641 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4642 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4643 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4644 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4645 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4646 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4647 } },
4648 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4649 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
4650 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4651 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4652 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4653 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4654 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4655 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4656 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4657 } },
4658 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4659 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4660 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
4661 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4662 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4663 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4664 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4665 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4666 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4667 } },
4668 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4669 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4670 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4671 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4672 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4673 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4674 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4675 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4676 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4677 } },
4678 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4679 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4680 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4681 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4682 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4683 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4684 { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
4685 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
4686 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
4687 } },
4688 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
4689 { PIN_A_NUMBER('R', 8), 28, 2 }, /* DU_DOTCLKIN2 */
4690 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST */
4691 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
4692 } },
4693 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4694 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
4695 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
4696 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4697 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4698 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4699 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4700 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4701 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4702 } },
4703 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4704 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4705 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4706 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4707 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4708 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4709 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4710 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4711 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4712 } },
4713 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4714 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4715 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4716 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4717 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4718 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4719 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4720 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4721 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4722 } },
4723 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4724 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4725 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4726 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4727 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4728 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4729 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4730 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4731 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4732 } },
4733 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4734 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4735 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4736 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4737 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4738 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4739 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4740 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4741 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4742 } },
4743 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4744 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4745 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4746 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4747 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4748 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4749 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4750 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4751 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4752 } },
4753 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4754 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4755 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4756 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4757 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4758 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4759 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4760 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4761 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4762 } },
4763 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4764 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4765 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4766 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4767 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4768 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4769 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4770 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
4771 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4772 } },
4773 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4774 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4775 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4776 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4777 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4778 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
4779 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
4780 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4781 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4782 } },
4783 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4784 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4785 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4786 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4787 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4788 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4789 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4790 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4791 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4792 } },
4793 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4794 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4795 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4796 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4797 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4798 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4799 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4800 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4801 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4802 } },
4803 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4804 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4805 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4806 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4807 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4808 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4809 { RCAR_GP_PIN(6, 30), 8, 3 }, /* GP6_30 */
4810 { RCAR_GP_PIN(6, 31), 4, 3 }, /* GP6_31 */
4811 } },
4812 { },
4813};
4814
c5901bdc
SH		 4815static int r8a7796_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
4816{
4817 int bit = -EINVAL;
4818
4819 *pocctrl = 0xe6060380;
4820
4821 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
4822 bit = pin & 0x1f;
4823
4824 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
4825 bit = (pin & 0x1f) + 12;
4826
4827 return bit;
4828}
4829
2d40bd24
NS		 4830#define PUEN 0xe6060400
4831#define PUD 0xe6060440
4832
4833#define PU0 0x00
4834#define PU1 0x04
4835#define PU2 0x08
4836#define PU3 0x0c
4837#define PU4 0x10
4838#define PU5 0x14
4839#define PU6 0x18
4840
4841static const struct sh_pfc_bias_info bias_info[] = {
4842 { RCAR_GP_PIN(2, 11), PU0, 31 }, /* AVB_PHY_INT */
4843 { RCAR_GP_PIN(2, 10), PU0, 30 }, /* AVB_MAGIC */
4844 { RCAR_GP_PIN(2, 9), PU0, 29 }, /* AVB_MDC */
4845 { PIN_NUMBER('A', 9), PU0, 28 }, /* AVB_MDIO */
4846 { PIN_NUMBER('A', 12), PU0, 27 }, /* AVB_TXCREFCLK */
4847 { PIN_NUMBER('B', 17), PU0, 26 }, /* AVB_TD3 */
4848 { PIN_NUMBER('A', 17), PU0, 25 }, /* AVB_TD2 */
4849 { PIN_NUMBER('B', 18), PU0, 24 }, /* AVB_TD1 */
4850 { PIN_NUMBER('A', 18), PU0, 23 }, /* AVB_TD0 */
4851 { PIN_NUMBER('A', 19), PU0, 22 }, /* AVB_TXC */
4852 { PIN_NUMBER('A', 8), PU0, 21 }, /* AVB_TX_CTL */
4853 { PIN_NUMBER('B', 14), PU0, 20 }, /* AVB_RD3 */
4854 { PIN_NUMBER('A', 14), PU0, 19 }, /* AVB_RD2 */
4855 { PIN_NUMBER('B', 13), PU0, 18 }, /* AVB_RD1 */
4856 { PIN_NUMBER('A', 13), PU0, 17 }, /* AVB_RD0 */
4857 { PIN_NUMBER('B', 19), PU0, 16 }, /* AVB_RXC */
4858 { PIN_NUMBER('A', 16), PU0, 15 }, /* AVB_RX_CTL */
4859 { PIN_NUMBER('V', 7), PU0, 14 }, /* RPC_RESET# */
4860 { PIN_NUMBER('V', 6), PU0, 13 }, /* RPC_WP# */
4861 { PIN_NUMBER('Y', 7), PU0, 12 }, /* RPC_INT# */
4862 { PIN_NUMBER('V', 5), PU0, 11 }, /* QSPI1_SSL */
4863 { PIN_A_NUMBER('C', 3), PU0, 10 }, /* QSPI1_IO3 */
4864 { PIN_A_NUMBER('E', 4), PU0, 9 }, /* QSPI1_IO2 */
4865 { PIN_A_NUMBER('E', 5), PU0, 8 }, /* QSPI1_MISO_IO1 */
4866 { PIN_A_NUMBER('C', 7), PU0, 7 }, /* QSPI1_MOSI_IO0 */
4867 { PIN_NUMBER('V', 3), PU0, 6 }, /* QSPI1_SPCLK */
4868 { PIN_NUMBER('Y', 3), PU0, 5 }, /* QSPI0_SSL */
4869 { PIN_A_NUMBER('B', 6), PU0, 4 }, /* QSPI0_IO3 */
4870 { PIN_NUMBER('Y', 6), PU0, 3 }, /* QSPI0_IO2 */
4871 { PIN_A_NUMBER('B', 4), PU0, 2 }, /* QSPI0_MISO_IO1 */
4872 { PIN_A_NUMBER('C', 5), PU0, 1 }, /* QSPI0_MOSI_IO0 */
4873 { PIN_NUMBER('W', 3), PU0, 0 }, /* QSPI0_SPCLK */
4874
4875 { RCAR_GP_PIN(1, 19), PU1, 31 }, /* A19 */
4876 { RCAR_GP_PIN(1, 18), PU1, 30 }, /* A18 */
4877 { RCAR_GP_PIN(1, 17), PU1, 29 }, /* A17 */
4878 { RCAR_GP_PIN(1, 16), PU1, 28 }, /* A16 */
4879 { RCAR_GP_PIN(1, 15), PU1, 27 }, /* A15 */
4880 { RCAR_GP_PIN(1, 14), PU1, 26 }, /* A14 */
4881 { RCAR_GP_PIN(1, 13), PU1, 25 }, /* A13 */
4882 { RCAR_GP_PIN(1, 12), PU1, 24 }, /* A12 */
4883 { RCAR_GP_PIN(1, 11), PU1, 23 }, /* A11 */
4884 { RCAR_GP_PIN(1, 10), PU1, 22 }, /* A10 */
4885 { RCAR_GP_PIN(1, 9), PU1, 21 }, /* A9 */
4886 { RCAR_GP_PIN(1, 8), PU1, 20 }, /* A8 */
4887 { RCAR_GP_PIN(1, 7), PU1, 19 }, /* A7 */
4888 { RCAR_GP_PIN(1, 6), PU1, 18 }, /* A6 */
4889 { RCAR_GP_PIN(1, 5), PU1, 17 }, /* A5 */
4890 { RCAR_GP_PIN(1, 4), PU1, 16 }, /* A4 */
4891 { RCAR_GP_PIN(1, 3), PU1, 15 }, /* A3 */
4892 { RCAR_GP_PIN(1, 2), PU1, 14 }, /* A2 */
4893 { RCAR_GP_PIN(1, 1), PU1, 13 }, /* A1 */
4894 { RCAR_GP_PIN(1, 0), PU1, 12 }, /* A0 */
4895 { RCAR_GP_PIN(2, 8), PU1, 11 }, /* PWM2_A */
4896 { RCAR_GP_PIN(2, 7), PU1, 10 }, /* PWM1_A */
4897 { RCAR_GP_PIN(2, 6), PU1, 9 }, /* PWM0 */
4898 { RCAR_GP_PIN(2, 5), PU1, 8 }, /* IRQ5 */
4899 { RCAR_GP_PIN(2, 4), PU1, 7 }, /* IRQ4 */
4900 { RCAR_GP_PIN(2, 3), PU1, 6 }, /* IRQ3 */
4901 { RCAR_GP_PIN(2, 2), PU1, 5 }, /* IRQ2 */
4902 { RCAR_GP_PIN(2, 1), PU1, 4 }, /* IRQ1 */
4903 { RCAR_GP_PIN(2, 0), PU1, 3 }, /* IRQ0 */
4904 { RCAR_GP_PIN(2, 14), PU1, 2 }, /* AVB_AVTP_CAPTURE_A */
4905 { RCAR_GP_PIN(2, 13), PU1, 1 }, /* AVB_AVTP_MATCH_A */
4906 { RCAR_GP_PIN(2, 12), PU1, 0 }, /* AVB_LINK */
4907
4908 { PIN_A_NUMBER('P', 8), PU2, 31 }, /* DU_DOTCLKIN1 */
4909 { PIN_A_NUMBER('P', 7), PU2, 30 }, /* DU_DOTCLKIN0 */
4910 { RCAR_GP_PIN(7, 3), PU2, 29 }, /* GP7_03 */
4911 { RCAR_GP_PIN(7, 2), PU2, 28 }, /* HDMI0_CEC */
4912 { RCAR_GP_PIN(7, 1), PU2, 27 }, /* AVS2 */
4913 { RCAR_GP_PIN(7, 0), PU2, 26 }, /* AVS1 */
4914 { RCAR_GP_PIN(0, 15), PU2, 25 }, /* D15 */
4915 { RCAR_GP_PIN(0, 14), PU2, 24 }, /* D14 */
4916 { RCAR_GP_PIN(0, 13), PU2, 23 }, /* D13 */
4917 { RCAR_GP_PIN(0, 12), PU2, 22 }, /* D12 */
4918 { RCAR_GP_PIN(0, 11), PU2, 21 }, /* D11 */
4919 { RCAR_GP_PIN(0, 10), PU2, 20 }, /* D10 */
4920 { RCAR_GP_PIN(0, 9), PU2, 19 }, /* D9 */
4921 { RCAR_GP_PIN(0, 8), PU2, 18 }, /* D8 */
4922 { RCAR_GP_PIN(0, 7), PU2, 17 }, /* D7 */
4923 { RCAR_GP_PIN(0, 6), PU2, 16 }, /* D6 */
4924 { RCAR_GP_PIN(0, 5), PU2, 15 }, /* D5 */
4925 { RCAR_GP_PIN(0, 4), PU2, 14 }, /* D4 */
4926 { RCAR_GP_PIN(0, 3), PU2, 13 }, /* D3 */
4927 { RCAR_GP_PIN(0, 2), PU2, 12 }, /* D2 */
4928 { RCAR_GP_PIN(0, 1), PU2, 11 }, /* D1 */
4929 { RCAR_GP_PIN(0, 0), PU2, 10 }, /* D0 */
4930 { PIN_NUMBER('C', 1), PU2, 9 }, /* PRESETOUT# */
4931 { RCAR_GP_PIN(1, 27), PU2, 8 }, /* EX_WAIT0_A */
4932 { RCAR_GP_PIN(1, 26), PU2, 7 }, /* WE1_N */
4933 { RCAR_GP_PIN(1, 25), PU2, 6 }, /* WE0_N */
4934 { RCAR_GP_PIN(1, 24), PU2, 5 }, /* RD_WR_N */
4935 { RCAR_GP_PIN(1, 23), PU2, 4 }, /* RD_N */
4936 { RCAR_GP_PIN(1, 22), PU2, 3 }, /* BS_N */
4937 { RCAR_GP_PIN(1, 21), PU2, 2 }, /* CS1_N_A26 */
4938 { RCAR_GP_PIN(1, 20), PU2, 1 }, /* CS0_N */
4939 { RCAR_GP_PIN(1, 28), PU2, 0 }, /* CLKOUT */
4940
4941 { RCAR_GP_PIN(4, 9), PU3, 31 }, /* SD3_DAT0 */
4942 { RCAR_GP_PIN(4, 8), PU3, 30 }, /* SD3_CMD */
4943 { RCAR_GP_PIN(4, 7), PU3, 29 }, /* SD3_CLK */
4944 { RCAR_GP_PIN(4, 6), PU3, 28 }, /* SD2_DS */
4945 { RCAR_GP_PIN(4, 5), PU3, 27 }, /* SD2_DAT3 */
4946 { RCAR_GP_PIN(4, 4), PU3, 26 }, /* SD2_DAT2 */
4947 { RCAR_GP_PIN(4, 3), PU3, 25 }, /* SD2_DAT1 */
4948 { RCAR_GP_PIN(4, 2), PU3, 24 }, /* SD2_DAT0 */
4949 { RCAR_GP_PIN(4, 1), PU3, 23 }, /* SD2_CMD */
4950 { RCAR_GP_PIN(4, 0), PU3, 22 }, /* SD2_CLK */
4951 { RCAR_GP_PIN(3, 11), PU3, 21 }, /* SD1_DAT3 */
4952 { RCAR_GP_PIN(3, 10), PU3, 20 }, /* SD1_DAT2 */
4953 { RCAR_GP_PIN(3, 9), PU3, 19 }, /* SD1_DAT1 */
4954 { RCAR_GP_PIN(3, 8), PU3, 18 }, /* SD1_DAT0 */
4955 { RCAR_GP_PIN(3, 7), PU3, 17 }, /* SD1_CMD */
4956 { RCAR_GP_PIN(3, 6), PU3, 16 }, /* SD1_CLK */
4957 { RCAR_GP_PIN(3, 5), PU3, 15 }, /* SD0_DAT3 */
4958 { RCAR_GP_PIN(3, 4), PU3, 14 }, /* SD0_DAT2 */
4959 { RCAR_GP_PIN(3, 3), PU3, 13 }, /* SD0_DAT1 */
4960 { RCAR_GP_PIN(3, 2), PU3, 12 }, /* SD0_DAT0 */
4961 { RCAR_GP_PIN(3, 1), PU3, 11 }, /* SD0_CMD */
4962 { RCAR_GP_PIN(3, 0), PU3, 10 }, /* SD0_CLK */
4963 { PIN_A_NUMBER('T', 30), PU3, 9 }, /* ASEBRK */
4964 /* bit 8 n/a */
4965 { PIN_A_NUMBER('R', 29), PU3, 7 }, /* TDI */
4966 { PIN_A_NUMBER('R', 30), PU3, 6 }, /* TMS */
4967 { PIN_A_NUMBER('T', 27), PU3, 5 }, /* TCK */
4968 { PIN_A_NUMBER('R', 26), PU3, 4 }, /* TRST# */
4969 { PIN_A_NUMBER('D', 39), PU3, 3 }, /* EXTALR*/
4970 { PIN_A_NUMBER('D', 38), PU3, 2 }, /* FSCLKST */
4971 /* bit 1 n/a on M3*/
4972 { PIN_A_NUMBER('R', 8), PU3, 0 }, /* DU_DOTCLKIN2 */
4973
4974 { RCAR_GP_PIN(5, 19), PU4, 31 }, /* MSIOF0_SS1 */
4975 { RCAR_GP_PIN(5, 18), PU4, 30 }, /* MSIOF0_SYNC */
4976 { RCAR_GP_PIN(5, 17), PU4, 29 }, /* MSIOF0_SCK */
4977 { RCAR_GP_PIN(5, 16), PU4, 28 }, /* HRTS0_N */
4978 { RCAR_GP_PIN(5, 15), PU4, 27 }, /* HCTS0_N */
4979 { RCAR_GP_PIN(5, 14), PU4, 26 }, /* HTX0 */
4980 { RCAR_GP_PIN(5, 13), PU4, 25 }, /* HRX0 */
4981 { RCAR_GP_PIN(5, 12), PU4, 24 }, /* HSCK0 */
4982 { RCAR_GP_PIN(5, 11), PU4, 23 }, /* RX2_A */
4983 { RCAR_GP_PIN(5, 10), PU4, 22 }, /* TX2_A */
4984 { RCAR_GP_PIN(5, 9), PU4, 21 }, /* SCK2 */
4985 { RCAR_GP_PIN(5, 8), PU4, 20 }, /* RTS1_N_TANS */
4986 { RCAR_GP_PIN(5, 7), PU4, 19 }, /* CTS1_N */
4987 { RCAR_GP_PIN(5, 6), PU4, 18 }, /* TX1_A */
4988 { RCAR_GP_PIN(5, 5), PU4, 17 }, /* RX1_A */
4989 { RCAR_GP_PIN(5, 4), PU4, 16 }, /* RTS0_N_TANS */
4990 { RCAR_GP_PIN(5, 3), PU4, 15 }, /* CTS0_N */
4991 { RCAR_GP_PIN(5, 2), PU4, 14 }, /* TX0 */
4992 { RCAR_GP_PIN(5, 1), PU4, 13 }, /* RX0 */
4993 { RCAR_GP_PIN(5, 0), PU4, 12 }, /* SCK0 */
4994 { RCAR_GP_PIN(3, 15), PU4, 11 }, /* SD1_WP */
4995 { RCAR_GP_PIN(3, 14), PU4, 10 }, /* SD1_CD */
4996 { RCAR_GP_PIN(3, 13), PU4, 9 }, /* SD0_WP */
4997 { RCAR_GP_PIN(3, 12), PU4, 8 }, /* SD0_CD */
4998 { RCAR_GP_PIN(4, 17), PU4, 7 }, /* SD3_DS */
4999 { RCAR_GP_PIN(4, 16), PU4, 6 }, /* SD3_DAT7 */
5000 { RCAR_GP_PIN(4, 15), PU4, 5 }, /* SD3_DAT6 */
5001 { RCAR_GP_PIN(4, 14), PU4, 4 }, /* SD3_DAT5 */
5002 { RCAR_GP_PIN(4, 13), PU4, 3 }, /* SD3_DAT4 */
5003 { RCAR_GP_PIN(4, 12), PU4, 2 }, /* SD3_DAT3 */
5004 { RCAR_GP_PIN(4, 11), PU4, 1 }, /* SD3_DAT2 */
5005 { RCAR_GP_PIN(4, 10), PU4, 0 }, /* SD3_DAT1 */
5006
5007 { RCAR_GP_PIN(6, 24), PU5, 31 }, /* USB0_PWEN */
5008 { RCAR_GP_PIN(6, 23), PU5, 30 }, /* AUDIO_CLKB_B */
5009 { RCAR_GP_PIN(6, 22), PU5, 29 }, /* AUDIO_CLKA_A */
5010 { RCAR_GP_PIN(6, 21), PU5, 28 }, /* SSI_SDATA9_A */
5011 { RCAR_GP_PIN(6, 20), PU5, 27 }, /* SSI_SDATA8 */
5012 { RCAR_GP_PIN(6, 19), PU5, 26 }, /* SSI_SDATA7 */
5013 { RCAR_GP_PIN(6, 18), PU5, 25 }, /* SSI_WS78 */
5014 { RCAR_GP_PIN(6, 17), PU5, 24 }, /* SSI_SCK78 */
5015 { RCAR_GP_PIN(6, 16), PU5, 23 }, /* SSI_SDATA6 */
5016 { RCAR_GP_PIN(6, 15), PU5, 22 }, /* SSI_WS6 */
5017 { RCAR_GP_PIN(6, 14), PU5, 21 }, /* SSI_SCK6 */
5018 { RCAR_GP_PIN(6, 13), PU5, 20 }, /* SSI_SDATA5 */
5019 { RCAR_GP_PIN(6, 12), PU5, 19 }, /* SSI_WS5 */
5020 { RCAR_GP_PIN(6, 11), PU5, 18 }, /* SSI_SCK5 */
5021 { RCAR_GP_PIN(6, 10), PU5, 17 }, /* SSI_SDATA4 */
5022 { RCAR_GP_PIN(6, 9), PU5, 16 }, /* SSI_WS4 */
5023 { RCAR_GP_PIN(6, 8), PU5, 15 }, /* SSI_SCK4 */
5024 { RCAR_GP_PIN(6, 7), PU5, 14 }, /* SSI_SDATA3 */
5025 { RCAR_GP_PIN(6, 6), PU5, 13 }, /* SSI_WS34 */
5026 { RCAR_GP_PIN(6, 5), PU5, 12 }, /* SSI_SCK34 */
5027 { RCAR_GP_PIN(6, 4), PU5, 11 }, /* SSI_SDATA2_A */
5028 { RCAR_GP_PIN(6, 3), PU5, 10 }, /* SSI_SDATA1_A */
5029 { RCAR_GP_PIN(6, 2), PU5, 9 }, /* SSI_SDATA0 */
5030 { RCAR_GP_PIN(6, 1), PU5, 8 }, /* SSI_WS01239 */
5031 { RCAR_GP_PIN(6, 0), PU5, 7 }, /* SSI_SCK01239 */
5032 { PIN_NUMBER('H', 37), PU5, 6 }, /* MLB_REF */
5033 { RCAR_GP_PIN(5, 25), PU5, 5 }, /* MLB_DAT */
5034 { RCAR_GP_PIN(5, 24), PU5, 4 }, /* MLB_SIG */
5035 { RCAR_GP_PIN(5, 23), PU5, 3 }, /* MLB_CLK */
5036 { RCAR_GP_PIN(5, 22), PU5, 2 }, /* MSIOF0_RXD */
5037 { RCAR_GP_PIN(5, 21), PU5, 1 }, /* MSIOF0_SS2 */
5038 { RCAR_GP_PIN(5, 20), PU5, 0 }, /* MSIOF0_TXD */
5039
5040 { RCAR_GP_PIN(6, 31), PU6, 6 }, /* GP6_31 */
5041 { RCAR_GP_PIN(6, 30), PU6, 5 }, /* GP6_30 */
5042 { RCAR_GP_PIN(6, 29), PU6, 4 }, /* USB30_OVC */
5043 { RCAR_GP_PIN(6, 28), PU6, 3 }, /* USB30_PWEN */
5044 { RCAR_GP_PIN(6, 27), PU6, 2 }, /* USB1_OVC */
5045 { RCAR_GP_PIN(6, 26), PU6, 1 }, /* USB1_PWEN */
5046 { RCAR_GP_PIN(6, 25), PU6, 0 }, /* USB0_OVC */
5047};
5048
5049static unsigned int r8a7796_pinmux_get_bias(struct sh_pfc *pfc,
5050 unsigned int pin)
5051{
5052 const struct sh_pfc_bias_info *info;
5053 u32 reg;
5054 u32 bit;
5055
5056 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5057 if (!info)
5058 return PIN_CONFIG_BIAS_DISABLE;
5059
5060 reg = info->reg;
5061 bit = BIT(info->bit);
5062
5063 if (!(sh_pfc_read_reg(pfc, PUEN + reg, 32) & bit))
5064 return PIN_CONFIG_BIAS_DISABLE;
5065 else if (sh_pfc_read_reg(pfc, PUD + reg, 32) & bit)
5066 return PIN_CONFIG_BIAS_PULL_UP;
5067 else
5068 return PIN_CONFIG_BIAS_PULL_DOWN;
5069}
5070
5071static void r8a7796_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
5072 unsigned int bias)
5073{
5074 const struct sh_pfc_bias_info *info;
5075 u32 enable, updown;
5076 u32 reg;
5077 u32 bit;
5078
5079 info = sh_pfc_pin_to_bias_info(bias_info, ARRAY_SIZE(bias_info), pin);
5080 if (!info)
5081 return;
5082
5083 reg = info->reg;
5084 bit = BIT(info->bit);
5085
5086 enable = sh_pfc_read_reg(pfc, PUEN + reg, 32) & ~bit;
5087 if (bias != PIN_CONFIG_BIAS_DISABLE)
5088 enable |= bit;
5089
5090 updown = sh_pfc_read_reg(pfc, PUD + reg, 32) & ~bit;
5091 if (bias == PIN_CONFIG_BIAS_PULL_UP)
5092 updown |= bit;
5093
5094 sh_pfc_write_reg(pfc, PUD + reg, 32, updown);
5095 sh_pfc_write_reg(pfc, PUEN + reg, 32, enable);
5096}
5097
c5901bdc
SH		 5098static const struct sh_pfc_soc_operations r8a7796_pinmux_ops = {
5099 .pin_to_pocctrl = r8a7796_pin_to_pocctrl,
2d40bd24
NS		 5100 .get_bias = r8a7796_pinmux_get_bias,
5101 .set_bias = r8a7796_pinmux_set_bias,
c5901bdc
SH		 5102};
5103
f9aece73
TK		 5104const struct sh_pfc_soc_info r8a7796_pinmux_info = {
5105 .name = "r8a77960_pfc",
c5901bdc 5106 .ops = &r8a7796_pinmux_ops,
f9aece73
TK		 5107 .unlock_reg = 0xe6060000, /* PMMR */
5108
5109 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5110
5111 .pins = pinmux_pins,
5112 .nr_pins = ARRAY_SIZE(pinmux_pins),
5113 .groups = pinmux_groups,
5114 .nr_groups = ARRAY_SIZE(pinmux_groups),
5115 .functions = pinmux_functions,
5116 .nr_functions = ARRAY_SIZE(pinmux_functions),
5117
5118 .cfg_regs = pinmux_config_regs,
9e35d6fa 5119 .drive_regs = pinmux_drive_regs,
f9aece73
TK		 5120
5121 .pinmux_data = pinmux_data,
5122 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5123};
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