[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"
#include "../core.h"
#include "../pinconf.h"

struct sh_pfc_pin_config {
	u32 type;
};

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct pinctrl_desc pctl_desc;

	struct sh_pfc *pfc;

	struct pinctrl_pin_desc *pins;
	struct sh_pfc_pin_config *configs;
};

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_groups;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->groups[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = pmx->pfc->info->groups[selector].pins;
	*num_pins = pmx->pfc->info->groups[selector].nr_pins;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->functions[selector].name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
				      unsigned selector,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = pmx->pfc->info->functions[selector].groups;
	*num_groups = pmx->pfc->info->functions[selector].nr_groups;

	return 0;
}

static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
			      unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;
	int ret = 0;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
		if (ret < 0)
			break;
	}

	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
				unsigned group)
{
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	switch (cfg->type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_OUTPUT:
		break;
	case PINMUX_TYPE_FUNCTION:
	default:
		pr_err("Unsupported mux type (%d), bailing...\n", cfg->type);
		ret = -ENOTSUPP;
		goto err;
	}

	ret = 0;

err:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	unsigned int mark = pin->enum_id;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	switch (cfg->type) {
	case PINMUX_TYPE_GPIO:
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		break;
	default:
		ret = -EINVAL;
		goto done;
	}

	ret = sh_pfc_config_mux(pfc, mark, new_type);
	if (ret < 0)
		goto done;

	cfg->type = new_type;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static const struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_func_enable,
	.disable		= sh_pfc_func_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
				    enum pin_config_param param)
{
	int idx = sh_pfc_get_pin_index(pfc, _pin);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		return true;

	case PIN_CONFIG_BIAS_PULL_UP:
		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;

	default:
		return false;
	}
}

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(*config);
	unsigned long flags;
	unsigned int bias;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
		if (!pfc->info->ops || !pfc->info->ops->get_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		bias = pfc->info->ops->get_bias(pfc, _pin);
		spin_unlock_irqrestore(&pfc->lock, flags);

		if (bias != param)
			return -EINVAL;

		*config = 0;
		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(config);
	unsigned long flags;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
	case PIN_CONFIG_BIAS_DISABLE:
		if (!pfc->info->ops || !pfc->info->ops->set_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		pfc->info->ops->set_bias(pfc, _pin, param);
		spin_unlock_irqrestore(&pfc->lock, flags);

		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
				    unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	const unsigned int *pins;
	unsigned int num_pins;
	unsigned int i;

	pins = pmx->pfc->info->groups[group].pins;
	num_pins = pmx->pfc->info->groups[group].nr_pins;

	for (i = 0; i < num_pins; ++i)
		sh_pfc_pinconf_set(pctldev, pins[i], config);

	return 0;
}

static const struct pinconf_ops sh_pfc_pinconf_ops = {
	.is_generic			= true,
	.pin_config_get			= sh_pfc_pinconf_get,
	.pin_config_set			= sh_pfc_pinconf_set,
	.pin_config_group_set		= sh_pfc_pinconf_group_set,
	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
};

/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
	const struct pinmux_range *ranges;
	struct pinmux_range def_range;
	unsigned int nr_ranges;
	unsigned int nr_pins;
	unsigned int i;

	if (pfc->info->ranges == NULL) {
		def_range.begin = 0;
		def_range.end = pfc->info->nr_pins - 1;
		ranges = &def_range;
		nr_ranges = 1;
	} else {
		ranges = pfc->info->ranges;
		nr_ranges = pfc->info->nr_ranges;
	}

	pmx->pins = devm_kzalloc(pfc->dev,
				 sizeof(*pmx->pins) * pfc->info->nr_pins,
				 GFP_KERNEL);
	if (unlikely(!pmx->pins))
		return -ENOMEM;

	pmx->configs = devm_kzalloc(pfc->dev,
				    sizeof(*pmx->configs) * pfc->info->nr_pins,
				    GFP_KERNEL);
	if (unlikely(!pmx->configs))
		return -ENOMEM;

	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
		const struct pinmux_range *range = &ranges[i];
		unsigned int number;

		for (number = range->begin; number <= range->end;
		     number++, nr_pins++) {
			struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
			struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
			const struct sh_pfc_pin *info =
				&pfc->info->pins[nr_pins];

			pin->number = number;
			pin->name = info->name;
			cfg->type = PINMUX_TYPE_GPIO;
		}
	}

	pfc->nr_pins = ranges[nr_ranges-1].end + 1;

	return nr_ranges;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx;
	int nr_ranges;

	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
	if (unlikely(!pmx))
		return -ENOMEM;

	pmx->pfc = pfc;
	pfc->pinctrl = pmx;

	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	if (unlikely(nr_ranges < 0))
		return nr_ranges;

	pmx->pctl_desc.name = DRV_NAME;
	pmx->pctl_desc.owner = THIS_MODULE;
	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
	pmx->pctl_desc.pins = pmx->pins;
	pmx->pctl_desc.npins = pfc->info->nr_pins;

	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
	if (pmx->pctl == NULL)
		return -EINVAL;

	return 0;
}

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;

	pinctrl_unregister(pmx->pctl);

	pfc->pinctrl = NULL;
	return 0;
}
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110	10
c6193eac	11	#define DRV_NAME "sh-pfc"
f9492fda	12	#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
ca5481c6	13
1724acfd	14	#include <linux/device.h>
90efde22	15	#include <linux/err.h>
ca5481c6 PM	16	#include <linux/init.h>
ca5481c6 PM	17	#include <linux/module.h>
ca5481c6	18	#include <linux/pinctrl/consumer.h>
ca5481c6	19	#include <linux/pinctrl/pinconf.h>
ca5481c6	20	#include <linux/pinctrl/pinconf-generic.h>
90efde22 LP	21	#include <linux/pinctrl/pinctrl.h>
90efde22 LP	22	#include <linux/pinctrl/pinmux.h>
90efde22 LP	23	#include <linux/slab.h>
90efde22 LP	24	#include <linux/spinlock.h>
ca5481c6	25
f9165132	26	#include "core.h"
c58d9c1b LP	27	#include "../core.h"
c58d9c1b LP	28	#include "../pinconf.h"
f9165132	29
1a0039dc LP	30	struct sh_pfc_pin_config {
	31	u32 type;
	32	};
	33
ca5481c6 PM	34	struct sh_pfc_pinctrl {
ca5481c6 PM	35	struct pinctrl_dev *pctl;
dcc427e1	36	struct pinctrl_desc pctl_desc;
dcc427e1	37
ca5481c6 PM	38	struct sh_pfc *pfc;
ca5481c6 PM	39
3d8d9f1d	40	struct pinctrl_pin_desc *pins;
1a0039dc	41	struct sh_pfc_pin_config *configs;
ca5481c6 PM	42	};
ca5481c6 PM	43
e3f805e8	44	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	45	{
e3f805e8 PM	46	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	47
3d8d9f1d	48	return pmx->pfc->info->nr_groups;
ca5481c6 PM	49	}
ca5481c6 PM	50
e3f805e8	51	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	52	unsigned selector)
ca5481c6 PM	53	{
e3f805e8 PM	54	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	55
3d8d9f1d	56	return pmx->pfc->info->groups[selector].name;
ca5481c6 PM	57	}
ca5481c6 PM	58
3d8d9f1d	59	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	60	const unsigned *pins, unsigned num_pins)
ca5481c6 PM	61	{
e3f805e8 PM	62	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	63
3d8d9f1d LP	64	*pins = pmx->pfc->info->groups[selector].pins;
3d8d9f1d LP	65	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
e3f805e8 PM	66
e3f805e8 PM	67	return 0;
ca5481c6 PM	68	}
ca5481c6 PM	69
fdd85ec3 PM	70	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	71	unsigned offset)
	72	{
	73	seq_printf(s, "%s", DRV_NAME);
	74	}
	75
fe330ce8	76	static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	77	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	78	.get_group_name = sh_pfc_get_group_name,
ca5481c6	79	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	80	.pin_dbg_show = sh_pfc_pin_dbg_show,
ca5481c6 PM	81	};
ca5481c6 PM	82
d93a891f PM	83	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	84	{
	85	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	86
3d8d9f1d	87	return pmx->pfc->info->nr_functions;
d93a891f PM	88	}
	89
	90	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	91	unsigned selector)
	92	{
	93	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	94
3d8d9f1d	95	return pmx->pfc->info->functions[selector].name;
d93a891f	96	}
ca5481c6	97
3d8d9f1d LP	98	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
3d8d9f1d LP	99	unsigned selector,
ca5481c6 PM	100	const char * const **groups,
	101	unsigned * const num_groups)
	102	{
d93a891f PM	103	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
d93a891f PM	104
3d8d9f1d LP	105	*groups = pmx->pfc->info->functions[selector].groups;
3d8d9f1d LP	106	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
d93a891f	107
ca5481c6 PM	108	return 0;
	109	}
	110
3d8d9f1d	111	static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	112	unsigned group)
ca5481c6 PM	113	{
3d8d9f1d LP	114	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	115	struct sh_pfc *pfc = pmx->pfc;
	116	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	117	unsigned long flags;
	118	unsigned int i;
b705c054	119	int ret = 0;
3d8d9f1d LP	120
	121	spin_lock_irqsave(&pfc->lock, flags);
	122
	123	for (i = 0; i < grp->nr_pins; ++i) {
b705c054 LP	124	ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
	125	if (ret < 0)
	126	break;
3d8d9f1d LP	127	}
3d8d9f1d LP	128
3d8d9f1d LP	129	spin_unlock_irqrestore(&pfc->lock, flags);
3d8d9f1d LP	130	return ret;
ca5481c6 PM	131	}
ca5481c6 PM	132
3d8d9f1d	133	static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	134	unsigned group)
	135	{
	136	}
	137
	138	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	139	struct pinctrl_gpio_range *range,
	140	unsigned offset)
	141	{
	142	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	143	struct sh_pfc *pfc = pmx->pfc;
1a0039dc LP	144	int idx = sh_pfc_get_pin_index(pfc, offset);
1a0039dc LP	145	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
ca5481c6	146	unsigned long flags;
1a0039dc	147	int ret;
ca5481c6 PM	148
	149	spin_lock_irqsave(&pfc->lock, flags);
	150
1a0039dc	151	switch (cfg->type) {
d93a891f	152	case PINMUX_TYPE_GPIO:
16d74ebe PM	153	case PINMUX_TYPE_INPUT:
16d74ebe PM	154	case PINMUX_TYPE_OUTPUT:
d93a891f	155	break;
2119f7c9	156	case PINMUX_TYPE_FUNCTION:
d93a891f	157	default:
1a0039dc	158	pr_err("Unsupported mux type (%d), bailing...\n", cfg->type);
077664a2 LP	159	ret = -ENOTSUPP;
077664a2 LP	160	goto err;
d93a891f	161	}
ca5481c6 PM	162
	163	ret = 0;
	164
	165	err:
	166	spin_unlock_irqrestore(&pfc->lock, flags);
	167
	168	return ret;
	169	}
	170
	171	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	172	struct pinctrl_gpio_range *range,
	173	unsigned offset)
	174	{
ca5481c6 PM	175	}
	176
	177	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	178	struct pinctrl_gpio_range *range,
	179	unsigned offset, bool input)
	180	{
	181	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0d00f00a LP	182	struct sh_pfc *pfc = pmx->pfc;
	183	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	184	int idx = sh_pfc_get_pin_index(pfc, offset);
	185	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	186	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	187	unsigned int mark = pin->enum_id;
	188	unsigned long flags;
	189	int ret;
ca5481c6	190
0d00f00a LP	191	spin_lock_irqsave(&pfc->lock, flags);
	192
	193	switch (cfg->type) {
	194	case PINMUX_TYPE_GPIO:
	195	case PINMUX_TYPE_OUTPUT:
	196	case PINMUX_TYPE_INPUT:
	197	case PINMUX_TYPE_INPUT_PULLUP:
	198	case PINMUX_TYPE_INPUT_PULLDOWN:
	199	break;
	200	default:
	201	ret = -EINVAL;
	202	goto done;
	203	}
	204
	205	ret = sh_pfc_config_mux(pfc, mark, new_type);
	206	if (ret < 0)
	207	goto done;
	208
	209	cfg->type = new_type;
	210
	211	done:
	212	spin_unlock_irqrestore(&pfc->lock, flags);
	213
	214	return ret;
ca5481c6 PM	215	}
ca5481c6 PM	216
fe330ce8	217	static const struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	218	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	219	.get_function_name = sh_pfc_get_function_name,
ca5481c6	220	.get_function_groups = sh_pfc_get_function_groups,
3d8d9f1d LP	221	.enable = sh_pfc_func_enable,
3d8d9f1d LP	222	.disable = sh_pfc_func_disable,
ca5481c6 PM	223	.gpio_request_enable = sh_pfc_gpio_request_enable,
	224	.gpio_disable_free = sh_pfc_gpio_disable_free,
	225	.gpio_set_direction = sh_pfc_gpio_set_direction,
	226	};
	227
c58d9c1b LP	228	/* Check whether the requested parameter is supported for a pin. */
	229	static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
	230	enum pin_config_param param)
	231	{
	232	int idx = sh_pfc_get_pin_index(pfc, _pin);
	233	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	234
	235	switch (param) {
	236	case PIN_CONFIG_BIAS_DISABLE:
	237	return true;
	238
	239	case PIN_CONFIG_BIAS_PULL_UP:
	240	return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
	241
	242	case PIN_CONFIG_BIAS_PULL_DOWN:
	243	return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
	244
	245	default:
	246	return false;
	247	}
	248	}
	249
934cb02b	250	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	251	unsigned long *config)
ca5481c6 PM	252	{
fdd85ec3 PM	253	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	254	struct sh_pfc *pfc = pmx->pfc;
c58d9c1b LP	255	enum pin_config_param param = pinconf_to_config_param(*config);
	256	unsigned long flags;
	257	unsigned int bias;
	258
	259	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
	260	return -ENOTSUPP;
	261
	262	switch (param) {
	263	case PIN_CONFIG_BIAS_DISABLE:
	264	case PIN_CONFIG_BIAS_PULL_UP:
	265	case PIN_CONFIG_BIAS_PULL_DOWN:
	266	if (!pfc->info->ops \|\| !pfc->info->ops->get_bias)
	267	return -ENOTSUPP;
	268
	269	spin_lock_irqsave(&pfc->lock, flags);
	270	bias = pfc->info->ops->get_bias(pfc, _pin);
	271	spin_unlock_irqrestore(&pfc->lock, flags);
	272
	273	if (bias != param)
	274	return -EINVAL;
	275
	276	*config = 0;
	277	break;
d93a891f	278
c58d9c1b LP	279	default:
	280	return -ENOTSUPP;
	281	}
d93a891f	282
fdd85ec3	283	return 0;
ca5481c6 PM	284	}
ca5481c6 PM	285
c58d9c1b	286	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	287	unsigned long config)
ca5481c6 PM	288	{
fdd85ec3	289	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
c58d9c1b LP	290	struct sh_pfc *pfc = pmx->pfc;
	291	enum pin_config_param param = pinconf_to_config_param(config);
	292	unsigned long flags;
fdd85ec3	293
c58d9c1b LP	294	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
c58d9c1b LP	295	return -ENOTSUPP;
fdd85ec3	296
c58d9c1b LP	297	switch (param) {
	298	case PIN_CONFIG_BIAS_PULL_UP:
	299	case PIN_CONFIG_BIAS_PULL_DOWN:
	300	case PIN_CONFIG_BIAS_DISABLE:
	301	if (!pfc->info->ops \|\| !pfc->info->ops->set_bias)
	302	return -ENOTSUPP;
	303
	304	spin_lock_irqsave(&pfc->lock, flags);
	305	pfc->info->ops->set_bias(pfc, _pin, param);
	306	spin_unlock_irqrestore(&pfc->lock, flags);
	307
	308	break;
	309
	310	default:
	311	return -ENOTSUPP;
	312	}
	313
	314	return 0;
fdd85ec3 PM	315	}
fdd85ec3 PM	316
c58d9c1b LP	317	static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
c58d9c1b LP	318	unsigned long config)
fdd85ec3	319	{
c58d9c1b LP	320	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	321	const unsigned int *pins;
	322	unsigned int num_pins;
	323	unsigned int i;
	324
	325	pins = pmx->pfc->info->groups[group].pins;
	326	num_pins = pmx->pfc->info->groups[group].nr_pins;
	327
	328	for (i = 0; i < num_pins; ++i)
	329	sh_pfc_pinconf_set(pctldev, pins[i], config);
	330
	331	return 0;
ca5481c6 PM	332	}
ca5481c6 PM	333
fe330ce8	334	static const struct pinconf_ops sh_pfc_pinconf_ops = {
c58d9c1b LP	335	.is_generic = true,
	336	.pin_config_get = sh_pfc_pinconf_get,
	337	.pin_config_set = sh_pfc_pinconf_set,
	338	.pin_config_group_set = sh_pfc_pinconf_group_set,
	339	.pin_config_config_dbg_show = pinconf_generic_dump_config,
ca5481c6 PM	340	};
ca5481c6 PM	341
63d57383 LP	342	/* PFC ranges -> pinctrl pin descs */
63d57383 LP	343	static int sh_pfc_map_pins(struct sh_pfc pfc, struct sh_pfc_pinctrl pmx)
ca5481c6	344	{
63d57383 LP	345	const struct pinmux_range *ranges;
	346	struct pinmux_range def_range;
	347	unsigned int nr_ranges;
	348	unsigned int nr_pins;
	349	unsigned int i;
	350
	351	if (pfc->info->ranges == NULL) {
	352	def_range.begin = 0;
	353	def_range.end = pfc->info->nr_pins - 1;
	354	ranges = &def_range;
	355	nr_ranges = 1;
	356	} else {
	357	ranges = pfc->info->ranges;
	358	nr_ranges = pfc->info->nr_ranges;
	359	}
ca5481c6	360
3d8d9f1d LP	361	pmx->pins = devm_kzalloc(pfc->dev,
3d8d9f1d LP	362	sizeof(pmx->pins) pfc->info->nr_pins,
1724acfd	363	GFP_KERNEL);
3d8d9f1d	364	if (unlikely(!pmx->pins))
ca5481c6	365	return -ENOMEM;
ca5481c6	366
1a0039dc LP	367	pmx->configs = devm_kzalloc(pfc->dev,
	368	sizeof(pmx->configs) pfc->info->nr_pins,
	369	GFP_KERNEL);
	370	if (unlikely(!pmx->configs))
	371	return -ENOMEM;
	372
63d57383 LP	373	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
	374	const struct pinmux_range *range = &ranges[i];
	375	unsigned int number;
	376
	377	for (number = range->begin; number <= range->end;
	378	number++, nr_pins++) {
1a0039dc	379	struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
3d8d9f1d	380	struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
cd3c1bee LP	381	const struct sh_pfc_pin *info =
cd3c1bee LP	382	&pfc->info->pins[nr_pins];
ca5481c6	383
63d57383 LP	384	pin->number = number;
63d57383 LP	385	pin->name = info->name;
1a0039dc	386	cfg->type = PINMUX_TYPE_GPIO;
63d57383	387	}
ca5481c6 PM	388	}
ca5481c6 PM	389
63d57383 LP	390	pfc->nr_pins = ranges[nr_ranges-1].end + 1;
	391
	392	return nr_ranges;
ca5481c6 PM	393	}
ca5481c6 PM	394
c6193eac	395	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
ca5481c6	396	{
c6193eac	397	struct sh_pfc_pinctrl *pmx;
63d57383	398	int nr_ranges;
ca5481c6	399
1724acfd	400	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
c6193eac LP	401	if (unlikely(!pmx))
	402	return -ENOMEM;
	403
c6193eac LP	404	pmx->pfc = pfc;
c6193eac LP	405	pfc->pinctrl = pmx;
ca5481c6	406
63d57383 LP	407	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	408	if (unlikely(nr_ranges < 0))
	409	return nr_ranges;
ca5481c6	410
dcc427e1 LP	411	pmx->pctl_desc.name = DRV_NAME;
	412	pmx->pctl_desc.owner = THIS_MODULE;
	413	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	414	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	415	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
3d8d9f1d	416	pmx->pctl_desc.pins = pmx->pins;
63d57383	417	pmx->pctl_desc.npins = pfc->info->nr_pins;
dcc427e1 LP	418
dcc427e1 LP	419	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
fd9d05b0 WY	420	if (pmx->pctl == NULL)
fd9d05b0 WY	421	return -EINVAL;
ca5481c6	422
ca5481c6	423	return 0;
ca5481c6 PM	424	}
ca5481c6 PM	425
c6193eac	426	int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
ca5481c6	427	{
c6193eac	428	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
ca5481c6	429
ca5481c6 PM	430	pinctrl_unregister(pmx->pctl);
ca5481c6 PM	431
c6193eac	432	pfc->pinctrl = NULL;
ca5481c6 PM	433	return 0;
ca5481c6 PM	434	}