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Commit | Line | Data |
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ca5481c6 PM |
1 | /* |
2 | * SuperH Pin Function Controller pinmux support. | |
3 | * | |
4 | * Copyright (C) 2012 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
54407110 | 10 | |
c6193eac | 11 | #define DRV_NAME "sh-pfc" |
ca5481c6 | 12 | |
1724acfd | 13 | #include <linux/device.h> |
90efde22 | 14 | #include <linux/err.h> |
ca5481c6 PM |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
ca5481c6 | 17 | #include <linux/pinctrl/consumer.h> |
ca5481c6 | 18 | #include <linux/pinctrl/pinconf.h> |
ca5481c6 | 19 | #include <linux/pinctrl/pinconf-generic.h> |
90efde22 LP |
20 | #include <linux/pinctrl/pinctrl.h> |
21 | #include <linux/pinctrl/pinmux.h> | |
90efde22 LP |
22 | #include <linux/slab.h> |
23 | #include <linux/spinlock.h> | |
ca5481c6 | 24 | |
f9165132 | 25 | #include "core.h" |
c58d9c1b LP |
26 | #include "../core.h" |
27 | #include "../pinconf.h" | |
f9165132 | 28 | |
1a0039dc LP |
29 | struct sh_pfc_pin_config { |
30 | u32 type; | |
31 | }; | |
32 | ||
ca5481c6 PM |
33 | struct sh_pfc_pinctrl { |
34 | struct pinctrl_dev *pctl; | |
dcc427e1 | 35 | struct pinctrl_desc pctl_desc; |
dcc427e1 | 36 | |
ca5481c6 PM |
37 | struct sh_pfc *pfc; |
38 | ||
3d8d9f1d | 39 | struct pinctrl_pin_desc *pins; |
1a0039dc | 40 | struct sh_pfc_pin_config *configs; |
ca5481c6 PM |
41 | }; |
42 | ||
e3f805e8 | 43 | static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) |
ca5481c6 | 44 | { |
e3f805e8 PM |
45 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
46 | ||
3d8d9f1d | 47 | return pmx->pfc->info->nr_groups; |
ca5481c6 PM |
48 | } |
49 | ||
e3f805e8 | 50 | static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, |
ca5481c6 PM |
51 | unsigned selector) |
52 | { | |
e3f805e8 PM |
53 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
54 | ||
3d8d9f1d | 55 | return pmx->pfc->info->groups[selector].name; |
ca5481c6 PM |
56 | } |
57 | ||
3d8d9f1d | 58 | static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
59 | const unsigned **pins, unsigned *num_pins) |
60 | { | |
e3f805e8 PM |
61 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
62 | ||
3d8d9f1d LP |
63 | *pins = pmx->pfc->info->groups[selector].pins; |
64 | *num_pins = pmx->pfc->info->groups[selector].nr_pins; | |
e3f805e8 PM |
65 | |
66 | return 0; | |
ca5481c6 PM |
67 | } |
68 | ||
fdd85ec3 PM |
69 | static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
70 | unsigned offset) | |
71 | { | |
72 | seq_printf(s, "%s", DRV_NAME); | |
73 | } | |
74 | ||
fe330ce8 | 75 | static const struct pinctrl_ops sh_pfc_pinctrl_ops = { |
e3f805e8 PM |
76 | .get_groups_count = sh_pfc_get_groups_count, |
77 | .get_group_name = sh_pfc_get_group_name, | |
ca5481c6 | 78 | .get_group_pins = sh_pfc_get_group_pins, |
fdd85ec3 | 79 | .pin_dbg_show = sh_pfc_pin_dbg_show, |
ca5481c6 PM |
80 | }; |
81 | ||
d93a891f PM |
82 | static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) |
83 | { | |
84 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
85 | ||
3d8d9f1d | 86 | return pmx->pfc->info->nr_functions; |
d93a891f PM |
87 | } |
88 | ||
89 | static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, | |
90 | unsigned selector) | |
91 | { | |
92 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
93 | ||
3d8d9f1d | 94 | return pmx->pfc->info->functions[selector].name; |
d93a891f | 95 | } |
ca5481c6 | 96 | |
3d8d9f1d LP |
97 | static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, |
98 | unsigned selector, | |
ca5481c6 PM |
99 | const char * const **groups, |
100 | unsigned * const num_groups) | |
101 | { | |
d93a891f PM |
102 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
103 | ||
3d8d9f1d LP |
104 | *groups = pmx->pfc->info->functions[selector].groups; |
105 | *num_groups = pmx->pfc->info->functions[selector].nr_groups; | |
d93a891f | 106 | |
ca5481c6 PM |
107 | return 0; |
108 | } | |
109 | ||
3d8d9f1d | 110 | static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
111 | unsigned group) |
112 | { | |
3d8d9f1d LP |
113 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
114 | struct sh_pfc *pfc = pmx->pfc; | |
115 | const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; | |
116 | unsigned long flags; | |
117 | unsigned int i; | |
b705c054 | 118 | int ret = 0; |
3d8d9f1d LP |
119 | |
120 | spin_lock_irqsave(&pfc->lock, flags); | |
121 | ||
9fddc4a5 LP |
122 | for (i = 0; i < grp->nr_pins; ++i) { |
123 | int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); | |
124 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
125 | ||
126 | if (cfg->type != PINMUX_TYPE_NONE) { | |
127 | ret = -EBUSY; | |
128 | goto done; | |
129 | } | |
130 | } | |
131 | ||
3d8d9f1d | 132 | for (i = 0; i < grp->nr_pins; ++i) { |
b705c054 LP |
133 | ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); |
134 | if (ret < 0) | |
135 | break; | |
3d8d9f1d LP |
136 | } |
137 | ||
9fddc4a5 | 138 | done: |
3d8d9f1d LP |
139 | spin_unlock_irqrestore(&pfc->lock, flags); |
140 | return ret; | |
ca5481c6 PM |
141 | } |
142 | ||
3d8d9f1d | 143 | static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
144 | unsigned group) |
145 | { | |
9fddc4a5 LP |
146 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
147 | struct sh_pfc *pfc = pmx->pfc; | |
148 | const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; | |
149 | unsigned long flags; | |
150 | unsigned int i; | |
151 | ||
152 | spin_lock_irqsave(&pfc->lock, flags); | |
153 | ||
154 | for (i = 0; i < grp->nr_pins; ++i) { | |
155 | int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); | |
156 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
157 | ||
158 | cfg->type = PINMUX_TYPE_NONE; | |
159 | } | |
160 | ||
161 | spin_unlock_irqrestore(&pfc->lock, flags); | |
ca5481c6 PM |
162 | } |
163 | ||
164 | static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, | |
165 | struct pinctrl_gpio_range *range, | |
166 | unsigned offset) | |
167 | { | |
168 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
169 | struct sh_pfc *pfc = pmx->pfc; | |
1a0039dc LP |
170 | int idx = sh_pfc_get_pin_index(pfc, offset); |
171 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
ca5481c6 | 172 | unsigned long flags; |
1a0039dc | 173 | int ret; |
ca5481c6 PM |
174 | |
175 | spin_lock_irqsave(&pfc->lock, flags); | |
176 | ||
9fddc4a5 | 177 | if (cfg->type != PINMUX_TYPE_NONE) { |
9a643c9a LP |
178 | dev_err(pfc->dev, |
179 | "Pin %u is busy, can't configure it as GPIO.\n", | |
180 | offset); | |
9fddc4a5 LP |
181 | ret = -EBUSY; |
182 | goto done; | |
d93a891f | 183 | } |
ca5481c6 | 184 | |
e3c47051 LP |
185 | if (!pfc->gpio) { |
186 | /* If GPIOs are handled externally the pin mux type need to be | |
187 | * set to GPIO here. | |
188 | */ | |
189 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
190 | ||
191 | ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); | |
192 | if (ret < 0) | |
193 | goto done; | |
194 | } | |
195 | ||
9fddc4a5 LP |
196 | cfg->type = PINMUX_TYPE_GPIO; |
197 | ||
ca5481c6 PM |
198 | ret = 0; |
199 | ||
9fddc4a5 | 200 | done: |
ca5481c6 PM |
201 | spin_unlock_irqrestore(&pfc->lock, flags); |
202 | ||
203 | return ret; | |
204 | } | |
205 | ||
206 | static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, | |
207 | struct pinctrl_gpio_range *range, | |
208 | unsigned offset) | |
209 | { | |
9fddc4a5 LP |
210 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
211 | struct sh_pfc *pfc = pmx->pfc; | |
212 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
213 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
214 | unsigned long flags; | |
215 | ||
216 | spin_lock_irqsave(&pfc->lock, flags); | |
217 | cfg->type = PINMUX_TYPE_NONE; | |
218 | spin_unlock_irqrestore(&pfc->lock, flags); | |
ca5481c6 PM |
219 | } |
220 | ||
221 | static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, | |
222 | struct pinctrl_gpio_range *range, | |
223 | unsigned offset, bool input) | |
224 | { | |
225 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
0d00f00a LP |
226 | struct sh_pfc *pfc = pmx->pfc; |
227 | int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; | |
228 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
0d00f00a | 229 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; |
9fddc4a5 | 230 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; |
0d00f00a | 231 | unsigned long flags; |
6dc9b455 | 232 | unsigned int dir; |
0d00f00a | 233 | int ret; |
ca5481c6 | 234 | |
6dc9b455 LP |
235 | /* Check if the requested direction is supported by the pin. Not all SoC |
236 | * provide pin config data, so perform the check conditionally. | |
237 | */ | |
238 | if (pin->configs) { | |
239 | dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; | |
240 | if (!(pin->configs & dir)) | |
241 | return -EINVAL; | |
242 | } | |
243 | ||
0d00f00a LP |
244 | spin_lock_irqsave(&pfc->lock, flags); |
245 | ||
9fddc4a5 | 246 | ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); |
0d00f00a LP |
247 | if (ret < 0) |
248 | goto done; | |
249 | ||
250 | cfg->type = new_type; | |
251 | ||
252 | done: | |
253 | spin_unlock_irqrestore(&pfc->lock, flags); | |
0d00f00a | 254 | return ret; |
ca5481c6 PM |
255 | } |
256 | ||
fe330ce8 | 257 | static const struct pinmux_ops sh_pfc_pinmux_ops = { |
d93a891f PM |
258 | .get_functions_count = sh_pfc_get_functions_count, |
259 | .get_function_name = sh_pfc_get_function_name, | |
ca5481c6 | 260 | .get_function_groups = sh_pfc_get_function_groups, |
3d8d9f1d LP |
261 | .enable = sh_pfc_func_enable, |
262 | .disable = sh_pfc_func_disable, | |
ca5481c6 PM |
263 | .gpio_request_enable = sh_pfc_gpio_request_enable, |
264 | .gpio_disable_free = sh_pfc_gpio_disable_free, | |
265 | .gpio_set_direction = sh_pfc_gpio_set_direction, | |
266 | }; | |
267 | ||
c58d9c1b LP |
268 | /* Check whether the requested parameter is supported for a pin. */ |
269 | static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, | |
270 | enum pin_config_param param) | |
271 | { | |
272 | int idx = sh_pfc_get_pin_index(pfc, _pin); | |
273 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
274 | ||
275 | switch (param) { | |
276 | case PIN_CONFIG_BIAS_DISABLE: | |
277 | return true; | |
278 | ||
279 | case PIN_CONFIG_BIAS_PULL_UP: | |
280 | return pin->configs & SH_PFC_PIN_CFG_PULL_UP; | |
281 | ||
282 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
283 | return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; | |
284 | ||
285 | default: | |
286 | return false; | |
287 | } | |
288 | } | |
289 | ||
934cb02b | 290 | static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, |
ca5481c6 PM |
291 | unsigned long *config) |
292 | { | |
fdd85ec3 PM |
293 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
294 | struct sh_pfc *pfc = pmx->pfc; | |
c58d9c1b LP |
295 | enum pin_config_param param = pinconf_to_config_param(*config); |
296 | unsigned long flags; | |
297 | unsigned int bias; | |
298 | ||
299 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) | |
300 | return -ENOTSUPP; | |
301 | ||
302 | switch (param) { | |
303 | case PIN_CONFIG_BIAS_DISABLE: | |
304 | case PIN_CONFIG_BIAS_PULL_UP: | |
305 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
306 | if (!pfc->info->ops || !pfc->info->ops->get_bias) | |
307 | return -ENOTSUPP; | |
308 | ||
309 | spin_lock_irqsave(&pfc->lock, flags); | |
310 | bias = pfc->info->ops->get_bias(pfc, _pin); | |
311 | spin_unlock_irqrestore(&pfc->lock, flags); | |
312 | ||
313 | if (bias != param) | |
314 | return -EINVAL; | |
315 | ||
316 | *config = 0; | |
317 | break; | |
d93a891f | 318 | |
c58d9c1b LP |
319 | default: |
320 | return -ENOTSUPP; | |
321 | } | |
d93a891f | 322 | |
fdd85ec3 | 323 | return 0; |
ca5481c6 PM |
324 | } |
325 | ||
c58d9c1b | 326 | static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, |
ca5481c6 PM |
327 | unsigned long config) |
328 | { | |
fdd85ec3 | 329 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
c58d9c1b LP |
330 | struct sh_pfc *pfc = pmx->pfc; |
331 | enum pin_config_param param = pinconf_to_config_param(config); | |
332 | unsigned long flags; | |
fdd85ec3 | 333 | |
c58d9c1b LP |
334 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) |
335 | return -ENOTSUPP; | |
fdd85ec3 | 336 | |
c58d9c1b LP |
337 | switch (param) { |
338 | case PIN_CONFIG_BIAS_PULL_UP: | |
339 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
340 | case PIN_CONFIG_BIAS_DISABLE: | |
341 | if (!pfc->info->ops || !pfc->info->ops->set_bias) | |
342 | return -ENOTSUPP; | |
343 | ||
344 | spin_lock_irqsave(&pfc->lock, flags); | |
345 | pfc->info->ops->set_bias(pfc, _pin, param); | |
346 | spin_unlock_irqrestore(&pfc->lock, flags); | |
347 | ||
348 | break; | |
349 | ||
350 | default: | |
351 | return -ENOTSUPP; | |
352 | } | |
353 | ||
354 | return 0; | |
fdd85ec3 PM |
355 | } |
356 | ||
c58d9c1b LP |
357 | static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
358 | unsigned long config) | |
fdd85ec3 | 359 | { |
c58d9c1b LP |
360 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
361 | const unsigned int *pins; | |
362 | unsigned int num_pins; | |
363 | unsigned int i; | |
364 | ||
365 | pins = pmx->pfc->info->groups[group].pins; | |
366 | num_pins = pmx->pfc->info->groups[group].nr_pins; | |
367 | ||
368 | for (i = 0; i < num_pins; ++i) | |
369 | sh_pfc_pinconf_set(pctldev, pins[i], config); | |
370 | ||
371 | return 0; | |
ca5481c6 PM |
372 | } |
373 | ||
fe330ce8 | 374 | static const struct pinconf_ops sh_pfc_pinconf_ops = { |
c58d9c1b LP |
375 | .is_generic = true, |
376 | .pin_config_get = sh_pfc_pinconf_get, | |
377 | .pin_config_set = sh_pfc_pinconf_set, | |
378 | .pin_config_group_set = sh_pfc_pinconf_group_set, | |
379 | .pin_config_config_dbg_show = pinconf_generic_dump_config, | |
ca5481c6 PM |
380 | }; |
381 | ||
63d57383 LP |
382 | /* PFC ranges -> pinctrl pin descs */ |
383 | static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) | |
ca5481c6 | 384 | { |
63d57383 LP |
385 | const struct pinmux_range *ranges; |
386 | struct pinmux_range def_range; | |
387 | unsigned int nr_ranges; | |
388 | unsigned int nr_pins; | |
389 | unsigned int i; | |
390 | ||
391 | if (pfc->info->ranges == NULL) { | |
392 | def_range.begin = 0; | |
393 | def_range.end = pfc->info->nr_pins - 1; | |
394 | ranges = &def_range; | |
395 | nr_ranges = 1; | |
396 | } else { | |
397 | ranges = pfc->info->ranges; | |
398 | nr_ranges = pfc->info->nr_ranges; | |
399 | } | |
ca5481c6 | 400 | |
3d8d9f1d LP |
401 | pmx->pins = devm_kzalloc(pfc->dev, |
402 | sizeof(*pmx->pins) * pfc->info->nr_pins, | |
1724acfd | 403 | GFP_KERNEL); |
3d8d9f1d | 404 | if (unlikely(!pmx->pins)) |
ca5481c6 | 405 | return -ENOMEM; |
ca5481c6 | 406 | |
1a0039dc LP |
407 | pmx->configs = devm_kzalloc(pfc->dev, |
408 | sizeof(*pmx->configs) * pfc->info->nr_pins, | |
409 | GFP_KERNEL); | |
410 | if (unlikely(!pmx->configs)) | |
411 | return -ENOMEM; | |
412 | ||
63d57383 LP |
413 | for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { |
414 | const struct pinmux_range *range = &ranges[i]; | |
415 | unsigned int number; | |
416 | ||
417 | for (number = range->begin; number <= range->end; | |
418 | number++, nr_pins++) { | |
1a0039dc | 419 | struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; |
3d8d9f1d | 420 | struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; |
cd3c1bee LP |
421 | const struct sh_pfc_pin *info = |
422 | &pfc->info->pins[nr_pins]; | |
ca5481c6 | 423 | |
63d57383 LP |
424 | pin->number = number; |
425 | pin->name = info->name; | |
9fddc4a5 | 426 | cfg->type = PINMUX_TYPE_NONE; |
63d57383 | 427 | } |
ca5481c6 PM |
428 | } |
429 | ||
63d57383 LP |
430 | pfc->nr_pins = ranges[nr_ranges-1].end + 1; |
431 | ||
432 | return nr_ranges; | |
ca5481c6 PM |
433 | } |
434 | ||
c6193eac | 435 | int sh_pfc_register_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 436 | { |
c6193eac | 437 | struct sh_pfc_pinctrl *pmx; |
63d57383 | 438 | int nr_ranges; |
ca5481c6 | 439 | |
1724acfd | 440 | pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); |
c6193eac LP |
441 | if (unlikely(!pmx)) |
442 | return -ENOMEM; | |
443 | ||
c6193eac LP |
444 | pmx->pfc = pfc; |
445 | pfc->pinctrl = pmx; | |
ca5481c6 | 446 | |
63d57383 LP |
447 | nr_ranges = sh_pfc_map_pins(pfc, pmx); |
448 | if (unlikely(nr_ranges < 0)) | |
449 | return nr_ranges; | |
ca5481c6 | 450 | |
dcc427e1 LP |
451 | pmx->pctl_desc.name = DRV_NAME; |
452 | pmx->pctl_desc.owner = THIS_MODULE; | |
453 | pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; | |
454 | pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; | |
455 | pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; | |
3d8d9f1d | 456 | pmx->pctl_desc.pins = pmx->pins; |
63d57383 | 457 | pmx->pctl_desc.npins = pfc->info->nr_pins; |
dcc427e1 LP |
458 | |
459 | pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); | |
fd9d05b0 WY |
460 | if (pmx->pctl == NULL) |
461 | return -EINVAL; | |
ca5481c6 | 462 | |
ca5481c6 | 463 | return 0; |
ca5481c6 PM |
464 | } |
465 | ||
c6193eac | 466 | int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 467 | { |
c6193eac | 468 | struct sh_pfc_pinctrl *pmx = pfc->pinctrl; |
ca5481c6 | 469 | |
ca5481c6 PM |
470 | pinctrl_unregister(pmx->pctl); |
471 | ||
c6193eac | 472 | pfc->pinctrl = NULL; |
ca5481c6 PM |
473 | return 0; |
474 | } |