[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"
#include "../core.h"
#include "../pinconf.h"

struct sh_pfc_pin_config {
	u32 type;
};

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct pinctrl_desc pctl_desc;

	struct sh_pfc *pfc;

	struct pinctrl_pin_desc *pins;
	struct sh_pfc_pin_config *configs;
};

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_groups;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->groups[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = pmx->pfc->info->groups[selector].pins;
	*num_pins = pmx->pfc->info->groups[selector].nr_pins;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->functions[selector].name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
				      unsigned selector,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = pmx->pfc->info->functions[selector].groups;
	*num_groups = pmx->pfc->info->functions[selector].nr_groups;

	return 0;
}

static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
			      unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;
	int ret = 0;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		if (cfg->type != PINMUX_TYPE_NONE) {
			ret = -EBUSY;
			goto done;
		}
	}

	for (i = 0; i < grp->nr_pins; ++i) {
		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
		if (ret < 0)
			break;
	}

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
				unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		cfg->type = PINMUX_TYPE_NONE;
	}

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	if (cfg->type != PINMUX_TYPE_NONE) {
		dev_err(pfc->dev,
			"Pin %u is busy, can't configure it as GPIO.\n",
			offset);
		ret = -EBUSY;
		goto done;
	}

	cfg->type = PINMUX_TYPE_GPIO;

	ret = 0;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;

	spin_lock_irqsave(&pfc->lock, flags);
	cfg->type = PINMUX_TYPE_NONE;
	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
	if (ret < 0)
		goto done;

	cfg->type = new_type;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static const struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_func_enable,
	.disable		= sh_pfc_func_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
				    enum pin_config_param param)
{
	int idx = sh_pfc_get_pin_index(pfc, _pin);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		return true;

	case PIN_CONFIG_BIAS_PULL_UP:
		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;

	default:
		return false;
	}
}

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(*config);
	unsigned long flags;
	unsigned int bias;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
		if (!pfc->info->ops || !pfc->info->ops->get_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		bias = pfc->info->ops->get_bias(pfc, _pin);
		spin_unlock_irqrestore(&pfc->lock, flags);

		if (bias != param)
			return -EINVAL;

		*config = 0;
		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(config);
	unsigned long flags;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
	case PIN_CONFIG_BIAS_DISABLE:
		if (!pfc->info->ops || !pfc->info->ops->set_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		pfc->info->ops->set_bias(pfc, _pin, param);
		spin_unlock_irqrestore(&pfc->lock, flags);

		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
				    unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	const unsigned int *pins;
	unsigned int num_pins;
	unsigned int i;

	pins = pmx->pfc->info->groups[group].pins;
	num_pins = pmx->pfc->info->groups[group].nr_pins;

	for (i = 0; i < num_pins; ++i)
		sh_pfc_pinconf_set(pctldev, pins[i], config);

	return 0;
}

static const struct pinconf_ops sh_pfc_pinconf_ops = {
	.is_generic			= true,
	.pin_config_get			= sh_pfc_pinconf_get,
	.pin_config_set			= sh_pfc_pinconf_set,
	.pin_config_group_set		= sh_pfc_pinconf_group_set,
	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
};

/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
	const struct pinmux_range *ranges;
	struct pinmux_range def_range;
	unsigned int nr_ranges;
	unsigned int nr_pins;
	unsigned int i;

	if (pfc->info->ranges == NULL) {
		def_range.begin = 0;
		def_range.end = pfc->info->nr_pins - 1;
		ranges = &def_range;
		nr_ranges = 1;
	} else {
		ranges = pfc->info->ranges;
		nr_ranges = pfc->info->nr_ranges;
	}

	pmx->pins = devm_kzalloc(pfc->dev,
				 sizeof(*pmx->pins) * pfc->info->nr_pins,
				 GFP_KERNEL);
	if (unlikely(!pmx->pins))
		return -ENOMEM;

	pmx->configs = devm_kzalloc(pfc->dev,
				    sizeof(*pmx->configs) * pfc->info->nr_pins,
				    GFP_KERNEL);
	if (unlikely(!pmx->configs))
		return -ENOMEM;

	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
		const struct pinmux_range *range = &ranges[i];
		unsigned int number;

		for (number = range->begin; number <= range->end;
		     number++, nr_pins++) {
			struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
			struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
			const struct sh_pfc_pin *info =
				&pfc->info->pins[nr_pins];

			pin->number = number;
			pin->name = info->name;
			cfg->type = PINMUX_TYPE_NONE;
		}
	}

	pfc->nr_pins = ranges[nr_ranges-1].end + 1;

	return nr_ranges;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx;
	int nr_ranges;

	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
	if (unlikely(!pmx))
		return -ENOMEM;

	pmx->pfc = pfc;
	pfc->pinctrl = pmx;

	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	if (unlikely(nr_ranges < 0))
		return nr_ranges;

	pmx->pctl_desc.name = DRV_NAME;
	pmx->pctl_desc.owner = THIS_MODULE;
	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
	pmx->pctl_desc.pins = pmx->pins;
	pmx->pctl_desc.npins = pfc->info->nr_pins;

	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
	if (pmx->pctl == NULL)
		return -EINVAL;

	return 0;
}

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;

	pinctrl_unregister(pmx->pctl);

	pfc->pinctrl = NULL;
	return 0;
}
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110	10
c6193eac	11	#define DRV_NAME "sh-pfc"
ca5481c6	12
1724acfd	13	#include <linux/device.h>
90efde22	14	#include <linux/err.h>
ca5481c6 PM	15	#include <linux/init.h>
ca5481c6 PM	16	#include <linux/module.h>
ca5481c6	17	#include <linux/pinctrl/consumer.h>
ca5481c6	18	#include <linux/pinctrl/pinconf.h>
ca5481c6	19	#include <linux/pinctrl/pinconf-generic.h>
90efde22 LP	20	#include <linux/pinctrl/pinctrl.h>
90efde22 LP	21	#include <linux/pinctrl/pinmux.h>
90efde22 LP	22	#include <linux/slab.h>
90efde22 LP	23	#include <linux/spinlock.h>
ca5481c6	24
f9165132	25	#include "core.h"
c58d9c1b LP	26	#include "../core.h"
c58d9c1b LP	27	#include "../pinconf.h"
f9165132	28
1a0039dc LP	29	struct sh_pfc_pin_config {
	30	u32 type;
	31	};
	32
ca5481c6 PM	33	struct sh_pfc_pinctrl {
ca5481c6 PM	34	struct pinctrl_dev *pctl;
dcc427e1	35	struct pinctrl_desc pctl_desc;
dcc427e1	36
ca5481c6 PM	37	struct sh_pfc *pfc;
ca5481c6 PM	38
3d8d9f1d	39	struct pinctrl_pin_desc *pins;
1a0039dc	40	struct sh_pfc_pin_config *configs;
ca5481c6 PM	41	};
ca5481c6 PM	42
e3f805e8	43	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	44	{
e3f805e8 PM	45	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	46
3d8d9f1d	47	return pmx->pfc->info->nr_groups;
ca5481c6 PM	48	}
ca5481c6 PM	49
e3f805e8	50	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	51	unsigned selector)
ca5481c6 PM	52	{
e3f805e8 PM	53	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	54
3d8d9f1d	55	return pmx->pfc->info->groups[selector].name;
ca5481c6 PM	56	}
ca5481c6 PM	57
3d8d9f1d	58	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	59	const unsigned *pins, unsigned num_pins)
ca5481c6 PM	60	{
e3f805e8 PM	61	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	62
3d8d9f1d LP	63	*pins = pmx->pfc->info->groups[selector].pins;
3d8d9f1d LP	64	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
e3f805e8 PM	65
e3f805e8 PM	66	return 0;
ca5481c6 PM	67	}
ca5481c6 PM	68
fdd85ec3 PM	69	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	70	unsigned offset)
	71	{
	72	seq_printf(s, "%s", DRV_NAME);
	73	}
	74
fe330ce8	75	static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	76	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	77	.get_group_name = sh_pfc_get_group_name,
ca5481c6	78	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	79	.pin_dbg_show = sh_pfc_pin_dbg_show,
ca5481c6 PM	80	};
ca5481c6 PM	81
d93a891f PM	82	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	83	{
	84	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	85
3d8d9f1d	86	return pmx->pfc->info->nr_functions;
d93a891f PM	87	}
	88
	89	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	90	unsigned selector)
	91	{
	92	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	93
3d8d9f1d	94	return pmx->pfc->info->functions[selector].name;
d93a891f	95	}
ca5481c6	96
3d8d9f1d LP	97	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
3d8d9f1d LP	98	unsigned selector,
ca5481c6 PM	99	const char * const **groups,
	100	unsigned * const num_groups)
	101	{
d93a891f PM	102	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
d93a891f PM	103
3d8d9f1d LP	104	*groups = pmx->pfc->info->functions[selector].groups;
3d8d9f1d LP	105	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
d93a891f	106
ca5481c6 PM	107	return 0;
	108	}
	109
3d8d9f1d	110	static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	111	unsigned group)
ca5481c6 PM	112	{
3d8d9f1d LP	113	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	114	struct sh_pfc *pfc = pmx->pfc;
	115	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	116	unsigned long flags;
	117	unsigned int i;
b705c054	118	int ret = 0;
3d8d9f1d LP	119
	120	spin_lock_irqsave(&pfc->lock, flags);
	121
9fddc4a5 LP	122	for (i = 0; i < grp->nr_pins; ++i) {
	123	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	124	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	125
	126	if (cfg->type != PINMUX_TYPE_NONE) {
	127	ret = -EBUSY;
	128	goto done;
	129	}
	130	}
	131
3d8d9f1d	132	for (i = 0; i < grp->nr_pins; ++i) {
b705c054 LP	133	ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
	134	if (ret < 0)
	135	break;
3d8d9f1d LP	136	}
3d8d9f1d LP	137
9fddc4a5	138	done:
3d8d9f1d LP	139	spin_unlock_irqrestore(&pfc->lock, flags);
3d8d9f1d LP	140	return ret;
ca5481c6 PM	141	}
ca5481c6 PM	142
3d8d9f1d	143	static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	144	unsigned group)
ca5481c6 PM	145	{
9fddc4a5 LP	146	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	147	struct sh_pfc *pfc = pmx->pfc;
	148	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	149	unsigned long flags;
	150	unsigned int i;
	151
	152	spin_lock_irqsave(&pfc->lock, flags);
	153
	154	for (i = 0; i < grp->nr_pins; ++i) {
	155	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	156	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	157
	158	cfg->type = PINMUX_TYPE_NONE;
	159	}
	160
	161	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	162	}
	163
	164	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	165	struct pinctrl_gpio_range *range,
	166	unsigned offset)
	167	{
	168	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	169	struct sh_pfc *pfc = pmx->pfc;
1a0039dc LP	170	int idx = sh_pfc_get_pin_index(pfc, offset);
1a0039dc LP	171	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
ca5481c6	172	unsigned long flags;
1a0039dc	173	int ret;
ca5481c6 PM	174
	175	spin_lock_irqsave(&pfc->lock, flags);
	176
9fddc4a5	177	if (cfg->type != PINMUX_TYPE_NONE) {
9a643c9a LP	178	dev_err(pfc->dev,
	179	"Pin %u is busy, can't configure it as GPIO.\n",
	180	offset);
9fddc4a5 LP	181	ret = -EBUSY;
9fddc4a5 LP	182	goto done;
d93a891f	183	}
ca5481c6	184
9fddc4a5 LP	185	cfg->type = PINMUX_TYPE_GPIO;
9fddc4a5 LP	186
ca5481c6 PM	187	ret = 0;
ca5481c6 PM	188
9fddc4a5	189	done:
ca5481c6 PM	190	spin_unlock_irqrestore(&pfc->lock, flags);
	191
	192	return ret;
	193	}
	194
	195	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	196	struct pinctrl_gpio_range *range,
	197	unsigned offset)
	198	{
9fddc4a5 LP	199	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	200	struct sh_pfc *pfc = pmx->pfc;
	201	int idx = sh_pfc_get_pin_index(pfc, offset);
	202	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	203	unsigned long flags;
	204
	205	spin_lock_irqsave(&pfc->lock, flags);
	206	cfg->type = PINMUX_TYPE_NONE;
	207	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	208	}
	209
	210	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	211	struct pinctrl_gpio_range *range,
	212	unsigned offset, bool input)
	213	{
	214	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0d00f00a LP	215	struct sh_pfc *pfc = pmx->pfc;
	216	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	217	int idx = sh_pfc_get_pin_index(pfc, offset);
0d00f00a	218	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
9fddc4a5	219	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0d00f00a LP	220	unsigned long flags;
0d00f00a LP	221	int ret;
ca5481c6	222
0d00f00a LP	223	spin_lock_irqsave(&pfc->lock, flags);
0d00f00a LP	224
9fddc4a5	225	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
0d00f00a LP	226	if (ret < 0)
	227	goto done;
	228
	229	cfg->type = new_type;
	230
	231	done:
	232	spin_unlock_irqrestore(&pfc->lock, flags);
0d00f00a	233	return ret;
ca5481c6 PM	234	}
ca5481c6 PM	235
fe330ce8	236	static const struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	237	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	238	.get_function_name = sh_pfc_get_function_name,
ca5481c6	239	.get_function_groups = sh_pfc_get_function_groups,
3d8d9f1d LP	240	.enable = sh_pfc_func_enable,
3d8d9f1d LP	241	.disable = sh_pfc_func_disable,
ca5481c6 PM	242	.gpio_request_enable = sh_pfc_gpio_request_enable,
	243	.gpio_disable_free = sh_pfc_gpio_disable_free,
	244	.gpio_set_direction = sh_pfc_gpio_set_direction,
	245	};
	246
c58d9c1b LP	247	/* Check whether the requested parameter is supported for a pin. */
	248	static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
	249	enum pin_config_param param)
	250	{
	251	int idx = sh_pfc_get_pin_index(pfc, _pin);
	252	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	253
	254	switch (param) {
	255	case PIN_CONFIG_BIAS_DISABLE:
	256	return true;
	257
	258	case PIN_CONFIG_BIAS_PULL_UP:
	259	return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
	260
	261	case PIN_CONFIG_BIAS_PULL_DOWN:
	262	return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
	263
	264	default:
	265	return false;
	266	}
	267	}
	268
934cb02b	269	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	270	unsigned long *config)
ca5481c6 PM	271	{
fdd85ec3 PM	272	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	273	struct sh_pfc *pfc = pmx->pfc;
c58d9c1b LP	274	enum pin_config_param param = pinconf_to_config_param(*config);
	275	unsigned long flags;
	276	unsigned int bias;
	277
	278	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
	279	return -ENOTSUPP;
	280
	281	switch (param) {
	282	case PIN_CONFIG_BIAS_DISABLE:
	283	case PIN_CONFIG_BIAS_PULL_UP:
	284	case PIN_CONFIG_BIAS_PULL_DOWN:
	285	if (!pfc->info->ops \|\| !pfc->info->ops->get_bias)
	286	return -ENOTSUPP;
	287
	288	spin_lock_irqsave(&pfc->lock, flags);
	289	bias = pfc->info->ops->get_bias(pfc, _pin);
	290	spin_unlock_irqrestore(&pfc->lock, flags);
	291
	292	if (bias != param)
	293	return -EINVAL;
	294
	295	*config = 0;
	296	break;
d93a891f	297
c58d9c1b LP	298	default:
	299	return -ENOTSUPP;
	300	}
d93a891f	301
fdd85ec3	302	return 0;
ca5481c6 PM	303	}
ca5481c6 PM	304
c58d9c1b	305	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	306	unsigned long config)
ca5481c6 PM	307	{
fdd85ec3	308	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
c58d9c1b LP	309	struct sh_pfc *pfc = pmx->pfc;
	310	enum pin_config_param param = pinconf_to_config_param(config);
	311	unsigned long flags;
fdd85ec3	312
c58d9c1b LP	313	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
c58d9c1b LP	314	return -ENOTSUPP;
fdd85ec3	315
c58d9c1b LP	316	switch (param) {
	317	case PIN_CONFIG_BIAS_PULL_UP:
	318	case PIN_CONFIG_BIAS_PULL_DOWN:
	319	case PIN_CONFIG_BIAS_DISABLE:
	320	if (!pfc->info->ops \|\| !pfc->info->ops->set_bias)
	321	return -ENOTSUPP;
	322
	323	spin_lock_irqsave(&pfc->lock, flags);
	324	pfc->info->ops->set_bias(pfc, _pin, param);
	325	spin_unlock_irqrestore(&pfc->lock, flags);
	326
	327	break;
	328
	329	default:
	330	return -ENOTSUPP;
	331	}
	332
	333	return 0;
fdd85ec3 PM	334	}
fdd85ec3 PM	335
c58d9c1b LP	336	static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
c58d9c1b LP	337	unsigned long config)
fdd85ec3	338	{
c58d9c1b LP	339	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	340	const unsigned int *pins;
	341	unsigned int num_pins;
	342	unsigned int i;
	343
	344	pins = pmx->pfc->info->groups[group].pins;
	345	num_pins = pmx->pfc->info->groups[group].nr_pins;
	346
	347	for (i = 0; i < num_pins; ++i)
	348	sh_pfc_pinconf_set(pctldev, pins[i], config);
	349
	350	return 0;
ca5481c6 PM	351	}
ca5481c6 PM	352
fe330ce8	353	static const struct pinconf_ops sh_pfc_pinconf_ops = {
c58d9c1b LP	354	.is_generic = true,
	355	.pin_config_get = sh_pfc_pinconf_get,
	356	.pin_config_set = sh_pfc_pinconf_set,
	357	.pin_config_group_set = sh_pfc_pinconf_group_set,
	358	.pin_config_config_dbg_show = pinconf_generic_dump_config,
ca5481c6 PM	359	};
ca5481c6 PM	360
63d57383 LP	361	/* PFC ranges -> pinctrl pin descs */
63d57383 LP	362	static int sh_pfc_map_pins(struct sh_pfc pfc, struct sh_pfc_pinctrl pmx)
ca5481c6	363	{
63d57383 LP	364	const struct pinmux_range *ranges;
	365	struct pinmux_range def_range;
	366	unsigned int nr_ranges;
	367	unsigned int nr_pins;
	368	unsigned int i;
	369
	370	if (pfc->info->ranges == NULL) {
	371	def_range.begin = 0;
	372	def_range.end = pfc->info->nr_pins - 1;
	373	ranges = &def_range;
	374	nr_ranges = 1;
	375	} else {
	376	ranges = pfc->info->ranges;
	377	nr_ranges = pfc->info->nr_ranges;
	378	}
ca5481c6	379
3d8d9f1d LP	380	pmx->pins = devm_kzalloc(pfc->dev,
3d8d9f1d LP	381	sizeof(pmx->pins) pfc->info->nr_pins,
1724acfd	382	GFP_KERNEL);
3d8d9f1d	383	if (unlikely(!pmx->pins))
ca5481c6	384	return -ENOMEM;
ca5481c6	385
1a0039dc LP	386	pmx->configs = devm_kzalloc(pfc->dev,
	387	sizeof(pmx->configs) pfc->info->nr_pins,
	388	GFP_KERNEL);
	389	if (unlikely(!pmx->configs))
	390	return -ENOMEM;
	391
63d57383 LP	392	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
	393	const struct pinmux_range *range = &ranges[i];
	394	unsigned int number;
	395
	396	for (number = range->begin; number <= range->end;
	397	number++, nr_pins++) {
1a0039dc	398	struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
3d8d9f1d	399	struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
cd3c1bee LP	400	const struct sh_pfc_pin *info =
cd3c1bee LP	401	&pfc->info->pins[nr_pins];
ca5481c6	402
63d57383 LP	403	pin->number = number;
63d57383 LP	404	pin->name = info->name;
9fddc4a5	405	cfg->type = PINMUX_TYPE_NONE;
63d57383	406	}
ca5481c6 PM	407	}
ca5481c6 PM	408
63d57383 LP	409	pfc->nr_pins = ranges[nr_ranges-1].end + 1;
	410
	411	return nr_ranges;
ca5481c6 PM	412	}
ca5481c6 PM	413
c6193eac	414	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
ca5481c6	415	{
c6193eac	416	struct sh_pfc_pinctrl *pmx;
63d57383	417	int nr_ranges;
ca5481c6	418
1724acfd	419	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
c6193eac LP	420	if (unlikely(!pmx))
	421	return -ENOMEM;
	422
c6193eac LP	423	pmx->pfc = pfc;
c6193eac LP	424	pfc->pinctrl = pmx;
ca5481c6	425
63d57383 LP	426	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	427	if (unlikely(nr_ranges < 0))
	428	return nr_ranges;
ca5481c6	429
dcc427e1 LP	430	pmx->pctl_desc.name = DRV_NAME;
	431	pmx->pctl_desc.owner = THIS_MODULE;
	432	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	433	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	434	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
3d8d9f1d	435	pmx->pctl_desc.pins = pmx->pins;
63d57383	436	pmx->pctl_desc.npins = pfc->info->nr_pins;
dcc427e1 LP	437
dcc427e1 LP	438	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
fd9d05b0 WY	439	if (pmx->pctl == NULL)
fd9d05b0 WY	440	return -EINVAL;
ca5481c6	441
ca5481c6	442	return 0;
ca5481c6 PM	443	}
ca5481c6 PM	444
c6193eac	445	int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
ca5481c6	446	{
c6193eac	447	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
ca5481c6	448
ca5481c6 PM	449	pinctrl_unregister(pmx->pctl);
ca5481c6 PM	450
c6193eac	451	pfc->pinctrl = NULL;
ca5481c6 PM	452	return 0;
ca5481c6 PM	453	}