]>
Commit | Line | Data |
---|---|---|
ca5481c6 PM |
1 | /* |
2 | * SuperH Pin Function Controller pinmux support. | |
3 | * | |
4 | * Copyright (C) 2012 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
54407110 | 10 | |
c6193eac | 11 | #define DRV_NAME "sh-pfc" |
ca5481c6 | 12 | |
1724acfd | 13 | #include <linux/device.h> |
90efde22 | 14 | #include <linux/err.h> |
ca5481c6 PM |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
fe1c9a82 | 17 | #include <linux/of.h> |
ca5481c6 | 18 | #include <linux/pinctrl/consumer.h> |
fe1c9a82 | 19 | #include <linux/pinctrl/machine.h> |
ca5481c6 | 20 | #include <linux/pinctrl/pinconf.h> |
ca5481c6 | 21 | #include <linux/pinctrl/pinconf-generic.h> |
90efde22 LP |
22 | #include <linux/pinctrl/pinctrl.h> |
23 | #include <linux/pinctrl/pinmux.h> | |
90efde22 LP |
24 | #include <linux/slab.h> |
25 | #include <linux/spinlock.h> | |
ca5481c6 | 26 | |
f9165132 | 27 | #include "core.h" |
c58d9c1b LP |
28 | #include "../core.h" |
29 | #include "../pinconf.h" | |
f9165132 | 30 | |
1a0039dc LP |
31 | struct sh_pfc_pin_config { |
32 | u32 type; | |
33 | }; | |
34 | ||
ca5481c6 PM |
35 | struct sh_pfc_pinctrl { |
36 | struct pinctrl_dev *pctl; | |
dcc427e1 | 37 | struct pinctrl_desc pctl_desc; |
dcc427e1 | 38 | |
ca5481c6 PM |
39 | struct sh_pfc *pfc; |
40 | ||
3d8d9f1d | 41 | struct pinctrl_pin_desc *pins; |
1a0039dc | 42 | struct sh_pfc_pin_config *configs; |
16ccaf5b LP |
43 | |
44 | const char *func_prop_name; | |
45 | const char *groups_prop_name; | |
46 | const char *pins_prop_name; | |
ca5481c6 PM |
47 | }; |
48 | ||
e3f805e8 | 49 | static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) |
ca5481c6 | 50 | { |
e3f805e8 PM |
51 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
52 | ||
3d8d9f1d | 53 | return pmx->pfc->info->nr_groups; |
ca5481c6 PM |
54 | } |
55 | ||
e3f805e8 | 56 | static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, |
ca5481c6 PM |
57 | unsigned selector) |
58 | { | |
e3f805e8 PM |
59 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
60 | ||
3d8d9f1d | 61 | return pmx->pfc->info->groups[selector].name; |
ca5481c6 PM |
62 | } |
63 | ||
3d8d9f1d | 64 | static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
65 | const unsigned **pins, unsigned *num_pins) |
66 | { | |
e3f805e8 PM |
67 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
68 | ||
3d8d9f1d LP |
69 | *pins = pmx->pfc->info->groups[selector].pins; |
70 | *num_pins = pmx->pfc->info->groups[selector].nr_pins; | |
e3f805e8 PM |
71 | |
72 | return 0; | |
ca5481c6 PM |
73 | } |
74 | ||
fdd85ec3 PM |
75 | static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
76 | unsigned offset) | |
77 | { | |
78 | seq_printf(s, "%s", DRV_NAME); | |
79 | } | |
80 | ||
3a8d63d4 | 81 | #ifdef CONFIG_OF |
12f3ad8d LP |
82 | static int sh_pfc_map_add_config(struct pinctrl_map *map, |
83 | const char *group_or_pin, | |
84 | enum pinctrl_map_type type, | |
85 | unsigned long *configs, | |
86 | unsigned int num_configs) | |
87 | { | |
88 | unsigned long *cfgs; | |
89 | ||
90 | cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), | |
91 | GFP_KERNEL); | |
92 | if (cfgs == NULL) | |
93 | return -ENOMEM; | |
94 | ||
95 | map->type = type; | |
96 | map->data.configs.group_or_pin = group_or_pin; | |
97 | map->data.configs.configs = cfgs; | |
98 | map->data.configs.num_configs = num_configs; | |
99 | ||
100 | return 0; | |
101 | } | |
102 | ||
16ccaf5b LP |
103 | static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev, |
104 | struct device_node *np, | |
fe1c9a82 LP |
105 | struct pinctrl_map **map, |
106 | unsigned int *num_maps, unsigned int *index) | |
107 | { | |
16ccaf5b LP |
108 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
109 | struct device *dev = pmx->pfc->dev; | |
fe1c9a82 LP |
110 | struct pinctrl_map *maps = *map; |
111 | unsigned int nmaps = *num_maps; | |
112 | unsigned int idx = *index; | |
12f3ad8d | 113 | unsigned int num_configs; |
fe1c9a82 | 114 | const char *function = NULL; |
12f3ad8d | 115 | unsigned long *configs; |
fe1c9a82 | 116 | struct property *prop; |
12f3ad8d LP |
117 | unsigned int num_groups; |
118 | unsigned int num_pins; | |
fe1c9a82 | 119 | const char *group; |
12f3ad8d | 120 | const char *pin; |
fe1c9a82 LP |
121 | int ret; |
122 | ||
16ccaf5b LP |
123 | /* Support both the old Renesas-specific properties and the new standard |
124 | * properties. Mixing old and new properties isn't allowed, neither | |
125 | * inside a subnode nor across subnodes. | |
126 | */ | |
127 | if (!pmx->func_prop_name) { | |
128 | if (of_find_property(np, "groups", NULL) || | |
129 | of_find_property(np, "pins", NULL)) { | |
130 | pmx->func_prop_name = "function"; | |
131 | pmx->groups_prop_name = "groups"; | |
132 | pmx->pins_prop_name = "pins"; | |
133 | } else { | |
134 | pmx->func_prop_name = "renesas,function"; | |
135 | pmx->groups_prop_name = "renesas,groups"; | |
136 | pmx->pins_prop_name = "renesas,pins"; | |
137 | } | |
138 | } | |
139 | ||
fe1c9a82 LP |
140 | /* Parse the function and configuration properties. At least a function |
141 | * or one configuration must be specified. | |
142 | */ | |
16ccaf5b | 143 | ret = of_property_read_string(np, pmx->func_prop_name, &function); |
fe1c9a82 LP |
144 | if (ret < 0 && ret != -EINVAL) { |
145 | dev_err(dev, "Invalid function in DT\n"); | |
146 | return ret; | |
147 | } | |
148 | ||
dd4d01f7 | 149 | ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); |
12f3ad8d LP |
150 | if (ret < 0) |
151 | return ret; | |
152 | ||
153 | if (!function && num_configs == 0) { | |
154 | dev_err(dev, | |
155 | "DT node must contain at least a function or config\n"); | |
16ccaf5b | 156 | ret = -ENODEV; |
fe1c9a82 LP |
157 | goto done; |
158 | } | |
159 | ||
12f3ad8d | 160 | /* Count the number of pins and groups and reallocate mappings. */ |
16ccaf5b | 161 | ret = of_property_count_strings(np, pmx->pins_prop_name); |
12f3ad8d LP |
162 | if (ret == -EINVAL) { |
163 | num_pins = 0; | |
164 | } else if (ret < 0) { | |
165 | dev_err(dev, "Invalid pins list in DT\n"); | |
166 | goto done; | |
167 | } else { | |
168 | num_pins = ret; | |
169 | } | |
170 | ||
16ccaf5b | 171 | ret = of_property_count_strings(np, pmx->groups_prop_name); |
12f3ad8d LP |
172 | if (ret == -EINVAL) { |
173 | num_groups = 0; | |
174 | } else if (ret < 0) { | |
fe1c9a82 LP |
175 | dev_err(dev, "Invalid pin groups list in DT\n"); |
176 | goto done; | |
12f3ad8d LP |
177 | } else { |
178 | num_groups = ret; | |
fe1c9a82 LP |
179 | } |
180 | ||
12f3ad8d LP |
181 | if (!num_pins && !num_groups) { |
182 | dev_err(dev, "No pin or group provided in DT node\n"); | |
fe1c9a82 LP |
183 | ret = -ENODEV; |
184 | goto done; | |
185 | } | |
186 | ||
12f3ad8d LP |
187 | if (function) |
188 | nmaps += num_groups; | |
189 | if (configs) | |
190 | nmaps += num_pins + num_groups; | |
fe1c9a82 LP |
191 | |
192 | maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL); | |
193 | if (maps == NULL) { | |
194 | ret = -ENOMEM; | |
195 | goto done; | |
196 | } | |
197 | ||
198 | *map = maps; | |
199 | *num_maps = nmaps; | |
200 | ||
201 | /* Iterate over pins and groups and create the mappings. */ | |
16ccaf5b | 202 | of_property_for_each_string(np, pmx->groups_prop_name, prop, group) { |
12f3ad8d LP |
203 | if (function) { |
204 | maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; | |
205 | maps[idx].data.mux.group = group; | |
206 | maps[idx].data.mux.function = function; | |
207 | idx++; | |
208 | } | |
209 | ||
210 | if (configs) { | |
211 | ret = sh_pfc_map_add_config(&maps[idx], group, | |
212 | PIN_MAP_TYPE_CONFIGS_GROUP, | |
213 | configs, num_configs); | |
214 | if (ret < 0) | |
215 | goto done; | |
216 | ||
217 | idx++; | |
218 | } | |
fe1c9a82 LP |
219 | } |
220 | ||
12f3ad8d LP |
221 | if (!configs) { |
222 | ret = 0; | |
223 | goto done; | |
224 | } | |
225 | ||
16ccaf5b | 226 | of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) { |
12f3ad8d LP |
227 | ret = sh_pfc_map_add_config(&maps[idx], pin, |
228 | PIN_MAP_TYPE_CONFIGS_PIN, | |
229 | configs, num_configs); | |
230 | if (ret < 0) | |
231 | goto done; | |
232 | ||
233 | idx++; | |
234 | } | |
fe1c9a82 LP |
235 | |
236 | done: | |
237 | *index = idx; | |
12f3ad8d | 238 | kfree(configs); |
fe1c9a82 LP |
239 | return ret; |
240 | } | |
241 | ||
242 | static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev, | |
243 | struct pinctrl_map *map, unsigned num_maps) | |
244 | { | |
12f3ad8d LP |
245 | unsigned int i; |
246 | ||
247 | if (map == NULL) | |
248 | return; | |
249 | ||
250 | for (i = 0; i < num_maps; ++i) { | |
251 | if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || | |
252 | map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) | |
253 | kfree(map[i].data.configs.configs); | |
254 | } | |
255 | ||
fe1c9a82 LP |
256 | kfree(map); |
257 | } | |
258 | ||
259 | static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev, | |
260 | struct device_node *np, | |
261 | struct pinctrl_map **map, unsigned *num_maps) | |
262 | { | |
263 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
264 | struct device *dev = pmx->pfc->dev; | |
265 | struct device_node *child; | |
266 | unsigned int index; | |
267 | int ret; | |
268 | ||
269 | *map = NULL; | |
270 | *num_maps = 0; | |
271 | index = 0; | |
272 | ||
273 | for_each_child_of_node(np, child) { | |
16ccaf5b | 274 | ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps, |
fe1c9a82 | 275 | &index); |
d0b3ed41 JL |
276 | if (ret < 0) { |
277 | of_node_put(child); | |
fe1c9a82 | 278 | goto done; |
d0b3ed41 | 279 | } |
fe1c9a82 LP |
280 | } |
281 | ||
282 | /* If no mapping has been found in child nodes try the config node. */ | |
283 | if (*num_maps == 0) { | |
16ccaf5b LP |
284 | ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps, |
285 | &index); | |
fe1c9a82 LP |
286 | if (ret < 0) |
287 | goto done; | |
288 | } | |
289 | ||
290 | if (*num_maps) | |
291 | return 0; | |
292 | ||
293 | dev_err(dev, "no mapping found in node %s\n", np->full_name); | |
294 | ret = -EINVAL; | |
295 | ||
296 | done: | |
297 | if (ret < 0) | |
298 | sh_pfc_dt_free_map(pctldev, *map, *num_maps); | |
299 | ||
300 | return ret; | |
301 | } | |
3a8d63d4 | 302 | #endif /* CONFIG_OF */ |
fe1c9a82 | 303 | |
fe330ce8 | 304 | static const struct pinctrl_ops sh_pfc_pinctrl_ops = { |
e3f805e8 PM |
305 | .get_groups_count = sh_pfc_get_groups_count, |
306 | .get_group_name = sh_pfc_get_group_name, | |
ca5481c6 | 307 | .get_group_pins = sh_pfc_get_group_pins, |
fdd85ec3 | 308 | .pin_dbg_show = sh_pfc_pin_dbg_show, |
3a8d63d4 | 309 | #ifdef CONFIG_OF |
fe1c9a82 LP |
310 | .dt_node_to_map = sh_pfc_dt_node_to_map, |
311 | .dt_free_map = sh_pfc_dt_free_map, | |
3a8d63d4 | 312 | #endif |
ca5481c6 PM |
313 | }; |
314 | ||
d93a891f PM |
315 | static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) |
316 | { | |
317 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
318 | ||
3d8d9f1d | 319 | return pmx->pfc->info->nr_functions; |
d93a891f PM |
320 | } |
321 | ||
322 | static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, | |
323 | unsigned selector) | |
324 | { | |
325 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
326 | ||
3d8d9f1d | 327 | return pmx->pfc->info->functions[selector].name; |
d93a891f | 328 | } |
ca5481c6 | 329 | |
3d8d9f1d LP |
330 | static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, |
331 | unsigned selector, | |
ca5481c6 PM |
332 | const char * const **groups, |
333 | unsigned * const num_groups) | |
334 | { | |
d93a891f PM |
335 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
336 | ||
3d8d9f1d LP |
337 | *groups = pmx->pfc->info->functions[selector].groups; |
338 | *num_groups = pmx->pfc->info->functions[selector].nr_groups; | |
d93a891f | 339 | |
ca5481c6 PM |
340 | return 0; |
341 | } | |
342 | ||
03e9f0ca LW |
343 | static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector, |
344 | unsigned group) | |
ca5481c6 | 345 | { |
3d8d9f1d LP |
346 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
347 | struct sh_pfc *pfc = pmx->pfc; | |
348 | const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; | |
349 | unsigned long flags; | |
350 | unsigned int i; | |
b705c054 | 351 | int ret = 0; |
3d8d9f1d LP |
352 | |
353 | spin_lock_irqsave(&pfc->lock, flags); | |
354 | ||
9fddc4a5 LP |
355 | for (i = 0; i < grp->nr_pins; ++i) { |
356 | int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); | |
357 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
358 | ||
359 | if (cfg->type != PINMUX_TYPE_NONE) { | |
360 | ret = -EBUSY; | |
361 | goto done; | |
362 | } | |
363 | } | |
364 | ||
3d8d9f1d | 365 | for (i = 0; i < grp->nr_pins; ++i) { |
b705c054 LP |
366 | ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); |
367 | if (ret < 0) | |
368 | break; | |
3d8d9f1d LP |
369 | } |
370 | ||
9fddc4a5 | 371 | done: |
3d8d9f1d LP |
372 | spin_unlock_irqrestore(&pfc->lock, flags); |
373 | return ret; | |
ca5481c6 PM |
374 | } |
375 | ||
ca5481c6 PM |
376 | static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, |
377 | struct pinctrl_gpio_range *range, | |
378 | unsigned offset) | |
379 | { | |
380 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
381 | struct sh_pfc *pfc = pmx->pfc; | |
1a0039dc LP |
382 | int idx = sh_pfc_get_pin_index(pfc, offset); |
383 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
ca5481c6 | 384 | unsigned long flags; |
1a0039dc | 385 | int ret; |
ca5481c6 PM |
386 | |
387 | spin_lock_irqsave(&pfc->lock, flags); | |
388 | ||
9fddc4a5 | 389 | if (cfg->type != PINMUX_TYPE_NONE) { |
9a643c9a LP |
390 | dev_err(pfc->dev, |
391 | "Pin %u is busy, can't configure it as GPIO.\n", | |
392 | offset); | |
9fddc4a5 LP |
393 | ret = -EBUSY; |
394 | goto done; | |
d93a891f | 395 | } |
ca5481c6 | 396 | |
e3c47051 LP |
397 | if (!pfc->gpio) { |
398 | /* If GPIOs are handled externally the pin mux type need to be | |
399 | * set to GPIO here. | |
400 | */ | |
401 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
402 | ||
403 | ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO); | |
404 | if (ret < 0) | |
405 | goto done; | |
406 | } | |
407 | ||
9fddc4a5 LP |
408 | cfg->type = PINMUX_TYPE_GPIO; |
409 | ||
ca5481c6 PM |
410 | ret = 0; |
411 | ||
9fddc4a5 | 412 | done: |
ca5481c6 PM |
413 | spin_unlock_irqrestore(&pfc->lock, flags); |
414 | ||
415 | return ret; | |
416 | } | |
417 | ||
418 | static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, | |
419 | struct pinctrl_gpio_range *range, | |
420 | unsigned offset) | |
421 | { | |
9fddc4a5 LP |
422 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
423 | struct sh_pfc *pfc = pmx->pfc; | |
424 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
425 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
426 | unsigned long flags; | |
427 | ||
428 | spin_lock_irqsave(&pfc->lock, flags); | |
429 | cfg->type = PINMUX_TYPE_NONE; | |
430 | spin_unlock_irqrestore(&pfc->lock, flags); | |
ca5481c6 PM |
431 | } |
432 | ||
433 | static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, | |
434 | struct pinctrl_gpio_range *range, | |
435 | unsigned offset, bool input) | |
436 | { | |
437 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
0d00f00a LP |
438 | struct sh_pfc *pfc = pmx->pfc; |
439 | int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; | |
440 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
0d00f00a | 441 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; |
9fddc4a5 | 442 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; |
0d00f00a | 443 | unsigned long flags; |
6dc9b455 | 444 | unsigned int dir; |
0d00f00a | 445 | int ret; |
ca5481c6 | 446 | |
6dc9b455 LP |
447 | /* Check if the requested direction is supported by the pin. Not all SoC |
448 | * provide pin config data, so perform the check conditionally. | |
449 | */ | |
450 | if (pin->configs) { | |
451 | dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; | |
452 | if (!(pin->configs & dir)) | |
453 | return -EINVAL; | |
454 | } | |
455 | ||
0d00f00a LP |
456 | spin_lock_irqsave(&pfc->lock, flags); |
457 | ||
9fddc4a5 | 458 | ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); |
0d00f00a LP |
459 | if (ret < 0) |
460 | goto done; | |
461 | ||
462 | cfg->type = new_type; | |
463 | ||
464 | done: | |
465 | spin_unlock_irqrestore(&pfc->lock, flags); | |
0d00f00a | 466 | return ret; |
ca5481c6 PM |
467 | } |
468 | ||
fe330ce8 | 469 | static const struct pinmux_ops sh_pfc_pinmux_ops = { |
d93a891f PM |
470 | .get_functions_count = sh_pfc_get_functions_count, |
471 | .get_function_name = sh_pfc_get_function_name, | |
ca5481c6 | 472 | .get_function_groups = sh_pfc_get_function_groups, |
03e9f0ca | 473 | .set_mux = sh_pfc_func_set_mux, |
ca5481c6 PM |
474 | .gpio_request_enable = sh_pfc_gpio_request_enable, |
475 | .gpio_disable_free = sh_pfc_gpio_disable_free, | |
476 | .gpio_set_direction = sh_pfc_gpio_set_direction, | |
477 | }; | |
478 | ||
3caa7d8c LP |
479 | static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, |
480 | unsigned int pin, unsigned int *offset, unsigned int *size) | |
481 | { | |
482 | const struct pinmux_drive_reg_field *field; | |
483 | const struct pinmux_drive_reg *reg; | |
484 | unsigned int i; | |
485 | ||
486 | for (reg = pfc->info->drive_regs; reg->reg; ++reg) { | |
487 | for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) { | |
488 | field = ®->fields[i]; | |
489 | ||
490 | if (field->size && field->pin == pin) { | |
491 | *offset = field->offset; | |
492 | *size = field->size; | |
493 | ||
494 | return reg->reg; | |
495 | } | |
496 | } | |
497 | } | |
498 | ||
499 | return 0; | |
500 | } | |
501 | ||
502 | static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc, | |
503 | unsigned int pin) | |
504 | { | |
505 | unsigned long flags; | |
506 | unsigned int offset; | |
507 | unsigned int size; | |
508 | u32 reg; | |
509 | u32 val; | |
510 | ||
511 | reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); | |
512 | if (!reg) | |
513 | return -EINVAL; | |
514 | ||
515 | spin_lock_irqsave(&pfc->lock, flags); | |
516 | val = sh_pfc_read_reg(pfc, reg, 32); | |
517 | spin_unlock_irqrestore(&pfc->lock, flags); | |
518 | ||
519 | val = (val >> offset) & GENMASK(size - 1, 0); | |
520 | ||
521 | /* Convert the value to mA based on a full drive strength value of 24mA. | |
522 | * We can make the full value configurable later if needed. | |
523 | */ | |
524 | return (val + 1) * (size == 2 ? 6 : 3); | |
525 | } | |
526 | ||
527 | static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc, | |
528 | unsigned int pin, u16 strength) | |
529 | { | |
530 | unsigned long flags; | |
531 | unsigned int offset; | |
532 | unsigned int size; | |
533 | unsigned int step; | |
534 | u32 reg; | |
535 | u32 val; | |
536 | ||
537 | reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size); | |
538 | if (!reg) | |
539 | return -EINVAL; | |
540 | ||
541 | step = size == 2 ? 6 : 3; | |
542 | ||
543 | if (strength < step || strength > 24) | |
544 | return -EINVAL; | |
545 | ||
546 | /* Convert the value from mA based on a full drive strength value of | |
547 | * 24mA. We can make the full value configurable later if needed. | |
548 | */ | |
549 | strength = strength / step - 1; | |
550 | ||
551 | spin_lock_irqsave(&pfc->lock, flags); | |
552 | ||
553 | val = sh_pfc_read_reg(pfc, reg, 32); | |
554 | val &= ~GENMASK(offset + size - 1, offset); | |
555 | val |= strength << offset; | |
556 | ||
557 | sh_pfc_write_reg(pfc, reg, 32, val); | |
558 | ||
559 | spin_unlock_irqrestore(&pfc->lock, flags); | |
560 | ||
561 | return 0; | |
562 | } | |
563 | ||
c58d9c1b LP |
564 | /* Check whether the requested parameter is supported for a pin. */ |
565 | static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, | |
566 | enum pin_config_param param) | |
567 | { | |
568 | int idx = sh_pfc_get_pin_index(pfc, _pin); | |
569 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
570 | ||
571 | switch (param) { | |
572 | case PIN_CONFIG_BIAS_DISABLE: | |
5d7400c4 NS |
573 | return pin->configs & |
574 | (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN); | |
c58d9c1b LP |
575 | |
576 | case PIN_CONFIG_BIAS_PULL_UP: | |
577 | return pin->configs & SH_PFC_PIN_CFG_PULL_UP; | |
578 | ||
579 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
580 | return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; | |
581 | ||
3caa7d8c LP |
582 | case PIN_CONFIG_DRIVE_STRENGTH: |
583 | return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH; | |
584 | ||
5b9eaa56 BH |
585 | case PIN_CONFIG_POWER_SOURCE: |
586 | return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE; | |
587 | ||
c58d9c1b LP |
588 | default: |
589 | return false; | |
590 | } | |
591 | } | |
592 | ||
934cb02b | 593 | static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, |
ca5481c6 PM |
594 | unsigned long *config) |
595 | { | |
fdd85ec3 PM |
596 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
597 | struct sh_pfc *pfc = pmx->pfc; | |
c58d9c1b LP |
598 | enum pin_config_param param = pinconf_to_config_param(*config); |
599 | unsigned long flags; | |
40ade582 | 600 | unsigned int arg; |
c58d9c1b LP |
601 | |
602 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) | |
603 | return -ENOTSUPP; | |
604 | ||
605 | switch (param) { | |
606 | case PIN_CONFIG_BIAS_DISABLE: | |
607 | case PIN_CONFIG_BIAS_PULL_UP: | |
5b9eaa56 BH |
608 | case PIN_CONFIG_BIAS_PULL_DOWN: { |
609 | unsigned int bias; | |
610 | ||
c58d9c1b LP |
611 | if (!pfc->info->ops || !pfc->info->ops->get_bias) |
612 | return -ENOTSUPP; | |
613 | ||
614 | spin_lock_irqsave(&pfc->lock, flags); | |
615 | bias = pfc->info->ops->get_bias(pfc, _pin); | |
616 | spin_unlock_irqrestore(&pfc->lock, flags); | |
617 | ||
618 | if (bias != param) | |
619 | return -EINVAL; | |
620 | ||
40ade582 | 621 | arg = 0; |
c58d9c1b | 622 | break; |
5b9eaa56 BH |
623 | } |
624 | ||
3caa7d8c LP |
625 | case PIN_CONFIG_DRIVE_STRENGTH: { |
626 | int ret; | |
627 | ||
628 | ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin); | |
629 | if (ret < 0) | |
630 | return ret; | |
631 | ||
40ade582 | 632 | arg = ret; |
3caa7d8c LP |
633 | break; |
634 | } | |
635 | ||
5b9eaa56 | 636 | case PIN_CONFIG_POWER_SOURCE: { |
8775306d WS |
637 | u32 pocctrl, val; |
638 | int bit; | |
5b9eaa56 | 639 | |
8775306d | 640 | if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) |
5b9eaa56 BH |
641 | return -ENOTSUPP; |
642 | ||
8775306d WS |
643 | bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); |
644 | if (WARN(bit < 0, "invalid pin %#x", _pin)) | |
645 | return bit; | |
646 | ||
5b9eaa56 | 647 | spin_lock_irqsave(&pfc->lock, flags); |
8775306d | 648 | val = sh_pfc_read_reg(pfc, pocctrl, 32); |
5b9eaa56 BH |
649 | spin_unlock_irqrestore(&pfc->lock, flags); |
650 | ||
40ade582 | 651 | arg = (val & BIT(bit)) ? 3300 : 1800; |
5b9eaa56 BH |
652 | break; |
653 | } | |
d93a891f | 654 | |
c58d9c1b LP |
655 | default: |
656 | return -ENOTSUPP; | |
657 | } | |
d93a891f | 658 | |
40ade582 | 659 | *config = pinconf_to_config_packed(param, arg); |
fdd85ec3 | 660 | return 0; |
ca5481c6 PM |
661 | } |
662 | ||
c58d9c1b | 663 | static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, |
03b054e9 | 664 | unsigned long *configs, unsigned num_configs) |
ca5481c6 | 665 | { |
fdd85ec3 | 666 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
c58d9c1b | 667 | struct sh_pfc *pfc = pmx->pfc; |
03b054e9 | 668 | enum pin_config_param param; |
c58d9c1b | 669 | unsigned long flags; |
03b054e9 | 670 | unsigned int i; |
fdd85ec3 | 671 | |
03b054e9 SY |
672 | for (i = 0; i < num_configs; i++) { |
673 | param = pinconf_to_config_param(configs[i]); | |
fdd85ec3 | 674 | |
03b054e9 | 675 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) |
c58d9c1b LP |
676 | return -ENOTSUPP; |
677 | ||
03b054e9 SY |
678 | switch (param) { |
679 | case PIN_CONFIG_BIAS_PULL_UP: | |
680 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
681 | case PIN_CONFIG_BIAS_DISABLE: | |
682 | if (!pfc->info->ops || !pfc->info->ops->set_bias) | |
683 | return -ENOTSUPP; | |
c58d9c1b | 684 | |
03b054e9 SY |
685 | spin_lock_irqsave(&pfc->lock, flags); |
686 | pfc->info->ops->set_bias(pfc, _pin, param); | |
687 | spin_unlock_irqrestore(&pfc->lock, flags); | |
c58d9c1b | 688 | |
03b054e9 SY |
689 | break; |
690 | ||
3caa7d8c LP |
691 | case PIN_CONFIG_DRIVE_STRENGTH: { |
692 | unsigned int arg = | |
693 | pinconf_to_config_argument(configs[i]); | |
694 | int ret; | |
695 | ||
696 | ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg); | |
697 | if (ret < 0) | |
698 | return ret; | |
699 | ||
700 | break; | |
701 | } | |
702 | ||
5b9eaa56 | 703 | case PIN_CONFIG_POWER_SOURCE: { |
8775306d WS |
704 | unsigned int mV = pinconf_to_config_argument(configs[i]); |
705 | u32 pocctrl, val; | |
706 | int bit; | |
5b9eaa56 | 707 | |
8775306d | 708 | if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl) |
5b9eaa56 BH |
709 | return -ENOTSUPP; |
710 | ||
8775306d WS |
711 | bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl); |
712 | if (WARN(bit < 0, "invalid pin %#x", _pin)) | |
713 | return bit; | |
714 | ||
715 | if (mV != 1800 && mV != 3300) | |
716 | return -EINVAL; | |
717 | ||
5b9eaa56 | 718 | spin_lock_irqsave(&pfc->lock, flags); |
8775306d WS |
719 | val = sh_pfc_read_reg(pfc, pocctrl, 32); |
720 | if (mV == 3300) | |
721 | val |= BIT(bit); | |
722 | else | |
723 | val &= ~BIT(bit); | |
724 | sh_pfc_write_reg(pfc, pocctrl, 32, val); | |
5b9eaa56 BH |
725 | spin_unlock_irqrestore(&pfc->lock, flags); |
726 | ||
5b9eaa56 BH |
727 | break; |
728 | } | |
729 | ||
03b054e9 SY |
730 | default: |
731 | return -ENOTSUPP; | |
732 | } | |
733 | } /* for each config */ | |
c58d9c1b LP |
734 | |
735 | return 0; | |
fdd85ec3 PM |
736 | } |
737 | ||
c58d9c1b | 738 | static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
03b054e9 SY |
739 | unsigned long *configs, |
740 | unsigned num_configs) | |
fdd85ec3 | 741 | { |
c58d9c1b LP |
742 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
743 | const unsigned int *pins; | |
744 | unsigned int num_pins; | |
745 | unsigned int i; | |
746 | ||
747 | pins = pmx->pfc->info->groups[group].pins; | |
748 | num_pins = pmx->pfc->info->groups[group].nr_pins; | |
749 | ||
750 | for (i = 0; i < num_pins; ++i) | |
03b054e9 | 751 | sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs); |
c58d9c1b LP |
752 | |
753 | return 0; | |
ca5481c6 PM |
754 | } |
755 | ||
fe330ce8 | 756 | static const struct pinconf_ops sh_pfc_pinconf_ops = { |
c58d9c1b LP |
757 | .is_generic = true, |
758 | .pin_config_get = sh_pfc_pinconf_get, | |
759 | .pin_config_set = sh_pfc_pinconf_set, | |
760 | .pin_config_group_set = sh_pfc_pinconf_group_set, | |
761 | .pin_config_config_dbg_show = pinconf_generic_dump_config, | |
ca5481c6 PM |
762 | }; |
763 | ||
63d57383 LP |
764 | /* PFC ranges -> pinctrl pin descs */ |
765 | static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) | |
ca5481c6 | 766 | { |
63d57383 LP |
767 | unsigned int i; |
768 | ||
acac8ed5 | 769 | /* Allocate and initialize the pins and configs arrays. */ |
3d8d9f1d LP |
770 | pmx->pins = devm_kzalloc(pfc->dev, |
771 | sizeof(*pmx->pins) * pfc->info->nr_pins, | |
1724acfd | 772 | GFP_KERNEL); |
3d8d9f1d | 773 | if (unlikely(!pmx->pins)) |
ca5481c6 | 774 | return -ENOMEM; |
ca5481c6 | 775 | |
1a0039dc LP |
776 | pmx->configs = devm_kzalloc(pfc->dev, |
777 | sizeof(*pmx->configs) * pfc->info->nr_pins, | |
778 | GFP_KERNEL); | |
779 | if (unlikely(!pmx->configs)) | |
780 | return -ENOMEM; | |
781 | ||
acac8ed5 LP |
782 | for (i = 0; i < pfc->info->nr_pins; ++i) { |
783 | const struct sh_pfc_pin *info = &pfc->info->pins[i]; | |
784 | struct sh_pfc_pin_config *cfg = &pmx->configs[i]; | |
785 | struct pinctrl_pin_desc *pin = &pmx->pins[i]; | |
63d57383 | 786 | |
acac8ed5 LP |
787 | /* If the pin number is equal to -1 all pins are considered */ |
788 | pin->number = info->pin != (u16)-1 ? info->pin : i; | |
789 | pin->name = info->name; | |
790 | cfg->type = PINMUX_TYPE_NONE; | |
ca5481c6 PM |
791 | } |
792 | ||
acac8ed5 | 793 | return 0; |
ca5481c6 PM |
794 | } |
795 | ||
c6193eac | 796 | int sh_pfc_register_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 797 | { |
c6193eac | 798 | struct sh_pfc_pinctrl *pmx; |
acac8ed5 | 799 | int ret; |
ca5481c6 | 800 | |
1724acfd | 801 | pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); |
c6193eac LP |
802 | if (unlikely(!pmx)) |
803 | return -ENOMEM; | |
804 | ||
c6193eac | 805 | pmx->pfc = pfc; |
ca5481c6 | 806 | |
acac8ed5 LP |
807 | ret = sh_pfc_map_pins(pfc, pmx); |
808 | if (ret < 0) | |
809 | return ret; | |
ca5481c6 | 810 | |
dcc427e1 LP |
811 | pmx->pctl_desc.name = DRV_NAME; |
812 | pmx->pctl_desc.owner = THIS_MODULE; | |
813 | pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; | |
814 | pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; | |
815 | pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; | |
3d8d9f1d | 816 | pmx->pctl_desc.pins = pmx->pins; |
63d57383 | 817 | pmx->pctl_desc.npins = pfc->info->nr_pins; |
dcc427e1 | 818 | |
61187142 TL |
819 | ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx, |
820 | &pmx->pctl); | |
821 | if (ret) { | |
822 | dev_err(pfc->dev, "could not register: %i\n", ret); | |
823 | ||
824 | return ret; | |
825 | } | |
826 | ||
827 | return pinctrl_enable(pmx->pctl); | |
ca5481c6 | 828 | } |