[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"
#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"
#include "../core.h"
#include "../pinconf.h"

struct sh_pfc_pin_config {
	u32 type;
};

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct pinctrl_desc pctl_desc;

	struct sh_pfc *pfc;

	struct pinctrl_pin_desc *pins;
	struct sh_pfc_pin_config *configs;
};

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_groups;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->groups[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = pmx->pfc->info->groups[selector].pins;
	*num_pins = pmx->pfc->info->groups[selector].nr_pins;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->functions[selector].name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
				      unsigned selector,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = pmx->pfc->info->functions[selector].groups;
	*num_groups = pmx->pfc->info->functions[selector].nr_groups;

	return 0;
}

static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
			      unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;
	int ret = 0;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		if (cfg->type != PINMUX_TYPE_NONE) {
			ret = -EBUSY;
			goto done;
		}
	}

	for (i = 0; i < grp->nr_pins; ++i) {
		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
		if (ret < 0)
			break;
	}

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
				unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		cfg->type = PINMUX_TYPE_NONE;
	}

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	if (cfg->type != PINMUX_TYPE_NONE) {
		pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset);
		ret = -EBUSY;
		goto done;
	}

	cfg->type = PINMUX_TYPE_GPIO;

	ret = 0;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;

	spin_lock_irqsave(&pfc->lock, flags);
	cfg->type = PINMUX_TYPE_NONE;
	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
	if (ret < 0)
		goto done;

	cfg->type = new_type;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static const struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_func_enable,
	.disable		= sh_pfc_func_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
				    enum pin_config_param param)
{
	int idx = sh_pfc_get_pin_index(pfc, _pin);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		return true;

	case PIN_CONFIG_BIAS_PULL_UP:
		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;

	default:
		return false;
	}
}

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(*config);
	unsigned long flags;
	unsigned int bias;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
		if (!pfc->info->ops || !pfc->info->ops->get_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		bias = pfc->info->ops->get_bias(pfc, _pin);
		spin_unlock_irqrestore(&pfc->lock, flags);

		if (bias != param)
			return -EINVAL;

		*config = 0;
		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(config);
	unsigned long flags;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
	case PIN_CONFIG_BIAS_DISABLE:
		if (!pfc->info->ops || !pfc->info->ops->set_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		pfc->info->ops->set_bias(pfc, _pin, param);
		spin_unlock_irqrestore(&pfc->lock, flags);

		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
				    unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	const unsigned int *pins;
	unsigned int num_pins;
	unsigned int i;

	pins = pmx->pfc->info->groups[group].pins;
	num_pins = pmx->pfc->info->groups[group].nr_pins;

	for (i = 0; i < num_pins; ++i)
		sh_pfc_pinconf_set(pctldev, pins[i], config);

	return 0;
}

static const struct pinconf_ops sh_pfc_pinconf_ops = {
	.is_generic			= true,
	.pin_config_get			= sh_pfc_pinconf_get,
	.pin_config_set			= sh_pfc_pinconf_set,
	.pin_config_group_set		= sh_pfc_pinconf_group_set,
	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
};

/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
	const struct pinmux_range *ranges;
	struct pinmux_range def_range;
	unsigned int nr_ranges;
	unsigned int nr_pins;
	unsigned int i;

	if (pfc->info->ranges == NULL) {
		def_range.begin = 0;
		def_range.end = pfc->info->nr_pins - 1;
		ranges = &def_range;
		nr_ranges = 1;
	} else {
		ranges = pfc->info->ranges;
		nr_ranges = pfc->info->nr_ranges;
	}

	pmx->pins = devm_kzalloc(pfc->dev,
				 sizeof(*pmx->pins) * pfc->info->nr_pins,
				 GFP_KERNEL);
	if (unlikely(!pmx->pins))
		return -ENOMEM;

	pmx->configs = devm_kzalloc(pfc->dev,
				    sizeof(*pmx->configs) * pfc->info->nr_pins,
				    GFP_KERNEL);
	if (unlikely(!pmx->configs))
		return -ENOMEM;

	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
		const struct pinmux_range *range = &ranges[i];
		unsigned int number;

		for (number = range->begin; number <= range->end;
		     number++, nr_pins++) {
			struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
			struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
			const struct sh_pfc_pin *info =
				&pfc->info->pins[nr_pins];

			pin->number = number;
			pin->name = info->name;
			cfg->type = PINMUX_TYPE_NONE;
		}
	}

	pfc->nr_pins = ranges[nr_ranges-1].end + 1;

	return nr_ranges;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx;
	int nr_ranges;

	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
	if (unlikely(!pmx))
		return -ENOMEM;

	pmx->pfc = pfc;
	pfc->pinctrl = pmx;

	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	if (unlikely(nr_ranges < 0))
		return nr_ranges;

	pmx->pctl_desc.name = DRV_NAME;
	pmx->pctl_desc.owner = THIS_MODULE;
	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
	pmx->pctl_desc.pins = pmx->pins;
	pmx->pctl_desc.npins = pfc->info->nr_pins;

	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
	if (pmx->pctl == NULL)
		return -EINVAL;

	return 0;
}

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;

	pinctrl_unregister(pmx->pctl);

	pfc->pinctrl = NULL;
	return 0;
}
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110	10
c6193eac	11	#define DRV_NAME "sh-pfc"
f9492fda	12	#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
ca5481c6	13
1724acfd	14	#include <linux/device.h>
90efde22	15	#include <linux/err.h>
ca5481c6 PM	16	#include <linux/init.h>
ca5481c6 PM	17	#include <linux/module.h>
ca5481c6	18	#include <linux/pinctrl/consumer.h>
ca5481c6	19	#include <linux/pinctrl/pinconf.h>
ca5481c6	20	#include <linux/pinctrl/pinconf-generic.h>
90efde22 LP	21	#include <linux/pinctrl/pinctrl.h>
90efde22 LP	22	#include <linux/pinctrl/pinmux.h>
90efde22 LP	23	#include <linux/slab.h>
90efde22 LP	24	#include <linux/spinlock.h>
ca5481c6	25
f9165132	26	#include "core.h"
c58d9c1b LP	27	#include "../core.h"
c58d9c1b LP	28	#include "../pinconf.h"
f9165132	29
1a0039dc LP	30	struct sh_pfc_pin_config {
	31	u32 type;
	32	};
	33
ca5481c6 PM	34	struct sh_pfc_pinctrl {
ca5481c6 PM	35	struct pinctrl_dev *pctl;
dcc427e1	36	struct pinctrl_desc pctl_desc;
dcc427e1	37
ca5481c6 PM	38	struct sh_pfc *pfc;
ca5481c6 PM	39
3d8d9f1d	40	struct pinctrl_pin_desc *pins;
1a0039dc	41	struct sh_pfc_pin_config *configs;
ca5481c6 PM	42	};
ca5481c6 PM	43
e3f805e8	44	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	45	{
e3f805e8 PM	46	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	47
3d8d9f1d	48	return pmx->pfc->info->nr_groups;
ca5481c6 PM	49	}
ca5481c6 PM	50
e3f805e8	51	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	52	unsigned selector)
ca5481c6 PM	53	{
e3f805e8 PM	54	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	55
3d8d9f1d	56	return pmx->pfc->info->groups[selector].name;
ca5481c6 PM	57	}
ca5481c6 PM	58
3d8d9f1d	59	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	60	const unsigned *pins, unsigned num_pins)
ca5481c6 PM	61	{
e3f805e8 PM	62	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	63
3d8d9f1d LP	64	*pins = pmx->pfc->info->groups[selector].pins;
3d8d9f1d LP	65	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
e3f805e8 PM	66
e3f805e8 PM	67	return 0;
ca5481c6 PM	68	}
ca5481c6 PM	69
fdd85ec3 PM	70	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	71	unsigned offset)
	72	{
	73	seq_printf(s, "%s", DRV_NAME);
	74	}
	75
fe330ce8	76	static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	77	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	78	.get_group_name = sh_pfc_get_group_name,
ca5481c6	79	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	80	.pin_dbg_show = sh_pfc_pin_dbg_show,
ca5481c6 PM	81	};
ca5481c6 PM	82
d93a891f PM	83	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	84	{
	85	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	86
3d8d9f1d	87	return pmx->pfc->info->nr_functions;
d93a891f PM	88	}
	89
	90	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	91	unsigned selector)
	92	{
	93	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	94
3d8d9f1d	95	return pmx->pfc->info->functions[selector].name;
d93a891f	96	}
ca5481c6	97
3d8d9f1d LP	98	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
3d8d9f1d LP	99	unsigned selector,
ca5481c6 PM	100	const char * const **groups,
	101	unsigned * const num_groups)
	102	{
d93a891f PM	103	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
d93a891f PM	104
3d8d9f1d LP	105	*groups = pmx->pfc->info->functions[selector].groups;
3d8d9f1d LP	106	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
d93a891f	107
ca5481c6 PM	108	return 0;
	109	}
	110
3d8d9f1d	111	static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	112	unsigned group)
ca5481c6 PM	113	{
3d8d9f1d LP	114	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	115	struct sh_pfc *pfc = pmx->pfc;
	116	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	117	unsigned long flags;
	118	unsigned int i;
b705c054	119	int ret = 0;
3d8d9f1d LP	120
	121	spin_lock_irqsave(&pfc->lock, flags);
	122
9fddc4a5 LP	123	for (i = 0; i < grp->nr_pins; ++i) {
	124	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	125	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	126
	127	if (cfg->type != PINMUX_TYPE_NONE) {
	128	ret = -EBUSY;
	129	goto done;
	130	}
	131	}
	132
3d8d9f1d	133	for (i = 0; i < grp->nr_pins; ++i) {
b705c054 LP	134	ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
	135	if (ret < 0)
	136	break;
3d8d9f1d LP	137	}
3d8d9f1d LP	138
9fddc4a5	139	done:
3d8d9f1d LP	140	spin_unlock_irqrestore(&pfc->lock, flags);
3d8d9f1d LP	141	return ret;
ca5481c6 PM	142	}
ca5481c6 PM	143
3d8d9f1d	144	static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	145	unsigned group)
ca5481c6 PM	146	{
9fddc4a5 LP	147	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	148	struct sh_pfc *pfc = pmx->pfc;
	149	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	150	unsigned long flags;
	151	unsigned int i;
	152
	153	spin_lock_irqsave(&pfc->lock, flags);
	154
	155	for (i = 0; i < grp->nr_pins; ++i) {
	156	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	157	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	158
	159	cfg->type = PINMUX_TYPE_NONE;
	160	}
	161
	162	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	163	}
	164
	165	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	166	struct pinctrl_gpio_range *range,
	167	unsigned offset)
	168	{
	169	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	170	struct sh_pfc *pfc = pmx->pfc;
1a0039dc LP	171	int idx = sh_pfc_get_pin_index(pfc, offset);
1a0039dc LP	172	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
ca5481c6	173	unsigned long flags;
1a0039dc	174	int ret;
ca5481c6 PM	175
	176	spin_lock_irqsave(&pfc->lock, flags);
	177
9fddc4a5 LP	178	if (cfg->type != PINMUX_TYPE_NONE) {
	179	pr_err("Pin %u is busy, can't configure it as GPIO.\n", offset);
	180	ret = -EBUSY;
	181	goto done;
d93a891f	182	}
ca5481c6	183
9fddc4a5 LP	184	cfg->type = PINMUX_TYPE_GPIO;
9fddc4a5 LP	185
ca5481c6 PM	186	ret = 0;
ca5481c6 PM	187
9fddc4a5	188	done:
ca5481c6 PM	189	spin_unlock_irqrestore(&pfc->lock, flags);
	190
	191	return ret;
	192	}
	193
	194	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	195	struct pinctrl_gpio_range *range,
	196	unsigned offset)
	197	{
9fddc4a5 LP	198	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	199	struct sh_pfc *pfc = pmx->pfc;
	200	int idx = sh_pfc_get_pin_index(pfc, offset);
	201	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	202	unsigned long flags;
	203
	204	spin_lock_irqsave(&pfc->lock, flags);
	205	cfg->type = PINMUX_TYPE_NONE;
	206	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	207	}
	208
	209	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	210	struct pinctrl_gpio_range *range,
	211	unsigned offset, bool input)
	212	{
	213	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0d00f00a LP	214	struct sh_pfc *pfc = pmx->pfc;
	215	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	216	int idx = sh_pfc_get_pin_index(pfc, offset);
0d00f00a	217	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
9fddc4a5	218	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0d00f00a LP	219	unsigned long flags;
0d00f00a LP	220	int ret;
ca5481c6	221
0d00f00a LP	222	spin_lock_irqsave(&pfc->lock, flags);
0d00f00a LP	223
9fddc4a5	224	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
0d00f00a LP	225	if (ret < 0)
	226	goto done;
	227
	228	cfg->type = new_type;
	229
	230	done:
	231	spin_unlock_irqrestore(&pfc->lock, flags);
0d00f00a	232	return ret;
ca5481c6 PM	233	}
ca5481c6 PM	234
fe330ce8	235	static const struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	236	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	237	.get_function_name = sh_pfc_get_function_name,
ca5481c6	238	.get_function_groups = sh_pfc_get_function_groups,
3d8d9f1d LP	239	.enable = sh_pfc_func_enable,
3d8d9f1d LP	240	.disable = sh_pfc_func_disable,
ca5481c6 PM	241	.gpio_request_enable = sh_pfc_gpio_request_enable,
	242	.gpio_disable_free = sh_pfc_gpio_disable_free,
	243	.gpio_set_direction = sh_pfc_gpio_set_direction,
	244	};
	245
c58d9c1b LP	246	/* Check whether the requested parameter is supported for a pin. */
	247	static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
	248	enum pin_config_param param)
	249	{
	250	int idx = sh_pfc_get_pin_index(pfc, _pin);
	251	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	252
	253	switch (param) {
	254	case PIN_CONFIG_BIAS_DISABLE:
	255	return true;
	256
	257	case PIN_CONFIG_BIAS_PULL_UP:
	258	return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
	259
	260	case PIN_CONFIG_BIAS_PULL_DOWN:
	261	return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
	262
	263	default:
	264	return false;
	265	}
	266	}
	267
934cb02b	268	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	269	unsigned long *config)
ca5481c6 PM	270	{
fdd85ec3 PM	271	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	272	struct sh_pfc *pfc = pmx->pfc;
c58d9c1b LP	273	enum pin_config_param param = pinconf_to_config_param(*config);
	274	unsigned long flags;
	275	unsigned int bias;
	276
	277	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
	278	return -ENOTSUPP;
	279
	280	switch (param) {
	281	case PIN_CONFIG_BIAS_DISABLE:
	282	case PIN_CONFIG_BIAS_PULL_UP:
	283	case PIN_CONFIG_BIAS_PULL_DOWN:
	284	if (!pfc->info->ops \|\| !pfc->info->ops->get_bias)
	285	return -ENOTSUPP;
	286
	287	spin_lock_irqsave(&pfc->lock, flags);
	288	bias = pfc->info->ops->get_bias(pfc, _pin);
	289	spin_unlock_irqrestore(&pfc->lock, flags);
	290
	291	if (bias != param)
	292	return -EINVAL;
	293
	294	*config = 0;
	295	break;
d93a891f	296
c58d9c1b LP	297	default:
	298	return -ENOTSUPP;
	299	}
d93a891f	300
fdd85ec3	301	return 0;
ca5481c6 PM	302	}
ca5481c6 PM	303
c58d9c1b	304	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	305	unsigned long config)
ca5481c6 PM	306	{
fdd85ec3	307	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
c58d9c1b LP	308	struct sh_pfc *pfc = pmx->pfc;
	309	enum pin_config_param param = pinconf_to_config_param(config);
	310	unsigned long flags;
fdd85ec3	311
c58d9c1b LP	312	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
c58d9c1b LP	313	return -ENOTSUPP;
fdd85ec3	314
c58d9c1b LP	315	switch (param) {
	316	case PIN_CONFIG_BIAS_PULL_UP:
	317	case PIN_CONFIG_BIAS_PULL_DOWN:
	318	case PIN_CONFIG_BIAS_DISABLE:
	319	if (!pfc->info->ops \|\| !pfc->info->ops->set_bias)
	320	return -ENOTSUPP;
	321
	322	spin_lock_irqsave(&pfc->lock, flags);
	323	pfc->info->ops->set_bias(pfc, _pin, param);
	324	spin_unlock_irqrestore(&pfc->lock, flags);
	325
	326	break;
	327
	328	default:
	329	return -ENOTSUPP;
	330	}
	331
	332	return 0;
fdd85ec3 PM	333	}
fdd85ec3 PM	334
c58d9c1b LP	335	static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
c58d9c1b LP	336	unsigned long config)
fdd85ec3	337	{
c58d9c1b LP	338	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	339	const unsigned int *pins;
	340	unsigned int num_pins;
	341	unsigned int i;
	342
	343	pins = pmx->pfc->info->groups[group].pins;
	344	num_pins = pmx->pfc->info->groups[group].nr_pins;
	345
	346	for (i = 0; i < num_pins; ++i)
	347	sh_pfc_pinconf_set(pctldev, pins[i], config);
	348
	349	return 0;
ca5481c6 PM	350	}
ca5481c6 PM	351
fe330ce8	352	static const struct pinconf_ops sh_pfc_pinconf_ops = {
c58d9c1b LP	353	.is_generic = true,
	354	.pin_config_get = sh_pfc_pinconf_get,
	355	.pin_config_set = sh_pfc_pinconf_set,
	356	.pin_config_group_set = sh_pfc_pinconf_group_set,
	357	.pin_config_config_dbg_show = pinconf_generic_dump_config,
ca5481c6 PM	358	};
ca5481c6 PM	359
63d57383 LP	360	/* PFC ranges -> pinctrl pin descs */
63d57383 LP	361	static int sh_pfc_map_pins(struct sh_pfc pfc, struct sh_pfc_pinctrl pmx)
ca5481c6	362	{
63d57383 LP	363	const struct pinmux_range *ranges;
	364	struct pinmux_range def_range;
	365	unsigned int nr_ranges;
	366	unsigned int nr_pins;
	367	unsigned int i;
	368
	369	if (pfc->info->ranges == NULL) {
	370	def_range.begin = 0;
	371	def_range.end = pfc->info->nr_pins - 1;
	372	ranges = &def_range;
	373	nr_ranges = 1;
	374	} else {
	375	ranges = pfc->info->ranges;
	376	nr_ranges = pfc->info->nr_ranges;
	377	}
ca5481c6	378
3d8d9f1d LP	379	pmx->pins = devm_kzalloc(pfc->dev,
3d8d9f1d LP	380	sizeof(pmx->pins) pfc->info->nr_pins,
1724acfd	381	GFP_KERNEL);
3d8d9f1d	382	if (unlikely(!pmx->pins))
ca5481c6	383	return -ENOMEM;
ca5481c6	384
1a0039dc LP	385	pmx->configs = devm_kzalloc(pfc->dev,
	386	sizeof(pmx->configs) pfc->info->nr_pins,
	387	GFP_KERNEL);
	388	if (unlikely(!pmx->configs))
	389	return -ENOMEM;
	390
63d57383 LP	391	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
	392	const struct pinmux_range *range = &ranges[i];
	393	unsigned int number;
	394
	395	for (number = range->begin; number <= range->end;
	396	number++, nr_pins++) {
1a0039dc	397	struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
3d8d9f1d	398	struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
cd3c1bee LP	399	const struct sh_pfc_pin *info =
cd3c1bee LP	400	&pfc->info->pins[nr_pins];
ca5481c6	401
63d57383 LP	402	pin->number = number;
63d57383 LP	403	pin->name = info->name;
9fddc4a5	404	cfg->type = PINMUX_TYPE_NONE;
63d57383	405	}
ca5481c6 PM	406	}
ca5481c6 PM	407
63d57383 LP	408	pfc->nr_pins = ranges[nr_ranges-1].end + 1;
	409
	410	return nr_ranges;
ca5481c6 PM	411	}
ca5481c6 PM	412
c6193eac	413	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
ca5481c6	414	{
c6193eac	415	struct sh_pfc_pinctrl *pmx;
63d57383	416	int nr_ranges;
ca5481c6	417
1724acfd	418	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
c6193eac LP	419	if (unlikely(!pmx))
	420	return -ENOMEM;
	421
c6193eac LP	422	pmx->pfc = pfc;
c6193eac LP	423	pfc->pinctrl = pmx;
ca5481c6	424
63d57383 LP	425	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	426	if (unlikely(nr_ranges < 0))
	427	return nr_ranges;
ca5481c6	428
dcc427e1 LP	429	pmx->pctl_desc.name = DRV_NAME;
	430	pmx->pctl_desc.owner = THIS_MODULE;
	431	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	432	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	433	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
3d8d9f1d	434	pmx->pctl_desc.pins = pmx->pins;
63d57383	435	pmx->pctl_desc.npins = pfc->info->nr_pins;
dcc427e1 LP	436
dcc427e1 LP	437	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
fd9d05b0 WY	438	if (pmx->pctl == NULL)
fd9d05b0 WY	439	return -EINVAL;
ca5481c6	440
ca5481c6	441	return 0;
ca5481c6 PM	442	}
ca5481c6 PM	443
c6193eac	444	int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
ca5481c6	445	{
c6193eac	446	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
ca5481c6	447
ca5481c6 PM	448	pinctrl_unregister(pmx->pctl);
ca5481c6 PM	449
c6193eac	450	pfc->pinctrl = NULL;
ca5481c6 PM	451	return 0;
ca5481c6 PM	452	}