[mirror_ubuntu-artful-kernel.git] / drivers / pinctrl / sh-pfc / pinctrl.c

/*
 * SuperH Pin Function Controller pinmux support.
 *
 * Copyright (C) 2012  Paul Mundt
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#define DRV_NAME "sh-pfc"

#include <linux/device.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/pinmux.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include "core.h"
#include "../core.h"
#include "../pinconf.h"

struct sh_pfc_pin_config {
	u32 type;
};

struct sh_pfc_pinctrl {
	struct pinctrl_dev *pctl;
	struct pinctrl_desc pctl_desc;

	struct sh_pfc *pfc;

	struct pinctrl_pin_desc *pins;
	struct sh_pfc_pin_config *configs;
};

static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_groups;
}

static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
					 unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->groups[selector].name;
}

static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
				 const unsigned **pins, unsigned *num_pins)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*pins = pmx->pfc->info->groups[selector].pins;
	*num_pins = pmx->pfc->info->groups[selector].nr_pins;

	return 0;
}

static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
				unsigned offset)
{
	seq_printf(s, "%s", DRV_NAME);
}

static int sh_pfc_map_add_config(struct pinctrl_map *map,
				 const char *group_or_pin,
				 enum pinctrl_map_type type,
				 unsigned long *configs,
				 unsigned int num_configs)
{
	unsigned long *cfgs;

	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
		       GFP_KERNEL);
	if (cfgs == NULL)
		return -ENOMEM;

	map->type = type;
	map->data.configs.group_or_pin = group_or_pin;
	map->data.configs.configs = cfgs;
	map->data.configs.num_configs = num_configs;

	return 0;
}

static int sh_pfc_dt_subnode_to_map(struct device *dev, struct device_node *np,
				    struct pinctrl_map **map,
				    unsigned int *num_maps, unsigned int *index)
{
	struct pinctrl_map *maps = *map;
	unsigned int nmaps = *num_maps;
	unsigned int idx = *index;
	unsigned int num_configs;
	const char *function = NULL;
	unsigned long *configs;
	struct property *prop;
	unsigned int num_groups;
	unsigned int num_pins;
	const char *group;
	const char *pin;
	int ret;

	/* Parse the function and configuration properties. At least a function
	 * or one configuration must be specified.
	 */
	ret = of_property_read_string(np, "renesas,function", &function);
	if (ret < 0 && ret != -EINVAL) {
		dev_err(dev, "Invalid function in DT\n");
		return ret;
	}

	ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
	if (ret < 0)
		return ret;

	if (!function && num_configs == 0) {
		dev_err(dev,
			"DT node must contain at least a function or config\n");
		goto done;
	}

	/* Count the number of pins and groups and reallocate mappings. */
	ret = of_property_count_strings(np, "renesas,pins");
	if (ret == -EINVAL) {
		num_pins = 0;
	} else if (ret < 0) {
		dev_err(dev, "Invalid pins list in DT\n");
		goto done;
	} else {
		num_pins = ret;
	}

	ret = of_property_count_strings(np, "renesas,groups");
	if (ret == -EINVAL) {
		num_groups = 0;
	} else if (ret < 0) {
		dev_err(dev, "Invalid pin groups list in DT\n");
		goto done;
	} else {
		num_groups = ret;
	}

	if (!num_pins && !num_groups) {
		dev_err(dev, "No pin or group provided in DT node\n");
		ret = -ENODEV;
		goto done;
	}

	if (function)
		nmaps += num_groups;
	if (configs)
		nmaps += num_pins + num_groups;

	maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
	if (maps == NULL) {
		ret = -ENOMEM;
		goto done;
	}

	*map = maps;
	*num_maps = nmaps;

	/* Iterate over pins and groups and create the mappings. */
	of_property_for_each_string(np, "renesas,groups", prop, group) {
		if (function) {
			maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
			maps[idx].data.mux.group = group;
			maps[idx].data.mux.function = function;
			idx++;
		}

		if (configs) {
			ret = sh_pfc_map_add_config(&maps[idx], group,
						    PIN_MAP_TYPE_CONFIGS_GROUP,
						    configs, num_configs);
			if (ret < 0)
				goto done;

			idx++;
		}
	}

	if (!configs) {
		ret = 0;
		goto done;
	}

	of_property_for_each_string(np, "renesas,pins", prop, pin) {
		ret = sh_pfc_map_add_config(&maps[idx], pin,
					    PIN_MAP_TYPE_CONFIGS_PIN,
					    configs, num_configs);
		if (ret < 0)
			goto done;

		idx++;
	}

done:
	*index = idx;
	kfree(configs);
	return ret;
}

static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
			       struct pinctrl_map *map, unsigned num_maps)
{
	unsigned int i;

	if (map == NULL)
		return;

	for (i = 0; i < num_maps; ++i) {
		if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
		    map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
			kfree(map[i].data.configs.configs);
	}

	kfree(map);
}

static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
				 struct device_node *np,
				 struct pinctrl_map **map, unsigned *num_maps)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct device *dev = pmx->pfc->dev;
	struct device_node *child;
	unsigned int index;
	int ret;

	*map = NULL;
	*num_maps = 0;
	index = 0;

	for_each_child_of_node(np, child) {
		ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
					       &index);
		if (ret < 0)
			goto done;
	}

	/* If no mapping has been found in child nodes try the config node. */
	if (*num_maps == 0) {
		ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
		if (ret < 0)
			goto done;
	}

	if (*num_maps)
		return 0;

	dev_err(dev, "no mapping found in node %s\n", np->full_name);
	ret = -EINVAL;

done:
	if (ret < 0)
		sh_pfc_dt_free_map(pctldev, *map, *num_maps);

	return ret;
}

static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
	.get_groups_count	= sh_pfc_get_groups_count,
	.get_group_name		= sh_pfc_get_group_name,
	.get_group_pins		= sh_pfc_get_group_pins,
	.pin_dbg_show		= sh_pfc_pin_dbg_show,
	.dt_node_to_map		= sh_pfc_dt_node_to_map,
	.dt_free_map		= sh_pfc_dt_free_map,
};

static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->nr_functions;
}

static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
					    unsigned selector)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	return pmx->pfc->info->functions[selector].name;
}

static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
				      unsigned selector,
				      const char * const **groups,
				      unsigned * const num_groups)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);

	*groups = pmx->pfc->info->functions[selector].groups;
	*num_groups = pmx->pfc->info->functions[selector].nr_groups;

	return 0;
}

static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
			      unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;
	int ret = 0;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		if (cfg->type != PINMUX_TYPE_NONE) {
			ret = -EBUSY;
			goto done;
		}
	}

	for (i = 0; i < grp->nr_pins; ++i) {
		ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
		if (ret < 0)
			break;
	}

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
				unsigned group)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	unsigned long flags;
	unsigned int i;

	spin_lock_irqsave(&pfc->lock, flags);

	for (i = 0; i < grp->nr_pins; ++i) {
		int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
		struct sh_pfc_pin_config *cfg = &pmx->configs[idx];

		cfg->type = PINMUX_TYPE_NONE;
	}

	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
				      struct pinctrl_gpio_range *range,
				      unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&pfc->lock, flags);

	if (cfg->type != PINMUX_TYPE_NONE) {
		dev_err(pfc->dev,
			"Pin %u is busy, can't configure it as GPIO.\n",
			offset);
		ret = -EBUSY;
		goto done;
	}

	if (!pfc->gpio) {
		/* If GPIOs are handled externally the pin mux type need to be
		 * set to GPIO here.
		 */
		const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

		ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
		if (ret < 0)
			goto done;
	}

	cfg->type = PINMUX_TYPE_GPIO;

	ret = 0;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);

	return ret;
}

static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;

	spin_lock_irqsave(&pfc->lock, flags);
	cfg->type = PINMUX_TYPE_NONE;
	spin_unlock_irqrestore(&pfc->lock, flags);
}

static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
				     struct pinctrl_gpio_range *range,
				     unsigned offset, bool input)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	int idx = sh_pfc_get_pin_index(pfc, offset);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	unsigned long flags;
	unsigned int dir;
	int ret;

	/* Check if the requested direction is supported by the pin. Not all SoC
	 * provide pin config data, so perform the check conditionally.
	 */
	if (pin->configs) {
		dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
		if (!(pin->configs & dir))
			return -EINVAL;
	}

	spin_lock_irqsave(&pfc->lock, flags);

	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
	if (ret < 0)
		goto done;

	cfg->type = new_type;

done:
	spin_unlock_irqrestore(&pfc->lock, flags);
	return ret;
}

static const struct pinmux_ops sh_pfc_pinmux_ops = {
	.get_functions_count	= sh_pfc_get_functions_count,
	.get_function_name	= sh_pfc_get_function_name,
	.get_function_groups	= sh_pfc_get_function_groups,
	.enable			= sh_pfc_func_enable,
	.disable		= sh_pfc_func_disable,
	.gpio_request_enable	= sh_pfc_gpio_request_enable,
	.gpio_disable_free	= sh_pfc_gpio_disable_free,
	.gpio_set_direction	= sh_pfc_gpio_set_direction,
};

/* Check whether the requested parameter is supported for a pin. */
static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
				    enum pin_config_param param)
{
	int idx = sh_pfc_get_pin_index(pfc, _pin);
	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
		return true;

	case PIN_CONFIG_BIAS_PULL_UP:
		return pin->configs & SH_PFC_PIN_CFG_PULL_UP;

	case PIN_CONFIG_BIAS_PULL_DOWN:
		return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;

	default:
		return false;
	}
}

static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long *config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(*config);
	unsigned long flags;
	unsigned int bias;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_DISABLE:
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
		if (!pfc->info->ops || !pfc->info->ops->get_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		bias = pfc->info->ops->get_bias(pfc, _pin);
		spin_unlock_irqrestore(&pfc->lock, flags);

		if (bias != param)
			return -EINVAL;

		*config = 0;
		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
			      unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	struct sh_pfc *pfc = pmx->pfc;
	enum pin_config_param param = pinconf_to_config_param(config);
	unsigned long flags;

	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
		return -ENOTSUPP;

	switch (param) {
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
	case PIN_CONFIG_BIAS_DISABLE:
		if (!pfc->info->ops || !pfc->info->ops->set_bias)
			return -ENOTSUPP;

		spin_lock_irqsave(&pfc->lock, flags);
		pfc->info->ops->set_bias(pfc, _pin, param);
		spin_unlock_irqrestore(&pfc->lock, flags);

		break;

	default:
		return -ENOTSUPP;
	}

	return 0;
}

static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
				    unsigned long config)
{
	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	const unsigned int *pins;
	unsigned int num_pins;
	unsigned int i;

	pins = pmx->pfc->info->groups[group].pins;
	num_pins = pmx->pfc->info->groups[group].nr_pins;

	for (i = 0; i < num_pins; ++i)
		sh_pfc_pinconf_set(pctldev, pins[i], config);

	return 0;
}

static const struct pinconf_ops sh_pfc_pinconf_ops = {
	.is_generic			= true,
	.pin_config_get			= sh_pfc_pinconf_get,
	.pin_config_set			= sh_pfc_pinconf_set,
	.pin_config_group_set		= sh_pfc_pinconf_group_set,
	.pin_config_config_dbg_show	= pinconf_generic_dump_config,
};

/* PFC ranges -> pinctrl pin descs */
static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
{
	const struct pinmux_range *ranges;
	struct pinmux_range def_range;
	unsigned int nr_ranges;
	unsigned int nr_pins;
	unsigned int i;

	if (pfc->info->ranges == NULL) {
		def_range.begin = 0;
		def_range.end = pfc->info->nr_pins - 1;
		ranges = &def_range;
		nr_ranges = 1;
	} else {
		ranges = pfc->info->ranges;
		nr_ranges = pfc->info->nr_ranges;
	}

	pmx->pins = devm_kzalloc(pfc->dev,
				 sizeof(*pmx->pins) * pfc->info->nr_pins,
				 GFP_KERNEL);
	if (unlikely(!pmx->pins))
		return -ENOMEM;

	pmx->configs = devm_kzalloc(pfc->dev,
				    sizeof(*pmx->configs) * pfc->info->nr_pins,
				    GFP_KERNEL);
	if (unlikely(!pmx->configs))
		return -ENOMEM;

	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
		const struct pinmux_range *range = &ranges[i];
		unsigned int number;

		for (number = range->begin; number <= range->end;
		     number++, nr_pins++) {
			struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
			struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
			const struct sh_pfc_pin *info =
				&pfc->info->pins[nr_pins];

			pin->number = number;
			pin->name = info->name;
			cfg->type = PINMUX_TYPE_NONE;
		}
	}

	pfc->nr_pins = ranges[nr_ranges-1].end + 1;

	return nr_ranges;
}

int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx;
	int nr_ranges;

	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
	if (unlikely(!pmx))
		return -ENOMEM;

	pmx->pfc = pfc;
	pfc->pinctrl = pmx;

	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	if (unlikely(nr_ranges < 0))
		return nr_ranges;

	pmx->pctl_desc.name = DRV_NAME;
	pmx->pctl_desc.owner = THIS_MODULE;
	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
	pmx->pctl_desc.pins = pmx->pins;
	pmx->pctl_desc.npins = pfc->info->nr_pins;

	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
	if (pmx->pctl == NULL)
		return -EINVAL;

	return 0;
}

int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
{
	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;

	pinctrl_unregister(pmx->pctl);

	pfc->pinctrl = NULL;
	return 0;
}
Commit	Line	Data
ca5481c6 PM	1	/*
	2	* SuperH Pin Function Controller pinmux support.
	3	*
	4	* Copyright (C) 2012 Paul Mundt
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
54407110	10
c6193eac	11	#define DRV_NAME "sh-pfc"
ca5481c6	12
1724acfd	13	#include <linux/device.h>
90efde22	14	#include <linux/err.h>
ca5481c6 PM	15	#include <linux/init.h>
ca5481c6 PM	16	#include <linux/module.h>
fe1c9a82	17	#include <linux/of.h>
ca5481c6	18	#include <linux/pinctrl/consumer.h>
fe1c9a82	19	#include <linux/pinctrl/machine.h>
ca5481c6	20	#include <linux/pinctrl/pinconf.h>
ca5481c6	21	#include <linux/pinctrl/pinconf-generic.h>
90efde22 LP	22	#include <linux/pinctrl/pinctrl.h>
90efde22 LP	23	#include <linux/pinctrl/pinmux.h>
90efde22 LP	24	#include <linux/slab.h>
90efde22 LP	25	#include <linux/spinlock.h>
ca5481c6	26
f9165132	27	#include "core.h"
c58d9c1b LP	28	#include "../core.h"
c58d9c1b LP	29	#include "../pinconf.h"
f9165132	30
1a0039dc LP	31	struct sh_pfc_pin_config {
	32	u32 type;
	33	};
	34
ca5481c6 PM	35	struct sh_pfc_pinctrl {
ca5481c6 PM	36	struct pinctrl_dev *pctl;
dcc427e1	37	struct pinctrl_desc pctl_desc;
dcc427e1	38
ca5481c6 PM	39	struct sh_pfc *pfc;
ca5481c6 PM	40
3d8d9f1d	41	struct pinctrl_pin_desc *pins;
1a0039dc	42	struct sh_pfc_pin_config *configs;
ca5481c6 PM	43	};
ca5481c6 PM	44
e3f805e8	45	static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
ca5481c6	46	{
e3f805e8 PM	47	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	48
3d8d9f1d	49	return pmx->pfc->info->nr_groups;
ca5481c6 PM	50	}
ca5481c6 PM	51
e3f805e8	52	static const char sh_pfc_get_group_name(struct pinctrl_dev pctldev,
ca5481c6 PM	53	unsigned selector)
ca5481c6 PM	54	{
e3f805e8 PM	55	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	56
3d8d9f1d	57	return pmx->pfc->info->groups[selector].name;
ca5481c6 PM	58	}
ca5481c6 PM	59
3d8d9f1d	60	static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	61	const unsigned *pins, unsigned num_pins)
ca5481c6 PM	62	{
e3f805e8 PM	63	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
e3f805e8 PM	64
3d8d9f1d LP	65	*pins = pmx->pfc->info->groups[selector].pins;
3d8d9f1d LP	66	*num_pins = pmx->pfc->info->groups[selector].nr_pins;
e3f805e8 PM	67
e3f805e8 PM	68	return 0;
ca5481c6 PM	69	}
ca5481c6 PM	70
fdd85ec3 PM	71	static void sh_pfc_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
	72	unsigned offset)
	73	{
	74	seq_printf(s, "%s", DRV_NAME);
	75	}
	76
12f3ad8d LP	77	static int sh_pfc_map_add_config(struct pinctrl_map *map,
	78	const char *group_or_pin,
	79	enum pinctrl_map_type type,
	80	unsigned long *configs,
	81	unsigned int num_configs)
	82	{
	83	unsigned long *cfgs;
	84
	85	cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
	86	GFP_KERNEL);
	87	if (cfgs == NULL)
	88	return -ENOMEM;
	89
	90	map->type = type;
	91	map->data.configs.group_or_pin = group_or_pin;
	92	map->data.configs.configs = cfgs;
	93	map->data.configs.num_configs = num_configs;
	94
	95	return 0;
	96	}
	97
fe1c9a82 LP	98	static int sh_pfc_dt_subnode_to_map(struct device dev, struct device_node np,
	99	struct pinctrl_map **map,
	100	unsigned int num_maps, unsigned int index)
	101	{
	102	struct pinctrl_map maps = map;
	103	unsigned int nmaps = *num_maps;
	104	unsigned int idx = *index;
12f3ad8d	105	unsigned int num_configs;
fe1c9a82	106	const char *function = NULL;
12f3ad8d	107	unsigned long *configs;
fe1c9a82	108	struct property *prop;
12f3ad8d LP	109	unsigned int num_groups;
12f3ad8d LP	110	unsigned int num_pins;
fe1c9a82	111	const char *group;
12f3ad8d	112	const char *pin;
fe1c9a82 LP	113	int ret;
	114
	115	/* Parse the function and configuration properties. At least a function
	116	* or one configuration must be specified.
	117	*/
	118	ret = of_property_read_string(np, "renesas,function", &function);
	119	if (ret < 0 && ret != -EINVAL) {
	120	dev_err(dev, "Invalid function in DT\n");
	121	return ret;
	122	}
	123
12f3ad8d LP	124	ret = pinconf_generic_parse_dt_config(np, &configs, &num_configs);
	125	if (ret < 0)
	126	return ret;
	127
	128	if (!function && num_configs == 0) {
	129	dev_err(dev,
	130	"DT node must contain at least a function or config\n");
fe1c9a82 LP	131	goto done;
	132	}
	133
12f3ad8d LP	134	/* Count the number of pins and groups and reallocate mappings. */
	135	ret = of_property_count_strings(np, "renesas,pins");
	136	if (ret == -EINVAL) {
	137	num_pins = 0;
	138	} else if (ret < 0) {
	139	dev_err(dev, "Invalid pins list in DT\n");
	140	goto done;
	141	} else {
	142	num_pins = ret;
	143	}
	144
fe1c9a82	145	ret = of_property_count_strings(np, "renesas,groups");
12f3ad8d LP	146	if (ret == -EINVAL) {
	147	num_groups = 0;
	148	} else if (ret < 0) {
fe1c9a82 LP	149	dev_err(dev, "Invalid pin groups list in DT\n");
fe1c9a82 LP	150	goto done;
12f3ad8d LP	151	} else {
12f3ad8d LP	152	num_groups = ret;
fe1c9a82 LP	153	}
fe1c9a82 LP	154
12f3ad8d LP	155	if (!num_pins && !num_groups) {
12f3ad8d LP	156	dev_err(dev, "No pin or group provided in DT node\n");
fe1c9a82 LP	157	ret = -ENODEV;
	158	goto done;
	159	}
	160
12f3ad8d LP	161	if (function)
	162	nmaps += num_groups;
	163	if (configs)
	164	nmaps += num_pins + num_groups;
fe1c9a82 LP	165
	166	maps = krealloc(maps, sizeof(maps) nmaps, GFP_KERNEL);
	167	if (maps == NULL) {
	168	ret = -ENOMEM;
	169	goto done;
	170	}
	171
	172	*map = maps;
	173	*num_maps = nmaps;
	174
	175	/* Iterate over pins and groups and create the mappings. */
	176	of_property_for_each_string(np, "renesas,groups", prop, group) {
12f3ad8d LP	177	if (function) {
	178	maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
	179	maps[idx].data.mux.group = group;
	180	maps[idx].data.mux.function = function;
	181	idx++;
	182	}
	183
	184	if (configs) {
	185	ret = sh_pfc_map_add_config(&maps[idx], group,
	186	PIN_MAP_TYPE_CONFIGS_GROUP,
	187	configs, num_configs);
	188	if (ret < 0)
	189	goto done;
	190
	191	idx++;
	192	}
fe1c9a82 LP	193	}
fe1c9a82 LP	194
12f3ad8d LP	195	if (!configs) {
	196	ret = 0;
	197	goto done;
	198	}
	199
	200	of_property_for_each_string(np, "renesas,pins", prop, pin) {
	201	ret = sh_pfc_map_add_config(&maps[idx], pin,
	202	PIN_MAP_TYPE_CONFIGS_PIN,
	203	configs, num_configs);
	204	if (ret < 0)
	205	goto done;
	206
	207	idx++;
	208	}
fe1c9a82 LP	209
	210	done:
	211	*index = idx;
12f3ad8d	212	kfree(configs);
fe1c9a82 LP	213	return ret;
	214	}
	215
	216	static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
	217	struct pinctrl_map *map, unsigned num_maps)
	218	{
12f3ad8d LP	219	unsigned int i;
	220
	221	if (map == NULL)
	222	return;
	223
	224	for (i = 0; i < num_maps; ++i) {
	225	if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP \|\|
	226	map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
	227	kfree(map[i].data.configs.configs);
	228	}
	229
fe1c9a82 LP	230	kfree(map);
	231	}
	232
	233	static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
	234	struct device_node *np,
	235	struct pinctrl_map *map, unsigned num_maps)
	236	{
	237	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	238	struct device *dev = pmx->pfc->dev;
	239	struct device_node *child;
	240	unsigned int index;
	241	int ret;
	242
	243	*map = NULL;
	244	*num_maps = 0;
	245	index = 0;
	246
	247	for_each_child_of_node(np, child) {
	248	ret = sh_pfc_dt_subnode_to_map(dev, child, map, num_maps,
	249	&index);
	250	if (ret < 0)
	251	goto done;
	252	}
	253
	254	/* If no mapping has been found in child nodes try the config node. */
	255	if (*num_maps == 0) {
	256	ret = sh_pfc_dt_subnode_to_map(dev, np, map, num_maps, &index);
	257	if (ret < 0)
	258	goto done;
	259	}
	260
	261	if (*num_maps)
	262	return 0;
	263
	264	dev_err(dev, "no mapping found in node %s\n", np->full_name);
	265	ret = -EINVAL;
	266
	267	done:
	268	if (ret < 0)
	269	sh_pfc_dt_free_map(pctldev, map, num_maps);
	270
	271	return ret;
	272	}
	273
fe330ce8	274	static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
e3f805e8 PM	275	.get_groups_count = sh_pfc_get_groups_count,
e3f805e8 PM	276	.get_group_name = sh_pfc_get_group_name,
ca5481c6	277	.get_group_pins = sh_pfc_get_group_pins,
fdd85ec3	278	.pin_dbg_show = sh_pfc_pin_dbg_show,
fe1c9a82 LP	279	.dt_node_to_map = sh_pfc_dt_node_to_map,
fe1c9a82 LP	280	.dt_free_map = sh_pfc_dt_free_map,
ca5481c6 PM	281	};
ca5481c6 PM	282
d93a891f PM	283	static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
	284	{
	285	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	286
3d8d9f1d	287	return pmx->pfc->info->nr_functions;
d93a891f PM	288	}
	289
	290	static const char sh_pfc_get_function_name(struct pinctrl_dev pctldev,
	291	unsigned selector)
	292	{
	293	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	294
3d8d9f1d	295	return pmx->pfc->info->functions[selector].name;
d93a891f	296	}
ca5481c6	297
3d8d9f1d LP	298	static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
3d8d9f1d LP	299	unsigned selector,
ca5481c6 PM	300	const char * const **groups,
	301	unsigned * const num_groups)
	302	{
d93a891f PM	303	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
d93a891f PM	304
3d8d9f1d LP	305	*groups = pmx->pfc->info->functions[selector].groups;
3d8d9f1d LP	306	*num_groups = pmx->pfc->info->functions[selector].nr_groups;
d93a891f	307
ca5481c6 PM	308	return 0;
	309	}
	310
3d8d9f1d	311	static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	312	unsigned group)
ca5481c6 PM	313	{
3d8d9f1d LP	314	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	315	struct sh_pfc *pfc = pmx->pfc;
	316	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	317	unsigned long flags;
	318	unsigned int i;
b705c054	319	int ret = 0;
3d8d9f1d LP	320
	321	spin_lock_irqsave(&pfc->lock, flags);
	322
9fddc4a5 LP	323	for (i = 0; i < grp->nr_pins; ++i) {
	324	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	325	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	326
	327	if (cfg->type != PINMUX_TYPE_NONE) {
	328	ret = -EBUSY;
	329	goto done;
	330	}
	331	}
	332
3d8d9f1d	333	for (i = 0; i < grp->nr_pins; ++i) {
b705c054 LP	334	ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
	335	if (ret < 0)
	336	break;
3d8d9f1d LP	337	}
3d8d9f1d LP	338
9fddc4a5	339	done:
3d8d9f1d LP	340	spin_unlock_irqrestore(&pfc->lock, flags);
3d8d9f1d LP	341	return ret;
ca5481c6 PM	342	}
ca5481c6 PM	343
3d8d9f1d	344	static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
ca5481c6 PM	345	unsigned group)
ca5481c6 PM	346	{
9fddc4a5 LP	347	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	348	struct sh_pfc *pfc = pmx->pfc;
	349	const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
	350	unsigned long flags;
	351	unsigned int i;
	352
	353	spin_lock_irqsave(&pfc->lock, flags);
	354
	355	for (i = 0; i < grp->nr_pins; ++i) {
	356	int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
	357	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	358
	359	cfg->type = PINMUX_TYPE_NONE;
	360	}
	361
	362	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	363	}
	364
	365	static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
	366	struct pinctrl_gpio_range *range,
	367	unsigned offset)
	368	{
	369	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	370	struct sh_pfc *pfc = pmx->pfc;
1a0039dc LP	371	int idx = sh_pfc_get_pin_index(pfc, offset);
1a0039dc LP	372	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
ca5481c6	373	unsigned long flags;
1a0039dc	374	int ret;
ca5481c6 PM	375
	376	spin_lock_irqsave(&pfc->lock, flags);
	377
9fddc4a5	378	if (cfg->type != PINMUX_TYPE_NONE) {
9a643c9a LP	379	dev_err(pfc->dev,
	380	"Pin %u is busy, can't configure it as GPIO.\n",
	381	offset);
9fddc4a5 LP	382	ret = -EBUSY;
9fddc4a5 LP	383	goto done;
d93a891f	384	}
ca5481c6	385
e3c47051 LP	386	if (!pfc->gpio) {
	387	/* If GPIOs are handled externally the pin mux type need to be
	388	* set to GPIO here.
	389	*/
	390	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	391
	392	ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
	393	if (ret < 0)
	394	goto done;
	395	}
	396
9fddc4a5 LP	397	cfg->type = PINMUX_TYPE_GPIO;
9fddc4a5 LP	398
ca5481c6 PM	399	ret = 0;
ca5481c6 PM	400
9fddc4a5	401	done:
ca5481c6 PM	402	spin_unlock_irqrestore(&pfc->lock, flags);
	403
	404	return ret;
	405	}
	406
	407	static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
	408	struct pinctrl_gpio_range *range,
	409	unsigned offset)
	410	{
9fddc4a5 LP	411	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	412	struct sh_pfc *pfc = pmx->pfc;
	413	int idx = sh_pfc_get_pin_index(pfc, offset);
	414	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
	415	unsigned long flags;
	416
	417	spin_lock_irqsave(&pfc->lock, flags);
	418	cfg->type = PINMUX_TYPE_NONE;
	419	spin_unlock_irqrestore(&pfc->lock, flags);
ca5481c6 PM	420	}
	421
	422	static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
	423	struct pinctrl_gpio_range *range,
	424	unsigned offset, bool input)
	425	{
	426	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
0d00f00a LP	427	struct sh_pfc *pfc = pmx->pfc;
	428	int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
	429	int idx = sh_pfc_get_pin_index(pfc, offset);
0d00f00a	430	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
9fddc4a5	431	struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
0d00f00a	432	unsigned long flags;
6dc9b455	433	unsigned int dir;
0d00f00a	434	int ret;
ca5481c6	435
6dc9b455 LP	436	/* Check if the requested direction is supported by the pin. Not all SoC
	437	* provide pin config data, so perform the check conditionally.
	438	*/
	439	if (pin->configs) {
	440	dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
	441	if (!(pin->configs & dir))
	442	return -EINVAL;
	443	}
	444
0d00f00a LP	445	spin_lock_irqsave(&pfc->lock, flags);
0d00f00a LP	446
9fddc4a5	447	ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
0d00f00a LP	448	if (ret < 0)
	449	goto done;
	450
	451	cfg->type = new_type;
	452
	453	done:
	454	spin_unlock_irqrestore(&pfc->lock, flags);
0d00f00a	455	return ret;
ca5481c6 PM	456	}
ca5481c6 PM	457
fe330ce8	458	static const struct pinmux_ops sh_pfc_pinmux_ops = {
d93a891f PM	459	.get_functions_count = sh_pfc_get_functions_count,
d93a891f PM	460	.get_function_name = sh_pfc_get_function_name,
ca5481c6	461	.get_function_groups = sh_pfc_get_function_groups,
3d8d9f1d LP	462	.enable = sh_pfc_func_enable,
3d8d9f1d LP	463	.disable = sh_pfc_func_disable,
ca5481c6 PM	464	.gpio_request_enable = sh_pfc_gpio_request_enable,
	465	.gpio_disable_free = sh_pfc_gpio_disable_free,
	466	.gpio_set_direction = sh_pfc_gpio_set_direction,
	467	};
	468
c58d9c1b LP	469	/* Check whether the requested parameter is supported for a pin. */
	470	static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
	471	enum pin_config_param param)
	472	{
	473	int idx = sh_pfc_get_pin_index(pfc, _pin);
	474	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
	475
	476	switch (param) {
	477	case PIN_CONFIG_BIAS_DISABLE:
	478	return true;
	479
	480	case PIN_CONFIG_BIAS_PULL_UP:
	481	return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
	482
	483	case PIN_CONFIG_BIAS_PULL_DOWN:
	484	return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
	485
	486	default:
	487	return false;
	488	}
	489	}
	490
934cb02b	491	static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	492	unsigned long *config)
ca5481c6 PM	493	{
fdd85ec3 PM	494	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
fdd85ec3 PM	495	struct sh_pfc *pfc = pmx->pfc;
c58d9c1b LP	496	enum pin_config_param param = pinconf_to_config_param(*config);
	497	unsigned long flags;
	498	unsigned int bias;
	499
	500	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
	501	return -ENOTSUPP;
	502
	503	switch (param) {
	504	case PIN_CONFIG_BIAS_DISABLE:
	505	case PIN_CONFIG_BIAS_PULL_UP:
	506	case PIN_CONFIG_BIAS_PULL_DOWN:
	507	if (!pfc->info->ops \|\| !pfc->info->ops->get_bias)
	508	return -ENOTSUPP;
	509
	510	spin_lock_irqsave(&pfc->lock, flags);
	511	bias = pfc->info->ops->get_bias(pfc, _pin);
	512	spin_unlock_irqrestore(&pfc->lock, flags);
	513
	514	if (bias != param)
	515	return -EINVAL;
	516
	517	*config = 0;
	518	break;
d93a891f	519
c58d9c1b LP	520	default:
	521	return -ENOTSUPP;
	522	}
d93a891f	523
fdd85ec3	524	return 0;
ca5481c6 PM	525	}
ca5481c6 PM	526
c58d9c1b	527	static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
ca5481c6 PM	528	unsigned long config)
ca5481c6 PM	529	{
fdd85ec3	530	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
c58d9c1b LP	531	struct sh_pfc *pfc = pmx->pfc;
	532	enum pin_config_param param = pinconf_to_config_param(config);
	533	unsigned long flags;
fdd85ec3	534
c58d9c1b LP	535	if (!sh_pfc_pinconf_validate(pfc, _pin, param))
c58d9c1b LP	536	return -ENOTSUPP;
fdd85ec3	537
c58d9c1b LP	538	switch (param) {
	539	case PIN_CONFIG_BIAS_PULL_UP:
	540	case PIN_CONFIG_BIAS_PULL_DOWN:
	541	case PIN_CONFIG_BIAS_DISABLE:
	542	if (!pfc->info->ops \|\| !pfc->info->ops->set_bias)
	543	return -ENOTSUPP;
	544
	545	spin_lock_irqsave(&pfc->lock, flags);
	546	pfc->info->ops->set_bias(pfc, _pin, param);
	547	spin_unlock_irqrestore(&pfc->lock, flags);
	548
	549	break;
	550
	551	default:
	552	return -ENOTSUPP;
	553	}
	554
	555	return 0;
fdd85ec3 PM	556	}
fdd85ec3 PM	557
c58d9c1b LP	558	static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
c58d9c1b LP	559	unsigned long config)
fdd85ec3	560	{
c58d9c1b LP	561	struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
	562	const unsigned int *pins;
	563	unsigned int num_pins;
	564	unsigned int i;
	565
	566	pins = pmx->pfc->info->groups[group].pins;
	567	num_pins = pmx->pfc->info->groups[group].nr_pins;
	568
	569	for (i = 0; i < num_pins; ++i)
	570	sh_pfc_pinconf_set(pctldev, pins[i], config);
	571
	572	return 0;
ca5481c6 PM	573	}
ca5481c6 PM	574
fe330ce8	575	static const struct pinconf_ops sh_pfc_pinconf_ops = {
c58d9c1b LP	576	.is_generic = true,
	577	.pin_config_get = sh_pfc_pinconf_get,
	578	.pin_config_set = sh_pfc_pinconf_set,
	579	.pin_config_group_set = sh_pfc_pinconf_group_set,
	580	.pin_config_config_dbg_show = pinconf_generic_dump_config,
ca5481c6 PM	581	};
ca5481c6 PM	582
63d57383 LP	583	/* PFC ranges -> pinctrl pin descs */
63d57383 LP	584	static int sh_pfc_map_pins(struct sh_pfc pfc, struct sh_pfc_pinctrl pmx)
ca5481c6	585	{
63d57383 LP	586	const struct pinmux_range *ranges;
	587	struct pinmux_range def_range;
	588	unsigned int nr_ranges;
	589	unsigned int nr_pins;
	590	unsigned int i;
	591
	592	if (pfc->info->ranges == NULL) {
	593	def_range.begin = 0;
	594	def_range.end = pfc->info->nr_pins - 1;
	595	ranges = &def_range;
	596	nr_ranges = 1;
	597	} else {
	598	ranges = pfc->info->ranges;
	599	nr_ranges = pfc->info->nr_ranges;
	600	}
ca5481c6	601
3d8d9f1d LP	602	pmx->pins = devm_kzalloc(pfc->dev,
3d8d9f1d LP	603	sizeof(pmx->pins) pfc->info->nr_pins,
1724acfd	604	GFP_KERNEL);
3d8d9f1d	605	if (unlikely(!pmx->pins))
ca5481c6	606	return -ENOMEM;
ca5481c6	607
1a0039dc LP	608	pmx->configs = devm_kzalloc(pfc->dev,
	609	sizeof(pmx->configs) pfc->info->nr_pins,
	610	GFP_KERNEL);
	611	if (unlikely(!pmx->configs))
	612	return -ENOMEM;
	613
63d57383 LP	614	for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
	615	const struct pinmux_range *range = &ranges[i];
	616	unsigned int number;
	617
	618	for (number = range->begin; number <= range->end;
	619	number++, nr_pins++) {
1a0039dc	620	struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
3d8d9f1d	621	struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
cd3c1bee LP	622	const struct sh_pfc_pin *info =
cd3c1bee LP	623	&pfc->info->pins[nr_pins];
ca5481c6	624
63d57383 LP	625	pin->number = number;
63d57383 LP	626	pin->name = info->name;
9fddc4a5	627	cfg->type = PINMUX_TYPE_NONE;
63d57383	628	}
ca5481c6 PM	629	}
ca5481c6 PM	630
63d57383 LP	631	pfc->nr_pins = ranges[nr_ranges-1].end + 1;
	632
	633	return nr_ranges;
ca5481c6 PM	634	}
ca5481c6 PM	635
c6193eac	636	int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
ca5481c6	637	{
c6193eac	638	struct sh_pfc_pinctrl *pmx;
63d57383	639	int nr_ranges;
ca5481c6	640
1724acfd	641	pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
c6193eac LP	642	if (unlikely(!pmx))
	643	return -ENOMEM;
	644
c6193eac LP	645	pmx->pfc = pfc;
c6193eac LP	646	pfc->pinctrl = pmx;
ca5481c6	647
63d57383 LP	648	nr_ranges = sh_pfc_map_pins(pfc, pmx);
	649	if (unlikely(nr_ranges < 0))
	650	return nr_ranges;
ca5481c6	651
dcc427e1 LP	652	pmx->pctl_desc.name = DRV_NAME;
	653	pmx->pctl_desc.owner = THIS_MODULE;
	654	pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
	655	pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
	656	pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
3d8d9f1d	657	pmx->pctl_desc.pins = pmx->pins;
63d57383	658	pmx->pctl_desc.npins = pfc->info->nr_pins;
dcc427e1 LP	659
dcc427e1 LP	660	pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
fd9d05b0 WY	661	if (pmx->pctl == NULL)
fd9d05b0 WY	662	return -EINVAL;
ca5481c6	663
ca5481c6	664	return 0;
ca5481c6 PM	665	}
ca5481c6 PM	666
c6193eac	667	int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc)
ca5481c6	668	{
c6193eac	669	struct sh_pfc_pinctrl *pmx = pfc->pinctrl;
ca5481c6	670
ca5481c6 PM	671	pinctrl_unregister(pmx->pctl);
ca5481c6 PM	672
c6193eac	673	pfc->pinctrl = NULL;
ca5481c6 PM	674	return 0;
ca5481c6 PM	675	}