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Commit | Line | Data |
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ca5481c6 PM |
1 | /* |
2 | * SuperH Pin Function Controller pinmux support. | |
3 | * | |
4 | * Copyright (C) 2012 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
54407110 | 10 | |
c6193eac | 11 | #define DRV_NAME "sh-pfc" |
ca5481c6 | 12 | |
1724acfd | 13 | #include <linux/device.h> |
90efde22 | 14 | #include <linux/err.h> |
ca5481c6 PM |
15 | #include <linux/init.h> |
16 | #include <linux/module.h> | |
ca5481c6 | 17 | #include <linux/pinctrl/consumer.h> |
ca5481c6 | 18 | #include <linux/pinctrl/pinconf.h> |
ca5481c6 | 19 | #include <linux/pinctrl/pinconf-generic.h> |
90efde22 LP |
20 | #include <linux/pinctrl/pinctrl.h> |
21 | #include <linux/pinctrl/pinmux.h> | |
90efde22 LP |
22 | #include <linux/slab.h> |
23 | #include <linux/spinlock.h> | |
ca5481c6 | 24 | |
f9165132 | 25 | #include "core.h" |
c58d9c1b LP |
26 | #include "../core.h" |
27 | #include "../pinconf.h" | |
f9165132 | 28 | |
1a0039dc LP |
29 | struct sh_pfc_pin_config { |
30 | u32 type; | |
31 | }; | |
32 | ||
ca5481c6 PM |
33 | struct sh_pfc_pinctrl { |
34 | struct pinctrl_dev *pctl; | |
dcc427e1 | 35 | struct pinctrl_desc pctl_desc; |
dcc427e1 | 36 | |
ca5481c6 PM |
37 | struct sh_pfc *pfc; |
38 | ||
3d8d9f1d | 39 | struct pinctrl_pin_desc *pins; |
1a0039dc | 40 | struct sh_pfc_pin_config *configs; |
ca5481c6 PM |
41 | }; |
42 | ||
e3f805e8 | 43 | static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) |
ca5481c6 | 44 | { |
e3f805e8 PM |
45 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
46 | ||
3d8d9f1d | 47 | return pmx->pfc->info->nr_groups; |
ca5481c6 PM |
48 | } |
49 | ||
e3f805e8 | 50 | static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, |
ca5481c6 PM |
51 | unsigned selector) |
52 | { | |
e3f805e8 PM |
53 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
54 | ||
3d8d9f1d | 55 | return pmx->pfc->info->groups[selector].name; |
ca5481c6 PM |
56 | } |
57 | ||
3d8d9f1d | 58 | static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
59 | const unsigned **pins, unsigned *num_pins) |
60 | { | |
e3f805e8 PM |
61 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
62 | ||
3d8d9f1d LP |
63 | *pins = pmx->pfc->info->groups[selector].pins; |
64 | *num_pins = pmx->pfc->info->groups[selector].nr_pins; | |
e3f805e8 PM |
65 | |
66 | return 0; | |
ca5481c6 PM |
67 | } |
68 | ||
fdd85ec3 PM |
69 | static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
70 | unsigned offset) | |
71 | { | |
72 | seq_printf(s, "%s", DRV_NAME); | |
73 | } | |
74 | ||
fe330ce8 | 75 | static const struct pinctrl_ops sh_pfc_pinctrl_ops = { |
e3f805e8 PM |
76 | .get_groups_count = sh_pfc_get_groups_count, |
77 | .get_group_name = sh_pfc_get_group_name, | |
ca5481c6 | 78 | .get_group_pins = sh_pfc_get_group_pins, |
fdd85ec3 | 79 | .pin_dbg_show = sh_pfc_pin_dbg_show, |
ca5481c6 PM |
80 | }; |
81 | ||
d93a891f PM |
82 | static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) |
83 | { | |
84 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
85 | ||
3d8d9f1d | 86 | return pmx->pfc->info->nr_functions; |
d93a891f PM |
87 | } |
88 | ||
89 | static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, | |
90 | unsigned selector) | |
91 | { | |
92 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
93 | ||
3d8d9f1d | 94 | return pmx->pfc->info->functions[selector].name; |
d93a891f | 95 | } |
ca5481c6 | 96 | |
3d8d9f1d LP |
97 | static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, |
98 | unsigned selector, | |
ca5481c6 PM |
99 | const char * const **groups, |
100 | unsigned * const num_groups) | |
101 | { | |
d93a891f PM |
102 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
103 | ||
3d8d9f1d LP |
104 | *groups = pmx->pfc->info->functions[selector].groups; |
105 | *num_groups = pmx->pfc->info->functions[selector].nr_groups; | |
d93a891f | 106 | |
ca5481c6 PM |
107 | return 0; |
108 | } | |
109 | ||
3d8d9f1d | 110 | static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
111 | unsigned group) |
112 | { | |
3d8d9f1d LP |
113 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
114 | struct sh_pfc *pfc = pmx->pfc; | |
115 | const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; | |
116 | unsigned long flags; | |
117 | unsigned int i; | |
b705c054 | 118 | int ret = 0; |
3d8d9f1d LP |
119 | |
120 | spin_lock_irqsave(&pfc->lock, flags); | |
121 | ||
9fddc4a5 LP |
122 | for (i = 0; i < grp->nr_pins; ++i) { |
123 | int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); | |
124 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
125 | ||
126 | if (cfg->type != PINMUX_TYPE_NONE) { | |
127 | ret = -EBUSY; | |
128 | goto done; | |
129 | } | |
130 | } | |
131 | ||
3d8d9f1d | 132 | for (i = 0; i < grp->nr_pins; ++i) { |
b705c054 LP |
133 | ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION); |
134 | if (ret < 0) | |
135 | break; | |
3d8d9f1d LP |
136 | } |
137 | ||
9fddc4a5 | 138 | done: |
3d8d9f1d LP |
139 | spin_unlock_irqrestore(&pfc->lock, flags); |
140 | return ret; | |
ca5481c6 PM |
141 | } |
142 | ||
3d8d9f1d | 143 | static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector, |
ca5481c6 PM |
144 | unsigned group) |
145 | { | |
9fddc4a5 LP |
146 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
147 | struct sh_pfc *pfc = pmx->pfc; | |
148 | const struct sh_pfc_pin_group *grp = &pfc->info->groups[group]; | |
149 | unsigned long flags; | |
150 | unsigned int i; | |
151 | ||
152 | spin_lock_irqsave(&pfc->lock, flags); | |
153 | ||
154 | for (i = 0; i < grp->nr_pins; ++i) { | |
155 | int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]); | |
156 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
157 | ||
158 | cfg->type = PINMUX_TYPE_NONE; | |
159 | } | |
160 | ||
161 | spin_unlock_irqrestore(&pfc->lock, flags); | |
ca5481c6 PM |
162 | } |
163 | ||
164 | static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, | |
165 | struct pinctrl_gpio_range *range, | |
166 | unsigned offset) | |
167 | { | |
168 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
169 | struct sh_pfc *pfc = pmx->pfc; | |
1a0039dc LP |
170 | int idx = sh_pfc_get_pin_index(pfc, offset); |
171 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
ca5481c6 | 172 | unsigned long flags; |
1a0039dc | 173 | int ret; |
ca5481c6 PM |
174 | |
175 | spin_lock_irqsave(&pfc->lock, flags); | |
176 | ||
9fddc4a5 | 177 | if (cfg->type != PINMUX_TYPE_NONE) { |
9a643c9a LP |
178 | dev_err(pfc->dev, |
179 | "Pin %u is busy, can't configure it as GPIO.\n", | |
180 | offset); | |
9fddc4a5 LP |
181 | ret = -EBUSY; |
182 | goto done; | |
d93a891f | 183 | } |
ca5481c6 | 184 | |
9fddc4a5 LP |
185 | cfg->type = PINMUX_TYPE_GPIO; |
186 | ||
ca5481c6 PM |
187 | ret = 0; |
188 | ||
9fddc4a5 | 189 | done: |
ca5481c6 PM |
190 | spin_unlock_irqrestore(&pfc->lock, flags); |
191 | ||
192 | return ret; | |
193 | } | |
194 | ||
195 | static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, | |
196 | struct pinctrl_gpio_range *range, | |
197 | unsigned offset) | |
198 | { | |
9fddc4a5 LP |
199 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
200 | struct sh_pfc *pfc = pmx->pfc; | |
201 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
202 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; | |
203 | unsigned long flags; | |
204 | ||
205 | spin_lock_irqsave(&pfc->lock, flags); | |
206 | cfg->type = PINMUX_TYPE_NONE; | |
207 | spin_unlock_irqrestore(&pfc->lock, flags); | |
ca5481c6 PM |
208 | } |
209 | ||
210 | static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, | |
211 | struct pinctrl_gpio_range *range, | |
212 | unsigned offset, bool input) | |
213 | { | |
214 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
0d00f00a LP |
215 | struct sh_pfc *pfc = pmx->pfc; |
216 | int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; | |
217 | int idx = sh_pfc_get_pin_index(pfc, offset); | |
0d00f00a | 218 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; |
9fddc4a5 | 219 | struct sh_pfc_pin_config *cfg = &pmx->configs[idx]; |
0d00f00a | 220 | unsigned long flags; |
6dc9b455 | 221 | unsigned int dir; |
0d00f00a | 222 | int ret; |
ca5481c6 | 223 | |
6dc9b455 LP |
224 | /* Check if the requested direction is supported by the pin. Not all SoC |
225 | * provide pin config data, so perform the check conditionally. | |
226 | */ | |
227 | if (pin->configs) { | |
228 | dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT; | |
229 | if (!(pin->configs & dir)) | |
230 | return -EINVAL; | |
231 | } | |
232 | ||
0d00f00a LP |
233 | spin_lock_irqsave(&pfc->lock, flags); |
234 | ||
9fddc4a5 | 235 | ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type); |
0d00f00a LP |
236 | if (ret < 0) |
237 | goto done; | |
238 | ||
239 | cfg->type = new_type; | |
240 | ||
241 | done: | |
242 | spin_unlock_irqrestore(&pfc->lock, flags); | |
0d00f00a | 243 | return ret; |
ca5481c6 PM |
244 | } |
245 | ||
fe330ce8 | 246 | static const struct pinmux_ops sh_pfc_pinmux_ops = { |
d93a891f PM |
247 | .get_functions_count = sh_pfc_get_functions_count, |
248 | .get_function_name = sh_pfc_get_function_name, | |
ca5481c6 | 249 | .get_function_groups = sh_pfc_get_function_groups, |
3d8d9f1d LP |
250 | .enable = sh_pfc_func_enable, |
251 | .disable = sh_pfc_func_disable, | |
ca5481c6 PM |
252 | .gpio_request_enable = sh_pfc_gpio_request_enable, |
253 | .gpio_disable_free = sh_pfc_gpio_disable_free, | |
254 | .gpio_set_direction = sh_pfc_gpio_set_direction, | |
255 | }; | |
256 | ||
c58d9c1b LP |
257 | /* Check whether the requested parameter is supported for a pin. */ |
258 | static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin, | |
259 | enum pin_config_param param) | |
260 | { | |
261 | int idx = sh_pfc_get_pin_index(pfc, _pin); | |
262 | const struct sh_pfc_pin *pin = &pfc->info->pins[idx]; | |
263 | ||
264 | switch (param) { | |
265 | case PIN_CONFIG_BIAS_DISABLE: | |
266 | return true; | |
267 | ||
268 | case PIN_CONFIG_BIAS_PULL_UP: | |
269 | return pin->configs & SH_PFC_PIN_CFG_PULL_UP; | |
270 | ||
271 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
272 | return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN; | |
273 | ||
274 | default: | |
275 | return false; | |
276 | } | |
277 | } | |
278 | ||
934cb02b | 279 | static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin, |
ca5481c6 PM |
280 | unsigned long *config) |
281 | { | |
fdd85ec3 PM |
282 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
283 | struct sh_pfc *pfc = pmx->pfc; | |
c58d9c1b LP |
284 | enum pin_config_param param = pinconf_to_config_param(*config); |
285 | unsigned long flags; | |
286 | unsigned int bias; | |
287 | ||
288 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) | |
289 | return -ENOTSUPP; | |
290 | ||
291 | switch (param) { | |
292 | case PIN_CONFIG_BIAS_DISABLE: | |
293 | case PIN_CONFIG_BIAS_PULL_UP: | |
294 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
295 | if (!pfc->info->ops || !pfc->info->ops->get_bias) | |
296 | return -ENOTSUPP; | |
297 | ||
298 | spin_lock_irqsave(&pfc->lock, flags); | |
299 | bias = pfc->info->ops->get_bias(pfc, _pin); | |
300 | spin_unlock_irqrestore(&pfc->lock, flags); | |
301 | ||
302 | if (bias != param) | |
303 | return -EINVAL; | |
304 | ||
305 | *config = 0; | |
306 | break; | |
d93a891f | 307 | |
c58d9c1b LP |
308 | default: |
309 | return -ENOTSUPP; | |
310 | } | |
d93a891f | 311 | |
fdd85ec3 | 312 | return 0; |
ca5481c6 PM |
313 | } |
314 | ||
c58d9c1b | 315 | static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin, |
ca5481c6 PM |
316 | unsigned long config) |
317 | { | |
fdd85ec3 | 318 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
c58d9c1b LP |
319 | struct sh_pfc *pfc = pmx->pfc; |
320 | enum pin_config_param param = pinconf_to_config_param(config); | |
321 | unsigned long flags; | |
fdd85ec3 | 322 | |
c58d9c1b LP |
323 | if (!sh_pfc_pinconf_validate(pfc, _pin, param)) |
324 | return -ENOTSUPP; | |
fdd85ec3 | 325 | |
c58d9c1b LP |
326 | switch (param) { |
327 | case PIN_CONFIG_BIAS_PULL_UP: | |
328 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
329 | case PIN_CONFIG_BIAS_DISABLE: | |
330 | if (!pfc->info->ops || !pfc->info->ops->set_bias) | |
331 | return -ENOTSUPP; | |
332 | ||
333 | spin_lock_irqsave(&pfc->lock, flags); | |
334 | pfc->info->ops->set_bias(pfc, _pin, param); | |
335 | spin_unlock_irqrestore(&pfc->lock, flags); | |
336 | ||
337 | break; | |
338 | ||
339 | default: | |
340 | return -ENOTSUPP; | |
341 | } | |
342 | ||
343 | return 0; | |
fdd85ec3 PM |
344 | } |
345 | ||
c58d9c1b LP |
346 | static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group, |
347 | unsigned long config) | |
fdd85ec3 | 348 | { |
c58d9c1b LP |
349 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
350 | const unsigned int *pins; | |
351 | unsigned int num_pins; | |
352 | unsigned int i; | |
353 | ||
354 | pins = pmx->pfc->info->groups[group].pins; | |
355 | num_pins = pmx->pfc->info->groups[group].nr_pins; | |
356 | ||
357 | for (i = 0; i < num_pins; ++i) | |
358 | sh_pfc_pinconf_set(pctldev, pins[i], config); | |
359 | ||
360 | return 0; | |
ca5481c6 PM |
361 | } |
362 | ||
fe330ce8 | 363 | static const struct pinconf_ops sh_pfc_pinconf_ops = { |
c58d9c1b LP |
364 | .is_generic = true, |
365 | .pin_config_get = sh_pfc_pinconf_get, | |
366 | .pin_config_set = sh_pfc_pinconf_set, | |
367 | .pin_config_group_set = sh_pfc_pinconf_group_set, | |
368 | .pin_config_config_dbg_show = pinconf_generic_dump_config, | |
ca5481c6 PM |
369 | }; |
370 | ||
63d57383 LP |
371 | /* PFC ranges -> pinctrl pin descs */ |
372 | static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) | |
ca5481c6 | 373 | { |
63d57383 LP |
374 | const struct pinmux_range *ranges; |
375 | struct pinmux_range def_range; | |
376 | unsigned int nr_ranges; | |
377 | unsigned int nr_pins; | |
378 | unsigned int i; | |
379 | ||
380 | if (pfc->info->ranges == NULL) { | |
381 | def_range.begin = 0; | |
382 | def_range.end = pfc->info->nr_pins - 1; | |
383 | ranges = &def_range; | |
384 | nr_ranges = 1; | |
385 | } else { | |
386 | ranges = pfc->info->ranges; | |
387 | nr_ranges = pfc->info->nr_ranges; | |
388 | } | |
ca5481c6 | 389 | |
3d8d9f1d LP |
390 | pmx->pins = devm_kzalloc(pfc->dev, |
391 | sizeof(*pmx->pins) * pfc->info->nr_pins, | |
1724acfd | 392 | GFP_KERNEL); |
3d8d9f1d | 393 | if (unlikely(!pmx->pins)) |
ca5481c6 | 394 | return -ENOMEM; |
ca5481c6 | 395 | |
1a0039dc LP |
396 | pmx->configs = devm_kzalloc(pfc->dev, |
397 | sizeof(*pmx->configs) * pfc->info->nr_pins, | |
398 | GFP_KERNEL); | |
399 | if (unlikely(!pmx->configs)) | |
400 | return -ENOMEM; | |
401 | ||
63d57383 LP |
402 | for (i = 0, nr_pins = 0; i < nr_ranges; ++i) { |
403 | const struct pinmux_range *range = &ranges[i]; | |
404 | unsigned int number; | |
405 | ||
406 | for (number = range->begin; number <= range->end; | |
407 | number++, nr_pins++) { | |
1a0039dc | 408 | struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins]; |
3d8d9f1d | 409 | struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins]; |
cd3c1bee LP |
410 | const struct sh_pfc_pin *info = |
411 | &pfc->info->pins[nr_pins]; | |
ca5481c6 | 412 | |
63d57383 LP |
413 | pin->number = number; |
414 | pin->name = info->name; | |
9fddc4a5 | 415 | cfg->type = PINMUX_TYPE_NONE; |
63d57383 | 416 | } |
ca5481c6 PM |
417 | } |
418 | ||
63d57383 LP |
419 | pfc->nr_pins = ranges[nr_ranges-1].end + 1; |
420 | ||
421 | return nr_ranges; | |
ca5481c6 PM |
422 | } |
423 | ||
c6193eac | 424 | int sh_pfc_register_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 425 | { |
c6193eac | 426 | struct sh_pfc_pinctrl *pmx; |
63d57383 | 427 | int nr_ranges; |
ca5481c6 | 428 | |
1724acfd | 429 | pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); |
c6193eac LP |
430 | if (unlikely(!pmx)) |
431 | return -ENOMEM; | |
432 | ||
c6193eac LP |
433 | pmx->pfc = pfc; |
434 | pfc->pinctrl = pmx; | |
ca5481c6 | 435 | |
63d57383 LP |
436 | nr_ranges = sh_pfc_map_pins(pfc, pmx); |
437 | if (unlikely(nr_ranges < 0)) | |
438 | return nr_ranges; | |
ca5481c6 | 439 | |
dcc427e1 LP |
440 | pmx->pctl_desc.name = DRV_NAME; |
441 | pmx->pctl_desc.owner = THIS_MODULE; | |
442 | pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops; | |
443 | pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops; | |
444 | pmx->pctl_desc.confops = &sh_pfc_pinconf_ops; | |
3d8d9f1d | 445 | pmx->pctl_desc.pins = pmx->pins; |
63d57383 | 446 | pmx->pctl_desc.npins = pfc->info->nr_pins; |
dcc427e1 LP |
447 | |
448 | pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx); | |
fd9d05b0 WY |
449 | if (pmx->pctl == NULL) |
450 | return -EINVAL; | |
ca5481c6 | 451 | |
ca5481c6 | 452 | return 0; |
ca5481c6 PM |
453 | } |
454 | ||
c6193eac | 455 | int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 456 | { |
c6193eac | 457 | struct sh_pfc_pinctrl *pmx = pfc->pinctrl; |
ca5481c6 | 458 | |
ca5481c6 PM |
459 | pinctrl_unregister(pmx->pctl); |
460 | ||
c6193eac | 461 | pfc->pinctrl = NULL; |
ca5481c6 PM |
462 | return 0; |
463 | } |