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Commit | Line | Data |
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ca5481c6 PM |
1 | /* |
2 | * SuperH Pin Function Controller pinmux support. | |
3 | * | |
4 | * Copyright (C) 2012 Paul Mundt | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
54407110 | 10 | |
c6193eac | 11 | #define DRV_NAME "sh-pfc" |
f9492fda | 12 | #define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt |
ca5481c6 | 13 | |
1724acfd | 14 | #include <linux/device.h> |
90efde22 | 15 | #include <linux/err.h> |
ca5481c6 PM |
16 | #include <linux/init.h> |
17 | #include <linux/module.h> | |
ca5481c6 | 18 | #include <linux/pinctrl/consumer.h> |
ca5481c6 | 19 | #include <linux/pinctrl/pinconf.h> |
ca5481c6 | 20 | #include <linux/pinctrl/pinconf-generic.h> |
90efde22 LP |
21 | #include <linux/pinctrl/pinctrl.h> |
22 | #include <linux/pinctrl/pinmux.h> | |
90efde22 LP |
23 | #include <linux/slab.h> |
24 | #include <linux/spinlock.h> | |
ca5481c6 | 25 | |
f9165132 LP |
26 | #include "core.h" |
27 | ||
ca5481c6 PM |
28 | struct sh_pfc_pinctrl { |
29 | struct pinctrl_dev *pctl; | |
30 | struct sh_pfc *pfc; | |
31 | ||
d93a891f PM |
32 | struct pinmux_gpio **functions; |
33 | unsigned int nr_functions; | |
34 | ||
ca5481c6 PM |
35 | struct pinctrl_pin_desc *pads; |
36 | unsigned int nr_pads; | |
d93a891f PM |
37 | |
38 | spinlock_t lock; | |
ca5481c6 PM |
39 | }; |
40 | ||
e3f805e8 | 41 | static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) |
ca5481c6 | 42 | { |
e3f805e8 PM |
43 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
44 | ||
45 | return pmx->nr_pads; | |
ca5481c6 PM |
46 | } |
47 | ||
e3f805e8 | 48 | static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, |
ca5481c6 PM |
49 | unsigned selector) |
50 | { | |
e3f805e8 PM |
51 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
52 | ||
53 | return pmx->pads[selector].name; | |
ca5481c6 PM |
54 | } |
55 | ||
56 | static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, | |
57 | const unsigned **pins, unsigned *num_pins) | |
58 | { | |
e3f805e8 PM |
59 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
60 | ||
61 | *pins = &pmx->pads[group].number; | |
62 | *num_pins = 1; | |
63 | ||
64 | return 0; | |
ca5481c6 PM |
65 | } |
66 | ||
fdd85ec3 PM |
67 | static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, |
68 | unsigned offset) | |
69 | { | |
70 | seq_printf(s, "%s", DRV_NAME); | |
71 | } | |
72 | ||
ca5481c6 | 73 | static struct pinctrl_ops sh_pfc_pinctrl_ops = { |
e3f805e8 PM |
74 | .get_groups_count = sh_pfc_get_groups_count, |
75 | .get_group_name = sh_pfc_get_group_name, | |
ca5481c6 | 76 | .get_group_pins = sh_pfc_get_group_pins, |
fdd85ec3 | 77 | .pin_dbg_show = sh_pfc_pin_dbg_show, |
ca5481c6 PM |
78 | }; |
79 | ||
d93a891f PM |
80 | static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev) |
81 | { | |
82 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
83 | ||
84 | return pmx->nr_functions; | |
85 | } | |
86 | ||
87 | static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, | |
88 | unsigned selector) | |
89 | { | |
90 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
91 | ||
92 | return pmx->functions[selector]->name; | |
93 | } | |
ca5481c6 | 94 | |
ca5481c6 PM |
95 | static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, |
96 | const char * const **groups, | |
97 | unsigned * const num_groups) | |
98 | { | |
d93a891f PM |
99 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
100 | ||
101 | *groups = &pmx->functions[func]->name; | |
102 | *num_groups = 1; | |
103 | ||
ca5481c6 PM |
104 | return 0; |
105 | } | |
106 | ||
107 | static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, | |
108 | unsigned group) | |
109 | { | |
110 | return 0; | |
111 | } | |
112 | ||
113 | static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, | |
114 | unsigned group) | |
115 | { | |
116 | } | |
117 | ||
4a2e0d18 | 118 | static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) |
d93a891f PM |
119 | { |
120 | if (sh_pfc_config_gpio(pfc, offset, | |
121 | PINMUX_TYPE_FUNCTION, | |
122 | GPIO_CFG_DRYRUN) != 0) | |
123 | return -EINVAL; | |
124 | ||
125 | if (sh_pfc_config_gpio(pfc, offset, | |
126 | PINMUX_TYPE_FUNCTION, | |
127 | GPIO_CFG_REQ) != 0) | |
128 | return -EINVAL; | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
fdd85ec3 PM |
133 | static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, |
134 | int new_type) | |
135 | { | |
136 | unsigned long flags; | |
137 | int pinmux_type; | |
138 | int ret = -EINVAL; | |
139 | ||
140 | spin_lock_irqsave(&pfc->lock, flags); | |
141 | ||
19bb7fe3 | 142 | pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; |
fdd85ec3 PM |
143 | |
144 | /* | |
145 | * See if the present config needs to first be de-configured. | |
146 | */ | |
147 | switch (pinmux_type) { | |
148 | case PINMUX_TYPE_GPIO: | |
149 | break; | |
150 | case PINMUX_TYPE_OUTPUT: | |
151 | case PINMUX_TYPE_INPUT: | |
152 | case PINMUX_TYPE_INPUT_PULLUP: | |
153 | case PINMUX_TYPE_INPUT_PULLDOWN: | |
154 | sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); | |
155 | break; | |
156 | default: | |
157 | goto err; | |
158 | } | |
159 | ||
160 | /* | |
161 | * Dry run | |
162 | */ | |
163 | if (sh_pfc_config_gpio(pfc, offset, new_type, | |
164 | GPIO_CFG_DRYRUN) != 0) | |
165 | goto err; | |
166 | ||
167 | /* | |
168 | * Request | |
169 | */ | |
170 | if (sh_pfc_config_gpio(pfc, offset, new_type, | |
171 | GPIO_CFG_REQ) != 0) | |
172 | goto err; | |
173 | ||
19bb7fe3 LP |
174 | pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE; |
175 | pfc->info->gpios[offset].flags |= new_type; | |
fdd85ec3 PM |
176 | |
177 | ret = 0; | |
178 | ||
179 | err: | |
180 | spin_unlock_irqrestore(&pfc->lock, flags); | |
181 | ||
182 | return ret; | |
183 | } | |
184 | ||
185 | ||
ca5481c6 PM |
186 | static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, |
187 | struct pinctrl_gpio_range *range, | |
188 | unsigned offset) | |
189 | { | |
190 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
191 | struct sh_pfc *pfc = pmx->pfc; | |
ca5481c6 | 192 | unsigned long flags; |
d93a891f | 193 | int ret, pinmux_type; |
ca5481c6 PM |
194 | |
195 | spin_lock_irqsave(&pfc->lock, flags); | |
196 | ||
19bb7fe3 | 197 | pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; |
ca5481c6 | 198 | |
d93a891f PM |
199 | switch (pinmux_type) { |
200 | case PINMUX_TYPE_FUNCTION: | |
201 | pr_notice_once("Use of GPIO API for function requests is " | |
202 | "deprecated, convert to pinctrl\n"); | |
203 | /* handle for now */ | |
204 | ret = sh_pfc_config_function(pfc, offset); | |
205 | if (unlikely(ret < 0)) | |
ca5481c6 | 206 | goto err; |
ca5481c6 | 207 | |
d93a891f PM |
208 | break; |
209 | case PINMUX_TYPE_GPIO: | |
16d74ebe PM |
210 | case PINMUX_TYPE_INPUT: |
211 | case PINMUX_TYPE_OUTPUT: | |
d93a891f PM |
212 | break; |
213 | default: | |
214 | pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type); | |
077664a2 LP |
215 | ret = -ENOTSUPP; |
216 | goto err; | |
d93a891f | 217 | } |
ca5481c6 PM |
218 | |
219 | ret = 0; | |
220 | ||
221 | err: | |
222 | spin_unlock_irqrestore(&pfc->lock, flags); | |
223 | ||
224 | return ret; | |
225 | } | |
226 | ||
227 | static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev, | |
228 | struct pinctrl_gpio_range *range, | |
229 | unsigned offset) | |
230 | { | |
231 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
232 | struct sh_pfc *pfc = pmx->pfc; | |
233 | unsigned long flags; | |
234 | int pinmux_type; | |
235 | ||
236 | spin_lock_irqsave(&pfc->lock, flags); | |
237 | ||
19bb7fe3 | 238 | pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; |
ca5481c6 PM |
239 | |
240 | sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE); | |
241 | ||
ca5481c6 PM |
242 | spin_unlock_irqrestore(&pfc->lock, flags); |
243 | } | |
244 | ||
245 | static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev, | |
246 | struct pinctrl_gpio_range *range, | |
247 | unsigned offset, bool input) | |
248 | { | |
249 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); | |
fdd85ec3 | 250 | int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; |
ca5481c6 | 251 | |
fdd85ec3 | 252 | return sh_pfc_reconfig_pin(pmx->pfc, offset, type); |
ca5481c6 PM |
253 | } |
254 | ||
255 | static struct pinmux_ops sh_pfc_pinmux_ops = { | |
d93a891f PM |
256 | .get_functions_count = sh_pfc_get_functions_count, |
257 | .get_function_name = sh_pfc_get_function_name, | |
ca5481c6 PM |
258 | .get_function_groups = sh_pfc_get_function_groups, |
259 | .enable = sh_pfc_noop_enable, | |
260 | .disable = sh_pfc_noop_disable, | |
261 | .gpio_request_enable = sh_pfc_gpio_request_enable, | |
262 | .gpio_disable_free = sh_pfc_gpio_disable_free, | |
263 | .gpio_set_direction = sh_pfc_gpio_set_direction, | |
264 | }; | |
265 | ||
266 | static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, | |
267 | unsigned long *config) | |
268 | { | |
fdd85ec3 PM |
269 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
270 | struct sh_pfc *pfc = pmx->pfc; | |
d93a891f | 271 | |
19bb7fe3 | 272 | *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; |
d93a891f | 273 | |
fdd85ec3 | 274 | return 0; |
ca5481c6 PM |
275 | } |
276 | ||
277 | static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, | |
278 | unsigned long config) | |
279 | { | |
fdd85ec3 | 280 | struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); |
fdd85ec3 PM |
281 | |
282 | /* Validate the new type */ | |
283 | if (config >= PINMUX_FLAG_TYPE) | |
284 | return -EINVAL; | |
285 | ||
286 | return sh_pfc_reconfig_pin(pmx->pfc, pin, config); | |
287 | } | |
288 | ||
289 | static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, | |
290 | struct seq_file *s, unsigned pin) | |
291 | { | |
292 | const char *pinmux_type_str[] = { | |
293 | [PINMUX_TYPE_NONE] = "none", | |
294 | [PINMUX_TYPE_FUNCTION] = "function", | |
295 | [PINMUX_TYPE_GPIO] = "gpio", | |
296 | [PINMUX_TYPE_OUTPUT] = "output", | |
297 | [PINMUX_TYPE_INPUT] = "input", | |
298 | [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up", | |
299 | [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down", | |
300 | }; | |
301 | unsigned long config; | |
302 | int rc; | |
303 | ||
304 | rc = sh_pfc_pinconf_get(pctldev, pin, &config); | |
305 | if (unlikely(rc != 0)) | |
306 | return; | |
307 | ||
308 | seq_printf(s, " %s", pinmux_type_str[config]); | |
ca5481c6 PM |
309 | } |
310 | ||
311 | static struct pinconf_ops sh_pfc_pinconf_ops = { | |
ca5481c6 PM |
312 | .pin_config_get = sh_pfc_pinconf_get, |
313 | .pin_config_set = sh_pfc_pinconf_set, | |
fdd85ec3 | 314 | .pin_config_dbg_show = sh_pfc_pinconf_dbg_show, |
ca5481c6 PM |
315 | }; |
316 | ||
317 | static struct pinctrl_gpio_range sh_pfc_gpio_range = { | |
54407110 | 318 | .name = DRV_NAME, |
ca5481c6 PM |
319 | .id = 0, |
320 | }; | |
321 | ||
322 | static struct pinctrl_desc sh_pfc_pinctrl_desc = { | |
54407110 | 323 | .name = DRV_NAME, |
ca5481c6 PM |
324 | .owner = THIS_MODULE, |
325 | .pctlops = &sh_pfc_pinctrl_ops, | |
326 | .pmxops = &sh_pfc_pinmux_ops, | |
327 | .confops = &sh_pfc_pinconf_ops, | |
328 | }; | |
329 | ||
4a2e0d18 LP |
330 | static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, |
331 | struct pinmux_gpio *gpio, unsigned offset) | |
d93a891f PM |
332 | { |
333 | struct pinmux_data_reg *dummy; | |
334 | unsigned long flags; | |
335 | int bit; | |
336 | ||
337 | gpio->flags &= ~PINMUX_FLAG_TYPE; | |
338 | ||
339 | if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) | |
340 | gpio->flags |= PINMUX_TYPE_GPIO; | |
341 | else { | |
342 | gpio->flags |= PINMUX_TYPE_FUNCTION; | |
343 | ||
344 | spin_lock_irqsave(&pmx->lock, flags); | |
345 | pmx->nr_functions++; | |
346 | spin_unlock_irqrestore(&pmx->lock, flags); | |
347 | } | |
348 | } | |
349 | ||
ca5481c6 | 350 | /* pinmux ranges -> pinctrl pin descs */ |
0fe763c5 | 351 | static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) |
ca5481c6 | 352 | { |
d93a891f | 353 | unsigned long flags; |
ca5481c6 PM |
354 | int i; |
355 | ||
19bb7fe3 | 356 | pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; |
ca5481c6 | 357 | |
1724acfd LP |
358 | pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, |
359 | GFP_KERNEL); | |
ca5481c6 PM |
360 | if (unlikely(!pmx->pads)) { |
361 | pmx->nr_pads = 0; | |
362 | return -ENOMEM; | |
363 | } | |
364 | ||
d93a891f PM |
365 | spin_lock_irqsave(&pfc->lock, flags); |
366 | ||
ca5481c6 PM |
367 | /* |
368 | * We don't necessarily have a 1:1 mapping between pin and linux | |
369 | * GPIO number, as the latter maps to the associated enum_id. | |
370 | * Care needs to be taken to translate back to pin space when | |
371 | * dealing with any pin configurations. | |
372 | */ | |
373 | for (i = 0; i < pmx->nr_pads; i++) { | |
374 | struct pinctrl_pin_desc *pin = pmx->pads + i; | |
19bb7fe3 | 375 | struct pinmux_gpio *gpio = pfc->info->gpios + i; |
ca5481c6 | 376 | |
19bb7fe3 | 377 | pin->number = pfc->info->first_gpio + i; |
ca5481c6 | 378 | pin->name = gpio->name; |
d93a891f | 379 | |
e3e79454 PM |
380 | /* XXX */ |
381 | if (unlikely(!gpio->enum_id)) | |
382 | continue; | |
383 | ||
d93a891f | 384 | sh_pfc_map_one_gpio(pfc, pmx, gpio, i); |
ca5481c6 PM |
385 | } |
386 | ||
d93a891f PM |
387 | spin_unlock_irqrestore(&pfc->lock, flags); |
388 | ||
ca5481c6 PM |
389 | sh_pfc_pinctrl_desc.pins = pmx->pads; |
390 | sh_pfc_pinctrl_desc.npins = pmx->nr_pads; | |
391 | ||
392 | return 0; | |
393 | } | |
394 | ||
0fe763c5 | 395 | static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) |
d93a891f PM |
396 | { |
397 | unsigned long flags; | |
398 | int i, fn; | |
399 | ||
1724acfd LP |
400 | pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * |
401 | sizeof(*pmx->functions), GFP_KERNEL); | |
d93a891f PM |
402 | if (unlikely(!pmx->functions)) |
403 | return -ENOMEM; | |
404 | ||
405 | spin_lock_irqsave(&pmx->lock, flags); | |
406 | ||
407 | for (i = fn = 0; i < pmx->nr_pads; i++) { | |
19bb7fe3 | 408 | struct pinmux_gpio *gpio = pfc->info->gpios + i; |
d93a891f PM |
409 | |
410 | if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) | |
411 | pmx->functions[fn++] = gpio; | |
412 | } | |
413 | ||
414 | spin_unlock_irqrestore(&pmx->lock, flags); | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
c6193eac | 419 | int sh_pfc_register_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 420 | { |
c6193eac | 421 | struct sh_pfc_pinctrl *pmx; |
ca5481c6 PM |
422 | int ret; |
423 | ||
1724acfd | 424 | pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); |
c6193eac LP |
425 | if (unlikely(!pmx)) |
426 | return -ENOMEM; | |
427 | ||
428 | spin_lock_init(&pmx->lock); | |
ca5481c6 | 429 | |
c6193eac LP |
430 | pmx->pfc = pfc; |
431 | pfc->pinctrl = pmx; | |
ca5481c6 | 432 | |
c6193eac | 433 | ret = sh_pfc_map_gpios(pfc, pmx); |
ca5481c6 PM |
434 | if (unlikely(ret != 0)) |
435 | return ret; | |
436 | ||
c6193eac | 437 | ret = sh_pfc_map_functions(pfc, pmx); |
d93a891f | 438 | if (unlikely(ret != 0)) |
1724acfd | 439 | return ret; |
d93a891f | 440 | |
c6193eac | 441 | pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); |
1724acfd LP |
442 | if (IS_ERR(pmx->pctl)) |
443 | return PTR_ERR(pmx->pctl); | |
ca5481c6 | 444 | |
19bb7fe3 LP |
445 | sh_pfc_gpio_range.npins = pfc->info->last_gpio |
446 | - pfc->info->first_gpio + 1; | |
447 | sh_pfc_gpio_range.base = pfc->info->first_gpio; | |
448 | sh_pfc_gpio_range.pin_base = pfc->info->first_gpio; | |
ca5481c6 | 449 | |
c6193eac | 450 | pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range); |
ca5481c6 PM |
451 | |
452 | return 0; | |
ca5481c6 PM |
453 | } |
454 | ||
c6193eac | 455 | int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc) |
ca5481c6 | 456 | { |
c6193eac | 457 | struct sh_pfc_pinctrl *pmx = pfc->pinctrl; |
ca5481c6 | 458 | |
ca5481c6 PM |
459 | pinctrl_unregister(pmx->pctl); |
460 | ||
c6193eac | 461 | pfc->pinctrl = NULL; |
ca5481c6 PM |
462 | return 0; |
463 | } |