[mirror_ubuntu-bionic-kernel.git] / drivers / pinctrl / sh-pfc / sh_pfc.h

/*
 * SuperH Pin Function Controller Support
 *
 * Copyright (c) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */

#ifndef __SH_PFC_H
#define __SH_PFC_H

#include <linux/bug.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/stringify.h>

enum {
	PINMUX_TYPE_NONE,
	PINMUX_TYPE_FUNCTION,
	PINMUX_TYPE_GPIO,
	PINMUX_TYPE_OUTPUT,
	PINMUX_TYPE_INPUT,
};

#define SH_PFC_PIN_CFG_INPUT		(1 << 0)
#define SH_PFC_PIN_CFG_OUTPUT		(1 << 1)
#define SH_PFC_PIN_CFG_PULL_UP		(1 << 2)
#define SH_PFC_PIN_CFG_PULL_DOWN	(1 << 3)
#define SH_PFC_PIN_CFG_IO_VOLTAGE	(1 << 4)
#define SH_PFC_PIN_CFG_NO_GPIO		(1 << 31)

struct sh_pfc_pin {
	u16 pin;
	u16 enum_id;
	const char *name;
	unsigned int configs;
};

#define SH_PFC_PIN_GROUP(n)				\
	{						\
		.name = #n,				\
		.pins = n##_pins,			\
		.mux = n##_mux,				\
		.nr_pins = ARRAY_SIZE(n##_pins),	\
	}

struct sh_pfc_pin_group {
	const char *name;
	const unsigned int *pins;
	const unsigned int *mux;
	unsigned int nr_pins;
};

/*
 * Using union vin_data saves memory occupied by the VIN data pins.
 * VIN_DATA_PIN_GROUP() is  a macro  used  to describe the VIN pin groups
 * in this case.
 */
#define VIN_DATA_PIN_GROUP(n, s)				\
	{							\
		.name = #n#s,					\
		.pins = n##_pins.data##s,			\
		.mux = n##_mux.data##s,				\
		.nr_pins = ARRAY_SIZE(n##_pins.data##s),	\
	}

union vin_data {
	unsigned int data24[24];
	unsigned int data20[20];
	unsigned int data16[16];
	unsigned int data12[12];
	unsigned int data10[10];
	unsigned int data8[8];
	unsigned int data4[4];
};

#define SH_PFC_FUNCTION(n)				\
	{						\
		.name = #n,				\
		.groups = n##_groups,			\
		.nr_groups = ARRAY_SIZE(n##_groups),	\
	}

struct sh_pfc_function {
	const char *name;
	const char * const *groups;
	unsigned int nr_groups;
};

struct pinmux_func {
	u16 enum_id;
	const char *name;
};

struct pinmux_cfg_reg {
	u32 reg;
	u8 reg_width, field_width;
	const u16 *enum_ids;
	const u8 *var_field_width;
};

#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	.reg = r, .reg_width = r_width, .field_width = f_width,		\
	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])

#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	.reg = r, .reg_width = r_width,	\
	.var_field_width = (const u8 [r_width]) \
		{ var_fw0, var_fwn, 0 }, \
	.enum_ids = (const u16 [])

struct pinmux_data_reg {
	u32 reg;
	u8 reg_width;
	const u16 *enum_ids;
};

#define PINMUX_DATA_REG(name, r, r_width) \
	.reg = r, .reg_width = r_width,	\
	.enum_ids = (const u16 [r_width]) \

struct pinmux_irq {
	const short *gpios;
};

#define PINMUX_IRQ(ids...)			   \
	{ .gpios = (const short []) { ids, -1 } }

struct pinmux_range {
	u16 begin;
	u16 end;
	u16 force;
};

struct sh_pfc;

struct sh_pfc_soc_operations {
	int (*init)(struct sh_pfc *pfc);
	unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
	void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
			 unsigned int bias);
	int (*get_io_voltage)(struct sh_pfc *pfc, unsigned int pin);
	int (*set_io_voltage)(struct sh_pfc *pfc, unsigned int pin,
			      u16 voltage_mV);
};

struct sh_pfc_soc_info {
	const char *name;
	const struct sh_pfc_soc_operations *ops;

	struct pinmux_range input;
	struct pinmux_range output;
	struct pinmux_range function;

	const struct sh_pfc_pin *pins;
	unsigned int nr_pins;
	const struct sh_pfc_pin_group *groups;
	unsigned int nr_groups;
	const struct sh_pfc_function *functions;
	unsigned int nr_functions;

#ifdef CONFIG_SUPERH
	const struct pinmux_func *func_gpios;
	unsigned int nr_func_gpios;
#endif

	const struct pinmux_cfg_reg *cfg_regs;
	const struct pinmux_data_reg *data_regs;

	const u16 *pinmux_data;
	unsigned int pinmux_data_size;

	const struct pinmux_irq *gpio_irq;
	unsigned int gpio_irq_size;

	u32 unlock_reg;
};

/* -----------------------------------------------------------------------------
 * Helper macros to create pin and port lists
 */

/*
 * sh_pfc_soc_info pinmux_data array macros
 */

#define PINMUX_DATA(data_or_mark, ids...)	data_or_mark, ids, 0

#define PINMUX_IPSR_NOGP(ispr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn)
#define PINMUX_IPSR_DATA(ipsr, fn)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
#define PINMUX_IPSR_NOGM(ispr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
#define PINMUX_IPSR_NOFN(ipsr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
#define PINMUX_IPSR_MSEL(ipsr, fn, ms)					\
	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)

/*
 * Describe a pinmux configuration for a single-function pin with GPIO
 * capability.
 *   - fn: Function name
 */
#define PINMUX_SINGLE(fn)						\
	PINMUX_DATA(fn##_MARK, FN_##fn)

/*
 * GP port style (32 ports banks)
 */

#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
#define PORT_GP_1(bank, pin, fn, sfx)	PORT_GP_CFG_1(bank, pin, fn, sfx, 0)

#define PORT_GP_CFG_4(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_1(bank, 0,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 1,  fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 2,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 3,  fn, sfx, cfg)
#define PORT_GP_4(bank, fn, sfx)	PORT_GP_CFG_4(bank, fn, sfx, 0)

#define PORT_GP_CFG_8(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_4(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 4,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 5,  fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 6,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 7,  fn, sfx, cfg)
#define PORT_GP_8(bank, fn, sfx)	PORT_GP_CFG_8(bank, fn, sfx, 0)

#define PORT_GP_CFG_9(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_8(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg)
#define PORT_GP_9(bank, fn, sfx)	PORT_GP_CFG_9(bank, fn, sfx, 0)

#define PORT_GP_CFG_12(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_8(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 8,  fn, sfx, cfg), PORT_GP_CFG_1(bank, 9,  fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
#define PORT_GP_12(bank, fn, sfx)	PORT_GP_CFG_12(bank, fn, sfx, 0)

#define PORT_GP_CFG_14(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_12(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
#define PORT_GP_14(bank, fn, sfx)	PORT_GP_CFG_14(bank, fn, sfx, 0)

#define PORT_GP_CFG_15(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_14(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
#define PORT_GP_15(bank, fn, sfx)	PORT_GP_CFG_15(bank, fn, sfx, 0)

#define PORT_GP_CFG_16(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_14(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
#define PORT_GP_16(bank, fn, sfx)	PORT_GP_CFG_16(bank, fn, sfx, 0)

#define PORT_GP_CFG_18(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_16(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
#define PORT_GP_18(bank, fn, sfx)	PORT_GP_CFG_18(bank, fn, sfx, 0)

#define PORT_GP_CFG_26(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_18(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg),	\
	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
#define PORT_GP_26(bank, fn, sfx)	PORT_GP_CFG_26(bank, fn, sfx, 0)

#define PORT_GP_CFG_28(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_26(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
#define PORT_GP_28(bank, fn, sfx)	PORT_GP_CFG_28(bank, fn, sfx, 0)

#define PORT_GP_CFG_30(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_28(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
#define PORT_GP_30(bank, fn, sfx)	PORT_GP_CFG_30(bank, fn, sfx, 0)

#define PORT_GP_CFG_32(bank, fn, sfx, cfg)						\
	PORT_GP_CFG_30(bank, fn, sfx, cfg),						\
	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
#define PORT_GP_32(bank, fn, sfx)	PORT_GP_CFG_32(bank, fn, sfx, 0)

#define PORT_GP_32_REV(bank, fn, sfx)					\
	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),	\
	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),	\
	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),	\
	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),	\
	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),	\
	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),	\
	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),	\
	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),	\
	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),	\
	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),	\
	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),	\
	PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),	\
	PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),	\
	PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),	\
	PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),	\
	PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)

/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
#define _GP_ALL(bank, pin, name, sfx, cfg)	name##_##sfx
#define GP_ALL(str)			CPU_ALL_PORT(_GP_ALL, str)

/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
#define _GP_GPIO(bank, _pin, _name, sfx, cfg)				\
	{								\
		.pin = (bank * 32) + _pin,				\
		.name = __stringify(_name),				\
		.enum_id = _name##_DATA,				\
		.configs = cfg,						\
	}
#define PINMUX_GPIO_GP_ALL()		CPU_ALL_PORT(_GP_GPIO, unused)

/* PINMUX_DATA_GP_ALL -  Expand to a list of name_DATA, name_FN marks */
#define _GP_DATA(bank, pin, name, sfx, cfg)	PINMUX_DATA(name##_DATA, name##_FN)
#define PINMUX_DATA_GP_ALL()		CPU_ALL_PORT(_GP_DATA, unused)

/*
 * PORT style (linear pin space)
 */

#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)

#define PORT_10(pn, fn, pfx, sfx)					  \
	PORT_1(pn,   fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx),	  \
	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx),	  \
	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx),	  \
	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx),	  \
	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)

#define PORT_90(pn, fn, pfx, sfx)					  \
	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
	PORT_10(pn+90, fn, pfx##9, sfx)

/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
#define _PORT_ALL(pn, pfx, sfx)		pfx##_##sfx
#define PORT_ALL(str)			CPU_ALL_PORT(_PORT_ALL, PORT, str)

/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
#define PINMUX_GPIO(_pin)						\
	[GPIO_##_pin] = {						\
		.pin = (u16)-1,						\
		.name = __stringify(GPIO_##_pin),			\
		.enum_id = _pin##_DATA,					\
	}

/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
#define SH_PFC_PIN_CFG(_pin, cfgs)					\
	{								\
		.pin = _pin,						\
		.name = __stringify(PORT##_pin),			\
		.enum_id = PORT##_pin##_DATA,				\
		.configs = cfgs,					\
	}

/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
#define SH_PFC_PIN_NAMED(row, col, _name)				\
	{								\
		.pin = PIN_NUMBER(row, col),				\
		.name = __stringify(PIN_##_name),			\
		.configs = SH_PFC_PIN_CFG_NO_GPIO,			\
	}

/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
 *		     PORT_name_OUT, PORT_name_IN marks
 */
#define _PORT_DATA(pn, pfx, sfx)					\
	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0,			\
		    PORT##pfx##_OUT, PORT##pfx##_IN)
#define PINMUX_DATA_ALL()		CPU_ALL_PORT(_PORT_DATA, , unused)

/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
#define PINMUX_GPIO_FN(gpio, base, data_or_mark)			\
	[gpio - (base)] = {						\
		.name = __stringify(gpio),				\
		.enum_id = data_or_mark,				\
	}
#define GPIO_FN(str)							\
	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)

/*
 * PORTnCR macro
 */
#define PORTCR(nr, reg)							\
	{								\
		PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
			/* PULMD[1:0], handled by .set_bias() */	\
			0, 0, 0, 0,					\
			/* IE and OE */					\
			0, PORT##nr##_OUT, PORT##nr##_IN, 0,		\
			/* SEC, not supported */			\
			0, 0,						\
			/* PTMD[2:0] */					\
			PORT##nr##_FN0, PORT##nr##_FN1,			\
			PORT##nr##_FN2, PORT##nr##_FN3,			\
			PORT##nr##_FN4, PORT##nr##_FN5,			\
			PORT##nr##_FN6, PORT##nr##_FN7			\
		}							\
	}

/*
 * GPIO number helper macro for R-Car
 */
#define RCAR_GP_PIN(bank, pin)		(((bank) * 32) + (pin))

#endif /* __SH_PFC_H */
Commit	Line	Data
fae43399 MD	1	/*
	2	* SuperH Pin Function Controller Support
	3	*
	4	* Copyright (c) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
	10
	11	#ifndef __SH_PFC_H
	12	#define __SH_PFC_H
	13
bf9f0674	14	#include <linux/bug.h>
5b9eaa56	15	#include <linux/pinctrl/pinconf-generic.h>
72c7afa1	16	#include <linux/stringify.h>
fae43399	17
06d5631f PM	18	enum {
06d5631f PM	19	PINMUX_TYPE_NONE,
06d5631f PM	20	PINMUX_TYPE_FUNCTION,
	21	PINMUX_TYPE_GPIO,
	22	PINMUX_TYPE_OUTPUT,
	23	PINMUX_TYPE_INPUT,
06d5631f	24	};
fae43399	25
c58d9c1b LP	26	#define SH_PFC_PIN_CFG_INPUT (1 << 0)
	27	#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
	28	#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
	29	#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
5b9eaa56	30	#define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
4f82e3ee	31	#define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
c58d9c1b	32
a3db40a6	33	struct sh_pfc_pin {
9689896c	34	u16 pin;
533743dc	35	u16 enum_id;
72c7afa1	36	const char *name;
c58d9c1b	37	unsigned int configs;
fae43399 MD	38	};
fae43399 MD	39
3d8d9f1d LP	40	#define SH_PFC_PIN_GROUP(n) \
	41	{ \
	42	.name = #n, \
	43	.pins = n##_pins, \
	44	.mux = n##_mux, \
	45	.nr_pins = ARRAY_SIZE(n##_pins), \
	46	}
	47
	48	struct sh_pfc_pin_group {
	49	const char *name;
	50	const unsigned int *pins;
	51	const unsigned int *mux;
	52	unsigned int nr_pins;
	53	};
	54
423caa52 SS	55	/*
	56	* Using union vin_data saves memory occupied by the VIN data pins.
	57	* VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
	58	* in this case.
	59	*/
	60	#define VIN_DATA_PIN_GROUP(n, s) \
	61	{ \
	62	.name = #n#s, \
	63	.pins = n##_pins.data##s, \
	64	.mux = n##_mux.data##s, \
	65	.nr_pins = ARRAY_SIZE(n##_pins.data##s), \
	66	}
	67
	68	union vin_data {
	69	unsigned int data24[24];
	70	unsigned int data20[20];
	71	unsigned int data16[16];
	72	unsigned int data12[12];
	73	unsigned int data10[10];
	74	unsigned int data8[8];
	75	unsigned int data4[4];
	76	};
	77
3d8d9f1d LP	78	#define SH_PFC_FUNCTION(n) \
	79	{ \
	80	.name = #n, \
	81	.groups = n##_groups, \
	82	.nr_groups = ARRAY_SIZE(n##_groups), \
	83	}
	84
	85	struct sh_pfc_function {
	86	const char *name;
	87	const char * const *groups;
	88	unsigned int nr_groups;
	89	};
	90
a373ed0a	91	struct pinmux_func {
533743dc	92	u16 enum_id;
a373ed0a LP	93	const char *name;
	94	};
	95
fae43399	96	struct pinmux_cfg_reg {
1f34de05	97	u32 reg;
dc700715	98	u8 reg_width, field_width;
533743dc	99	const u16 *enum_ids;
dc700715	100	const u8 *var_field_width;
fae43399 MD	101	};
	102
	103	#define PINMUX_CFG_REG(name, r, r_width, f_width) \
	104	.reg = r, .reg_width = r_width, .field_width = f_width, \
9aecff58	105	.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
f78a26f5 MD	106
	107	#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
	108	.reg = r, .reg_width = r_width, \
dc700715	109	.var_field_width = (const u8 [r_width]) \
9aecff58 LP	110	{ var_fw0, var_fwn, 0 }, \
9aecff58 LP	111	.enum_ids = (const u16 [])
fae43399 MD	112
fae43399 MD	113	struct pinmux_data_reg {
1f34de05	114	u32 reg;
dc700715	115	u8 reg_width;
533743dc	116	const u16 *enum_ids;
fae43399 MD	117	};
	118
	119	#define PINMUX_DATA_REG(name, r, r_width) \
	120	.reg = r, .reg_width = r_width, \
9aecff58	121	.enum_ids = (const u16 [r_width]) \
fae43399	122
ad2a8e7e	123	struct pinmux_irq {
6d5bddd5	124	const short *gpios;
ad2a8e7e MD	125	};
ad2a8e7e MD	126
4adeabd0	127	#define PINMUX_IRQ(ids...) \
0e26e8df	128	{ .gpios = (const short []) { ids, -1 } }
ad2a8e7e	129
fae43399	130	struct pinmux_range {
533743dc LP	131	u16 begin;
	132	u16 end;
	133	u16 force;
fae43399 MD	134	};
fae43399 MD	135
c58d9c1b LP	136	struct sh_pfc;
	137
	138	struct sh_pfc_soc_operations {
0c151062	139	int (init)(struct sh_pfc pfc);
c58d9c1b LP	140	unsigned int (get_bias)(struct sh_pfc pfc, unsigned int pin);
	141	void (set_bias)(struct sh_pfc pfc, unsigned int pin,
	142	unsigned int bias);
5b9eaa56 BH	143	int (get_io_voltage)(struct sh_pfc pfc, unsigned int pin);
	144	int (set_io_voltage)(struct sh_pfc pfc, unsigned int pin,
	145	u16 voltage_mV);
c58d9c1b LP	146	};
c58d9c1b LP	147
19bb7fe3	148	struct sh_pfc_soc_info {
cd3c1bee	149	const char *name;
c58d9c1b LP	150	const struct sh_pfc_soc_operations *ops;
c58d9c1b LP	151
fae43399	152	struct pinmux_range input;
fae43399	153	struct pinmux_range output;
fae43399 MD	154	struct pinmux_range function;
fae43399 MD	155
cd3c1bee	156	const struct sh_pfc_pin *pins;
caa5bac3	157	unsigned int nr_pins;
3d8d9f1d LP	158	const struct sh_pfc_pin_group *groups;
	159	unsigned int nr_groups;
	160	const struct sh_pfc_function *functions;
	161	unsigned int nr_functions;
	162
56f891b4	163	#ifdef CONFIG_SUPERH
cd3c1bee	164	const struct pinmux_func *func_gpios;
a373ed0a	165	unsigned int nr_func_gpios;
56f891b4	166	#endif
d7a7ca57	167
cd3c1bee LP	168	const struct pinmux_cfg_reg *cfg_regs;
cd3c1bee LP	169	const struct pinmux_data_reg *data_regs;
fae43399	170
b8b47d67 GU	171	const u16 *pinmux_data;
b8b47d67 GU	172	unsigned int pinmux_data_size;
fae43399	173
cd3c1bee	174	const struct pinmux_irq *gpio_irq;
ad2a8e7e MD	175	unsigned int gpio_irq_size;
ad2a8e7e MD	176
1f34de05	177	u32 unlock_reg;
fae43399 MD	178	};
fae43399 MD	179
e3d93b46 LP	180	/* -----------------------------------------------------------------------------
	181	* Helper macros to create pin and port lists
	182	*/
	183
	184	/*
b8b47d67	185	* sh_pfc_soc_info pinmux_data array macros
e3d93b46 LP	186	*/
	187
	188	#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
	189
	190	#define PINMUX_IPSR_NOGP(ispr, fn) \
	191	PINMUX_DATA(fn##_MARK, FN_##fn)
	192	#define PINMUX_IPSR_DATA(ipsr, fn) \
	193	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
	194	#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
	195	PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
4c9e4735 NS	196	#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
4c9e4735 NS	197	PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
e3d93b46	198	#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
2b67bccb	199	PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
e3d93b46	200
dcd803be GU	201	/*
	202	* Describe a pinmux configuration for a single-function pin with GPIO
	203	* capability.
	204	* - fn: Function name
	205	*/
	206	#define PINMUX_SINGLE(fn) \
	207	PINMUX_DATA(fn##_MARK, FN_##fn)
	208
e3d93b46 LP	209	/*
	210	* GP port style (32 ports banks)
	211	*/
	212
22768fc6 UH	213	#define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
	214	#define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
	215
2d24fe67	216	#define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
22768fc6	217	PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
2d24fe67 KM	218	PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
	219	#define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
	220
	221	#define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
	222	PORT_GP_CFG_4(bank, fn, sfx, cfg), \
22768fc6	223	PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \
2d24fe67 KM	224	PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
	225	#define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
	226
	227	#define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
	228	PORT_GP_CFG_8(bank, fn, sfx, cfg), \
	229	PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
	230	#define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
	231
	232	#define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
	233	PORT_GP_CFG_8(bank, fn, sfx, cfg), \
22768fc6	234	PORT_GP_CFG_1(bank, 8, fn, sfx, cfg), PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \
2d24fe67 KM	235	PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
	236	#define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
	237
	238	#define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
	239	PORT_GP_CFG_12(bank, fn, sfx, cfg), \
	240	PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
	241	#define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
	242
	243	#define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
	244	PORT_GP_CFG_14(bank, fn, sfx, cfg), \
	245	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
	246	#define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
	247
	248	#define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
	249	PORT_GP_CFG_14(bank, fn, sfx, cfg), \
	250	PORT_GP_CFG_1(bank, 14, fn, sfx, cfg), PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
	251	#define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
	252
	253	#define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
	254	PORT_GP_CFG_16(bank, fn, sfx, cfg), \
	255	PORT_GP_CFG_1(bank, 16, fn, sfx, cfg), PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
	256	#define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
	257
	258	#define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
	259	PORT_GP_CFG_18(bank, fn, sfx, cfg), \
22768fc6 UH	260	PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \
	261	PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \
	262	PORT_GP_CFG_1(bank, 22, fn, sfx, cfg), PORT_GP_CFG_1(bank, 23, fn, sfx, cfg), \
2d24fe67 KM	263	PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
	264	#define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
	265
	266	#define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
	267	PORT_GP_CFG_26(bank, fn, sfx, cfg), \
	268	PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
	269	#define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
	270
	271	#define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
	272	PORT_GP_CFG_28(bank, fn, sfx, cfg), \
	273	PORT_GP_CFG_1(bank, 28, fn, sfx, cfg), PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
	274	#define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
	275
	276	#define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
	277	PORT_GP_CFG_30(bank, fn, sfx, cfg), \
22768fc6 UH	278	PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
22768fc6 UH	279	#define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
e3d93b46 LP	280
	281	#define PORT_GP_32_REV(bank, fn, sfx) \
	282	PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
	283	PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
	284	PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
	285	PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
	286	PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
	287	PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
	288	PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
	289	PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
	290	PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
	291	PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
	292	PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
	293	PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
	294	PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
	295	PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
	296	PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
	297	PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
	298
	299	/* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
22768fc6	300	#define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
e3d93b46 LP	301	#define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
	302
	303	/* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
22768fc6	304	#define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
61bb3aef	305	{ \
9689896c	306	.pin = (bank * 32) + _pin, \
e3d93b46 LP	307	.name = __stringify(_name), \
e3d93b46 LP	308	.enum_id = _name##_DATA, \
22768fc6	309	.configs = cfg, \
e3d93b46 LP	310	}
	311	#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
	312
	313	/* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
22768fc6	314	#define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
e3d93b46 LP	315	#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
	316
	317	/*
	318	* PORT style (linear pin space)
	319	*/
	320
3ce0d7eb	321	#define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
16b915e4 LP	322
	323	#define PORT_10(pn, fn, pfx, sfx) \
	324	PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
	325	PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
	326	PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
	327	PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
	328	PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
	329
	330	#define PORT_90(pn, fn, pfx, sfx) \
	331	PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
	332	PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
	333	PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
	334	PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
	335	PORT_10(pn+90, fn, pfx##9, sfx)
972c3fb6	336
e3d93b46	337	/* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
3ce0d7eb	338	#define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
e3d93b46	339	#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
972c3fb6	340
e3d93b46	341	/* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
9689896c LP	342	#define PINMUX_GPIO(_pin) \
	343	[GPIO_##_pin] = { \
	344	.pin = (u16)-1, \
8620f394	345	.name = __stringify(GPIO_##_pin), \
9689896c	346	.enum_id = _pin##_DATA, \
e3d93b46 LP	347	}
e3d93b46 LP	348
df020272	349	/* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
9689896c	350	#define SH_PFC_PIN_CFG(_pin, cfgs) \
df020272	351	{ \
9689896c LP	352	.pin = _pin, \
	353	.name = __stringify(PORT##_pin), \
	354	.enum_id = PORT##_pin##_DATA, \
df020272 LP	355	.configs = cfgs, \
	356	}
	357
4f82e3ee LP	358	/* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
	359	#define SH_PFC_PIN_NAMED(row, col, _name) \
	360	{ \
	361	.pin = PIN_NUMBER(row, col), \
	362	.name = __stringify(PIN_##_name), \
	363	.configs = SH_PFC_PIN_CFG_NO_GPIO, \
	364	}
	365
e3d93b46 LP	366	/* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
	367	* PORT_name_OUT, PORT_name_IN marks
	368	*/
3ce0d7eb	369	#define _PORT_DATA(pn, pfx, sfx) \
e3d93b46 LP	370	PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
	371	PORT##pfx##_OUT, PORT##pfx##_IN)
	372	#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
	373
	374	/* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
	375	#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
	376	[gpio - (base)] = { \
	377	.name = __stringify(gpio), \
	378	.enum_id = data_or_mark, \
	379	}
	380	#define GPIO_FN(str) \
	381	PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
bd8d0cba	382
e3d93b46 LP	383	/*
	384	* PORTnCR macro
	385	*/
9b49139b KM	386	#define PORTCR(nr, reg) \
9b49139b KM	387	{ \
05c5f265 GU	388	PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\
	389	/* PULMD[1:0], handled by .set_bias() */ \
	390	0, 0, 0, 0, \
	391	/* IE and OE */ \
	392	0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
	393	/* SEC, not supported */ \
	394	0, 0, \
	395	/* PTMD[2:0] */ \
	396	PORT##nr##_FN0, PORT##nr##_FN1, \
	397	PORT##nr##_FN2, PORT##nr##_FN3, \
	398	PORT##nr##_FN4, PORT##nr##_FN5, \
	399	PORT##nr##_FN6, PORT##nr##_FN7 \
	400	} \
9b49139b	401	}
bd8d0cba	402
69af775a GU	403	/*
	404	* GPIO number helper macro for R-Car
	405	*/
	406	#define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
	407
fae43399	408	#endif /* __SH_PFC_H */