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fae43399 MD |
1 | /* |
2 | * SuperH Pin Function Controller Support | |
3 | * | |
4 | * Copyright (c) 2008 Magnus Damm | |
5 | * | |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | ||
11 | #ifndef __SH_PFC_H | |
12 | #define __SH_PFC_H | |
13 | ||
bf9f0674 | 14 | #include <linux/bug.h> |
5b9eaa56 | 15 | #include <linux/pinctrl/pinconf-generic.h> |
07d36d29 | 16 | #include <linux/spinlock.h> |
72c7afa1 | 17 | #include <linux/stringify.h> |
fae43399 | 18 | |
06d5631f PM |
19 | enum { |
20 | PINMUX_TYPE_NONE, | |
06d5631f PM |
21 | PINMUX_TYPE_FUNCTION, |
22 | PINMUX_TYPE_GPIO, | |
23 | PINMUX_TYPE_OUTPUT, | |
24 | PINMUX_TYPE_INPUT, | |
06d5631f | 25 | }; |
fae43399 | 26 | |
c58d9c1b LP |
27 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
28 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) | |
29 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) | |
30 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) | |
5b9eaa56 | 31 | #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) |
3caa7d8c | 32 | #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) |
4f82e3ee | 33 | #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) |
c58d9c1b | 34 | |
a3db40a6 | 35 | struct sh_pfc_pin { |
9689896c | 36 | u16 pin; |
533743dc | 37 | u16 enum_id; |
72c7afa1 | 38 | const char *name; |
c58d9c1b | 39 | unsigned int configs; |
fae43399 MD |
40 | }; |
41 | ||
3d8d9f1d LP |
42 | #define SH_PFC_PIN_GROUP(n) \ |
43 | { \ | |
44 | .name = #n, \ | |
45 | .pins = n##_pins, \ | |
46 | .mux = n##_mux, \ | |
47 | .nr_pins = ARRAY_SIZE(n##_pins), \ | |
48 | } | |
49 | ||
50 | struct sh_pfc_pin_group { | |
51 | const char *name; | |
52 | const unsigned int *pins; | |
53 | const unsigned int *mux; | |
54 | unsigned int nr_pins; | |
55 | }; | |
56 | ||
423caa52 SS |
57 | /* |
58 | * Using union vin_data saves memory occupied by the VIN data pins. | |
59 | * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups | |
60 | * in this case. | |
61 | */ | |
62 | #define VIN_DATA_PIN_GROUP(n, s) \ | |
63 | { \ | |
64 | .name = #n#s, \ | |
65 | .pins = n##_pins.data##s, \ | |
66 | .mux = n##_mux.data##s, \ | |
67 | .nr_pins = ARRAY_SIZE(n##_pins.data##s), \ | |
68 | } | |
69 | ||
70 | union vin_data { | |
71 | unsigned int data24[24]; | |
72 | unsigned int data20[20]; | |
73 | unsigned int data16[16]; | |
74 | unsigned int data12[12]; | |
75 | unsigned int data10[10]; | |
76 | unsigned int data8[8]; | |
77 | unsigned int data4[4]; | |
78 | }; | |
79 | ||
3d8d9f1d LP |
80 | #define SH_PFC_FUNCTION(n) \ |
81 | { \ | |
82 | .name = #n, \ | |
83 | .groups = n##_groups, \ | |
84 | .nr_groups = ARRAY_SIZE(n##_groups), \ | |
85 | } | |
86 | ||
87 | struct sh_pfc_function { | |
88 | const char *name; | |
89 | const char * const *groups; | |
90 | unsigned int nr_groups; | |
91 | }; | |
92 | ||
a373ed0a | 93 | struct pinmux_func { |
533743dc | 94 | u16 enum_id; |
a373ed0a LP |
95 | const char *name; |
96 | }; | |
97 | ||
fae43399 | 98 | struct pinmux_cfg_reg { |
1f34de05 | 99 | u32 reg; |
dc700715 | 100 | u8 reg_width, field_width; |
533743dc | 101 | const u16 *enum_ids; |
dc700715 | 102 | const u8 *var_field_width; |
fae43399 MD |
103 | }; |
104 | ||
cbc983f8 GU |
105 | /* |
106 | * Describe a config register consisting of several fields of the same width | |
107 | * - name: Register name (unused, for documentation purposes only) | |
108 | * - r: Physical register address | |
109 | * - r_width: Width of the register (in bits) | |
110 | * - f_width: Width of the fixed-width register fields (in bits) | |
111 | * This macro must be followed by initialization data: For each register field | |
112 | * (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified, | |
113 | * one for each possible combination of the register field bit values. | |
114 | */ | |
fae43399 MD |
115 | #define PINMUX_CFG_REG(name, r, r_width, f_width) \ |
116 | .reg = r, .reg_width = r_width, .field_width = f_width, \ | |
9aecff58 | 117 | .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) |
f78a26f5 | 118 | |
cbc983f8 GU |
119 | /* |
120 | * Describe a config register consisting of several fields of different widths | |
121 | * - name: Register name (unused, for documentation purposes only) | |
122 | * - r: Physical register address | |
123 | * - r_width: Width of the register (in bits) | |
124 | * - var_fw0, var_fwn...: List of widths of the register fields (in bits), | |
125 | * From left to right (i.e. MSB to LSB) | |
126 | * This macro must be followed by initialization data: For each register field | |
127 | * (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified, | |
128 | * one for each possible combination of the register field bit values. | |
129 | */ | |
f78a26f5 MD |
130 | #define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ |
131 | .reg = r, .reg_width = r_width, \ | |
dc700715 | 132 | .var_field_width = (const u8 [r_width]) \ |
9aecff58 LP |
133 | { var_fw0, var_fwn, 0 }, \ |
134 | .enum_ids = (const u16 []) | |
fae43399 | 135 | |
3caa7d8c LP |
136 | struct pinmux_drive_reg_field { |
137 | u16 pin; | |
138 | u8 offset; | |
139 | u8 size; | |
140 | }; | |
141 | ||
142 | struct pinmux_drive_reg { | |
143 | u32 reg; | |
144 | const struct pinmux_drive_reg_field fields[8]; | |
145 | }; | |
146 | ||
147 | #define PINMUX_DRIVE_REG(name, r) \ | |
148 | .reg = r, \ | |
149 | .fields = | |
150 | ||
fae43399 | 151 | struct pinmux_data_reg { |
1f34de05 | 152 | u32 reg; |
dc700715 | 153 | u8 reg_width; |
533743dc | 154 | const u16 *enum_ids; |
fae43399 MD |
155 | }; |
156 | ||
cbc983f8 GU |
157 | /* |
158 | * Describe a data register | |
159 | * - name: Register name (unused, for documentation purposes only) | |
160 | * - r: Physical register address | |
161 | * - r_width: Width of the register (in bits) | |
162 | * This macro must be followed by initialization data: For each register bit | |
163 | * (from left to right, i.e. MSB to LSB), one enum ID must be specified. | |
164 | */ | |
fae43399 MD |
165 | #define PINMUX_DATA_REG(name, r, r_width) \ |
166 | .reg = r, .reg_width = r_width, \ | |
9aecff58 | 167 | .enum_ids = (const u16 [r_width]) \ |
fae43399 | 168 | |
ad2a8e7e | 169 | struct pinmux_irq { |
6d5bddd5 | 170 | const short *gpios; |
ad2a8e7e MD |
171 | }; |
172 | ||
cbc983f8 GU |
173 | /* |
174 | * Describe the mapping from GPIOs to a single IRQ | |
175 | * - ids...: List of GPIOs that are mapped to the same IRQ | |
176 | */ | |
4adeabd0 | 177 | #define PINMUX_IRQ(ids...) \ |
0e26e8df | 178 | { .gpios = (const short []) { ids, -1 } } |
ad2a8e7e | 179 | |
fae43399 | 180 | struct pinmux_range { |
533743dc LP |
181 | u16 begin; |
182 | u16 end; | |
183 | u16 force; | |
fae43399 MD |
184 | }; |
185 | ||
07d36d29 GU |
186 | struct sh_pfc_window { |
187 | phys_addr_t phys; | |
188 | void __iomem *virt; | |
189 | unsigned long size; | |
190 | }; | |
191 | ||
192 | struct sh_pfc_pin_range; | |
193 | ||
194 | struct sh_pfc { | |
195 | struct device *dev; | |
196 | const struct sh_pfc_soc_info *info; | |
197 | spinlock_t lock; | |
198 | ||
199 | unsigned int num_windows; | |
200 | struct sh_pfc_window *windows; | |
201 | unsigned int num_irqs; | |
202 | unsigned int *irqs; | |
203 | ||
204 | struct sh_pfc_pin_range *ranges; | |
205 | unsigned int nr_ranges; | |
206 | ||
207 | unsigned int nr_gpio_pins; | |
208 | ||
209 | struct sh_pfc_chip *gpio; | |
07d36d29 | 210 | }; |
c58d9c1b LP |
211 | |
212 | struct sh_pfc_soc_operations { | |
0c151062 | 213 | int (*init)(struct sh_pfc *pfc); |
c58d9c1b LP |
214 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
215 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, | |
216 | unsigned int bias); | |
8775306d | 217 | int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); |
c58d9c1b LP |
218 | }; |
219 | ||
19bb7fe3 | 220 | struct sh_pfc_soc_info { |
cd3c1bee | 221 | const char *name; |
c58d9c1b LP |
222 | const struct sh_pfc_soc_operations *ops; |
223 | ||
fae43399 | 224 | struct pinmux_range input; |
fae43399 | 225 | struct pinmux_range output; |
fae43399 MD |
226 | struct pinmux_range function; |
227 | ||
cd3c1bee | 228 | const struct sh_pfc_pin *pins; |
caa5bac3 | 229 | unsigned int nr_pins; |
3d8d9f1d LP |
230 | const struct sh_pfc_pin_group *groups; |
231 | unsigned int nr_groups; | |
232 | const struct sh_pfc_function *functions; | |
233 | unsigned int nr_functions; | |
234 | ||
56f891b4 | 235 | #ifdef CONFIG_SUPERH |
cd3c1bee | 236 | const struct pinmux_func *func_gpios; |
a373ed0a | 237 | unsigned int nr_func_gpios; |
56f891b4 | 238 | #endif |
d7a7ca57 | 239 | |
cd3c1bee | 240 | const struct pinmux_cfg_reg *cfg_regs; |
3caa7d8c | 241 | const struct pinmux_drive_reg *drive_regs; |
cd3c1bee | 242 | const struct pinmux_data_reg *data_regs; |
fae43399 | 243 | |
b8b47d67 GU |
244 | const u16 *pinmux_data; |
245 | unsigned int pinmux_data_size; | |
fae43399 | 246 | |
cd3c1bee | 247 | const struct pinmux_irq *gpio_irq; |
ad2a8e7e MD |
248 | unsigned int gpio_irq_size; |
249 | ||
1f34de05 | 250 | u32 unlock_reg; |
fae43399 MD |
251 | }; |
252 | ||
9f4ca14e GU |
253 | extern const struct sh_pfc_soc_info emev2_pinmux_info; |
254 | extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; | |
255 | extern const struct sh_pfc_soc_info r8a7740_pinmux_info; | |
256 | extern const struct sh_pfc_soc_info r8a7778_pinmux_info; | |
257 | extern const struct sh_pfc_soc_info r8a7779_pinmux_info; | |
258 | extern const struct sh_pfc_soc_info r8a7790_pinmux_info; | |
259 | extern const struct sh_pfc_soc_info r8a7791_pinmux_info; | |
2cf59e0c | 260 | extern const struct sh_pfc_soc_info r8a7792_pinmux_info; |
9f4ca14e GU |
261 | extern const struct sh_pfc_soc_info r8a7793_pinmux_info; |
262 | extern const struct sh_pfc_soc_info r8a7794_pinmux_info; | |
263 | extern const struct sh_pfc_soc_info r8a7795_pinmux_info; | |
f9aece73 | 264 | extern const struct sh_pfc_soc_info r8a7796_pinmux_info; |
9f4ca14e GU |
265 | extern const struct sh_pfc_soc_info sh7203_pinmux_info; |
266 | extern const struct sh_pfc_soc_info sh7264_pinmux_info; | |
267 | extern const struct sh_pfc_soc_info sh7269_pinmux_info; | |
268 | extern const struct sh_pfc_soc_info sh73a0_pinmux_info; | |
269 | extern const struct sh_pfc_soc_info sh7720_pinmux_info; | |
270 | extern const struct sh_pfc_soc_info sh7722_pinmux_info; | |
271 | extern const struct sh_pfc_soc_info sh7723_pinmux_info; | |
272 | extern const struct sh_pfc_soc_info sh7724_pinmux_info; | |
273 | extern const struct sh_pfc_soc_info sh7734_pinmux_info; | |
274 | extern const struct sh_pfc_soc_info sh7757_pinmux_info; | |
275 | extern const struct sh_pfc_soc_info sh7785_pinmux_info; | |
276 | extern const struct sh_pfc_soc_info sh7786_pinmux_info; | |
277 | extern const struct sh_pfc_soc_info shx3_pinmux_info; | |
278 | ||
e3d93b46 LP |
279 | /* ----------------------------------------------------------------------------- |
280 | * Helper macros to create pin and port lists | |
281 | */ | |
282 | ||
283 | /* | |
b8b47d67 | 284 | * sh_pfc_soc_info pinmux_data array macros |
e3d93b46 LP |
285 | */ |
286 | ||
cbc983f8 GU |
287 | /* |
288 | * Describe generic pinmux data | |
289 | * - data_or_mark: *_DATA or *_MARK enum ID | |
290 | * - ids...: List of enum IDs to associate with data_or_mark | |
291 | */ | |
e3d93b46 LP |
292 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
293 | ||
cbc983f8 GU |
294 | /* |
295 | * Describe a pinmux configuration without GPIO function that needs | |
296 | * configuration in a Peripheral Function Select Register (IPSR) | |
297 | * - ipsr: IPSR field (unused, for documentation purposes only) | |
298 | * - fn: Function name, referring to a field in the IPSR | |
299 | */ | |
300 | #define PINMUX_IPSR_NOGP(ipsr, fn) \ | |
e3d93b46 | 301 | PINMUX_DATA(fn##_MARK, FN_##fn) |
cbc983f8 GU |
302 | |
303 | /* | |
304 | * Describe a pinmux configuration with GPIO function that needs configuration | |
305 | * in both a Peripheral Function Select Register (IPSR) and in a | |
306 | * GPIO/Peripheral Function Select Register (GPSR) | |
307 | * - ipsr: IPSR field | |
308 | * - fn: Function name, also referring to the IPSR field | |
309 | */ | |
e01678e3 | 310 | #define PINMUX_IPSR_GPSR(ipsr, fn) \ |
e3d93b46 | 311 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) |
cbc983f8 GU |
312 | |
313 | /* | |
314 | * Describe a pinmux configuration without GPIO function that needs | |
315 | * configuration in a Peripheral Function Select Register (IPSR), and where the | |
316 | * pinmux function has a representation in a Module Select Register (MOD_SEL). | |
317 | * - ipsr: IPSR field (unused, for documentation purposes only) | |
318 | * - fn: Function name, also referring to the IPSR field | |
319 | * - msel: Module selector | |
320 | */ | |
321 | #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ | |
322 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) | |
323 | ||
324 | /* | |
325 | * Describe a pinmux configuration with GPIO function where the pinmux function | |
326 | * has no representation in a Peripheral Function Select Register (IPSR), but | |
327 | * instead solely depends on a group selection. | |
328 | * - gpsr: GPSR field | |
329 | * - fn: Function name, also referring to the GPSR field | |
330 | * - gsel: Group selector | |
331 | */ | |
332 | #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ | |
333 | PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) | |
334 | ||
335 | /* | |
336 | * Describe a pinmux configuration with GPIO function that needs configuration | |
337 | * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral | |
338 | * Function Select Register (GPSR), and where the pinmux function has a | |
339 | * representation in a Module Select Register (MOD_SEL). | |
340 | * - ipsr: IPSR field | |
341 | * - fn: Function name, also referring to the IPSR field | |
342 | * - msel: Module selector | |
343 | */ | |
344 | #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ | |
93d2185d | 345 | PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) |
e3d93b46 | 346 | |
dcd803be GU |
347 | /* |
348 | * Describe a pinmux configuration for a single-function pin with GPIO | |
349 | * capability. | |
350 | * - fn: Function name | |
351 | */ | |
352 | #define PINMUX_SINGLE(fn) \ | |
353 | PINMUX_DATA(fn##_MARK, FN_##fn) | |
354 | ||
e3d93b46 LP |
355 | /* |
356 | * GP port style (32 ports banks) | |
357 | */ | |
358 | ||
e729bbc1 SS |
359 | #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ |
360 | fn(bank, pin, GP_##bank##_##pin, sfx, cfg) | |
22768fc6 UH |
361 | #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) |
362 | ||
e729bbc1 SS |
363 | #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ |
364 | PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ | |
365 | PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ | |
366 | PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ | |
367 | PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) | |
2d24fe67 KM |
368 | #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) |
369 | ||
e729bbc1 SS |
370 | #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ |
371 | PORT_GP_CFG_4(bank, fn, sfx, cfg), \ | |
372 | PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ | |
373 | PORT_GP_CFG_1(bank, 5, fn, sfx, cfg), \ | |
374 | PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ | |
375 | PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) | |
2d24fe67 KM |
376 | #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) |
377 | ||
e729bbc1 SS |
378 | #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ |
379 | PORT_GP_CFG_8(bank, fn, sfx, cfg), \ | |
2d24fe67 KM |
380 | PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) |
381 | #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) | |
382 | ||
e729bbc1 SS |
383 | #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ |
384 | PORT_GP_CFG_9(bank, fn, sfx, cfg), \ | |
385 | PORT_GP_CFG_1(bank, 9, fn, sfx, cfg), \ | |
386 | PORT_GP_CFG_1(bank, 10, fn, sfx, cfg), \ | |
387 | PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) | |
2d24fe67 KM |
388 | #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) |
389 | ||
e729bbc1 SS |
390 | #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ |
391 | PORT_GP_CFG_12(bank, fn, sfx, cfg), \ | |
392 | PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ | |
393 | PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) | |
2d24fe67 KM |
394 | #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) |
395 | ||
e729bbc1 SS |
396 | #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ |
397 | PORT_GP_CFG_14(bank, fn, sfx, cfg), \ | |
2d24fe67 KM |
398 | PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) |
399 | #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) | |
400 | ||
e729bbc1 SS |
401 | #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ |
402 | PORT_GP_CFG_15(bank, fn, sfx, cfg), \ | |
403 | PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) | |
2d24fe67 KM |
404 | #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) |
405 | ||
2cf59e0c | 406 | #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ |
e729bbc1 | 407 | PORT_GP_CFG_16(bank, fn, sfx, cfg), \ |
2cf59e0c SS |
408 | PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) |
409 | #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) | |
410 | ||
411 | #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ | |
412 | PORT_GP_CFG_17(bank, fn, sfx, cfg), \ | |
e729bbc1 | 413 | PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) |
2d24fe67 KM |
414 | #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) |
415 | ||
2cf59e0c | 416 | #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ |
e729bbc1 SS |
417 | PORT_GP_CFG_18(bank, fn, sfx, cfg), \ |
418 | PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ | |
419 | PORT_GP_CFG_1(bank, 19, fn, sfx, cfg), \ | |
420 | PORT_GP_CFG_1(bank, 20, fn, sfx, cfg), \ | |
421 | PORT_GP_CFG_1(bank, 21, fn, sfx, cfg), \ | |
2cf59e0c SS |
422 | PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) |
423 | #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) | |
424 | ||
9a6caa13 | 425 | #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ |
2cf59e0c | 426 | PORT_GP_CFG_23(bank, fn, sfx, cfg), \ |
9a6caa13 SH |
427 | PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) |
428 | #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) | |
429 | ||
430 | #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ | |
431 | PORT_GP_CFG_24(bank, fn, sfx, cfg), \ | |
e729bbc1 SS |
432 | PORT_GP_CFG_1(bank, 24, fn, sfx, cfg), \ |
433 | PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) | |
2d24fe67 KM |
434 | #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) |
435 | ||
e729bbc1 SS |
436 | #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ |
437 | PORT_GP_CFG_26(bank, fn, sfx, cfg), \ | |
438 | PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ | |
439 | PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) | |
2d24fe67 KM |
440 | #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) |
441 | ||
2cf59e0c | 442 | #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ |
e729bbc1 | 443 | PORT_GP_CFG_28(bank, fn, sfx, cfg), \ |
2cf59e0c SS |
444 | PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) |
445 | #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) | |
446 | ||
447 | #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ | |
448 | PORT_GP_CFG_29(bank, fn, sfx, cfg), \ | |
e729bbc1 | 449 | PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) |
2d24fe67 KM |
450 | #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) |
451 | ||
e729bbc1 SS |
452 | #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ |
453 | PORT_GP_CFG_30(bank, fn, sfx, cfg), \ | |
454 | PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ | |
455 | PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) | |
22768fc6 | 456 | #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) |
e3d93b46 LP |
457 | |
458 | #define PORT_GP_32_REV(bank, fn, sfx) \ | |
459 | PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ | |
460 | PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ | |
461 | PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ | |
462 | PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ | |
463 | PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ | |
464 | PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ | |
465 | PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ | |
466 | PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ | |
467 | PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ | |
468 | PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ | |
469 | PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ | |
470 | PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ | |
471 | PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ | |
472 | PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ | |
473 | PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ | |
474 | PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) | |
475 | ||
476 | /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ | |
22768fc6 | 477 | #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx |
e3d93b46 LP |
478 | #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str) |
479 | ||
480 | /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ | |
22768fc6 | 481 | #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ |
61bb3aef | 482 | { \ |
9689896c | 483 | .pin = (bank * 32) + _pin, \ |
e3d93b46 LP |
484 | .name = __stringify(_name), \ |
485 | .enum_id = _name##_DATA, \ | |
22768fc6 | 486 | .configs = cfg, \ |
e3d93b46 LP |
487 | } |
488 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused) | |
489 | ||
490 | /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ | |
22768fc6 | 491 | #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) |
e3d93b46 LP |
492 | #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused) |
493 | ||
494 | /* | |
495 | * PORT style (linear pin space) | |
496 | */ | |
497 | ||
3ce0d7eb | 498 | #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) |
16b915e4 LP |
499 | |
500 | #define PORT_10(pn, fn, pfx, sfx) \ | |
501 | PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ | |
502 | PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ | |
503 | PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ | |
504 | PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ | |
505 | PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) | |
506 | ||
507 | #define PORT_90(pn, fn, pfx, sfx) \ | |
508 | PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ | |
509 | PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ | |
510 | PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ | |
511 | PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ | |
512 | PORT_10(pn+90, fn, pfx##9, sfx) | |
972c3fb6 | 513 | |
e3d93b46 | 514 | /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ |
3ce0d7eb | 515 | #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx |
e3d93b46 | 516 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
972c3fb6 | 517 | |
e3d93b46 | 518 | /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ |
9689896c LP |
519 | #define PINMUX_GPIO(_pin) \ |
520 | [GPIO_##_pin] = { \ | |
521 | .pin = (u16)-1, \ | |
8620f394 | 522 | .name = __stringify(GPIO_##_pin), \ |
9689896c | 523 | .enum_id = _pin##_DATA, \ |
e3d93b46 LP |
524 | } |
525 | ||
df020272 | 526 | /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ |
9689896c | 527 | #define SH_PFC_PIN_CFG(_pin, cfgs) \ |
df020272 | 528 | { \ |
9689896c LP |
529 | .pin = _pin, \ |
530 | .name = __stringify(PORT##_pin), \ | |
531 | .enum_id = PORT##_pin##_DATA, \ | |
df020272 LP |
532 | .configs = cfgs, \ |
533 | } | |
534 | ||
4f82e3ee LP |
535 | /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ |
536 | #define SH_PFC_PIN_NAMED(row, col, _name) \ | |
537 | { \ | |
538 | .pin = PIN_NUMBER(row, col), \ | |
539 | .name = __stringify(PIN_##_name), \ | |
540 | .configs = SH_PFC_PIN_CFG_NO_GPIO, \ | |
541 | } | |
542 | ||
e3d93b46 LP |
543 | /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, |
544 | * PORT_name_OUT, PORT_name_IN marks | |
545 | */ | |
3ce0d7eb | 546 | #define _PORT_DATA(pn, pfx, sfx) \ |
e3d93b46 LP |
547 | PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ |
548 | PORT##pfx##_OUT, PORT##pfx##_IN) | |
549 | #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) | |
550 | ||
551 | /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ | |
552 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ | |
553 | [gpio - (base)] = { \ | |
554 | .name = __stringify(gpio), \ | |
555 | .enum_id = data_or_mark, \ | |
556 | } | |
557 | #define GPIO_FN(str) \ | |
558 | PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) | |
bd8d0cba | 559 | |
e3d93b46 | 560 | /* |
cbc983f8 | 561 | * PORTnCR helper macro for SH-Mobile/R-Mobile |
e3d93b46 | 562 | */ |
9b49139b KM |
563 | #define PORTCR(nr, reg) \ |
564 | { \ | |
05c5f265 GU |
565 | PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, 2, 2, 1, 3) {\ |
566 | /* PULMD[1:0], handled by .set_bias() */ \ | |
567 | 0, 0, 0, 0, \ | |
568 | /* IE and OE */ \ | |
569 | 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ | |
570 | /* SEC, not supported */ \ | |
571 | 0, 0, \ | |
572 | /* PTMD[2:0] */ \ | |
573 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
574 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
575 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
576 | PORT##nr##_FN6, PORT##nr##_FN7 \ | |
577 | } \ | |
9b49139b | 578 | } |
bd8d0cba | 579 | |
69af775a GU |
580 | /* |
581 | * GPIO number helper macro for R-Car | |
582 | */ | |
583 | #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) | |
584 | ||
fae43399 | 585 | #endif /* __SH_PFC_H */ |