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63b6d7e7 KM |
1 | /* SPDX-License-Identifier: GPL-2.0 |
2 | * | |
fae43399 MD |
3 | * SuperH Pin Function Controller Support |
4 | * | |
5 | * Copyright (c) 2008 Magnus Damm | |
fae43399 MD |
6 | */ |
7 | ||
8 | #ifndef __SH_PFC_H | |
9 | #define __SH_PFC_H | |
10 | ||
bf9f0674 | 11 | #include <linux/bug.h> |
5b9eaa56 | 12 | #include <linux/pinctrl/pinconf-generic.h> |
07d36d29 | 13 | #include <linux/spinlock.h> |
72c7afa1 | 14 | #include <linux/stringify.h> |
fae43399 | 15 | |
06d5631f PM |
16 | enum { |
17 | PINMUX_TYPE_NONE, | |
06d5631f PM |
18 | PINMUX_TYPE_FUNCTION, |
19 | PINMUX_TYPE_GPIO, | |
20 | PINMUX_TYPE_OUTPUT, | |
21 | PINMUX_TYPE_INPUT, | |
06d5631f | 22 | }; |
fae43399 | 23 | |
c58d9c1b LP |
24 | #define SH_PFC_PIN_CFG_INPUT (1 << 0) |
25 | #define SH_PFC_PIN_CFG_OUTPUT (1 << 1) | |
26 | #define SH_PFC_PIN_CFG_PULL_UP (1 << 2) | |
27 | #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3) | |
5b9eaa56 | 28 | #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4) |
3caa7d8c | 29 | #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5) |
4f82e3ee | 30 | #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31) |
c58d9c1b | 31 | |
a3db40a6 | 32 | struct sh_pfc_pin { |
9689896c | 33 | u16 pin; |
533743dc | 34 | u16 enum_id; |
72c7afa1 | 35 | const char *name; |
c58d9c1b | 36 | unsigned int configs; |
fae43399 MD |
37 | }; |
38 | ||
43a51cd5 | 39 | #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \ |
3d8d9f1d | 40 | { \ |
43a51cd5 | 41 | .name = #alias, \ |
3d8d9f1d LP |
42 | .pins = n##_pins, \ |
43 | .mux = n##_mux, \ | |
9925e879 GU |
44 | .nr_pins = ARRAY_SIZE(n##_pins) + \ |
45 | BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \ | |
3d8d9f1d | 46 | } |
43a51cd5 | 47 | #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n) |
3d8d9f1d LP |
48 | |
49 | struct sh_pfc_pin_group { | |
50 | const char *name; | |
51 | const unsigned int *pins; | |
52 | const unsigned int *mux; | |
53 | unsigned int nr_pins; | |
54 | }; | |
55 | ||
423caa52 | 56 | /* |
50f3f2d7 GU |
57 | * Using union vin_data{,12,16} saves memory occupied by the VIN data pins. |
58 | * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups | |
e889b298 JM |
59 | * in this case. It accepts an optional 'version' argument used when the |
60 | * same group can appear on a different set of pins. | |
423caa52 | 61 | */ |
e889b298 JM |
62 | #define VIN_DATA_PIN_GROUP(n, s, ...) \ |
63 | { \ | |
64 | .name = #n#s#__VA_ARGS__, \ | |
65 | .pins = n##__VA_ARGS__##_pins.data##s, \ | |
66 | .mux = n##__VA_ARGS__##_mux.data##s, \ | |
67 | .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \ | |
423caa52 SS |
68 | } |
69 | ||
50f3f2d7 GU |
70 | union vin_data12 { |
71 | unsigned int data12[12]; | |
72 | unsigned int data10[10]; | |
73 | unsigned int data8[8]; | |
74 | }; | |
75 | ||
76 | union vin_data16 { | |
77 | unsigned int data16[16]; | |
78 | unsigned int data12[12]; | |
79 | unsigned int data10[10]; | |
80 | unsigned int data8[8]; | |
81 | }; | |
82 | ||
423caa52 SS |
83 | union vin_data { |
84 | unsigned int data24[24]; | |
85 | unsigned int data20[20]; | |
86 | unsigned int data16[16]; | |
87 | unsigned int data12[12]; | |
88 | unsigned int data10[10]; | |
89 | unsigned int data8[8]; | |
90 | unsigned int data4[4]; | |
91 | }; | |
92 | ||
3d8d9f1d LP |
93 | #define SH_PFC_FUNCTION(n) \ |
94 | { \ | |
95 | .name = #n, \ | |
96 | .groups = n##_groups, \ | |
97 | .nr_groups = ARRAY_SIZE(n##_groups), \ | |
98 | } | |
99 | ||
100 | struct sh_pfc_function { | |
101 | const char *name; | |
102 | const char * const *groups; | |
103 | unsigned int nr_groups; | |
104 | }; | |
105 | ||
a373ed0a | 106 | struct pinmux_func { |
533743dc | 107 | u16 enum_id; |
a373ed0a LP |
108 | const char *name; |
109 | }; | |
110 | ||
fae43399 | 111 | struct pinmux_cfg_reg { |
1f34de05 | 112 | u32 reg; |
dc700715 | 113 | u8 reg_width, field_width; |
fa4d3671 GU |
114 | #ifdef DEBUG |
115 | u16 nr_enum_ids; /* for variable width regs only */ | |
116 | #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n, | |
117 | #else | |
118 | #define SET_NR_ENUM_IDS(n) | |
119 | #endif | |
533743dc | 120 | const u16 *enum_ids; |
dc700715 | 121 | const u8 *var_field_width; |
fae43399 MD |
122 | }; |
123 | ||
efca8da0 GU |
124 | #define GROUP(...) __VA_ARGS__ |
125 | ||
cbc983f8 GU |
126 | /* |
127 | * Describe a config register consisting of several fields of the same width | |
128 | * - name: Register name (unused, for documentation purposes only) | |
129 | * - r: Physical register address | |
130 | * - r_width: Width of the register (in bits) | |
131 | * - f_width: Width of the fixed-width register fields (in bits) | |
efca8da0 GU |
132 | * - ids: For each register field (from left to right, i.e. MSB to LSB), |
133 | * 2^f_width enum IDs must be specified, one for each possible | |
134 | * combination of the register field bit values, all wrapped using | |
135 | * the GROUP() macro. | |
cbc983f8 | 136 | */ |
efca8da0 | 137 | #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \ |
5e8588c8 | 138 | .reg = r, .reg_width = r_width, \ |
c481c817 GU |
139 | .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \ |
140 | BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ | |
141 | (r_width / f_width) * (1 << f_width)), \ | |
efca8da0 GU |
142 | .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \ |
143 | { ids } | |
f78a26f5 | 144 | |
cbc983f8 GU |
145 | /* |
146 | * Describe a config register consisting of several fields of different widths | |
147 | * - name: Register name (unused, for documentation purposes only) | |
148 | * - r: Physical register address | |
149 | * - r_width: Width of the register (in bits) | |
69f7be1c GU |
150 | * - f_widths: List of widths of the register fields (in bits), from left |
151 | * to right (i.e. MSB to LSB), wrapped using the GROUP() macro. | |
152 | * - ids: For each register field (from left to right, i.e. MSB to LSB), | |
153 | * 2^f_widths[i] enum IDs must be specified, one for each possible | |
154 | * combination of the register field bit values, all wrapped using | |
155 | * the GROUP() macro. | |
cbc983f8 | 156 | */ |
69f7be1c GU |
157 | #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \ |
158 | .reg = r, .reg_width = r_width, \ | |
159 | .var_field_width = (const u8 []) { f_widths, 0 }, \ | |
fa4d3671 | 160 | SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \ |
69f7be1c | 161 | .enum_ids = (const u16 []) { ids } |
fae43399 | 162 | |
3caa7d8c LP |
163 | struct pinmux_drive_reg_field { |
164 | u16 pin; | |
165 | u8 offset; | |
166 | u8 size; | |
167 | }; | |
168 | ||
169 | struct pinmux_drive_reg { | |
170 | u32 reg; | |
171 | const struct pinmux_drive_reg_field fields[8]; | |
172 | }; | |
173 | ||
174 | #define PINMUX_DRIVE_REG(name, r) \ | |
175 | .reg = r, \ | |
176 | .fields = | |
177 | ||
beaa34d9 GU |
178 | struct pinmux_bias_reg { |
179 | u32 puen; /* Pull-enable or pull-up control register */ | |
180 | u32 pud; /* Pull-up/down control register (optional) */ | |
181 | const u16 pins[32]; | |
182 | }; | |
183 | ||
184 | #define PINMUX_BIAS_REG(name1, r1, name2, r2) \ | |
185 | .puen = r1, \ | |
186 | .pud = r2, \ | |
187 | .pins = | |
188 | ||
9e9bd06a GU |
189 | struct pinmux_ioctrl_reg { |
190 | u32 reg; | |
191 | }; | |
192 | ||
fae43399 | 193 | struct pinmux_data_reg { |
1f34de05 | 194 | u32 reg; |
dc700715 | 195 | u8 reg_width; |
533743dc | 196 | const u16 *enum_ids; |
fae43399 MD |
197 | }; |
198 | ||
cbc983f8 GU |
199 | /* |
200 | * Describe a data register | |
201 | * - name: Register name (unused, for documentation purposes only) | |
202 | * - r: Physical register address | |
203 | * - r_width: Width of the register (in bits) | |
19b593a1 GU |
204 | * - ids: For each register bit (from left to right, i.e. MSB to LSB), one |
205 | * enum ID must be specified, all wrapped using the GROUP() macro. | |
cbc983f8 | 206 | */ |
19b593a1 | 207 | #define PINMUX_DATA_REG(name, r, r_width, ids) \ |
c481c817 GU |
208 | .reg = r, .reg_width = r_width + \ |
209 | BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \ | |
210 | r_width), \ | |
19b593a1 | 211 | .enum_ids = (const u16 [r_width]) { ids } |
fae43399 | 212 | |
ad2a8e7e | 213 | struct pinmux_irq { |
6d5bddd5 | 214 | const short *gpios; |
ad2a8e7e MD |
215 | }; |
216 | ||
cbc983f8 GU |
217 | /* |
218 | * Describe the mapping from GPIOs to a single IRQ | |
219 | * - ids...: List of GPIOs that are mapped to the same IRQ | |
220 | */ | |
4adeabd0 | 221 | #define PINMUX_IRQ(ids...) \ |
0e26e8df | 222 | { .gpios = (const short []) { ids, -1 } } |
ad2a8e7e | 223 | |
fae43399 | 224 | struct pinmux_range { |
533743dc LP |
225 | u16 begin; |
226 | u16 end; | |
227 | u16 force; | |
fae43399 MD |
228 | }; |
229 | ||
07d36d29 GU |
230 | struct sh_pfc_window { |
231 | phys_addr_t phys; | |
232 | void __iomem *virt; | |
233 | unsigned long size; | |
234 | }; | |
235 | ||
236 | struct sh_pfc_pin_range; | |
237 | ||
238 | struct sh_pfc { | |
239 | struct device *dev; | |
240 | const struct sh_pfc_soc_info *info; | |
241 | spinlock_t lock; | |
242 | ||
243 | unsigned int num_windows; | |
244 | struct sh_pfc_window *windows; | |
245 | unsigned int num_irqs; | |
246 | unsigned int *irqs; | |
247 | ||
248 | struct sh_pfc_pin_range *ranges; | |
249 | unsigned int nr_ranges; | |
250 | ||
251 | unsigned int nr_gpio_pins; | |
252 | ||
253 | struct sh_pfc_chip *gpio; | |
8843797d | 254 | u32 *saved_regs; |
07d36d29 | 255 | }; |
c58d9c1b LP |
256 | |
257 | struct sh_pfc_soc_operations { | |
0c151062 | 258 | int (*init)(struct sh_pfc *pfc); |
c58d9c1b LP |
259 | unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin); |
260 | void (*set_bias)(struct sh_pfc *pfc, unsigned int pin, | |
261 | unsigned int bias); | |
8775306d | 262 | int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl); |
c58d9c1b LP |
263 | }; |
264 | ||
19bb7fe3 | 265 | struct sh_pfc_soc_info { |
cd3c1bee | 266 | const char *name; |
c58d9c1b LP |
267 | const struct sh_pfc_soc_operations *ops; |
268 | ||
fae43399 | 269 | struct pinmux_range input; |
fae43399 | 270 | struct pinmux_range output; |
fae43399 MD |
271 | struct pinmux_range function; |
272 | ||
cd3c1bee | 273 | const struct sh_pfc_pin *pins; |
caa5bac3 | 274 | unsigned int nr_pins; |
3d8d9f1d LP |
275 | const struct sh_pfc_pin_group *groups; |
276 | unsigned int nr_groups; | |
277 | const struct sh_pfc_function *functions; | |
278 | unsigned int nr_functions; | |
279 | ||
0ace9596 | 280 | #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO |
cd3c1bee | 281 | const struct pinmux_func *func_gpios; |
a373ed0a | 282 | unsigned int nr_func_gpios; |
56f891b4 | 283 | #endif |
d7a7ca57 | 284 | |
cd3c1bee | 285 | const struct pinmux_cfg_reg *cfg_regs; |
3caa7d8c | 286 | const struct pinmux_drive_reg *drive_regs; |
beaa34d9 | 287 | const struct pinmux_bias_reg *bias_regs; |
9e9bd06a | 288 | const struct pinmux_ioctrl_reg *ioctrl_regs; |
cd3c1bee | 289 | const struct pinmux_data_reg *data_regs; |
fae43399 | 290 | |
b8b47d67 GU |
291 | const u16 *pinmux_data; |
292 | unsigned int pinmux_data_size; | |
fae43399 | 293 | |
cd3c1bee | 294 | const struct pinmux_irq *gpio_irq; |
ad2a8e7e MD |
295 | unsigned int gpio_irq_size; |
296 | ||
1f34de05 | 297 | u32 unlock_reg; |
fae43399 MD |
298 | }; |
299 | ||
9f4ca14e GU |
300 | extern const struct sh_pfc_soc_info emev2_pinmux_info; |
301 | extern const struct sh_pfc_soc_info r8a73a4_pinmux_info; | |
302 | extern const struct sh_pfc_soc_info r8a7740_pinmux_info; | |
8df62701 | 303 | extern const struct sh_pfc_soc_info r8a7743_pinmux_info; |
d7097b97 | 304 | extern const struct sh_pfc_soc_info r8a7744_pinmux_info; |
c8bac70f | 305 | extern const struct sh_pfc_soc_info r8a7745_pinmux_info; |
73dacc34 | 306 | extern const struct sh_pfc_soc_info r8a77470_pinmux_info; |
91d627a7 | 307 | extern const struct sh_pfc_soc_info r8a774a1_pinmux_info; |
9f2b76a2 | 308 | extern const struct sh_pfc_soc_info r8a774c0_pinmux_info; |
9f4ca14e GU |
309 | extern const struct sh_pfc_soc_info r8a7778_pinmux_info; |
310 | extern const struct sh_pfc_soc_info r8a7779_pinmux_info; | |
311 | extern const struct sh_pfc_soc_info r8a7790_pinmux_info; | |
312 | extern const struct sh_pfc_soc_info r8a7791_pinmux_info; | |
2cf59e0c | 313 | extern const struct sh_pfc_soc_info r8a7792_pinmux_info; |
9f4ca14e GU |
314 | extern const struct sh_pfc_soc_info r8a7793_pinmux_info; |
315 | extern const struct sh_pfc_soc_info r8a7794_pinmux_info; | |
316 | extern const struct sh_pfc_soc_info r8a7795_pinmux_info; | |
b205914c | 317 | extern const struct sh_pfc_soc_info r8a7795es1_pinmux_info; |
f9aece73 | 318 | extern const struct sh_pfc_soc_info r8a7796_pinmux_info; |
490e687e | 319 | extern const struct sh_pfc_soc_info r8a77965_pinmux_info; |
b92ac66a | 320 | extern const struct sh_pfc_soc_info r8a77970_pinmux_info; |
f5912524 | 321 | extern const struct sh_pfc_soc_info r8a77980_pinmux_info; |
6d4036a1 | 322 | extern const struct sh_pfc_soc_info r8a77990_pinmux_info; |
794a6711 | 323 | extern const struct sh_pfc_soc_info r8a77995_pinmux_info; |
9f4ca14e GU |
324 | extern const struct sh_pfc_soc_info sh7203_pinmux_info; |
325 | extern const struct sh_pfc_soc_info sh7264_pinmux_info; | |
326 | extern const struct sh_pfc_soc_info sh7269_pinmux_info; | |
327 | extern const struct sh_pfc_soc_info sh73a0_pinmux_info; | |
328 | extern const struct sh_pfc_soc_info sh7720_pinmux_info; | |
329 | extern const struct sh_pfc_soc_info sh7722_pinmux_info; | |
330 | extern const struct sh_pfc_soc_info sh7723_pinmux_info; | |
331 | extern const struct sh_pfc_soc_info sh7724_pinmux_info; | |
332 | extern const struct sh_pfc_soc_info sh7734_pinmux_info; | |
333 | extern const struct sh_pfc_soc_info sh7757_pinmux_info; | |
334 | extern const struct sh_pfc_soc_info sh7785_pinmux_info; | |
335 | extern const struct sh_pfc_soc_info sh7786_pinmux_info; | |
336 | extern const struct sh_pfc_soc_info shx3_pinmux_info; | |
337 | ||
e3d93b46 LP |
338 | /* ----------------------------------------------------------------------------- |
339 | * Helper macros to create pin and port lists | |
340 | */ | |
341 | ||
342 | /* | |
b8b47d67 | 343 | * sh_pfc_soc_info pinmux_data array macros |
e3d93b46 LP |
344 | */ |
345 | ||
cbc983f8 GU |
346 | /* |
347 | * Describe generic pinmux data | |
348 | * - data_or_mark: *_DATA or *_MARK enum ID | |
349 | * - ids...: List of enum IDs to associate with data_or_mark | |
350 | */ | |
e3d93b46 LP |
351 | #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 |
352 | ||
cbc983f8 GU |
353 | /* |
354 | * Describe a pinmux configuration without GPIO function that needs | |
355 | * configuration in a Peripheral Function Select Register (IPSR) | |
356 | * - ipsr: IPSR field (unused, for documentation purposes only) | |
357 | * - fn: Function name, referring to a field in the IPSR | |
358 | */ | |
359 | #define PINMUX_IPSR_NOGP(ipsr, fn) \ | |
e3d93b46 | 360 | PINMUX_DATA(fn##_MARK, FN_##fn) |
cbc983f8 GU |
361 | |
362 | /* | |
363 | * Describe a pinmux configuration with GPIO function that needs configuration | |
364 | * in both a Peripheral Function Select Register (IPSR) and in a | |
365 | * GPIO/Peripheral Function Select Register (GPSR) | |
366 | * - ipsr: IPSR field | |
367 | * - fn: Function name, also referring to the IPSR field | |
368 | */ | |
e01678e3 | 369 | #define PINMUX_IPSR_GPSR(ipsr, fn) \ |
e3d93b46 | 370 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr) |
cbc983f8 GU |
371 | |
372 | /* | |
373 | * Describe a pinmux configuration without GPIO function that needs | |
374 | * configuration in a Peripheral Function Select Register (IPSR), and where the | |
375 | * pinmux function has a representation in a Module Select Register (MOD_SEL). | |
376 | * - ipsr: IPSR field (unused, for documentation purposes only) | |
377 | * - fn: Function name, also referring to the IPSR field | |
378 | * - msel: Module selector | |
379 | */ | |
380 | #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \ | |
381 | PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel) | |
382 | ||
383 | /* | |
384 | * Describe a pinmux configuration with GPIO function where the pinmux function | |
385 | * has no representation in a Peripheral Function Select Register (IPSR), but | |
386 | * instead solely depends on a group selection. | |
387 | * - gpsr: GPSR field | |
388 | * - fn: Function name, also referring to the GPSR field | |
389 | * - gsel: Group selector | |
390 | */ | |
391 | #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \ | |
392 | PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel) | |
393 | ||
394 | /* | |
395 | * Describe a pinmux configuration with GPIO function that needs configuration | |
396 | * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral | |
397 | * Function Select Register (GPSR), and where the pinmux function has a | |
398 | * representation in a Module Select Register (MOD_SEL). | |
399 | * - ipsr: IPSR field | |
400 | * - fn: Function name, also referring to the IPSR field | |
401 | * - msel: Module selector | |
402 | */ | |
403 | #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \ | |
93d2185d | 404 | PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr) |
e3d93b46 | 405 | |
50d1ba17 UH |
406 | /* |
407 | * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with | |
408 | * an additional select register that controls physical multiplexing | |
409 | * with another pin. | |
410 | * - ipsr: IPSR field | |
411 | * - fn: Function name, also referring to the IPSR field | |
412 | * - psel: Physical multiplexing selector | |
413 | * - msel: Module selector | |
414 | */ | |
415 | #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \ | |
416 | PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr) | |
417 | ||
418 | /* | |
419 | * Describe a pinmux configuration in which a pin is physically multiplexed | |
420 | * with other pins. | |
360328c7 GU |
421 | * - ipsr: IPSR field (unused, for documentation purposes only) |
422 | * - fn: Function name | |
50d1ba17 UH |
423 | * - psel: Physical multiplexing selector |
424 | */ | |
425 | #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \ | |
426 | PINMUX_DATA(fn##_MARK, FN_##psel) | |
427 | ||
dcd803be GU |
428 | /* |
429 | * Describe a pinmux configuration for a single-function pin with GPIO | |
430 | * capability. | |
431 | * - fn: Function name | |
432 | */ | |
433 | #define PINMUX_SINGLE(fn) \ | |
434 | PINMUX_DATA(fn##_MARK, FN_##fn) | |
435 | ||
e3d93b46 LP |
436 | /* |
437 | * GP port style (32 ports banks) | |
438 | */ | |
439 | ||
e729bbc1 SS |
440 | #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \ |
441 | fn(bank, pin, GP_##bank##_##pin, sfx, cfg) | |
22768fc6 UH |
442 | #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0) |
443 | ||
e729bbc1 SS |
444 | #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \ |
445 | PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \ | |
446 | PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \ | |
447 | PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \ | |
448 | PORT_GP_CFG_1(bank, 3, fn, sfx, cfg) | |
2d24fe67 KM |
449 | #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0) |
450 | ||
5a0e6988 | 451 | #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \ |
e729bbc1 SS |
452 | PORT_GP_CFG_4(bank, fn, sfx, cfg), \ |
453 | PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \ | |
5a0e6988 SS |
454 | PORT_GP_CFG_1(bank, 5, fn, sfx, cfg) |
455 | #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0) | |
456 | ||
457 | #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \ | |
458 | PORT_GP_CFG_6(bank, fn, sfx, cfg), \ | |
e729bbc1 SS |
459 | PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \ |
460 | PORT_GP_CFG_1(bank, 7, fn, sfx, cfg) | |
2d24fe67 KM |
461 | #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0) |
462 | ||
e729bbc1 SS |
463 | #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \ |
464 | PORT_GP_CFG_8(bank, fn, sfx, cfg), \ | |
2d24fe67 KM |
465 | PORT_GP_CFG_1(bank, 8, fn, sfx, cfg) |
466 | #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0) | |
467 | ||
afdf04c1 | 468 | #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \ |
e729bbc1 | 469 | PORT_GP_CFG_9(bank, fn, sfx, cfg), \ |
afdf04c1 YS |
470 | PORT_GP_CFG_1(bank, 9, fn, sfx, cfg) |
471 | #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0) | |
472 | ||
ec96db58 | 473 | #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \ |
afdf04c1 | 474 | PORT_GP_CFG_10(bank, fn, sfx, cfg), \ |
ec96db58 TK |
475 | PORT_GP_CFG_1(bank, 10, fn, sfx, cfg) |
476 | #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0) | |
477 | ||
478 | #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \ | |
479 | PORT_GP_CFG_11(bank, fn, sfx, cfg), \ | |
e729bbc1 | 480 | PORT_GP_CFG_1(bank, 11, fn, sfx, cfg) |
2d24fe67 KM |
481 | #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0) |
482 | ||
e729bbc1 SS |
483 | #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \ |
484 | PORT_GP_CFG_12(bank, fn, sfx, cfg), \ | |
485 | PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \ | |
486 | PORT_GP_CFG_1(bank, 13, fn, sfx, cfg) | |
2d24fe67 KM |
487 | #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0) |
488 | ||
e729bbc1 SS |
489 | #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \ |
490 | PORT_GP_CFG_14(bank, fn, sfx, cfg), \ | |
2d24fe67 KM |
491 | PORT_GP_CFG_1(bank, 14, fn, sfx, cfg) |
492 | #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0) | |
493 | ||
e729bbc1 SS |
494 | #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \ |
495 | PORT_GP_CFG_15(bank, fn, sfx, cfg), \ | |
496 | PORT_GP_CFG_1(bank, 15, fn, sfx, cfg) | |
2d24fe67 KM |
497 | #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0) |
498 | ||
2cf59e0c | 499 | #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \ |
e729bbc1 | 500 | PORT_GP_CFG_16(bank, fn, sfx, cfg), \ |
2cf59e0c SS |
501 | PORT_GP_CFG_1(bank, 16, fn, sfx, cfg) |
502 | #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0) | |
503 | ||
504 | #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \ | |
505 | PORT_GP_CFG_17(bank, fn, sfx, cfg), \ | |
e729bbc1 | 506 | PORT_GP_CFG_1(bank, 17, fn, sfx, cfg) |
2d24fe67 KM |
507 | #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0) |
508 | ||
afdf04c1 | 509 | #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \ |
e729bbc1 SS |
510 | PORT_GP_CFG_18(bank, fn, sfx, cfg), \ |
511 | PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \ | |
afdf04c1 YS |
512 | PORT_GP_CFG_1(bank, 19, fn, sfx, cfg) |
513 | #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0) | |
514 | ||
515 | #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \ | |
516 | PORT_GP_CFG_20(bank, fn, sfx, cfg), \ | |
517 | PORT_GP_CFG_1(bank, 20, fn, sfx, cfg) | |
518 | #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0) | |
519 | ||
5a0e6988 | 520 | #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \ |
afdf04c1 | 521 | PORT_GP_CFG_21(bank, fn, sfx, cfg), \ |
5a0e6988 SS |
522 | PORT_GP_CFG_1(bank, 21, fn, sfx, cfg) |
523 | #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0) | |
524 | ||
525 | #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \ | |
526 | PORT_GP_CFG_22(bank, fn, sfx, cfg), \ | |
2cf59e0c SS |
527 | PORT_GP_CFG_1(bank, 22, fn, sfx, cfg) |
528 | #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0) | |
529 | ||
9a6caa13 | 530 | #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \ |
2cf59e0c | 531 | PORT_GP_CFG_23(bank, fn, sfx, cfg), \ |
9a6caa13 SH |
532 | PORT_GP_CFG_1(bank, 23, fn, sfx, cfg) |
533 | #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0) | |
534 | ||
c21a3e30 | 535 | #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \ |
9a6caa13 | 536 | PORT_GP_CFG_24(bank, fn, sfx, cfg), \ |
c21a3e30 SS |
537 | PORT_GP_CFG_1(bank, 24, fn, sfx, cfg) |
538 | #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0) | |
539 | ||
540 | #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \ | |
541 | PORT_GP_CFG_25(bank, fn, sfx, cfg), \ | |
e729bbc1 | 542 | PORT_GP_CFG_1(bank, 25, fn, sfx, cfg) |
2d24fe67 KM |
543 | #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0) |
544 | ||
e729bbc1 SS |
545 | #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \ |
546 | PORT_GP_CFG_26(bank, fn, sfx, cfg), \ | |
547 | PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \ | |
548 | PORT_GP_CFG_1(bank, 27, fn, sfx, cfg) | |
2d24fe67 KM |
549 | #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0) |
550 | ||
2cf59e0c | 551 | #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \ |
e729bbc1 | 552 | PORT_GP_CFG_28(bank, fn, sfx, cfg), \ |
2cf59e0c SS |
553 | PORT_GP_CFG_1(bank, 28, fn, sfx, cfg) |
554 | #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0) | |
555 | ||
556 | #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \ | |
557 | PORT_GP_CFG_29(bank, fn, sfx, cfg), \ | |
e729bbc1 | 558 | PORT_GP_CFG_1(bank, 29, fn, sfx, cfg) |
2d24fe67 KM |
559 | #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0) |
560 | ||
e729bbc1 SS |
561 | #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \ |
562 | PORT_GP_CFG_30(bank, fn, sfx, cfg), \ | |
563 | PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \ | |
564 | PORT_GP_CFG_1(bank, 31, fn, sfx, cfg) | |
22768fc6 | 565 | #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0) |
e3d93b46 LP |
566 | |
567 | #define PORT_GP_32_REV(bank, fn, sfx) \ | |
568 | PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \ | |
569 | PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \ | |
570 | PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \ | |
571 | PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \ | |
572 | PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \ | |
573 | PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \ | |
574 | PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \ | |
575 | PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \ | |
576 | PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \ | |
577 | PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \ | |
578 | PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \ | |
579 | PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \ | |
580 | PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \ | |
581 | PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \ | |
582 | PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \ | |
583 | PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx) | |
584 | ||
585 | /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */ | |
22768fc6 | 586 | #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx |
bd79c920 | 587 | #define GP_ALL(str) CPU_ALL_GP(_GP_ALL, str) |
e3d93b46 LP |
588 | |
589 | /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */ | |
22768fc6 | 590 | #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \ |
61bb3aef | 591 | { \ |
9689896c | 592 | .pin = (bank * 32) + _pin, \ |
e3d93b46 LP |
593 | .name = __stringify(_name), \ |
594 | .enum_id = _name##_DATA, \ | |
22768fc6 | 595 | .configs = cfg, \ |
e3d93b46 | 596 | } |
bd79c920 | 597 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_GP(_GP_GPIO, unused) |
e3d93b46 LP |
598 | |
599 | /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */ | |
22768fc6 | 600 | #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN) |
bd79c920 | 601 | #define PINMUX_DATA_GP_ALL() CPU_ALL_GP(_GP_DATA, unused) |
e3d93b46 LP |
602 | |
603 | /* | |
604 | * PORT style (linear pin space) | |
605 | */ | |
606 | ||
3ce0d7eb | 607 | #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx) |
16b915e4 LP |
608 | |
609 | #define PORT_10(pn, fn, pfx, sfx) \ | |
610 | PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \ | |
611 | PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \ | |
612 | PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \ | |
613 | PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \ | |
614 | PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx) | |
615 | ||
616 | #define PORT_90(pn, fn, pfx, sfx) \ | |
617 | PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \ | |
618 | PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \ | |
619 | PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \ | |
620 | PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \ | |
621 | PORT_10(pn+90, fn, pfx##9, sfx) | |
972c3fb6 | 622 | |
e3d93b46 | 623 | /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */ |
3ce0d7eb | 624 | #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx |
e3d93b46 | 625 | #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) |
972c3fb6 | 626 | |
e3d93b46 | 627 | /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */ |
9689896c LP |
628 | #define PINMUX_GPIO(_pin) \ |
629 | [GPIO_##_pin] = { \ | |
630 | .pin = (u16)-1, \ | |
8620f394 | 631 | .name = __stringify(GPIO_##_pin), \ |
9689896c | 632 | .enum_id = _pin##_DATA, \ |
e3d93b46 LP |
633 | } |
634 | ||
df020272 | 635 | /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */ |
9689896c | 636 | #define SH_PFC_PIN_CFG(_pin, cfgs) \ |
df020272 | 637 | { \ |
9689896c LP |
638 | .pin = _pin, \ |
639 | .name = __stringify(PORT##_pin), \ | |
640 | .enum_id = PORT##_pin##_DATA, \ | |
df020272 LP |
641 | .configs = cfgs, \ |
642 | } | |
643 | ||
4f82e3ee LP |
644 | /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */ |
645 | #define SH_PFC_PIN_NAMED(row, col, _name) \ | |
646 | { \ | |
647 | .pin = PIN_NUMBER(row, col), \ | |
648 | .name = __stringify(PIN_##_name), \ | |
649 | .configs = SH_PFC_PIN_CFG_NO_GPIO, \ | |
650 | } | |
651 | ||
1ce56aea NS |
652 | /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */ |
653 | #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \ | |
654 | { \ | |
655 | .pin = PIN_NUMBER(row, col), \ | |
656 | .name = __stringify(PIN_##_name), \ | |
657 | .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \ | |
658 | } | |
659 | ||
e3d93b46 LP |
660 | /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0, |
661 | * PORT_name_OUT, PORT_name_IN marks | |
662 | */ | |
3ce0d7eb | 663 | #define _PORT_DATA(pn, pfx, sfx) \ |
e3d93b46 LP |
664 | PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \ |
665 | PORT##pfx##_OUT, PORT##pfx##_IN) | |
666 | #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused) | |
667 | ||
668 | /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */ | |
669 | #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \ | |
670 | [gpio - (base)] = { \ | |
671 | .name = __stringify(gpio), \ | |
672 | .enum_id = data_or_mark, \ | |
673 | } | |
674 | #define GPIO_FN(str) \ | |
675 | PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK) | |
bd8d0cba | 676 | |
e3d93b46 | 677 | /* |
cbc983f8 | 678 | * PORTnCR helper macro for SH-Mobile/R-Mobile |
e3d93b46 | 679 | */ |
9b49139b KM |
680 | #define PORTCR(nr, reg) \ |
681 | { \ | |
69f7be1c GU |
682 | PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \ |
683 | GROUP(2, 2, 1, 3), \ | |
684 | GROUP( \ | |
05c5f265 GU |
685 | /* PULMD[1:0], handled by .set_bias() */ \ |
686 | 0, 0, 0, 0, \ | |
687 | /* IE and OE */ \ | |
688 | 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \ | |
689 | /* SEC, not supported */ \ | |
690 | 0, 0, \ | |
691 | /* PTMD[2:0] */ \ | |
692 | PORT##nr##_FN0, PORT##nr##_FN1, \ | |
693 | PORT##nr##_FN2, PORT##nr##_FN3, \ | |
694 | PORT##nr##_FN4, PORT##nr##_FN5, \ | |
695 | PORT##nr##_FN6, PORT##nr##_FN7 \ | |
69f7be1c | 696 | )) \ |
9b49139b | 697 | } |
bd8d0cba | 698 | |
69af775a GU |
699 | /* |
700 | * GPIO number helper macro for R-Car | |
701 | */ | |
702 | #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin)) | |
703 | ||
fae43399 | 704 | #endif /* __SH_PFC_H */ |