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[mirror_ubuntu-jammy-kernel.git] / drivers / pinctrl / sirf / pinctrl-prima2.c
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393daa81 1/*
3370dc91 2 * pinctrl pads, groups, functions for CSR SiRFprimaII
393daa81
RY		 3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
393daa81 9#include <linux/pinctrl/pinctrl.h>
393daa81 10#include <linux/bitops.h>
3370dc91
BS		 11
12#include "pinctrl-sirf.h"
51302162 13
393daa81
RY		 14/*
15 * pad list for the pinmux subsystem
16 * refer to CS-131858-DC-6A.xls
17 */
25aec320 18static const struct pinctrl_pin_desc sirfsoc_pads[] = {
8dd9766f
BS		 19 PINCTRL_PIN(0, "gpio0-0"),
20 PINCTRL_PIN(1, "gpio0-1"),
21 PINCTRL_PIN(2, "gpio0-2"),
22 PINCTRL_PIN(3, "gpio0-3"),
393daa81
RY		 23 PINCTRL_PIN(4, "pwm0"),
24 PINCTRL_PIN(5, "pwm1"),
25 PINCTRL_PIN(6, "pwm2"),
26 PINCTRL_PIN(7, "pwm3"),
27 PINCTRL_PIN(8, "warm_rst_b"),
28 PINCTRL_PIN(9, "odo_0"),
29 PINCTRL_PIN(10, "odo_1"),
30 PINCTRL_PIN(11, "dr_dir"),
8dd9766f 31 PINCTRL_PIN(12, "viprom_fa"),
393daa81 32 PINCTRL_PIN(13, "scl_1"),
8dd9766f 33 PINCTRL_PIN(14, "ntrst"),
393daa81
RY		 34 PINCTRL_PIN(15, "sda_1"),
35 PINCTRL_PIN(16, "x_ldd[16]"),
36 PINCTRL_PIN(17, "x_ldd[17]"),
37 PINCTRL_PIN(18, "x_ldd[18]"),
38 PINCTRL_PIN(19, "x_ldd[19]"),
39 PINCTRL_PIN(20, "x_ldd[20]"),
40 PINCTRL_PIN(21, "x_ldd[21]"),
41 PINCTRL_PIN(22, "x_ldd[22]"),
42 PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
43 PINCTRL_PIN(24, "gps_sgn"),
44 PINCTRL_PIN(25, "gps_mag"),
45 PINCTRL_PIN(26, "gps_clk"),
46 PINCTRL_PIN(27, "sd_cd_b_1"),
47 PINCTRL_PIN(28, "sd_vcc_on_1"),
48 PINCTRL_PIN(29, "sd_wp_b_1"),
49 PINCTRL_PIN(30, "sd_clk_3"),
50 PINCTRL_PIN(31, "sd_cmd_3"),
51
52 PINCTRL_PIN(32, "x_sd_dat_3[0]"),
53 PINCTRL_PIN(33, "x_sd_dat_3[1]"),
54 PINCTRL_PIN(34, "x_sd_dat_3[2]"),
55 PINCTRL_PIN(35, "x_sd_dat_3[3]"),
56 PINCTRL_PIN(36, "x_sd_clk_4"),
57 PINCTRL_PIN(37, "x_sd_cmd_4"),
58 PINCTRL_PIN(38, "x_sd_dat_4[0]"),
59 PINCTRL_PIN(39, "x_sd_dat_4[1]"),
60 PINCTRL_PIN(40, "x_sd_dat_4[2]"),
61 PINCTRL_PIN(41, "x_sd_dat_4[3]"),
62 PINCTRL_PIN(42, "x_cko_1"),
63 PINCTRL_PIN(43, "x_ac97_bit_clk"),
64 PINCTRL_PIN(44, "x_ac97_dout"),
65 PINCTRL_PIN(45, "x_ac97_din"),
66 PINCTRL_PIN(46, "x_ac97_sync"),
67 PINCTRL_PIN(47, "x_txd_1"),
68 PINCTRL_PIN(48, "x_txd_2"),
69 PINCTRL_PIN(49, "x_rxd_1"),
70 PINCTRL_PIN(50, "x_rxd_2"),
71 PINCTRL_PIN(51, "x_usclk_0"),
72 PINCTRL_PIN(52, "x_utxd_0"),
73 PINCTRL_PIN(53, "x_urxd_0"),
74 PINCTRL_PIN(54, "x_utfs_0"),
75 PINCTRL_PIN(55, "x_urfs_0"),
76 PINCTRL_PIN(56, "x_usclk_1"),
77 PINCTRL_PIN(57, "x_utxd_1"),
78 PINCTRL_PIN(58, "x_urxd_1"),
79 PINCTRL_PIN(59, "x_utfs_1"),
80 PINCTRL_PIN(60, "x_urfs_1"),
81 PINCTRL_PIN(61, "x_usclk_2"),
82 PINCTRL_PIN(62, "x_utxd_2"),
83 PINCTRL_PIN(63, "x_urxd_2"),
84
85 PINCTRL_PIN(64, "x_utfs_2"),
86 PINCTRL_PIN(65, "x_urfs_2"),
87 PINCTRL_PIN(66, "x_df_we_b"),
88 PINCTRL_PIN(67, "x_df_re_b"),
89 PINCTRL_PIN(68, "x_txd_0"),
90 PINCTRL_PIN(69, "x_rxd_0"),
91 PINCTRL_PIN(78, "x_cko_0"),
92 PINCTRL_PIN(79, "x_vip_pxd[7]"),
93 PINCTRL_PIN(80, "x_vip_pxd[6]"),
94 PINCTRL_PIN(81, "x_vip_pxd[5]"),
95 PINCTRL_PIN(82, "x_vip_pxd[4]"),
96 PINCTRL_PIN(83, "x_vip_pxd[3]"),
97 PINCTRL_PIN(84, "x_vip_pxd[2]"),
98 PINCTRL_PIN(85, "x_vip_pxd[1]"),
99 PINCTRL_PIN(86, "x_vip_pxd[0]"),
100 PINCTRL_PIN(87, "x_vip_vsync"),
101 PINCTRL_PIN(88, "x_vip_hsync"),
102 PINCTRL_PIN(89, "x_vip_pxclk"),
103 PINCTRL_PIN(90, "x_sda_0"),
104 PINCTRL_PIN(91, "x_scl_0"),
105 PINCTRL_PIN(92, "x_df_ry_by"),
106 PINCTRL_PIN(93, "x_df_cs_b[1]"),
107 PINCTRL_PIN(94, "x_df_cs_b[0]"),
108 PINCTRL_PIN(95, "x_l_pclk"),
109
110 PINCTRL_PIN(96, "x_l_lck"),
111 PINCTRL_PIN(97, "x_l_fck"),
112 PINCTRL_PIN(98, "x_l_de"),
113 PINCTRL_PIN(99, "x_ldd[0]"),
114 PINCTRL_PIN(100, "x_ldd[1]"),
115 PINCTRL_PIN(101, "x_ldd[2]"),
116 PINCTRL_PIN(102, "x_ldd[3]"),
117 PINCTRL_PIN(103, "x_ldd[4]"),
118 PINCTRL_PIN(104, "x_ldd[5]"),
119 PINCTRL_PIN(105, "x_ldd[6]"),
120 PINCTRL_PIN(106, "x_ldd[7]"),
121 PINCTRL_PIN(107, "x_ldd[8]"),
122 PINCTRL_PIN(108, "x_ldd[9]"),
123 PINCTRL_PIN(109, "x_ldd[10]"),
124 PINCTRL_PIN(110, "x_ldd[11]"),
125 PINCTRL_PIN(111, "x_ldd[12]"),
126 PINCTRL_PIN(112, "x_ldd[13]"),
127 PINCTRL_PIN(113, "x_ldd[14]"),
128 PINCTRL_PIN(114, "x_ldd[15]"),
6a08a92e
RW		 129
130 PINCTRL_PIN(115, "x_usb1_dp"),
131 PINCTRL_PIN(116, "x_usb1_dn"),
393daa81
RY		 132};
133
393daa81
RY		 134static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
135 {
136 .group = 3,
137 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
138 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
139 BIT(17) | BIT(18),
140 }, {
141 .group = 2,
142 .mask = BIT(31),
143 },
144};
145
146static const struct sirfsoc_padmux lcd_16bits_padmux = {
147 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
148 .muxmask = lcd_16bits_sirfsoc_muxmask,
6a08a92e 149 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 150 .funcmask = BIT(4),
151 .funcval = 0,
152};
153
154static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
155 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
156
157static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
158 {
159 .group = 3,
160 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
161 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
162 BIT(17) | BIT(18),
163 }, {
164 .group = 2,
165 .mask = BIT(31),
166 }, {
167 .group = 0,
168 .mask = BIT(16) | BIT(17),
169 },
170};
171
172static const struct sirfsoc_padmux lcd_18bits_padmux = {
173 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
174 .muxmask = lcd_18bits_muxmask,
6a08a92e 175 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 176 .funcmask = BIT(4),
177 .funcval = 0,
178};
179
180static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
181 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
182
183static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
184 {
185 .group = 3,
186 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
187 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
188 BIT(17) | BIT(18),
189 }, {
190 .group = 2,
191 .mask = BIT(31),
192 }, {
193 .group = 0,
194 .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
195 },
196};
197
198static const struct sirfsoc_padmux lcd_24bits_padmux = {
199 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
200 .muxmask = lcd_24bits_muxmask,
6a08a92e 201 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 202 .funcmask = BIT(4),
203 .funcval = 0,
204};
205
206static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
207 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
208
209static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
210 {
211 .group = 3,
212 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) |
213 BIT(9) | BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
214 BIT(17) | BIT(18),
215 }, {
216 .group = 2,
217 .mask = BIT(31),
218 }, {
219 .group = 0,
220 .mask = BIT(23),
221 },
222};
223
224static const struct sirfsoc_padmux lcdrom_padmux = {
225 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
226 .muxmask = lcdrom_muxmask,
6a08a92e 227 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 228 .funcmask = BIT(4),
229 .funcval = BIT(4),
230};
231
232static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104,
233 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
234
235static const struct sirfsoc_muxmask uart0_muxmask[] = {
236 {
237 .group = 2,
238 .mask = BIT(4) | BIT(5),
239 }, {
240 .group = 1,
241 .mask = BIT(23) | BIT(28),
242 },
243};
244
245static const struct sirfsoc_padmux uart0_padmux = {
246 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
247 .muxmask = uart0_muxmask,
6a08a92e 248 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 249 .funcmask = BIT(9),
250 .funcval = BIT(9),
251};
252
253static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
254
255static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
256 {
257 .group = 2,
258 .mask = BIT(4) | BIT(5),
259 },
260};
261
262static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
263 .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
264 .muxmask = uart0_nostreamctrl_muxmask,
265};
266
3370dc91 267static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
393daa81
RY		 268
269static const struct sirfsoc_muxmask uart1_muxmask[] = {
270 {
271 .group = 1,
272 .mask = BIT(15) | BIT(17),
273 },
274};
275
276static const struct sirfsoc_padmux uart1_padmux = {
277 .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
278 .muxmask = uart1_muxmask,
279};
280
281static const unsigned uart1_pins[] = { 47, 49 };
282
283static const struct sirfsoc_muxmask uart2_muxmask[] = {
284 {
285 .group = 1,
286 .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
287 },
288};
289
290static const struct sirfsoc_padmux uart2_padmux = {
291 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
292 .muxmask = uart2_muxmask,
6a08a92e 293 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 294 .funcmask = BIT(10),
295 .funcval = BIT(10),
296};
297
298static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
299
300static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
301 {
302 .group = 1,
303 .mask = BIT(16) | BIT(18),
304 },
305};
306
307static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
308 .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
309 .muxmask = uart2_nostreamctrl_muxmask,
310};
311
312static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
313
314static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
315 {
316 .group = 0,
317 .mask = BIT(30) | BIT(31),
318 }, {
319 .group = 1,
320 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
321 },
322};
323
324static const struct sirfsoc_padmux sdmmc3_padmux = {
325 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
326 .muxmask = sdmmc3_muxmask,
6a08a92e 327 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 328 .funcmask = BIT(7),
329 .funcval = 0,
330};
331
332static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
333
334static const struct sirfsoc_muxmask spi0_muxmask[] = {
335 {
336 .group = 1,
337 .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
338 },
339};
340
341static const struct sirfsoc_padmux spi0_padmux = {
342 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
343 .muxmask = spi0_muxmask,
6a08a92e 344 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 345 .funcmask = BIT(7),
346 .funcval = BIT(7),
347};
348
349static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
350
351static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
352 {
353 .group = 1,
354 .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
355 },
356};
357
358static const struct sirfsoc_padmux sdmmc4_padmux = {
359 .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
360 .muxmask = sdmmc4_muxmask,
361};
362
363static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
364
365static const struct sirfsoc_muxmask cko1_muxmask[] = {
366 {
367 .group = 1,
368 .mask = BIT(10),
369 },
370};
371
372static const struct sirfsoc_padmux cko1_padmux = {
373 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
374 .muxmask = cko1_muxmask,
6a08a92e 375 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 376 .funcmask = BIT(3),
377 .funcval = 0,
378};
379
380static const unsigned cko1_pins[] = { 42 };
381
382static const struct sirfsoc_muxmask i2s_muxmask[] = {
383 {
384 .group = 1,
385 .mask =
386 BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(19)
387 | BIT(23) | BIT(28),
388 },
389};
390
391static const struct sirfsoc_padmux i2s_padmux = {
392 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
393 .muxmask = i2s_muxmask,
6a08a92e 394 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 395 .funcmask = BIT(3) | BIT(9),
396 .funcval = BIT(3),
397};
398
399static const unsigned i2s_pins[] = { 42, 43, 44, 45, 46, 51, 55, 60 };
400
401static const struct sirfsoc_muxmask ac97_muxmask[] = {
402 {
403 .group = 1,
404 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
405 },
406};
407
408static const struct sirfsoc_padmux ac97_padmux = {
409 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
410 .muxmask = ac97_muxmask,
6a08a92e 411 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 412 .funcmask = BIT(8),
413 .funcval = 0,
414};
415
fa74d0d3 416static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
393daa81
RY		 417
418static const struct sirfsoc_muxmask spi1_muxmask[] = {
419 {
420 .group = 1,
421 .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
422 },
423};
424
425static const struct sirfsoc_padmux spi1_padmux = {
426 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
427 .muxmask = spi1_muxmask,
6a08a92e 428 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 429 .funcmask = BIT(8),
430 .funcval = BIT(8),
431};
432
f59d28dc 433static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
393daa81
RY		 434
435static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
436 {
437 .group = 0,
438 .mask = BIT(27) | BIT(28) | BIT(29),
439 },
440};
441
442static const struct sirfsoc_padmux sdmmc1_padmux = {
443 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
444 .muxmask = sdmmc1_muxmask,
445};
446
447static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
448
449static const struct sirfsoc_muxmask gps_muxmask[] = {
450 {
451 .group = 0,
452 .mask = BIT(24) | BIT(25) | BIT(26),
453 },
454};
455
456static const struct sirfsoc_padmux gps_padmux = {
457 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
458 .muxmask = gps_muxmask,
6a08a92e 459 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 460 .funcmask = BIT(12) | BIT(13) | BIT(14),
461 .funcval = BIT(12),
462};
463
464static const unsigned gps_pins[] = { 24, 25, 26 };
465
466static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
467 {
468 .group = 0,
469 .mask = BIT(24) | BIT(25) | BIT(26),
393daa81
RY		 470 },
471};
472
473static const struct sirfsoc_padmux sdmmc5_padmux = {
474 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
475 .muxmask = sdmmc5_muxmask,
6a08a92e 476 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 477 .funcmask = BIT(13) | BIT(14),
478 .funcval = BIT(13) | BIT(14),
479};
480
cbc3b873 481static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
393daa81
RY		 482
483static const struct sirfsoc_muxmask usp0_muxmask[] = {
484 {
485 .group = 1,
486 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
487 },
488};
489
490static const struct sirfsoc_padmux usp0_padmux = {
491 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
492 .muxmask = usp0_muxmask,
6a08a92e 493 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 494 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
495 .funcval = 0,
496};
497
498static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
499
8385af02
RY		 500static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
501 {
502 .group = 1,
503 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
504 },
505};
506
507static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
508 .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
509 .muxmask = usp0_only_utfs_muxmask,
510 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
511 .funcmask = BIT(1) | BIT(2) | BIT(6),
512 .funcval = 0,
513};
514
515static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
516
517static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
518 {
519 .group = 1,
520 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
521 },
522};
523
524static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
525 .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
526 .muxmask = usp0_only_urfs_muxmask,
527 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
528 .funcmask = BIT(1) | BIT(2) | BIT(9),
529 .funcval = 0,
530};
531
532static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
533
af614b23
QL		 534static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
535 {
536 .group = 1,
537 .mask = BIT(20) | BIT(21),
538 },
539};
540
541static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
542 .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
543 .muxmask = usp0_uart_nostreamctrl_muxmask,
544};
545
546static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
547
393daa81
RY		 548static const struct sirfsoc_muxmask usp1_muxmask[] = {
549 {
550 .group = 1,
551 .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
552 },
553};
554
555static const struct sirfsoc_padmux usp1_padmux = {
556 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
557 .muxmask = usp1_muxmask,
6a08a92e 558 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 559 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
560 .funcval = 0,
561};
562
563static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
564
af614b23
QL		 565static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
566 {
567 .group = 1,
568 .mask = BIT(25) | BIT(26),
569 },
570};
571
572static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
573 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
574 .muxmask = usp1_uart_nostreamctrl_muxmask,
575};
576
577static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
578
393daa81
RY		 579static const struct sirfsoc_muxmask usp2_muxmask[] = {
580 {
581 .group = 1,
582 .mask = BIT(29) | BIT(30) | BIT(31),
583 }, {
584 .group = 2,
585 .mask = BIT(0) | BIT(1),
586 },
587};
588
589static const struct sirfsoc_padmux usp2_padmux = {
590 .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
591 .muxmask = usp2_muxmask,
6a08a92e 592 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 593 .funcmask = BIT(13) | BIT(14),
594 .funcval = 0,
595};
596
597static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
598
af614b23
QL		 599static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
600 {
601 .group = 1,
602 .mask = BIT(30) | BIT(31),
603 },
604};
605
606static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
607 .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
608 .muxmask = usp2_uart_nostreamctrl_muxmask,
609};
610
611static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
612
393daa81
RY		 613static const struct sirfsoc_muxmask nand_muxmask[] = {
614 {
615 .group = 2,
616 .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
617 },
618};
619
620static const struct sirfsoc_padmux nand_padmux = {
621 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
622 .muxmask = nand_muxmask,
6a08a92e 623 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 624 .funcmask = BIT(5),
625 .funcval = 0,
626};
627
628static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
629
630static const struct sirfsoc_padmux sdmmc0_padmux = {
631 .muxmask_counts = 0,
6a08a92e 632 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 633 .funcmask = BIT(5),
634 .funcval = 0,
635};
636
637static const unsigned sdmmc0_pins[] = { };
638
639static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
640 {
641 .group = 2,
642 .mask = BIT(2) | BIT(3),
643 },
644};
645
646static const struct sirfsoc_padmux sdmmc2_padmux = {
647 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
648 .muxmask = sdmmc2_muxmask,
6a08a92e 649 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 650 .funcmask = BIT(5),
651 .funcval = BIT(5),
652};
653
654static const unsigned sdmmc2_pins[] = { 66, 67 };
655
656static const struct sirfsoc_muxmask cko0_muxmask[] = {
657 {
658 .group = 2,
659 .mask = BIT(14),
660 },
661};
662
663static const struct sirfsoc_padmux cko0_padmux = {
664 .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
665 .muxmask = cko0_muxmask,
666};
667
668static const unsigned cko0_pins[] = { 78 };
669
670static const struct sirfsoc_muxmask vip_muxmask[] = {
671 {
672 .group = 2,
673 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
674 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
675 BIT(25),
676 },
677};
678
679static const struct sirfsoc_padmux vip_padmux = {
680 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
681 .muxmask = vip_muxmask,
6a08a92e 682 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 683 .funcmask = BIT(0),
684 .funcval = 0,
685};
686
687static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
688
689static const struct sirfsoc_muxmask i2c0_muxmask[] = {
690 {
691 .group = 2,
692 .mask = BIT(26) | BIT(27),
693 },
694};
695
696static const struct sirfsoc_padmux i2c0_padmux = {
697 .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
698 .muxmask = i2c0_muxmask,
699};
700
701static const unsigned i2c0_pins[] = { 90, 91 };
702
703static const struct sirfsoc_muxmask i2c1_muxmask[] = {
704 {
705 .group = 0,
706 .mask = BIT(13) | BIT(15),
707 },
708};
709
710static const struct sirfsoc_padmux i2c1_padmux = {
711 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
712 .muxmask = i2c1_muxmask,
713};
714
715static const unsigned i2c1_pins[] = { 13, 15 };
716
717static const struct sirfsoc_muxmask viprom_muxmask[] = {
718 {
719 .group = 2,
720 .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
721 | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
722 BIT(25),
723 }, {
724 .group = 0,
725 .mask = BIT(12),
726 },
727};
728
729static const struct sirfsoc_padmux viprom_padmux = {
730 .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
731 .muxmask = viprom_muxmask,
6a08a92e 732 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 733 .funcmask = BIT(0),
734 .funcval = BIT(0),
735};
736
737static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89 };
738
739static const struct sirfsoc_muxmask pwm0_muxmask[] = {
740 {
741 .group = 0,
742 .mask = BIT(4),
743 },
744};
745
746static const struct sirfsoc_padmux pwm0_padmux = {
747 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
748 .muxmask = pwm0_muxmask,
6a08a92e 749 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 750 .funcmask = BIT(12),
751 .funcval = 0,
752};
753
754static const unsigned pwm0_pins[] = { 4 };
755
756static const struct sirfsoc_muxmask pwm1_muxmask[] = {
757 {
758 .group = 0,
759 .mask = BIT(5),
760 },
761};
762
763static const struct sirfsoc_padmux pwm1_padmux = {
764 .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
765 .muxmask = pwm1_muxmask,
766};
767
768static const unsigned pwm1_pins[] = { 5 };
769
770static const struct sirfsoc_muxmask pwm2_muxmask[] = {
771 {
772 .group = 0,
773 .mask = BIT(6),
774 },
775};
776
777static const struct sirfsoc_padmux pwm2_padmux = {
778 .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
779 .muxmask = pwm2_muxmask,
780};
781
782static const unsigned pwm2_pins[] = { 6 };
783
784static const struct sirfsoc_muxmask pwm3_muxmask[] = {
785 {
786 .group = 0,
787 .mask = BIT(7),
788 },
789};
790
791static const struct sirfsoc_padmux pwm3_padmux = {
792 .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
793 .muxmask = pwm3_muxmask,
794};
795
796static const unsigned pwm3_pins[] = { 7 };
797
798static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
799 {
800 .group = 0,
801 .mask = BIT(8),
802 },
803};
804
805static const struct sirfsoc_padmux warm_rst_padmux = {
806 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
807 .muxmask = warm_rst_muxmask,
808};
809
810static const unsigned warm_rst_pins[] = { 8 };
811
812static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
813 {
814 .group = 1,
815 .mask = BIT(22),
816 },
817};
818static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
819 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
820 .muxmask = usb0_utmi_drvbus_muxmask,
6a08a92e 821 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 822 .funcmask = BIT(6),
823 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
824};
825
826static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
827
828static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
829 {
830 .group = 1,
831 .mask = BIT(27),
832 },
833};
834
835static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
836 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
837 .muxmask = usb1_utmi_drvbus_muxmask,
6a08a92e 838 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393daa81
RY		 839 .funcmask = BIT(11),
840 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
841};
842
843static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
844
6a08a92e
RW		 845static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
846 .muxmask_counts = 0,
847 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
848 .funcmask = BIT(2),
849 .funcval = BIT(2),
850};
851
852static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
853
854static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
855 .muxmask_counts = 0,
856 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
857 .funcmask = BIT(2),
858 .funcval = 0,
859};
860
861static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
862
393daa81
RY		 863static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
864 {
865 .group = 0,
866 .mask = BIT(9) | BIT(10) | BIT(11),
867 },
868};
869
870static const struct sirfsoc_padmux pulse_count_padmux = {
871 .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
872 .muxmask = pulse_count_muxmask,
873};
874
875static const unsigned pulse_count_pins[] = { 9, 10, 11 };
876
393daa81
RY		 877static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
878 SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
879 SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
880 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
881 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
882 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
fb85f429 883 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
393daa81
RY		 884 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
885 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
886 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
887 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
af614b23
QL		 888 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
889 usp0_uart_nostreamctrl_pins),
8385af02
RY		 890 SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
891 SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
393daa81 892 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
af614b23
QL		 893 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
894 usp1_uart_nostreamctrl_pins),
393daa81 895 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
af614b23
QL		 896 SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
897 usp2_uart_nostreamctrl_pins),
393daa81
RY		 898 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
899 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
900 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
901 SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
902 SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
903 SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
904 SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
905 SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
906 SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
3370dc91
BS		 907 SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
908 SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
393daa81
RY		 909 SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
910 SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
911 SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
912 SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
913 SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
914 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
915 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
916 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
6a08a92e
RW		 917 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
918 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
393daa81
RY		 919 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
920 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
921 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
922 SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
923 SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
924 SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
925 SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
926};
927
393daa81
RY		 928static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
929static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
930static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
931static const char * const lcdromgrp[] = { "lcdromgrp" };
932static const char * const uart0grp[] = { "uart0grp" };
fb85f429 933static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
393daa81
RY		 934static const char * const uart1grp[] = { "uart1grp" };
935static const char * const uart2grp[] = { "uart2grp" };
936static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
937static const char * const usp0grp[] = { "usp0grp" };
af614b23
QL		 938static const char * const usp0_uart_nostreamctrl_grp[] =
939 { "usp0_uart_nostreamctrl_grp" };
8385af02
RY		 940static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
941static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
393daa81 942static const char * const usp1grp[] = { "usp1grp" };
af614b23
QL		 943static const char * const usp1_uart_nostreamctrl_grp[] =
944 { "usp1_uart_nostreamctrl_grp" };
393daa81 945static const char * const usp2grp[] = { "usp2grp" };
af614b23
QL		 946static const char * const usp2_uart_nostreamctrl_grp[] =
947 { "usp2_uart_nostreamctrl_grp" };
393daa81
RY		 948static const char * const i2c0grp[] = { "i2c0grp" };
949static const char * const i2c1grp[] = { "i2c1grp" };
950static const char * const pwm0grp[] = { "pwm0grp" };
951static const char * const pwm1grp[] = { "pwm1grp" };
952static const char * const pwm2grp[] = { "pwm2grp" };
953static const char * const pwm3grp[] = { "pwm3grp" };
954static const char * const vipgrp[] = { "vipgrp" };
955static const char * const vipromgrp[] = { "vipromgrp" };
956static const char * const warm_rstgrp[] = { "warm_rstgrp" };
957static const char * const cko0grp[] = { "cko0grp" };
958static const char * const cko1grp[] = { "cko1grp" };
959static const char * const sdmmc0grp[] = { "sdmmc0grp" };
960static const char * const sdmmc1grp[] = { "sdmmc1grp" };
961static const char * const sdmmc2grp[] = { "sdmmc2grp" };
962static const char * const sdmmc3grp[] = { "sdmmc3grp" };
963static const char * const sdmmc4grp[] = { "sdmmc4grp" };
964static const char * const sdmmc5grp[] = { "sdmmc5grp" };
965static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
966static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
6a08a92e
RW		 967static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
968static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
393daa81
RY		 969static const char * const pulse_countgrp[] = { "pulse_countgrp" };
970static const char * const i2sgrp[] = { "i2sgrp" };
971static const char * const ac97grp[] = { "ac97grp" };
972static const char * const nandgrp[] = { "nandgrp" };
973static const char * const spi0grp[] = { "spi0grp" };
974static const char * const spi1grp[] = { "spi1grp" };
975static const char * const gpsgrp[] = { "gpsgrp" };
976
393daa81
RY		 977static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
978 SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
979 SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
980 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
981 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
982 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
fb85f429 983 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
393daa81
RY		 984 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
985 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
986 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
987 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
af614b23
QL		 988 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
989 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
8385af02
RY		 990 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
991 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
393daa81 992 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
af614b23
QL		 993 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
994 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
393daa81 995 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
af614b23
QL		 996 SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
997 usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
393daa81
RY		 998 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
999 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
1000 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
1001 SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
1002 SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
1003 SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
1004 SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
1005 SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
1006 SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
1007 SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
1008 SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
1009 SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
1010 SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
1011 SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
1012 SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
1013 SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
1014 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
1015 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
1016 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
6a08a92e
RW		 1017 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1018 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
393daa81
RY		 1019 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
1020 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
1021 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
1022 SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
1023 SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
1024 SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
1025 SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
1026};
1027
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BS		 1028struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
1029 (struct pinctrl_pin_desc *)sirfsoc_pads,
1030 ARRAY_SIZE(sirfsoc_pads),
1031 (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
1032 ARRAY_SIZE(sirfsoc_pin_groups),
1033 (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
1034 ARRAY_SIZE(sirfsoc_pmx_functions),
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RY		 1035};
1036
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