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deda8287 VK |
1 | /* |
2 | * Driver header file for the ST Microelectronics SPEAr pinmux | |
3 | * | |
4 | * Copyright (C) 2012 ST Microelectronics | |
da89947b | 5 | * Viresh Kumar <vireshk@kernel.org> |
deda8287 VK |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #ifndef __PINMUX_SPEAR_H__ | |
13 | #define __PINMUX_SPEAR_H__ | |
14 | ||
f4f8e563 | 15 | #include <linux/gpio.h> |
826d6ca8 | 16 | #include <linux/io.h> |
deda8287 VK |
17 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/types.h> | |
19 | ||
20 | struct platform_device; | |
21 | struct device; | |
826d6ca8 | 22 | struct spear_pmx; |
deda8287 VK |
23 | |
24 | /** | |
25 | * struct spear_pmx_mode - SPEAr pmx mode | |
26 | * @name: name of pmx mode | |
27 | * @mode: mode id | |
28 | * @reg: register for configuring this mode | |
29 | * @mask: mask of this mode in reg | |
30 | * @val: val to be configured at reg after doing (val & mask) | |
31 | */ | |
32 | struct spear_pmx_mode { | |
33 | const char *const name; | |
34 | u16 mode; | |
35 | u16 reg; | |
36 | u16 mask; | |
37 | u32 val; | |
38 | }; | |
39 | ||
40 | /** | |
41 | * struct spear_muxreg - SPEAr mux reg configuration | |
42 | * @reg: register offset | |
43 | * @mask: mask bits | |
44 | * @val: val to be written on mask bits | |
45 | */ | |
46 | struct spear_muxreg { | |
47 | u16 reg; | |
48 | u32 mask; | |
49 | u32 val; | |
50 | }; | |
51 | ||
f4f8e563 VK |
52 | struct spear_gpio_pingroup { |
53 | const unsigned *pins; | |
54 | unsigned npins; | |
55 | struct spear_muxreg *muxregs; | |
56 | u8 nmuxregs; | |
57 | }; | |
58 | ||
59 | /* ste: set to enable */ | |
60 | #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \ | |
61 | static struct spear_muxreg __pins##_muxregs[] = { \ | |
62 | { \ | |
63 | .reg = __muxreg, \ | |
64 | .mask = __mask, \ | |
65 | .val = __ste ? __mask : 0, \ | |
66 | }, \ | |
67 | } | |
68 | ||
69 | #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \ | |
70 | static struct spear_muxreg __pins##_muxregs[] = { \ | |
71 | { \ | |
72 | .reg = __muxreg1, \ | |
73 | .mask = __mask, \ | |
74 | .val = __ste1 ? __mask : 0, \ | |
75 | }, { \ | |
76 | .reg = __muxreg2, \ | |
77 | .mask = __mask, \ | |
78 | .val = __ste2 ? __mask : 0, \ | |
79 | }, \ | |
80 | } | |
81 | ||
82 | #define GPIO_PINGROUP(__pins) \ | |
83 | { \ | |
84 | .pins = __pins, \ | |
85 | .npins = ARRAY_SIZE(__pins), \ | |
86 | .muxregs = __pins##_muxregs, \ | |
87 | .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \ | |
88 | } | |
89 | ||
deda8287 VK |
90 | /** |
91 | * struct spear_modemux - SPEAr mode mux configuration | |
92 | * @modes: mode ids supported by this group of muxregs | |
93 | * @nmuxregs: number of muxreg configurations to be done for modes | |
94 | * @muxregs: array of muxreg configurations to be done for modes | |
95 | */ | |
96 | struct spear_modemux { | |
97 | u16 modes; | |
98 | u8 nmuxregs; | |
99 | struct spear_muxreg *muxregs; | |
100 | }; | |
101 | ||
102 | /** | |
103 | * struct spear_pingroup - SPEAr pin group configurations | |
104 | * @name: name of pin group | |
105 | * @pins: array containing pin numbers | |
106 | * @npins: size of pins array | |
107 | * @modemuxs: array of modemux configurations for this pin group | |
108 | * @nmodemuxs: size of array modemuxs | |
109 | * | |
110 | * A representation of a group of pins in the SPEAr pin controller. Each group | |
111 | * allows some parameter or parameters to be configured. | |
112 | */ | |
113 | struct spear_pingroup { | |
114 | const char *name; | |
115 | const unsigned *pins; | |
116 | unsigned npins; | |
117 | struct spear_modemux *modemuxs; | |
118 | unsigned nmodemuxs; | |
119 | }; | |
120 | ||
121 | /** | |
122 | * struct spear_function - SPEAr pinctrl mux function | |
123 | * @name: The name of the function, exported to pinctrl core. | |
124 | * @groups: An array of pin groups that may select this function. | |
125 | * @ngroups: The number of entries in @groups. | |
126 | */ | |
127 | struct spear_function { | |
128 | const char *name; | |
129 | const char *const *groups; | |
130 | unsigned ngroups; | |
131 | }; | |
132 | ||
133 | /** | |
134 | * struct spear_pinctrl_machdata - SPEAr pin controller machine driver | |
135 | * configuration | |
136 | * @pins: An array describing all pins the pin controller affects. | |
137 | * All pins which are also GPIOs must be listed first within the *array, | |
138 | * and be numbered identically to the GPIO controller's *numbering. | |
139 | * @npins: The numbmer of entries in @pins. | |
140 | * @functions: An array describing all mux functions the SoC supports. | |
141 | * @nfunctions: The numbmer of entries in @functions. | |
142 | * @groups: An array describing all pin groups the pin SoC supports. | |
143 | * @ngroups: The numbmer of entries in @groups. | |
f4f8e563 VK |
144 | * @gpio_pingroups: gpio pingroups |
145 | * @ngpio_pingroups: gpio pingroups count | |
deda8287 VK |
146 | * |
147 | * @modes_supported: Does SoC support modes | |
148 | * @mode: mode configured from probe | |
149 | * @pmx_modes: array of modes supported by SoC | |
150 | * @npmx_modes: number of entries in pmx_modes. | |
151 | */ | |
152 | struct spear_pinctrl_machdata { | |
153 | const struct pinctrl_pin_desc *pins; | |
154 | unsigned npins; | |
155 | struct spear_function **functions; | |
156 | unsigned nfunctions; | |
157 | struct spear_pingroup **groups; | |
158 | unsigned ngroups; | |
f4f8e563 | 159 | struct spear_gpio_pingroup *gpio_pingroups; |
826d6ca8 SH |
160 | void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset, |
161 | bool enable); | |
f4f8e563 | 162 | unsigned ngpio_pingroups; |
deda8287 VK |
163 | |
164 | bool modes_supported; | |
165 | u16 mode; | |
166 | struct spear_pmx_mode **pmx_modes; | |
167 | unsigned npmx_modes; | |
168 | }; | |
169 | ||
170 | /** | |
171 | * struct spear_pmx - SPEAr pinctrl mux | |
172 | * @dev: pointer to struct dev of platform_device registered | |
173 | * @pctl: pointer to struct pinctrl_dev | |
174 | * @machdata: pointer to SoC or machine specific structure | |
175 | * @vbase: virtual base address of pinmux controller | |
176 | */ | |
177 | struct spear_pmx { | |
178 | struct device *dev; | |
179 | struct pinctrl_dev *pctl; | |
180 | struct spear_pinctrl_machdata *machdata; | |
181 | void __iomem *vbase; | |
182 | }; | |
183 | ||
184 | /* exported routines */ | |
826d6ca8 SH |
185 | static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) |
186 | { | |
187 | return readl_relaxed(pmx->vbase + reg); | |
188 | } | |
189 | ||
190 | static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) | |
191 | { | |
192 | writel_relaxed(val, pmx->vbase + reg); | |
193 | } | |
194 | ||
150632b0 GKH |
195 | void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); |
196 | void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup, | |
197 | unsigned count, u16 reg); | |
198 | int spear_pinctrl_probe(struct platform_device *pdev, | |
199 | struct spear_pinctrl_machdata *machdata); | |
f90f54b3 | 200 | int spear_pinctrl_remove(struct platform_device *pdev); |
d1e77afe VK |
201 | |
202 | #define SPEAR_PIN_0_TO_101 \ | |
203 | PINCTRL_PIN(0, "PLGPIO0"), \ | |
204 | PINCTRL_PIN(1, "PLGPIO1"), \ | |
205 | PINCTRL_PIN(2, "PLGPIO2"), \ | |
206 | PINCTRL_PIN(3, "PLGPIO3"), \ | |
207 | PINCTRL_PIN(4, "PLGPIO4"), \ | |
208 | PINCTRL_PIN(5, "PLGPIO5"), \ | |
209 | PINCTRL_PIN(6, "PLGPIO6"), \ | |
210 | PINCTRL_PIN(7, "PLGPIO7"), \ | |
211 | PINCTRL_PIN(8, "PLGPIO8"), \ | |
212 | PINCTRL_PIN(9, "PLGPIO9"), \ | |
213 | PINCTRL_PIN(10, "PLGPIO10"), \ | |
214 | PINCTRL_PIN(11, "PLGPIO11"), \ | |
215 | PINCTRL_PIN(12, "PLGPIO12"), \ | |
216 | PINCTRL_PIN(13, "PLGPIO13"), \ | |
217 | PINCTRL_PIN(14, "PLGPIO14"), \ | |
218 | PINCTRL_PIN(15, "PLGPIO15"), \ | |
219 | PINCTRL_PIN(16, "PLGPIO16"), \ | |
220 | PINCTRL_PIN(17, "PLGPIO17"), \ | |
221 | PINCTRL_PIN(18, "PLGPIO18"), \ | |
222 | PINCTRL_PIN(19, "PLGPIO19"), \ | |
223 | PINCTRL_PIN(20, "PLGPIO20"), \ | |
224 | PINCTRL_PIN(21, "PLGPIO21"), \ | |
225 | PINCTRL_PIN(22, "PLGPIO22"), \ | |
226 | PINCTRL_PIN(23, "PLGPIO23"), \ | |
227 | PINCTRL_PIN(24, "PLGPIO24"), \ | |
228 | PINCTRL_PIN(25, "PLGPIO25"), \ | |
229 | PINCTRL_PIN(26, "PLGPIO26"), \ | |
230 | PINCTRL_PIN(27, "PLGPIO27"), \ | |
231 | PINCTRL_PIN(28, "PLGPIO28"), \ | |
232 | PINCTRL_PIN(29, "PLGPIO29"), \ | |
233 | PINCTRL_PIN(30, "PLGPIO30"), \ | |
234 | PINCTRL_PIN(31, "PLGPIO31"), \ | |
235 | PINCTRL_PIN(32, "PLGPIO32"), \ | |
236 | PINCTRL_PIN(33, "PLGPIO33"), \ | |
237 | PINCTRL_PIN(34, "PLGPIO34"), \ | |
238 | PINCTRL_PIN(35, "PLGPIO35"), \ | |
239 | PINCTRL_PIN(36, "PLGPIO36"), \ | |
240 | PINCTRL_PIN(37, "PLGPIO37"), \ | |
241 | PINCTRL_PIN(38, "PLGPIO38"), \ | |
242 | PINCTRL_PIN(39, "PLGPIO39"), \ | |
243 | PINCTRL_PIN(40, "PLGPIO40"), \ | |
244 | PINCTRL_PIN(41, "PLGPIO41"), \ | |
245 | PINCTRL_PIN(42, "PLGPIO42"), \ | |
246 | PINCTRL_PIN(43, "PLGPIO43"), \ | |
247 | PINCTRL_PIN(44, "PLGPIO44"), \ | |
248 | PINCTRL_PIN(45, "PLGPIO45"), \ | |
249 | PINCTRL_PIN(46, "PLGPIO46"), \ | |
250 | PINCTRL_PIN(47, "PLGPIO47"), \ | |
251 | PINCTRL_PIN(48, "PLGPIO48"), \ | |
252 | PINCTRL_PIN(49, "PLGPIO49"), \ | |
253 | PINCTRL_PIN(50, "PLGPIO50"), \ | |
254 | PINCTRL_PIN(51, "PLGPIO51"), \ | |
255 | PINCTRL_PIN(52, "PLGPIO52"), \ | |
256 | PINCTRL_PIN(53, "PLGPIO53"), \ | |
257 | PINCTRL_PIN(54, "PLGPIO54"), \ | |
258 | PINCTRL_PIN(55, "PLGPIO55"), \ | |
259 | PINCTRL_PIN(56, "PLGPIO56"), \ | |
260 | PINCTRL_PIN(57, "PLGPIO57"), \ | |
261 | PINCTRL_PIN(58, "PLGPIO58"), \ | |
262 | PINCTRL_PIN(59, "PLGPIO59"), \ | |
263 | PINCTRL_PIN(60, "PLGPIO60"), \ | |
264 | PINCTRL_PIN(61, "PLGPIO61"), \ | |
265 | PINCTRL_PIN(62, "PLGPIO62"), \ | |
266 | PINCTRL_PIN(63, "PLGPIO63"), \ | |
267 | PINCTRL_PIN(64, "PLGPIO64"), \ | |
268 | PINCTRL_PIN(65, "PLGPIO65"), \ | |
269 | PINCTRL_PIN(66, "PLGPIO66"), \ | |
270 | PINCTRL_PIN(67, "PLGPIO67"), \ | |
271 | PINCTRL_PIN(68, "PLGPIO68"), \ | |
272 | PINCTRL_PIN(69, "PLGPIO69"), \ | |
273 | PINCTRL_PIN(70, "PLGPIO70"), \ | |
274 | PINCTRL_PIN(71, "PLGPIO71"), \ | |
275 | PINCTRL_PIN(72, "PLGPIO72"), \ | |
276 | PINCTRL_PIN(73, "PLGPIO73"), \ | |
277 | PINCTRL_PIN(74, "PLGPIO74"), \ | |
278 | PINCTRL_PIN(75, "PLGPIO75"), \ | |
279 | PINCTRL_PIN(76, "PLGPIO76"), \ | |
280 | PINCTRL_PIN(77, "PLGPIO77"), \ | |
281 | PINCTRL_PIN(78, "PLGPIO78"), \ | |
282 | PINCTRL_PIN(79, "PLGPIO79"), \ | |
283 | PINCTRL_PIN(80, "PLGPIO80"), \ | |
284 | PINCTRL_PIN(81, "PLGPIO81"), \ | |
285 | PINCTRL_PIN(82, "PLGPIO82"), \ | |
286 | PINCTRL_PIN(83, "PLGPIO83"), \ | |
287 | PINCTRL_PIN(84, "PLGPIO84"), \ | |
288 | PINCTRL_PIN(85, "PLGPIO85"), \ | |
289 | PINCTRL_PIN(86, "PLGPIO86"), \ | |
290 | PINCTRL_PIN(87, "PLGPIO87"), \ | |
291 | PINCTRL_PIN(88, "PLGPIO88"), \ | |
292 | PINCTRL_PIN(89, "PLGPIO89"), \ | |
293 | PINCTRL_PIN(90, "PLGPIO90"), \ | |
294 | PINCTRL_PIN(91, "PLGPIO91"), \ | |
295 | PINCTRL_PIN(92, "PLGPIO92"), \ | |
296 | PINCTRL_PIN(93, "PLGPIO93"), \ | |
297 | PINCTRL_PIN(94, "PLGPIO94"), \ | |
298 | PINCTRL_PIN(95, "PLGPIO95"), \ | |
299 | PINCTRL_PIN(96, "PLGPIO96"), \ | |
300 | PINCTRL_PIN(97, "PLGPIO97"), \ | |
301 | PINCTRL_PIN(98, "PLGPIO98"), \ | |
302 | PINCTRL_PIN(99, "PLGPIO99"), \ | |
303 | PINCTRL_PIN(100, "PLGPIO100"), \ | |
304 | PINCTRL_PIN(101, "PLGPIO101") | |
305 | ||
85ed41a7 VK |
306 | #define SPEAR_PIN_102_TO_245 \ |
307 | PINCTRL_PIN(102, "PLGPIO102"), \ | |
308 | PINCTRL_PIN(103, "PLGPIO103"), \ | |
309 | PINCTRL_PIN(104, "PLGPIO104"), \ | |
310 | PINCTRL_PIN(105, "PLGPIO105"), \ | |
311 | PINCTRL_PIN(106, "PLGPIO106"), \ | |
312 | PINCTRL_PIN(107, "PLGPIO107"), \ | |
313 | PINCTRL_PIN(108, "PLGPIO108"), \ | |
314 | PINCTRL_PIN(109, "PLGPIO109"), \ | |
315 | PINCTRL_PIN(110, "PLGPIO110"), \ | |
316 | PINCTRL_PIN(111, "PLGPIO111"), \ | |
317 | PINCTRL_PIN(112, "PLGPIO112"), \ | |
318 | PINCTRL_PIN(113, "PLGPIO113"), \ | |
319 | PINCTRL_PIN(114, "PLGPIO114"), \ | |
320 | PINCTRL_PIN(115, "PLGPIO115"), \ | |
321 | PINCTRL_PIN(116, "PLGPIO116"), \ | |
322 | PINCTRL_PIN(117, "PLGPIO117"), \ | |
323 | PINCTRL_PIN(118, "PLGPIO118"), \ | |
324 | PINCTRL_PIN(119, "PLGPIO119"), \ | |
325 | PINCTRL_PIN(120, "PLGPIO120"), \ | |
326 | PINCTRL_PIN(121, "PLGPIO121"), \ | |
327 | PINCTRL_PIN(122, "PLGPIO122"), \ | |
328 | PINCTRL_PIN(123, "PLGPIO123"), \ | |
329 | PINCTRL_PIN(124, "PLGPIO124"), \ | |
330 | PINCTRL_PIN(125, "PLGPIO125"), \ | |
331 | PINCTRL_PIN(126, "PLGPIO126"), \ | |
332 | PINCTRL_PIN(127, "PLGPIO127"), \ | |
333 | PINCTRL_PIN(128, "PLGPIO128"), \ | |
334 | PINCTRL_PIN(129, "PLGPIO129"), \ | |
335 | PINCTRL_PIN(130, "PLGPIO130"), \ | |
336 | PINCTRL_PIN(131, "PLGPIO131"), \ | |
337 | PINCTRL_PIN(132, "PLGPIO132"), \ | |
338 | PINCTRL_PIN(133, "PLGPIO133"), \ | |
339 | PINCTRL_PIN(134, "PLGPIO134"), \ | |
340 | PINCTRL_PIN(135, "PLGPIO135"), \ | |
341 | PINCTRL_PIN(136, "PLGPIO136"), \ | |
342 | PINCTRL_PIN(137, "PLGPIO137"), \ | |
343 | PINCTRL_PIN(138, "PLGPIO138"), \ | |
344 | PINCTRL_PIN(139, "PLGPIO139"), \ | |
345 | PINCTRL_PIN(140, "PLGPIO140"), \ | |
346 | PINCTRL_PIN(141, "PLGPIO141"), \ | |
347 | PINCTRL_PIN(142, "PLGPIO142"), \ | |
348 | PINCTRL_PIN(143, "PLGPIO143"), \ | |
349 | PINCTRL_PIN(144, "PLGPIO144"), \ | |
350 | PINCTRL_PIN(145, "PLGPIO145"), \ | |
351 | PINCTRL_PIN(146, "PLGPIO146"), \ | |
352 | PINCTRL_PIN(147, "PLGPIO147"), \ | |
353 | PINCTRL_PIN(148, "PLGPIO148"), \ | |
354 | PINCTRL_PIN(149, "PLGPIO149"), \ | |
355 | PINCTRL_PIN(150, "PLGPIO150"), \ | |
356 | PINCTRL_PIN(151, "PLGPIO151"), \ | |
357 | PINCTRL_PIN(152, "PLGPIO152"), \ | |
358 | PINCTRL_PIN(153, "PLGPIO153"), \ | |
359 | PINCTRL_PIN(154, "PLGPIO154"), \ | |
360 | PINCTRL_PIN(155, "PLGPIO155"), \ | |
361 | PINCTRL_PIN(156, "PLGPIO156"), \ | |
362 | PINCTRL_PIN(157, "PLGPIO157"), \ | |
363 | PINCTRL_PIN(158, "PLGPIO158"), \ | |
364 | PINCTRL_PIN(159, "PLGPIO159"), \ | |
365 | PINCTRL_PIN(160, "PLGPIO160"), \ | |
366 | PINCTRL_PIN(161, "PLGPIO161"), \ | |
367 | PINCTRL_PIN(162, "PLGPIO162"), \ | |
368 | PINCTRL_PIN(163, "PLGPIO163"), \ | |
369 | PINCTRL_PIN(164, "PLGPIO164"), \ | |
370 | PINCTRL_PIN(165, "PLGPIO165"), \ | |
371 | PINCTRL_PIN(166, "PLGPIO166"), \ | |
372 | PINCTRL_PIN(167, "PLGPIO167"), \ | |
373 | PINCTRL_PIN(168, "PLGPIO168"), \ | |
374 | PINCTRL_PIN(169, "PLGPIO169"), \ | |
375 | PINCTRL_PIN(170, "PLGPIO170"), \ | |
376 | PINCTRL_PIN(171, "PLGPIO171"), \ | |
377 | PINCTRL_PIN(172, "PLGPIO172"), \ | |
378 | PINCTRL_PIN(173, "PLGPIO173"), \ | |
379 | PINCTRL_PIN(174, "PLGPIO174"), \ | |
380 | PINCTRL_PIN(175, "PLGPIO175"), \ | |
381 | PINCTRL_PIN(176, "PLGPIO176"), \ | |
382 | PINCTRL_PIN(177, "PLGPIO177"), \ | |
383 | PINCTRL_PIN(178, "PLGPIO178"), \ | |
384 | PINCTRL_PIN(179, "PLGPIO179"), \ | |
385 | PINCTRL_PIN(180, "PLGPIO180"), \ | |
386 | PINCTRL_PIN(181, "PLGPIO181"), \ | |
387 | PINCTRL_PIN(182, "PLGPIO182"), \ | |
388 | PINCTRL_PIN(183, "PLGPIO183"), \ | |
389 | PINCTRL_PIN(184, "PLGPIO184"), \ | |
390 | PINCTRL_PIN(185, "PLGPIO185"), \ | |
391 | PINCTRL_PIN(186, "PLGPIO186"), \ | |
392 | PINCTRL_PIN(187, "PLGPIO187"), \ | |
393 | PINCTRL_PIN(188, "PLGPIO188"), \ | |
394 | PINCTRL_PIN(189, "PLGPIO189"), \ | |
395 | PINCTRL_PIN(190, "PLGPIO190"), \ | |
396 | PINCTRL_PIN(191, "PLGPIO191"), \ | |
397 | PINCTRL_PIN(192, "PLGPIO192"), \ | |
398 | PINCTRL_PIN(193, "PLGPIO193"), \ | |
399 | PINCTRL_PIN(194, "PLGPIO194"), \ | |
400 | PINCTRL_PIN(195, "PLGPIO195"), \ | |
401 | PINCTRL_PIN(196, "PLGPIO196"), \ | |
402 | PINCTRL_PIN(197, "PLGPIO197"), \ | |
403 | PINCTRL_PIN(198, "PLGPIO198"), \ | |
404 | PINCTRL_PIN(199, "PLGPIO199"), \ | |
405 | PINCTRL_PIN(200, "PLGPIO200"), \ | |
406 | PINCTRL_PIN(201, "PLGPIO201"), \ | |
407 | PINCTRL_PIN(202, "PLGPIO202"), \ | |
408 | PINCTRL_PIN(203, "PLGPIO203"), \ | |
409 | PINCTRL_PIN(204, "PLGPIO204"), \ | |
410 | PINCTRL_PIN(205, "PLGPIO205"), \ | |
411 | PINCTRL_PIN(206, "PLGPIO206"), \ | |
412 | PINCTRL_PIN(207, "PLGPIO207"), \ | |
413 | PINCTRL_PIN(208, "PLGPIO208"), \ | |
414 | PINCTRL_PIN(209, "PLGPIO209"), \ | |
415 | PINCTRL_PIN(210, "PLGPIO210"), \ | |
416 | PINCTRL_PIN(211, "PLGPIO211"), \ | |
417 | PINCTRL_PIN(212, "PLGPIO212"), \ | |
418 | PINCTRL_PIN(213, "PLGPIO213"), \ | |
419 | PINCTRL_PIN(214, "PLGPIO214"), \ | |
420 | PINCTRL_PIN(215, "PLGPIO215"), \ | |
421 | PINCTRL_PIN(216, "PLGPIO216"), \ | |
422 | PINCTRL_PIN(217, "PLGPIO217"), \ | |
423 | PINCTRL_PIN(218, "PLGPIO218"), \ | |
424 | PINCTRL_PIN(219, "PLGPIO219"), \ | |
425 | PINCTRL_PIN(220, "PLGPIO220"), \ | |
426 | PINCTRL_PIN(221, "PLGPIO221"), \ | |
427 | PINCTRL_PIN(222, "PLGPIO222"), \ | |
428 | PINCTRL_PIN(223, "PLGPIO223"), \ | |
429 | PINCTRL_PIN(224, "PLGPIO224"), \ | |
430 | PINCTRL_PIN(225, "PLGPIO225"), \ | |
431 | PINCTRL_PIN(226, "PLGPIO226"), \ | |
432 | PINCTRL_PIN(227, "PLGPIO227"), \ | |
433 | PINCTRL_PIN(228, "PLGPIO228"), \ | |
434 | PINCTRL_PIN(229, "PLGPIO229"), \ | |
435 | PINCTRL_PIN(230, "PLGPIO230"), \ | |
436 | PINCTRL_PIN(231, "PLGPIO231"), \ | |
437 | PINCTRL_PIN(232, "PLGPIO232"), \ | |
438 | PINCTRL_PIN(233, "PLGPIO233"), \ | |
439 | PINCTRL_PIN(234, "PLGPIO234"), \ | |
440 | PINCTRL_PIN(235, "PLGPIO235"), \ | |
441 | PINCTRL_PIN(236, "PLGPIO236"), \ | |
442 | PINCTRL_PIN(237, "PLGPIO237"), \ | |
443 | PINCTRL_PIN(238, "PLGPIO238"), \ | |
444 | PINCTRL_PIN(239, "PLGPIO239"), \ | |
445 | PINCTRL_PIN(240, "PLGPIO240"), \ | |
446 | PINCTRL_PIN(241, "PLGPIO241"), \ | |
447 | PINCTRL_PIN(242, "PLGPIO242"), \ | |
448 | PINCTRL_PIN(243, "PLGPIO243"), \ | |
449 | PINCTRL_PIN(244, "PLGPIO244"), \ | |
450 | PINCTRL_PIN(245, "PLGPIO245") | |
451 | ||
deda8287 | 452 | #endif /* __PINMUX_SPEAR_H__ */ |