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85ed41a7 VK |
1 | /* |
2 | * Driver for the ST Microelectronics SPEAr1340 pinmux | |
3 | * | |
4 | * Copyright (C) 2012 ST Microelectronics | |
da89947b | 5 | * Viresh Kumar <vireshk@kernel.org> |
85ed41a7 VK |
6 | * |
7 | * This file is licensed under the terms of the GNU General Public | |
8 | * License version 2. This program is licensed "as is" without any | |
9 | * warranty of any kind, whether express or implied. | |
10 | */ | |
11 | ||
12 | #include <linux/err.h> | |
13 | #include <linux/init.h> | |
85ed41a7 VK |
14 | #include <linux/of_device.h> |
15 | #include <linux/platform_device.h> | |
16 | #include "pinctrl-spear.h" | |
17 | ||
18 | #define DRIVER_NAME "spear1340-pinmux" | |
19 | ||
20 | /* pins */ | |
21 | static const struct pinctrl_pin_desc spear1340_pins[] = { | |
22 | SPEAR_PIN_0_TO_101, | |
23 | SPEAR_PIN_102_TO_245, | |
24 | PINCTRL_PIN(246, "PLGPIO246"), | |
25 | PINCTRL_PIN(247, "PLGPIO247"), | |
26 | PINCTRL_PIN(248, "PLGPIO248"), | |
27 | PINCTRL_PIN(249, "PLGPIO249"), | |
28 | PINCTRL_PIN(250, "PLGPIO250"), | |
29 | PINCTRL_PIN(251, "PLGPIO251"), | |
30 | }; | |
31 | ||
32 | /* In SPEAr1340 there are two levels of pad muxing */ | |
33 | /* - pads as gpio OR peripherals */ | |
34 | #define PAD_FUNCTION_EN_1 0x668 | |
35 | #define PAD_FUNCTION_EN_2 0x66C | |
36 | #define PAD_FUNCTION_EN_3 0x670 | |
37 | #define PAD_FUNCTION_EN_4 0x674 | |
38 | #define PAD_FUNCTION_EN_5 0x690 | |
39 | #define PAD_FUNCTION_EN_6 0x694 | |
40 | #define PAD_FUNCTION_EN_7 0x698 | |
41 | #define PAD_FUNCTION_EN_8 0x69C | |
42 | ||
43 | /* - If peripherals, then primary OR alternate peripheral */ | |
44 | #define PAD_SHARED_IP_EN_1 0x6A0 | |
45 | #define PAD_SHARED_IP_EN_2 0x6A4 | |
46 | ||
47 | /* | |
48 | * Macro's for first level of pmx - pads as gpio OR peripherals. There are 8 | |
49 | * registers with 32 bits each for handling gpio pads, register 8 has only 26 | |
50 | * relevant bits. | |
51 | */ | |
52 | /* macro's for making pads as gpio's */ | |
53 | #define PADS_AS_GPIO_REG0_MASK 0xFFFFFFFE | |
54 | #define PADS_AS_GPIO_REGS_MASK 0xFFFFFFFF | |
55 | #define PADS_AS_GPIO_REG7_MASK 0x07FFFFFF | |
56 | ||
57 | /* macro's for making pads as peripherals */ | |
58 | #define FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK 0x00000FFE | |
59 | #define UART0_ENH_AND_GPT_REG0_MASK 0x0003F000 | |
60 | #define PWM1_AND_KBD_COL5_REG0_MASK 0x00040000 | |
61 | #define I2C1_REG0_MASK 0x01080000 | |
62 | #define SPDIF_IN_REG0_MASK 0x00100000 | |
63 | #define PWM2_AND_GPT0_TMR0_CPT_REG0_MASK 0x00400000 | |
64 | #define PWM3_AND_GPT0_TMR1_CLK_REG0_MASK 0x00800000 | |
65 | #define PWM0_AND_SSP0_CS1_REG0_MASK 0x02000000 | |
66 | #define VIP_AND_CAM3_REG0_MASK 0xFC200000 | |
67 | #define VIP_AND_CAM3_REG1_MASK 0x0000000F | |
68 | #define VIP_REG1_MASK 0x00001EF0 | |
69 | #define VIP_AND_CAM2_REG1_MASK 0x007FE100 | |
70 | #define VIP_AND_CAM1_REG1_MASK 0xFF800000 | |
71 | #define VIP_AND_CAM1_REG2_MASK 0x00000003 | |
72 | #define VIP_AND_CAM0_REG2_MASK 0x00001FFC | |
73 | #define SMI_REG2_MASK 0x0021E000 | |
74 | #define SSP0_REG2_MASK 0x001E0000 | |
75 | #define TS_AND_SSP0_CS2_REG2_MASK 0x00400000 | |
76 | #define UART0_REG2_MASK 0x01800000 | |
77 | #define UART1_REG2_MASK 0x06000000 | |
78 | #define I2S_IN_REG2_MASK 0xF8000000 | |
79 | #define DEVS_GRP_AND_MIPHY_DBG_REG3_MASK 0x000001FE | |
80 | #define I2S_OUT_REG3_MASK 0x000001EF | |
81 | #define I2S_IN_REG3_MASK 0x00000010 | |
82 | #define GMAC_REG3_MASK 0xFFFFFE00 | |
83 | #define GMAC_REG4_MASK 0x0000001F | |
84 | #define DEVS_GRP_AND_MIPHY_DBG_REG4_MASK 0x7FFFFF20 | |
85 | #define SSP0_CS3_REG4_MASK 0x00000020 | |
86 | #define I2C0_REG4_MASK 0x000000C0 | |
87 | #define CEC0_REG4_MASK 0x00000100 | |
88 | #define CEC1_REG4_MASK 0x00000200 | |
89 | #define SPDIF_OUT_REG4_MASK 0x00000400 | |
90 | #define CLCD_REG4_MASK 0x7FFFF800 | |
91 | #define CLCD_AND_ARM_TRACE_REG4_MASK 0x80000000 | |
92 | #define CLCD_AND_ARM_TRACE_REG5_MASK 0xFFFFFFFF | |
93 | #define CLCD_AND_ARM_TRACE_REG6_MASK 0x00000001 | |
94 | #define FSMC_PNOR_AND_MCIF_REG6_MASK 0x073FFFFE | |
95 | #define MCIF_REG6_MASK 0xF8C00000 | |
96 | #define MCIF_REG7_MASK 0x000043FF | |
97 | #define FSMC_8BIT_REG7_MASK 0x07FFBC00 | |
98 | ||
99 | /* other registers */ | |
100 | #define PERIP_CFG 0x42C | |
101 | /* PERIP_CFG register masks */ | |
102 | #define SSP_CS_CTL_HW 0 | |
103 | #define SSP_CS_CTL_SW 1 | |
104 | #define SSP_CS_CTL_MASK 1 | |
105 | #define SSP_CS_CTL_SHIFT 21 | |
106 | #define SSP_CS_VAL_MASK 1 | |
107 | #define SSP_CS_VAL_SHIFT 20 | |
108 | #define SSP_CS_SEL_CS0 0 | |
109 | #define SSP_CS_SEL_CS1 1 | |
110 | #define SSP_CS_SEL_CS2 2 | |
111 | #define SSP_CS_SEL_MASK 3 | |
112 | #define SSP_CS_SEL_SHIFT 18 | |
113 | ||
114 | #define I2S_CHNL_2_0 (0) | |
115 | #define I2S_CHNL_3_1 (1) | |
116 | #define I2S_CHNL_5_1 (2) | |
117 | #define I2S_CHNL_7_1 (3) | |
118 | #define I2S_CHNL_PLAY_SHIFT (4) | |
119 | #define I2S_CHNL_PLAY_MASK (3 << 4) | |
120 | #define I2S_CHNL_REC_SHIFT (6) | |
121 | #define I2S_CHNL_REC_MASK (3 << 6) | |
122 | ||
123 | #define SPDIF_OUT_ENB_MASK (1 << 2) | |
124 | #define SPDIF_OUT_ENB_SHIFT 2 | |
125 | ||
126 | #define MCIF_SEL_SD 1 | |
127 | #define MCIF_SEL_CF 2 | |
128 | #define MCIF_SEL_XD 3 | |
129 | #define MCIF_SEL_MASK 3 | |
130 | #define MCIF_SEL_SHIFT 0 | |
131 | ||
132 | #define GMAC_CLK_CFG 0x248 | |
133 | #define GMAC_PHY_IF_GMII_VAL (0 << 3) | |
134 | #define GMAC_PHY_IF_RGMII_VAL (1 << 3) | |
135 | #define GMAC_PHY_IF_SGMII_VAL (2 << 3) | |
136 | #define GMAC_PHY_IF_RMII_VAL (4 << 3) | |
137 | #define GMAC_PHY_IF_SEL_MASK (7 << 3) | |
138 | #define GMAC_PHY_INPUT_ENB_VAL 0 | |
139 | #define GMAC_PHY_SYNT_ENB_VAL 1 | |
140 | #define GMAC_PHY_CLK_MASK 1 | |
141 | #define GMAC_PHY_CLK_SHIFT 2 | |
142 | #define GMAC_PHY_125M_PAD_VAL 0 | |
143 | #define GMAC_PHY_PLL2_VAL 1 | |
144 | #define GMAC_PHY_OSC3_VAL 2 | |
145 | #define GMAC_PHY_INPUT_CLK_MASK 3 | |
146 | #define GMAC_PHY_INPUT_CLK_SHIFT 0 | |
147 | ||
148 | #define PCIE_SATA_CFG 0x424 | |
149 | /* PCIE CFG MASks */ | |
150 | #define PCIE_CFG_DEVICE_PRESENT (1 << 11) | |
151 | #define PCIE_CFG_POWERUP_RESET (1 << 10) | |
152 | #define PCIE_CFG_CORE_CLK_EN (1 << 9) | |
153 | #define PCIE_CFG_AUX_CLK_EN (1 << 8) | |
154 | #define SATA_CFG_TX_CLK_EN (1 << 4) | |
155 | #define SATA_CFG_RX_CLK_EN (1 << 3) | |
156 | #define SATA_CFG_POWERUP_RESET (1 << 2) | |
157 | #define SATA_CFG_PM_CLK_EN (1 << 1) | |
158 | #define PCIE_SATA_SEL_PCIE (0) | |
159 | #define PCIE_SATA_SEL_SATA (1) | |
160 | #define SATA_PCIE_CFG_MASK 0xF1F | |
161 | #define PCIE_CFG_VAL (PCIE_SATA_SEL_PCIE | PCIE_CFG_AUX_CLK_EN | \ | |
162 | PCIE_CFG_CORE_CLK_EN | PCIE_CFG_POWERUP_RESET |\ | |
163 | PCIE_CFG_DEVICE_PRESENT) | |
164 | #define SATA_CFG_VAL (PCIE_SATA_SEL_SATA | SATA_CFG_PM_CLK_EN | \ | |
165 | SATA_CFG_POWERUP_RESET | SATA_CFG_RX_CLK_EN | \ | |
166 | SATA_CFG_TX_CLK_EN) | |
167 | ||
168 | /* Macro's for second level of pmx - pads as primary OR alternate peripheral */ | |
169 | /* Write 0 to enable FSMC_16_BIT */ | |
170 | #define KBD_ROW_COL_MASK (1 << 0) | |
171 | ||
172 | /* Write 0 to enable UART0_ENH */ | |
173 | #define GPT_MASK (1 << 1) /* Only clk & cpt */ | |
174 | ||
175 | /* Write 0 to enable PWM1 */ | |
176 | #define KBD_COL5_MASK (1 << 2) | |
177 | ||
178 | /* Write 0 to enable PWM2 */ | |
179 | #define GPT0_TMR0_CPT_MASK (1 << 3) /* Only clk & cpt */ | |
180 | ||
181 | /* Write 0 to enable PWM3 */ | |
182 | #define GPT0_TMR1_CLK_MASK (1 << 4) /* Only clk & cpt */ | |
183 | ||
184 | /* Write 0 to enable PWM0 */ | |
185 | #define SSP0_CS1_MASK (1 << 5) | |
186 | ||
187 | /* Write 0 to enable VIP */ | |
188 | #define CAM3_MASK (1 << 6) | |
189 | ||
190 | /* Write 0 to enable VIP */ | |
191 | #define CAM2_MASK (1 << 7) | |
192 | ||
193 | /* Write 0 to enable VIP */ | |
194 | #define CAM1_MASK (1 << 8) | |
195 | ||
196 | /* Write 0 to enable VIP */ | |
197 | #define CAM0_MASK (1 << 9) | |
198 | ||
199 | /* Write 0 to enable TS */ | |
200 | #define SSP0_CS2_MASK (1 << 10) | |
201 | ||
202 | /* Write 0 to enable FSMC PNOR */ | |
203 | #define MCIF_MASK (1 << 11) | |
204 | ||
205 | /* Write 0 to enable CLCD */ | |
206 | #define ARM_TRACE_MASK (1 << 12) | |
207 | ||
208 | /* Write 0 to enable I2S, SSP0_CS2, CEC0, 1, SPDIF out, CLCD */ | |
209 | #define MIPHY_DBG_MASK (1 << 13) | |
210 | ||
211 | /* | |
212 | * Pad multiplexing for making all pads as gpio's. This is done to override the | |
213 | * values passed from bootloader and start from scratch. | |
214 | */ | |
35d14806 | 215 | static const unsigned pads_as_gpio_pins[] = { 12, 88, 89, 251 }; |
85ed41a7 VK |
216 | static struct spear_muxreg pads_as_gpio_muxreg[] = { |
217 | { | |
218 | .reg = PAD_FUNCTION_EN_1, | |
219 | .mask = PADS_AS_GPIO_REG0_MASK, | |
220 | .val = 0x0, | |
221 | }, { | |
222 | .reg = PAD_FUNCTION_EN_2, | |
223 | .mask = PADS_AS_GPIO_REGS_MASK, | |
224 | .val = 0x0, | |
225 | }, { | |
226 | .reg = PAD_FUNCTION_EN_3, | |
227 | .mask = PADS_AS_GPIO_REGS_MASK, | |
228 | .val = 0x0, | |
229 | }, { | |
230 | .reg = PAD_FUNCTION_EN_4, | |
231 | .mask = PADS_AS_GPIO_REGS_MASK, | |
232 | .val = 0x0, | |
233 | }, { | |
234 | .reg = PAD_FUNCTION_EN_5, | |
235 | .mask = PADS_AS_GPIO_REGS_MASK, | |
236 | .val = 0x0, | |
237 | }, { | |
238 | .reg = PAD_FUNCTION_EN_6, | |
239 | .mask = PADS_AS_GPIO_REGS_MASK, | |
240 | .val = 0x0, | |
241 | }, { | |
242 | .reg = PAD_FUNCTION_EN_7, | |
243 | .mask = PADS_AS_GPIO_REGS_MASK, | |
244 | .val = 0x0, | |
245 | }, { | |
246 | .reg = PAD_FUNCTION_EN_8, | |
247 | .mask = PADS_AS_GPIO_REG7_MASK, | |
248 | .val = 0x0, | |
249 | }, | |
250 | }; | |
251 | ||
252 | static struct spear_modemux pads_as_gpio_modemux[] = { | |
253 | { | |
254 | .muxregs = pads_as_gpio_muxreg, | |
255 | .nmuxregs = ARRAY_SIZE(pads_as_gpio_muxreg), | |
256 | }, | |
257 | }; | |
258 | ||
259 | static struct spear_pingroup pads_as_gpio_pingroup = { | |
260 | .name = "pads_as_gpio_grp", | |
261 | .pins = pads_as_gpio_pins, | |
262 | .npins = ARRAY_SIZE(pads_as_gpio_pins), | |
263 | .modemuxs = pads_as_gpio_modemux, | |
264 | .nmodemuxs = ARRAY_SIZE(pads_as_gpio_modemux), | |
265 | }; | |
266 | ||
267 | static const char *const pads_as_gpio_grps[] = { "pads_as_gpio_grp" }; | |
268 | static struct spear_function pads_as_gpio_function = { | |
269 | .name = "pads_as_gpio", | |
270 | .groups = pads_as_gpio_grps, | |
271 | .ngroups = ARRAY_SIZE(pads_as_gpio_grps), | |
272 | }; | |
273 | ||
274 | /* Pad multiplexing for fsmc_8bit device */ | |
275 | static const unsigned fsmc_8bit_pins[] = { 233, 234, 235, 236, 238, 239, 240, | |
276 | 241, 242, 243, 244, 245, 246, 247, 248, 249 }; | |
277 | static struct spear_muxreg fsmc_8bit_muxreg[] = { | |
278 | { | |
279 | .reg = PAD_FUNCTION_EN_8, | |
280 | .mask = FSMC_8BIT_REG7_MASK, | |
281 | .val = FSMC_8BIT_REG7_MASK, | |
282 | } | |
283 | }; | |
284 | ||
285 | static struct spear_modemux fsmc_8bit_modemux[] = { | |
286 | { | |
287 | .muxregs = fsmc_8bit_muxreg, | |
288 | .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), | |
289 | }, | |
290 | }; | |
291 | ||
292 | static struct spear_pingroup fsmc_8bit_pingroup = { | |
293 | .name = "fsmc_8bit_grp", | |
294 | .pins = fsmc_8bit_pins, | |
295 | .npins = ARRAY_SIZE(fsmc_8bit_pins), | |
296 | .modemuxs = fsmc_8bit_modemux, | |
297 | .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), | |
298 | }; | |
299 | ||
300 | /* Pad multiplexing for fsmc_16bit device */ | |
301 | static const unsigned fsmc_16bit_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 }; | |
302 | static struct spear_muxreg fsmc_16bit_muxreg[] = { | |
303 | { | |
304 | .reg = PAD_SHARED_IP_EN_1, | |
305 | .mask = KBD_ROW_COL_MASK, | |
306 | .val = 0, | |
307 | }, { | |
308 | .reg = PAD_FUNCTION_EN_1, | |
309 | .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, | |
310 | .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, | |
311 | }, | |
312 | }; | |
313 | ||
314 | static struct spear_modemux fsmc_16bit_modemux[] = { | |
315 | { | |
316 | .muxregs = fsmc_16bit_muxreg, | |
317 | .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), | |
318 | }, | |
319 | }; | |
320 | ||
321 | static struct spear_pingroup fsmc_16bit_pingroup = { | |
322 | .name = "fsmc_16bit_grp", | |
323 | .pins = fsmc_16bit_pins, | |
324 | .npins = ARRAY_SIZE(fsmc_16bit_pins), | |
325 | .modemuxs = fsmc_16bit_modemux, | |
326 | .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), | |
327 | }; | |
328 | ||
329 | /* pad multiplexing for fsmc_pnor device */ | |
330 | static const unsigned fsmc_pnor_pins[] = { 192, 193, 194, 195, 196, 197, 198, | |
331 | 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, | |
332 | 215, 216, 217 }; | |
333 | static struct spear_muxreg fsmc_pnor_muxreg[] = { | |
334 | { | |
335 | .reg = PAD_SHARED_IP_EN_1, | |
336 | .mask = MCIF_MASK, | |
337 | .val = 0, | |
338 | }, { | |
339 | .reg = PAD_FUNCTION_EN_7, | |
340 | .mask = FSMC_PNOR_AND_MCIF_REG6_MASK, | |
341 | .val = FSMC_PNOR_AND_MCIF_REG6_MASK, | |
342 | }, | |
343 | }; | |
344 | ||
345 | static struct spear_modemux fsmc_pnor_modemux[] = { | |
346 | { | |
347 | .muxregs = fsmc_pnor_muxreg, | |
348 | .nmuxregs = ARRAY_SIZE(fsmc_pnor_muxreg), | |
349 | }, | |
350 | }; | |
351 | ||
352 | static struct spear_pingroup fsmc_pnor_pingroup = { | |
353 | .name = "fsmc_pnor_grp", | |
354 | .pins = fsmc_pnor_pins, | |
355 | .npins = ARRAY_SIZE(fsmc_pnor_pins), | |
356 | .modemuxs = fsmc_pnor_modemux, | |
357 | .nmodemuxs = ARRAY_SIZE(fsmc_pnor_modemux), | |
358 | }; | |
359 | ||
360 | static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp", | |
361 | "fsmc_pnor_grp" }; | |
362 | static struct spear_function fsmc_function = { | |
363 | .name = "fsmc", | |
364 | .groups = fsmc_grps, | |
365 | .ngroups = ARRAY_SIZE(fsmc_grps), | |
366 | }; | |
367 | ||
368 | /* pad multiplexing for keyboard rows-cols device */ | |
369 | static const unsigned keyboard_row_col_pins[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, | |
370 | 10 }; | |
371 | static struct spear_muxreg keyboard_row_col_muxreg[] = { | |
372 | { | |
373 | .reg = PAD_SHARED_IP_EN_1, | |
374 | .mask = KBD_ROW_COL_MASK, | |
375 | .val = KBD_ROW_COL_MASK, | |
376 | }, { | |
377 | .reg = PAD_FUNCTION_EN_1, | |
378 | .mask = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, | |
379 | .val = FSMC_16_BIT_AND_KBD_ROW_COL_REG0_MASK, | |
380 | }, | |
381 | }; | |
382 | ||
383 | static struct spear_modemux keyboard_row_col_modemux[] = { | |
384 | { | |
385 | .muxregs = keyboard_row_col_muxreg, | |
386 | .nmuxregs = ARRAY_SIZE(keyboard_row_col_muxreg), | |
387 | }, | |
388 | }; | |
389 | ||
390 | static struct spear_pingroup keyboard_row_col_pingroup = { | |
391 | .name = "keyboard_row_col_grp", | |
392 | .pins = keyboard_row_col_pins, | |
393 | .npins = ARRAY_SIZE(keyboard_row_col_pins), | |
394 | .modemuxs = keyboard_row_col_modemux, | |
395 | .nmodemuxs = ARRAY_SIZE(keyboard_row_col_modemux), | |
396 | }; | |
397 | ||
398 | /* pad multiplexing for keyboard col5 device */ | |
399 | static const unsigned keyboard_col5_pins[] = { 17 }; | |
400 | static struct spear_muxreg keyboard_col5_muxreg[] = { | |
401 | { | |
402 | .reg = PAD_SHARED_IP_EN_1, | |
403 | .mask = KBD_COL5_MASK, | |
404 | .val = KBD_COL5_MASK, | |
405 | }, { | |
406 | .reg = PAD_FUNCTION_EN_1, | |
407 | .mask = PWM1_AND_KBD_COL5_REG0_MASK, | |
408 | .val = PWM1_AND_KBD_COL5_REG0_MASK, | |
409 | }, | |
410 | }; | |
411 | ||
412 | static struct spear_modemux keyboard_col5_modemux[] = { | |
413 | { | |
414 | .muxregs = keyboard_col5_muxreg, | |
415 | .nmuxregs = ARRAY_SIZE(keyboard_col5_muxreg), | |
416 | }, | |
417 | }; | |
418 | ||
419 | static struct spear_pingroup keyboard_col5_pingroup = { | |
420 | .name = "keyboard_col5_grp", | |
421 | .pins = keyboard_col5_pins, | |
422 | .npins = ARRAY_SIZE(keyboard_col5_pins), | |
423 | .modemuxs = keyboard_col5_modemux, | |
424 | .nmodemuxs = ARRAY_SIZE(keyboard_col5_modemux), | |
425 | }; | |
426 | ||
427 | static const char *const keyboard_grps[] = { "keyboard_row_col_grp", | |
428 | "keyboard_col5_grp" }; | |
429 | static struct spear_function keyboard_function = { | |
430 | .name = "keyboard", | |
431 | .groups = keyboard_grps, | |
432 | .ngroups = ARRAY_SIZE(keyboard_grps), | |
433 | }; | |
434 | ||
435 | /* pad multiplexing for spdif_in device */ | |
436 | static const unsigned spdif_in_pins[] = { 19 }; | |
437 | static struct spear_muxreg spdif_in_muxreg[] = { | |
438 | { | |
439 | .reg = PAD_FUNCTION_EN_1, | |
440 | .mask = SPDIF_IN_REG0_MASK, | |
441 | .val = SPDIF_IN_REG0_MASK, | |
442 | }, | |
443 | }; | |
444 | ||
445 | static struct spear_modemux spdif_in_modemux[] = { | |
446 | { | |
447 | .muxregs = spdif_in_muxreg, | |
448 | .nmuxregs = ARRAY_SIZE(spdif_in_muxreg), | |
449 | }, | |
450 | }; | |
451 | ||
452 | static struct spear_pingroup spdif_in_pingroup = { | |
453 | .name = "spdif_in_grp", | |
454 | .pins = spdif_in_pins, | |
455 | .npins = ARRAY_SIZE(spdif_in_pins), | |
456 | .modemuxs = spdif_in_modemux, | |
457 | .nmodemuxs = ARRAY_SIZE(spdif_in_modemux), | |
458 | }; | |
459 | ||
460 | static const char *const spdif_in_grps[] = { "spdif_in_grp" }; | |
461 | static struct spear_function spdif_in_function = { | |
462 | .name = "spdif_in", | |
463 | .groups = spdif_in_grps, | |
464 | .ngroups = ARRAY_SIZE(spdif_in_grps), | |
465 | }; | |
466 | ||
467 | /* pad multiplexing for spdif_out device */ | |
468 | static const unsigned spdif_out_pins[] = { 137 }; | |
469 | static struct spear_muxreg spdif_out_muxreg[] = { | |
470 | { | |
471 | .reg = PAD_FUNCTION_EN_5, | |
472 | .mask = SPDIF_OUT_REG4_MASK, | |
473 | .val = SPDIF_OUT_REG4_MASK, | |
474 | }, { | |
475 | .reg = PERIP_CFG, | |
476 | .mask = SPDIF_OUT_ENB_MASK, | |
477 | .val = SPDIF_OUT_ENB_MASK, | |
478 | } | |
479 | }; | |
480 | ||
481 | static struct spear_modemux spdif_out_modemux[] = { | |
482 | { | |
483 | .muxregs = spdif_out_muxreg, | |
484 | .nmuxregs = ARRAY_SIZE(spdif_out_muxreg), | |
485 | }, | |
486 | }; | |
487 | ||
488 | static struct spear_pingroup spdif_out_pingroup = { | |
489 | .name = "spdif_out_grp", | |
490 | .pins = spdif_out_pins, | |
491 | .npins = ARRAY_SIZE(spdif_out_pins), | |
492 | .modemuxs = spdif_out_modemux, | |
493 | .nmodemuxs = ARRAY_SIZE(spdif_out_modemux), | |
494 | }; | |
495 | ||
496 | static const char *const spdif_out_grps[] = { "spdif_out_grp" }; | |
497 | static struct spear_function spdif_out_function = { | |
498 | .name = "spdif_out", | |
499 | .groups = spdif_out_grps, | |
500 | .ngroups = ARRAY_SIZE(spdif_out_grps), | |
501 | }; | |
502 | ||
503 | /* pad multiplexing for gpt_0_1 device */ | |
504 | static const unsigned gpt_0_1_pins[] = { 11, 12, 13, 14, 15, 16, 21, 22 }; | |
505 | static struct spear_muxreg gpt_0_1_muxreg[] = { | |
506 | { | |
507 | .reg = PAD_SHARED_IP_EN_1, | |
508 | .mask = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, | |
509 | .val = GPT_MASK | GPT0_TMR0_CPT_MASK | GPT0_TMR1_CLK_MASK, | |
510 | }, { | |
511 | .reg = PAD_FUNCTION_EN_1, | |
512 | .mask = UART0_ENH_AND_GPT_REG0_MASK | | |
513 | PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | | |
514 | PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, | |
515 | .val = UART0_ENH_AND_GPT_REG0_MASK | | |
516 | PWM2_AND_GPT0_TMR0_CPT_REG0_MASK | | |
517 | PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, | |
518 | }, | |
519 | }; | |
520 | ||
521 | static struct spear_modemux gpt_0_1_modemux[] = { | |
522 | { | |
523 | .muxregs = gpt_0_1_muxreg, | |
524 | .nmuxregs = ARRAY_SIZE(gpt_0_1_muxreg), | |
525 | }, | |
526 | }; | |
527 | ||
528 | static struct spear_pingroup gpt_0_1_pingroup = { | |
529 | .name = "gpt_0_1_grp", | |
530 | .pins = gpt_0_1_pins, | |
531 | .npins = ARRAY_SIZE(gpt_0_1_pins), | |
532 | .modemuxs = gpt_0_1_modemux, | |
533 | .nmodemuxs = ARRAY_SIZE(gpt_0_1_modemux), | |
534 | }; | |
535 | ||
536 | static const char *const gpt_0_1_grps[] = { "gpt_0_1_grp" }; | |
537 | static struct spear_function gpt_0_1_function = { | |
538 | .name = "gpt_0_1", | |
539 | .groups = gpt_0_1_grps, | |
540 | .ngroups = ARRAY_SIZE(gpt_0_1_grps), | |
541 | }; | |
542 | ||
543 | /* pad multiplexing for pwm0 device */ | |
544 | static const unsigned pwm0_pins[] = { 24 }; | |
545 | static struct spear_muxreg pwm0_muxreg[] = { | |
546 | { | |
547 | .reg = PAD_SHARED_IP_EN_1, | |
548 | .mask = SSP0_CS1_MASK, | |
549 | .val = 0, | |
550 | }, { | |
551 | .reg = PAD_FUNCTION_EN_1, | |
552 | .mask = PWM0_AND_SSP0_CS1_REG0_MASK, | |
553 | .val = PWM0_AND_SSP0_CS1_REG0_MASK, | |
554 | }, | |
555 | }; | |
556 | ||
557 | static struct spear_modemux pwm0_modemux[] = { | |
558 | { | |
559 | .muxregs = pwm0_muxreg, | |
560 | .nmuxregs = ARRAY_SIZE(pwm0_muxreg), | |
561 | }, | |
562 | }; | |
563 | ||
564 | static struct spear_pingroup pwm0_pingroup = { | |
565 | .name = "pwm0_grp", | |
566 | .pins = pwm0_pins, | |
567 | .npins = ARRAY_SIZE(pwm0_pins), | |
568 | .modemuxs = pwm0_modemux, | |
569 | .nmodemuxs = ARRAY_SIZE(pwm0_modemux), | |
570 | }; | |
571 | ||
572 | /* pad multiplexing for pwm1 device */ | |
573 | static const unsigned pwm1_pins[] = { 17 }; | |
574 | static struct spear_muxreg pwm1_muxreg[] = { | |
575 | { | |
576 | .reg = PAD_SHARED_IP_EN_1, | |
577 | .mask = KBD_COL5_MASK, | |
578 | .val = 0, | |
579 | }, { | |
580 | .reg = PAD_FUNCTION_EN_1, | |
581 | .mask = PWM1_AND_KBD_COL5_REG0_MASK, | |
582 | .val = PWM1_AND_KBD_COL5_REG0_MASK, | |
583 | }, | |
584 | }; | |
585 | ||
586 | static struct spear_modemux pwm1_modemux[] = { | |
587 | { | |
588 | .muxregs = pwm1_muxreg, | |
589 | .nmuxregs = ARRAY_SIZE(pwm1_muxreg), | |
590 | }, | |
591 | }; | |
592 | ||
593 | static struct spear_pingroup pwm1_pingroup = { | |
594 | .name = "pwm1_grp", | |
595 | .pins = pwm1_pins, | |
596 | .npins = ARRAY_SIZE(pwm1_pins), | |
597 | .modemuxs = pwm1_modemux, | |
598 | .nmodemuxs = ARRAY_SIZE(pwm1_modemux), | |
599 | }; | |
600 | ||
601 | /* pad multiplexing for pwm2 device */ | |
602 | static const unsigned pwm2_pins[] = { 21 }; | |
603 | static struct spear_muxreg pwm2_muxreg[] = { | |
604 | { | |
605 | .reg = PAD_SHARED_IP_EN_1, | |
606 | .mask = GPT0_TMR0_CPT_MASK, | |
607 | .val = 0, | |
608 | }, { | |
609 | .reg = PAD_FUNCTION_EN_1, | |
610 | .mask = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, | |
611 | .val = PWM2_AND_GPT0_TMR0_CPT_REG0_MASK, | |
612 | }, | |
613 | }; | |
614 | ||
615 | static struct spear_modemux pwm2_modemux[] = { | |
616 | { | |
617 | .muxregs = pwm2_muxreg, | |
618 | .nmuxregs = ARRAY_SIZE(pwm2_muxreg), | |
619 | }, | |
620 | }; | |
621 | ||
622 | static struct spear_pingroup pwm2_pingroup = { | |
623 | .name = "pwm2_grp", | |
624 | .pins = pwm2_pins, | |
625 | .npins = ARRAY_SIZE(pwm2_pins), | |
626 | .modemuxs = pwm2_modemux, | |
627 | .nmodemuxs = ARRAY_SIZE(pwm2_modemux), | |
628 | }; | |
629 | ||
630 | /* pad multiplexing for pwm3 device */ | |
631 | static const unsigned pwm3_pins[] = { 22 }; | |
632 | static struct spear_muxreg pwm3_muxreg[] = { | |
633 | { | |
634 | .reg = PAD_SHARED_IP_EN_1, | |
635 | .mask = GPT0_TMR1_CLK_MASK, | |
636 | .val = 0, | |
637 | }, { | |
638 | .reg = PAD_FUNCTION_EN_1, | |
639 | .mask = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, | |
640 | .val = PWM3_AND_GPT0_TMR1_CLK_REG0_MASK, | |
641 | }, | |
642 | }; | |
643 | ||
644 | static struct spear_modemux pwm3_modemux[] = { | |
645 | { | |
646 | .muxregs = pwm3_muxreg, | |
647 | .nmuxregs = ARRAY_SIZE(pwm3_muxreg), | |
648 | }, | |
649 | }; | |
650 | ||
651 | static struct spear_pingroup pwm3_pingroup = { | |
652 | .name = "pwm3_grp", | |
653 | .pins = pwm3_pins, | |
654 | .npins = ARRAY_SIZE(pwm3_pins), | |
655 | .modemuxs = pwm3_modemux, | |
656 | .nmodemuxs = ARRAY_SIZE(pwm3_modemux), | |
657 | }; | |
658 | ||
659 | static const char *const pwm_grps[] = { "pwm0_grp", "pwm1_grp", "pwm2_grp", | |
660 | "pwm3_grp" }; | |
661 | static struct spear_function pwm_function = { | |
662 | .name = "pwm", | |
663 | .groups = pwm_grps, | |
664 | .ngroups = ARRAY_SIZE(pwm_grps), | |
665 | }; | |
666 | ||
667 | /* pad multiplexing for vip_mux device */ | |
668 | static const unsigned vip_mux_pins[] = { 35, 36, 37, 38, 40, 41, 42, 43 }; | |
669 | static struct spear_muxreg vip_mux_muxreg[] = { | |
670 | { | |
671 | .reg = PAD_FUNCTION_EN_2, | |
672 | .mask = VIP_REG1_MASK, | |
673 | .val = VIP_REG1_MASK, | |
674 | }, | |
675 | }; | |
676 | ||
677 | static struct spear_modemux vip_mux_modemux[] = { | |
678 | { | |
679 | .muxregs = vip_mux_muxreg, | |
680 | .nmuxregs = ARRAY_SIZE(vip_mux_muxreg), | |
681 | }, | |
682 | }; | |
683 | ||
684 | static struct spear_pingroup vip_mux_pingroup = { | |
685 | .name = "vip_mux_grp", | |
686 | .pins = vip_mux_pins, | |
687 | .npins = ARRAY_SIZE(vip_mux_pins), | |
688 | .modemuxs = vip_mux_modemux, | |
689 | .nmodemuxs = ARRAY_SIZE(vip_mux_modemux), | |
690 | }; | |
691 | ||
692 | /* pad multiplexing for vip_mux_cam0 (disables cam0) device */ | |
693 | static const unsigned vip_mux_cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, | |
694 | 73, 74, 75 }; | |
695 | static struct spear_muxreg vip_mux_cam0_muxreg[] = { | |
696 | { | |
697 | .reg = PAD_SHARED_IP_EN_1, | |
698 | .mask = CAM0_MASK, | |
699 | .val = 0, | |
700 | }, { | |
701 | .reg = PAD_FUNCTION_EN_3, | |
702 | .mask = VIP_AND_CAM0_REG2_MASK, | |
703 | .val = VIP_AND_CAM0_REG2_MASK, | |
704 | }, | |
705 | }; | |
706 | ||
707 | static struct spear_modemux vip_mux_cam0_modemux[] = { | |
708 | { | |
709 | .muxregs = vip_mux_cam0_muxreg, | |
710 | .nmuxregs = ARRAY_SIZE(vip_mux_cam0_muxreg), | |
711 | }, | |
712 | }; | |
713 | ||
714 | static struct spear_pingroup vip_mux_cam0_pingroup = { | |
715 | .name = "vip_mux_cam0_grp", | |
716 | .pins = vip_mux_cam0_pins, | |
717 | .npins = ARRAY_SIZE(vip_mux_cam0_pins), | |
718 | .modemuxs = vip_mux_cam0_modemux, | |
719 | .nmodemuxs = ARRAY_SIZE(vip_mux_cam0_modemux), | |
720 | }; | |
721 | ||
722 | /* pad multiplexing for vip_mux_cam1 (disables cam1) device */ | |
723 | static const unsigned vip_mux_cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, | |
724 | 62, 63, 64 }; | |
725 | static struct spear_muxreg vip_mux_cam1_muxreg[] = { | |
726 | { | |
727 | .reg = PAD_SHARED_IP_EN_1, | |
728 | .mask = CAM1_MASK, | |
729 | .val = 0, | |
730 | }, { | |
731 | .reg = PAD_FUNCTION_EN_2, | |
732 | .mask = VIP_AND_CAM1_REG1_MASK, | |
733 | .val = VIP_AND_CAM1_REG1_MASK, | |
734 | }, { | |
735 | .reg = PAD_FUNCTION_EN_3, | |
736 | .mask = VIP_AND_CAM1_REG2_MASK, | |
737 | .val = VIP_AND_CAM1_REG2_MASK, | |
738 | }, | |
739 | }; | |
740 | ||
741 | static struct spear_modemux vip_mux_cam1_modemux[] = { | |
742 | { | |
743 | .muxregs = vip_mux_cam1_muxreg, | |
744 | .nmuxregs = ARRAY_SIZE(vip_mux_cam1_muxreg), | |
745 | }, | |
746 | }; | |
747 | ||
748 | static struct spear_pingroup vip_mux_cam1_pingroup = { | |
749 | .name = "vip_mux_cam1_grp", | |
750 | .pins = vip_mux_cam1_pins, | |
751 | .npins = ARRAY_SIZE(vip_mux_cam1_pins), | |
752 | .modemuxs = vip_mux_cam1_modemux, | |
753 | .nmodemuxs = ARRAY_SIZE(vip_mux_cam1_modemux), | |
754 | }; | |
755 | ||
756 | /* pad multiplexing for vip_mux_cam2 (disables cam2) device */ | |
757 | static const unsigned vip_mux_cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, | |
758 | 51, 52, 53 }; | |
759 | static struct spear_muxreg vip_mux_cam2_muxreg[] = { | |
760 | { | |
761 | .reg = PAD_SHARED_IP_EN_1, | |
762 | .mask = CAM2_MASK, | |
763 | .val = 0, | |
764 | }, { | |
765 | .reg = PAD_FUNCTION_EN_2, | |
766 | .mask = VIP_AND_CAM2_REG1_MASK, | |
767 | .val = VIP_AND_CAM2_REG1_MASK, | |
768 | }, | |
769 | }; | |
770 | ||
771 | static struct spear_modemux vip_mux_cam2_modemux[] = { | |
772 | { | |
773 | .muxregs = vip_mux_cam2_muxreg, | |
774 | .nmuxregs = ARRAY_SIZE(vip_mux_cam2_muxreg), | |
775 | }, | |
776 | }; | |
777 | ||
778 | static struct spear_pingroup vip_mux_cam2_pingroup = { | |
779 | .name = "vip_mux_cam2_grp", | |
780 | .pins = vip_mux_cam2_pins, | |
781 | .npins = ARRAY_SIZE(vip_mux_cam2_pins), | |
782 | .modemuxs = vip_mux_cam2_modemux, | |
783 | .nmodemuxs = ARRAY_SIZE(vip_mux_cam2_modemux), | |
784 | }; | |
785 | ||
786 | /* pad multiplexing for vip_mux_cam3 (disables cam3) device */ | |
787 | static const unsigned vip_mux_cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, | |
788 | 32, 33, 34 }; | |
789 | static struct spear_muxreg vip_mux_cam3_muxreg[] = { | |
790 | { | |
791 | .reg = PAD_SHARED_IP_EN_1, | |
792 | .mask = CAM3_MASK, | |
793 | .val = 0, | |
794 | }, { | |
795 | .reg = PAD_FUNCTION_EN_1, | |
796 | .mask = VIP_AND_CAM3_REG0_MASK, | |
797 | .val = VIP_AND_CAM3_REG0_MASK, | |
798 | }, { | |
799 | .reg = PAD_FUNCTION_EN_2, | |
800 | .mask = VIP_AND_CAM3_REG1_MASK, | |
801 | .val = VIP_AND_CAM3_REG1_MASK, | |
802 | }, | |
803 | }; | |
804 | ||
805 | static struct spear_modemux vip_mux_cam3_modemux[] = { | |
806 | { | |
807 | .muxregs = vip_mux_cam3_muxreg, | |
808 | .nmuxregs = ARRAY_SIZE(vip_mux_cam3_muxreg), | |
809 | }, | |
810 | }; | |
811 | ||
812 | static struct spear_pingroup vip_mux_cam3_pingroup = { | |
813 | .name = "vip_mux_cam3_grp", | |
814 | .pins = vip_mux_cam3_pins, | |
815 | .npins = ARRAY_SIZE(vip_mux_cam3_pins), | |
816 | .modemuxs = vip_mux_cam3_modemux, | |
817 | .nmodemuxs = ARRAY_SIZE(vip_mux_cam3_modemux), | |
818 | }; | |
819 | ||
820 | static const char *const vip_grps[] = { "vip_mux_grp", "vip_mux_cam0_grp" , | |
821 | "vip_mux_cam1_grp" , "vip_mux_cam2_grp", "vip_mux_cam3_grp" }; | |
822 | static struct spear_function vip_function = { | |
823 | .name = "vip", | |
824 | .groups = vip_grps, | |
825 | .ngroups = ARRAY_SIZE(vip_grps), | |
826 | }; | |
827 | ||
828 | /* pad multiplexing for cam0 device */ | |
829 | static const unsigned cam0_pins[] = { 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75 | |
830 | }; | |
831 | static struct spear_muxreg cam0_muxreg[] = { | |
832 | { | |
833 | .reg = PAD_SHARED_IP_EN_1, | |
834 | .mask = CAM0_MASK, | |
835 | .val = CAM0_MASK, | |
836 | }, { | |
837 | .reg = PAD_FUNCTION_EN_3, | |
838 | .mask = VIP_AND_CAM0_REG2_MASK, | |
839 | .val = VIP_AND_CAM0_REG2_MASK, | |
840 | }, | |
841 | }; | |
842 | ||
843 | static struct spear_modemux cam0_modemux[] = { | |
844 | { | |
845 | .muxregs = cam0_muxreg, | |
846 | .nmuxregs = ARRAY_SIZE(cam0_muxreg), | |
847 | }, | |
848 | }; | |
849 | ||
850 | static struct spear_pingroup cam0_pingroup = { | |
851 | .name = "cam0_grp", | |
852 | .pins = cam0_pins, | |
853 | .npins = ARRAY_SIZE(cam0_pins), | |
854 | .modemuxs = cam0_modemux, | |
855 | .nmodemuxs = ARRAY_SIZE(cam0_modemux), | |
856 | }; | |
857 | ||
858 | static const char *const cam0_grps[] = { "cam0_grp" }; | |
859 | static struct spear_function cam0_function = { | |
860 | .name = "cam0", | |
861 | .groups = cam0_grps, | |
862 | .ngroups = ARRAY_SIZE(cam0_grps), | |
863 | }; | |
864 | ||
865 | /* pad multiplexing for cam1 device */ | |
866 | static const unsigned cam1_pins[] = { 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64 | |
867 | }; | |
868 | static struct spear_muxreg cam1_muxreg[] = { | |
869 | { | |
870 | .reg = PAD_SHARED_IP_EN_1, | |
871 | .mask = CAM1_MASK, | |
872 | .val = CAM1_MASK, | |
873 | }, { | |
874 | .reg = PAD_FUNCTION_EN_2, | |
875 | .mask = VIP_AND_CAM1_REG1_MASK, | |
876 | .val = VIP_AND_CAM1_REG1_MASK, | |
877 | }, { | |
878 | .reg = PAD_FUNCTION_EN_3, | |
879 | .mask = VIP_AND_CAM1_REG2_MASK, | |
880 | .val = VIP_AND_CAM1_REG2_MASK, | |
881 | }, | |
882 | }; | |
883 | ||
884 | static struct spear_modemux cam1_modemux[] = { | |
885 | { | |
886 | .muxregs = cam1_muxreg, | |
887 | .nmuxregs = ARRAY_SIZE(cam1_muxreg), | |
888 | }, | |
889 | }; | |
890 | ||
891 | static struct spear_pingroup cam1_pingroup = { | |
892 | .name = "cam1_grp", | |
893 | .pins = cam1_pins, | |
894 | .npins = ARRAY_SIZE(cam1_pins), | |
895 | .modemuxs = cam1_modemux, | |
896 | .nmodemuxs = ARRAY_SIZE(cam1_modemux), | |
897 | }; | |
898 | ||
899 | static const char *const cam1_grps[] = { "cam1_grp" }; | |
900 | static struct spear_function cam1_function = { | |
901 | .name = "cam1", | |
902 | .groups = cam1_grps, | |
903 | .ngroups = ARRAY_SIZE(cam1_grps), | |
904 | }; | |
905 | ||
906 | /* pad multiplexing for cam2 device */ | |
907 | static const unsigned cam2_pins[] = { 39, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 | |
908 | }; | |
909 | static struct spear_muxreg cam2_muxreg[] = { | |
910 | { | |
911 | .reg = PAD_SHARED_IP_EN_1, | |
912 | .mask = CAM2_MASK, | |
913 | .val = CAM2_MASK, | |
914 | }, { | |
915 | .reg = PAD_FUNCTION_EN_2, | |
916 | .mask = VIP_AND_CAM2_REG1_MASK, | |
917 | .val = VIP_AND_CAM2_REG1_MASK, | |
918 | }, | |
919 | }; | |
920 | ||
921 | static struct spear_modemux cam2_modemux[] = { | |
922 | { | |
923 | .muxregs = cam2_muxreg, | |
924 | .nmuxregs = ARRAY_SIZE(cam2_muxreg), | |
925 | }, | |
926 | }; | |
927 | ||
928 | static struct spear_pingroup cam2_pingroup = { | |
929 | .name = "cam2_grp", | |
930 | .pins = cam2_pins, | |
931 | .npins = ARRAY_SIZE(cam2_pins), | |
932 | .modemuxs = cam2_modemux, | |
933 | .nmodemuxs = ARRAY_SIZE(cam2_modemux), | |
934 | }; | |
935 | ||
936 | static const char *const cam2_grps[] = { "cam2_grp" }; | |
937 | static struct spear_function cam2_function = { | |
938 | .name = "cam2", | |
939 | .groups = cam2_grps, | |
940 | .ngroups = ARRAY_SIZE(cam2_grps), | |
941 | }; | |
942 | ||
943 | /* pad multiplexing for cam3 device */ | |
944 | static const unsigned cam3_pins[] = { 20, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 | |
945 | }; | |
946 | static struct spear_muxreg cam3_muxreg[] = { | |
947 | { | |
948 | .reg = PAD_SHARED_IP_EN_1, | |
949 | .mask = CAM3_MASK, | |
950 | .val = CAM3_MASK, | |
951 | }, { | |
952 | .reg = PAD_FUNCTION_EN_1, | |
953 | .mask = VIP_AND_CAM3_REG0_MASK, | |
954 | .val = VIP_AND_CAM3_REG0_MASK, | |
955 | }, { | |
956 | .reg = PAD_FUNCTION_EN_2, | |
957 | .mask = VIP_AND_CAM3_REG1_MASK, | |
958 | .val = VIP_AND_CAM3_REG1_MASK, | |
959 | }, | |
960 | }; | |
961 | ||
962 | static struct spear_modemux cam3_modemux[] = { | |
963 | { | |
964 | .muxregs = cam3_muxreg, | |
965 | .nmuxregs = ARRAY_SIZE(cam3_muxreg), | |
966 | }, | |
967 | }; | |
968 | ||
969 | static struct spear_pingroup cam3_pingroup = { | |
970 | .name = "cam3_grp", | |
971 | .pins = cam3_pins, | |
972 | .npins = ARRAY_SIZE(cam3_pins), | |
973 | .modemuxs = cam3_modemux, | |
974 | .nmodemuxs = ARRAY_SIZE(cam3_modemux), | |
975 | }; | |
976 | ||
977 | static const char *const cam3_grps[] = { "cam3_grp" }; | |
978 | static struct spear_function cam3_function = { | |
979 | .name = "cam3", | |
980 | .groups = cam3_grps, | |
981 | .ngroups = ARRAY_SIZE(cam3_grps), | |
982 | }; | |
983 | ||
984 | /* pad multiplexing for smi device */ | |
985 | static const unsigned smi_pins[] = { 76, 77, 78, 79, 84 }; | |
986 | static struct spear_muxreg smi_muxreg[] = { | |
987 | { | |
988 | .reg = PAD_FUNCTION_EN_3, | |
989 | .mask = SMI_REG2_MASK, | |
990 | .val = SMI_REG2_MASK, | |
991 | }, | |
992 | }; | |
993 | ||
994 | static struct spear_modemux smi_modemux[] = { | |
995 | { | |
996 | .muxregs = smi_muxreg, | |
997 | .nmuxregs = ARRAY_SIZE(smi_muxreg), | |
998 | }, | |
999 | }; | |
1000 | ||
1001 | static struct spear_pingroup smi_pingroup = { | |
1002 | .name = "smi_grp", | |
1003 | .pins = smi_pins, | |
1004 | .npins = ARRAY_SIZE(smi_pins), | |
1005 | .modemuxs = smi_modemux, | |
1006 | .nmodemuxs = ARRAY_SIZE(smi_modemux), | |
1007 | }; | |
1008 | ||
1009 | static const char *const smi_grps[] = { "smi_grp" }; | |
1010 | static struct spear_function smi_function = { | |
1011 | .name = "smi", | |
1012 | .groups = smi_grps, | |
1013 | .ngroups = ARRAY_SIZE(smi_grps), | |
1014 | }; | |
1015 | ||
1016 | /* pad multiplexing for ssp0 device */ | |
1017 | static const unsigned ssp0_pins[] = { 80, 81, 82, 83 }; | |
1018 | static struct spear_muxreg ssp0_muxreg[] = { | |
1019 | { | |
1020 | .reg = PAD_FUNCTION_EN_3, | |
1021 | .mask = SSP0_REG2_MASK, | |
1022 | .val = SSP0_REG2_MASK, | |
1023 | }, | |
1024 | }; | |
1025 | ||
1026 | static struct spear_modemux ssp0_modemux[] = { | |
1027 | { | |
1028 | .muxregs = ssp0_muxreg, | |
1029 | .nmuxregs = ARRAY_SIZE(ssp0_muxreg), | |
1030 | }, | |
1031 | }; | |
1032 | ||
1033 | static struct spear_pingroup ssp0_pingroup = { | |
1034 | .name = "ssp0_grp", | |
1035 | .pins = ssp0_pins, | |
1036 | .npins = ARRAY_SIZE(ssp0_pins), | |
1037 | .modemuxs = ssp0_modemux, | |
1038 | .nmodemuxs = ARRAY_SIZE(ssp0_modemux), | |
1039 | }; | |
1040 | ||
1041 | /* pad multiplexing for ssp0_cs1 device */ | |
1042 | static const unsigned ssp0_cs1_pins[] = { 24 }; | |
1043 | static struct spear_muxreg ssp0_cs1_muxreg[] = { | |
1044 | { | |
1045 | .reg = PAD_SHARED_IP_EN_1, | |
1046 | .mask = SSP0_CS1_MASK, | |
1047 | .val = SSP0_CS1_MASK, | |
1048 | }, { | |
1049 | .reg = PAD_FUNCTION_EN_1, | |
1050 | .mask = PWM0_AND_SSP0_CS1_REG0_MASK, | |
1051 | .val = PWM0_AND_SSP0_CS1_REG0_MASK, | |
1052 | }, | |
1053 | }; | |
1054 | ||
1055 | static struct spear_modemux ssp0_cs1_modemux[] = { | |
1056 | { | |
1057 | .muxregs = ssp0_cs1_muxreg, | |
1058 | .nmuxregs = ARRAY_SIZE(ssp0_cs1_muxreg), | |
1059 | }, | |
1060 | }; | |
1061 | ||
1062 | static struct spear_pingroup ssp0_cs1_pingroup = { | |
1063 | .name = "ssp0_cs1_grp", | |
1064 | .pins = ssp0_cs1_pins, | |
1065 | .npins = ARRAY_SIZE(ssp0_cs1_pins), | |
1066 | .modemuxs = ssp0_cs1_modemux, | |
1067 | .nmodemuxs = ARRAY_SIZE(ssp0_cs1_modemux), | |
1068 | }; | |
1069 | ||
1070 | /* pad multiplexing for ssp0_cs2 device */ | |
1071 | static const unsigned ssp0_cs2_pins[] = { 85 }; | |
1072 | static struct spear_muxreg ssp0_cs2_muxreg[] = { | |
1073 | { | |
1074 | .reg = PAD_SHARED_IP_EN_1, | |
1075 | .mask = SSP0_CS2_MASK, | |
1076 | .val = SSP0_CS2_MASK, | |
1077 | }, { | |
1078 | .reg = PAD_FUNCTION_EN_3, | |
1079 | .mask = TS_AND_SSP0_CS2_REG2_MASK, | |
1080 | .val = TS_AND_SSP0_CS2_REG2_MASK, | |
1081 | }, | |
1082 | }; | |
1083 | ||
1084 | static struct spear_modemux ssp0_cs2_modemux[] = { | |
1085 | { | |
1086 | .muxregs = ssp0_cs2_muxreg, | |
1087 | .nmuxregs = ARRAY_SIZE(ssp0_cs2_muxreg), | |
1088 | }, | |
1089 | }; | |
1090 | ||
1091 | static struct spear_pingroup ssp0_cs2_pingroup = { | |
1092 | .name = "ssp0_cs2_grp", | |
1093 | .pins = ssp0_cs2_pins, | |
1094 | .npins = ARRAY_SIZE(ssp0_cs2_pins), | |
1095 | .modemuxs = ssp0_cs2_modemux, | |
1096 | .nmodemuxs = ARRAY_SIZE(ssp0_cs2_modemux), | |
1097 | }; | |
1098 | ||
1099 | /* pad multiplexing for ssp0_cs3 device */ | |
1100 | static const unsigned ssp0_cs3_pins[] = { 132 }; | |
1101 | static struct spear_muxreg ssp0_cs3_muxreg[] = { | |
1102 | { | |
1103 | .reg = PAD_FUNCTION_EN_5, | |
1104 | .mask = SSP0_CS3_REG4_MASK, | |
1105 | .val = SSP0_CS3_REG4_MASK, | |
1106 | }, | |
1107 | }; | |
1108 | ||
1109 | static struct spear_modemux ssp0_cs3_modemux[] = { | |
1110 | { | |
1111 | .muxregs = ssp0_cs3_muxreg, | |
1112 | .nmuxregs = ARRAY_SIZE(ssp0_cs3_muxreg), | |
1113 | }, | |
1114 | }; | |
1115 | ||
1116 | static struct spear_pingroup ssp0_cs3_pingroup = { | |
1117 | .name = "ssp0_cs3_grp", | |
1118 | .pins = ssp0_cs3_pins, | |
1119 | .npins = ARRAY_SIZE(ssp0_cs3_pins), | |
1120 | .modemuxs = ssp0_cs3_modemux, | |
1121 | .nmodemuxs = ARRAY_SIZE(ssp0_cs3_modemux), | |
1122 | }; | |
1123 | ||
1124 | static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs1_grp", | |
1125 | "ssp0_cs2_grp", "ssp0_cs3_grp" }; | |
1126 | static struct spear_function ssp0_function = { | |
1127 | .name = "ssp0", | |
1128 | .groups = ssp0_grps, | |
1129 | .ngroups = ARRAY_SIZE(ssp0_grps), | |
1130 | }; | |
1131 | ||
1132 | /* pad multiplexing for uart0 device */ | |
1133 | static const unsigned uart0_pins[] = { 86, 87 }; | |
1134 | static struct spear_muxreg uart0_muxreg[] = { | |
1135 | { | |
1136 | .reg = PAD_FUNCTION_EN_3, | |
1137 | .mask = UART0_REG2_MASK, | |
1138 | .val = UART0_REG2_MASK, | |
1139 | }, | |
1140 | }; | |
1141 | ||
1142 | static struct spear_modemux uart0_modemux[] = { | |
1143 | { | |
1144 | .muxregs = uart0_muxreg, | |
1145 | .nmuxregs = ARRAY_SIZE(uart0_muxreg), | |
1146 | }, | |
1147 | }; | |
1148 | ||
1149 | static struct spear_pingroup uart0_pingroup = { | |
1150 | .name = "uart0_grp", | |
1151 | .pins = uart0_pins, | |
1152 | .npins = ARRAY_SIZE(uart0_pins), | |
1153 | .modemuxs = uart0_modemux, | |
1154 | .nmodemuxs = ARRAY_SIZE(uart0_modemux), | |
1155 | }; | |
1156 | ||
1157 | /* pad multiplexing for uart0_enh device */ | |
1158 | static const unsigned uart0_enh_pins[] = { 11, 12, 13, 14, 15, 16 }; | |
1159 | static struct spear_muxreg uart0_enh_muxreg[] = { | |
1160 | { | |
1161 | .reg = PAD_SHARED_IP_EN_1, | |
1162 | .mask = GPT_MASK, | |
1163 | .val = 0, | |
1164 | }, { | |
1165 | .reg = PAD_FUNCTION_EN_1, | |
1166 | .mask = UART0_ENH_AND_GPT_REG0_MASK, | |
1167 | .val = UART0_ENH_AND_GPT_REG0_MASK, | |
1168 | }, | |
1169 | }; | |
1170 | ||
1171 | static struct spear_modemux uart0_enh_modemux[] = { | |
1172 | { | |
1173 | .muxregs = uart0_enh_muxreg, | |
1174 | .nmuxregs = ARRAY_SIZE(uart0_enh_muxreg), | |
1175 | }, | |
1176 | }; | |
1177 | ||
1178 | static struct spear_pingroup uart0_enh_pingroup = { | |
1179 | .name = "uart0_enh_grp", | |
1180 | .pins = uart0_enh_pins, | |
1181 | .npins = ARRAY_SIZE(uart0_enh_pins), | |
1182 | .modemuxs = uart0_enh_modemux, | |
1183 | .nmodemuxs = ARRAY_SIZE(uart0_enh_modemux), | |
1184 | }; | |
1185 | ||
1186 | static const char *const uart0_grps[] = { "uart0_grp", "uart0_enh_grp" }; | |
1187 | static struct spear_function uart0_function = { | |
1188 | .name = "uart0", | |
1189 | .groups = uart0_grps, | |
1190 | .ngroups = ARRAY_SIZE(uart0_grps), | |
1191 | }; | |
1192 | ||
1193 | /* pad multiplexing for uart1 device */ | |
1194 | static const unsigned uart1_pins[] = { 88, 89 }; | |
1195 | static struct spear_muxreg uart1_muxreg[] = { | |
1196 | { | |
1197 | .reg = PAD_FUNCTION_EN_3, | |
1198 | .mask = UART1_REG2_MASK, | |
1199 | .val = UART1_REG2_MASK, | |
1200 | }, | |
1201 | }; | |
1202 | ||
1203 | static struct spear_modemux uart1_modemux[] = { | |
1204 | { | |
1205 | .muxregs = uart1_muxreg, | |
1206 | .nmuxregs = ARRAY_SIZE(uart1_muxreg), | |
1207 | }, | |
1208 | }; | |
1209 | ||
1210 | static struct spear_pingroup uart1_pingroup = { | |
1211 | .name = "uart1_grp", | |
1212 | .pins = uart1_pins, | |
1213 | .npins = ARRAY_SIZE(uart1_pins), | |
1214 | .modemuxs = uart1_modemux, | |
1215 | .nmodemuxs = ARRAY_SIZE(uart1_modemux), | |
1216 | }; | |
1217 | ||
1218 | static const char *const uart1_grps[] = { "uart1_grp" }; | |
1219 | static struct spear_function uart1_function = { | |
1220 | .name = "uart1", | |
1221 | .groups = uart1_grps, | |
1222 | .ngroups = ARRAY_SIZE(uart1_grps), | |
1223 | }; | |
1224 | ||
1225 | /* pad multiplexing for i2s_in device */ | |
1226 | static const unsigned i2s_in_pins[] = { 90, 91, 92, 93, 94, 99 }; | |
1227 | static struct spear_muxreg i2s_in_muxreg[] = { | |
1228 | { | |
1229 | .reg = PAD_FUNCTION_EN_3, | |
1230 | .mask = I2S_IN_REG2_MASK, | |
1231 | .val = I2S_IN_REG2_MASK, | |
1232 | }, { | |
1233 | .reg = PAD_FUNCTION_EN_4, | |
1234 | .mask = I2S_IN_REG3_MASK, | |
1235 | .val = I2S_IN_REG3_MASK, | |
1236 | }, | |
1237 | }; | |
1238 | ||
1239 | static struct spear_modemux i2s_in_modemux[] = { | |
1240 | { | |
1241 | .muxregs = i2s_in_muxreg, | |
1242 | .nmuxregs = ARRAY_SIZE(i2s_in_muxreg), | |
1243 | }, | |
1244 | }; | |
1245 | ||
1246 | static struct spear_pingroup i2s_in_pingroup = { | |
1247 | .name = "i2s_in_grp", | |
1248 | .pins = i2s_in_pins, | |
1249 | .npins = ARRAY_SIZE(i2s_in_pins), | |
1250 | .modemuxs = i2s_in_modemux, | |
1251 | .nmodemuxs = ARRAY_SIZE(i2s_in_modemux), | |
1252 | }; | |
1253 | ||
1254 | /* pad multiplexing for i2s_out device */ | |
1255 | static const unsigned i2s_out_pins[] = { 95, 96, 97, 98, 100, 101, 102, 103 }; | |
1256 | static struct spear_muxreg i2s_out_muxreg[] = { | |
1257 | { | |
1258 | .reg = PAD_FUNCTION_EN_4, | |
1259 | .mask = I2S_OUT_REG3_MASK, | |
1260 | .val = I2S_OUT_REG3_MASK, | |
1261 | }, | |
1262 | }; | |
1263 | ||
1264 | static struct spear_modemux i2s_out_modemux[] = { | |
1265 | { | |
1266 | .muxregs = i2s_out_muxreg, | |
1267 | .nmuxregs = ARRAY_SIZE(i2s_out_muxreg), | |
1268 | }, | |
1269 | }; | |
1270 | ||
1271 | static struct spear_pingroup i2s_out_pingroup = { | |
1272 | .name = "i2s_out_grp", | |
1273 | .pins = i2s_out_pins, | |
1274 | .npins = ARRAY_SIZE(i2s_out_pins), | |
1275 | .modemuxs = i2s_out_modemux, | |
1276 | .nmodemuxs = ARRAY_SIZE(i2s_out_modemux), | |
1277 | }; | |
1278 | ||
1279 | static const char *const i2s_grps[] = { "i2s_in_grp", "i2s_out_grp" }; | |
1280 | static struct spear_function i2s_function = { | |
1281 | .name = "i2s", | |
1282 | .groups = i2s_grps, | |
1283 | .ngroups = ARRAY_SIZE(i2s_grps), | |
1284 | }; | |
1285 | ||
1286 | /* pad multiplexing for gmac device */ | |
1287 | static const unsigned gmac_pins[] = { 104, 105, 106, 107, 108, 109, 110, 111, | |
1288 | 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, | |
1289 | 126, 127, 128, 129, 130, 131 }; | |
1290 | #define GMAC_MUXREG \ | |
1291 | { \ | |
1292 | .reg = PAD_FUNCTION_EN_4, \ | |
1293 | .mask = GMAC_REG3_MASK, \ | |
1294 | .val = GMAC_REG3_MASK, \ | |
1295 | }, { \ | |
1296 | .reg = PAD_FUNCTION_EN_5, \ | |
1297 | .mask = GMAC_REG4_MASK, \ | |
1298 | .val = GMAC_REG4_MASK, \ | |
1299 | } | |
1300 | ||
1301 | /* pad multiplexing for gmii device */ | |
1302 | static struct spear_muxreg gmii_muxreg[] = { | |
1303 | GMAC_MUXREG, | |
1304 | { | |
1305 | .reg = GMAC_CLK_CFG, | |
1306 | .mask = GMAC_PHY_IF_SEL_MASK, | |
1307 | .val = GMAC_PHY_IF_GMII_VAL, | |
1308 | }, | |
1309 | }; | |
1310 | ||
1311 | static struct spear_modemux gmii_modemux[] = { | |
1312 | { | |
1313 | .muxregs = gmii_muxreg, | |
1314 | .nmuxregs = ARRAY_SIZE(gmii_muxreg), | |
1315 | }, | |
1316 | }; | |
1317 | ||
1318 | static struct spear_pingroup gmii_pingroup = { | |
1319 | .name = "gmii_grp", | |
1320 | .pins = gmac_pins, | |
1321 | .npins = ARRAY_SIZE(gmac_pins), | |
1322 | .modemuxs = gmii_modemux, | |
1323 | .nmodemuxs = ARRAY_SIZE(gmii_modemux), | |
1324 | }; | |
1325 | ||
1326 | /* pad multiplexing for rgmii device */ | |
1327 | static struct spear_muxreg rgmii_muxreg[] = { | |
1328 | GMAC_MUXREG, | |
1329 | { | |
1330 | .reg = GMAC_CLK_CFG, | |
1331 | .mask = GMAC_PHY_IF_SEL_MASK, | |
1332 | .val = GMAC_PHY_IF_RGMII_VAL, | |
1333 | }, | |
1334 | }; | |
1335 | ||
1336 | static struct spear_modemux rgmii_modemux[] = { | |
1337 | { | |
1338 | .muxregs = rgmii_muxreg, | |
1339 | .nmuxregs = ARRAY_SIZE(rgmii_muxreg), | |
1340 | }, | |
1341 | }; | |
1342 | ||
1343 | static struct spear_pingroup rgmii_pingroup = { | |
1344 | .name = "rgmii_grp", | |
1345 | .pins = gmac_pins, | |
1346 | .npins = ARRAY_SIZE(gmac_pins), | |
1347 | .modemuxs = rgmii_modemux, | |
1348 | .nmodemuxs = ARRAY_SIZE(rgmii_modemux), | |
1349 | }; | |
1350 | ||
1351 | /* pad multiplexing for rmii device */ | |
1352 | static struct spear_muxreg rmii_muxreg[] = { | |
1353 | GMAC_MUXREG, | |
1354 | { | |
1355 | .reg = GMAC_CLK_CFG, | |
1356 | .mask = GMAC_PHY_IF_SEL_MASK, | |
1357 | .val = GMAC_PHY_IF_RMII_VAL, | |
1358 | }, | |
1359 | }; | |
1360 | ||
1361 | static struct spear_modemux rmii_modemux[] = { | |
1362 | { | |
1363 | .muxregs = rmii_muxreg, | |
1364 | .nmuxregs = ARRAY_SIZE(rmii_muxreg), | |
1365 | }, | |
1366 | }; | |
1367 | ||
1368 | static struct spear_pingroup rmii_pingroup = { | |
1369 | .name = "rmii_grp", | |
1370 | .pins = gmac_pins, | |
1371 | .npins = ARRAY_SIZE(gmac_pins), | |
1372 | .modemuxs = rmii_modemux, | |
1373 | .nmodemuxs = ARRAY_SIZE(rmii_modemux), | |
1374 | }; | |
1375 | ||
1376 | /* pad multiplexing for sgmii device */ | |
1377 | static struct spear_muxreg sgmii_muxreg[] = { | |
1378 | GMAC_MUXREG, | |
1379 | { | |
1380 | .reg = GMAC_CLK_CFG, | |
1381 | .mask = GMAC_PHY_IF_SEL_MASK, | |
1382 | .val = GMAC_PHY_IF_SGMII_VAL, | |
1383 | }, | |
1384 | }; | |
1385 | ||
1386 | static struct spear_modemux sgmii_modemux[] = { | |
1387 | { | |
1388 | .muxregs = sgmii_muxreg, | |
1389 | .nmuxregs = ARRAY_SIZE(sgmii_muxreg), | |
1390 | }, | |
1391 | }; | |
1392 | ||
1393 | static struct spear_pingroup sgmii_pingroup = { | |
1394 | .name = "sgmii_grp", | |
1395 | .pins = gmac_pins, | |
1396 | .npins = ARRAY_SIZE(gmac_pins), | |
1397 | .modemuxs = sgmii_modemux, | |
1398 | .nmodemuxs = ARRAY_SIZE(sgmii_modemux), | |
1399 | }; | |
1400 | ||
1401 | static const char *const gmac_grps[] = { "gmii_grp", "rgmii_grp", "rmii_grp", | |
1402 | "sgmii_grp" }; | |
1403 | static struct spear_function gmac_function = { | |
1404 | .name = "gmac", | |
1405 | .groups = gmac_grps, | |
1406 | .ngroups = ARRAY_SIZE(gmac_grps), | |
1407 | }; | |
1408 | ||
1409 | /* pad multiplexing for i2c0 device */ | |
1410 | static const unsigned i2c0_pins[] = { 133, 134 }; | |
1411 | static struct spear_muxreg i2c0_muxreg[] = { | |
1412 | { | |
1413 | .reg = PAD_FUNCTION_EN_5, | |
1414 | .mask = I2C0_REG4_MASK, | |
1415 | .val = I2C0_REG4_MASK, | |
1416 | }, | |
1417 | }; | |
1418 | ||
1419 | static struct spear_modemux i2c0_modemux[] = { | |
1420 | { | |
1421 | .muxregs = i2c0_muxreg, | |
1422 | .nmuxregs = ARRAY_SIZE(i2c0_muxreg), | |
1423 | }, | |
1424 | }; | |
1425 | ||
1426 | static struct spear_pingroup i2c0_pingroup = { | |
1427 | .name = "i2c0_grp", | |
1428 | .pins = i2c0_pins, | |
1429 | .npins = ARRAY_SIZE(i2c0_pins), | |
1430 | .modemuxs = i2c0_modemux, | |
1431 | .nmodemuxs = ARRAY_SIZE(i2c0_modemux), | |
1432 | }; | |
1433 | ||
1434 | static const char *const i2c0_grps[] = { "i2c0_grp" }; | |
1435 | static struct spear_function i2c0_function = { | |
1436 | .name = "i2c0", | |
1437 | .groups = i2c0_grps, | |
1438 | .ngroups = ARRAY_SIZE(i2c0_grps), | |
1439 | }; | |
1440 | ||
1441 | /* pad multiplexing for i2c1 device */ | |
1442 | static const unsigned i2c1_pins[] = { 18, 23 }; | |
1443 | static struct spear_muxreg i2c1_muxreg[] = { | |
1444 | { | |
1445 | .reg = PAD_FUNCTION_EN_1, | |
1446 | .mask = I2C1_REG0_MASK, | |
1447 | .val = I2C1_REG0_MASK, | |
1448 | }, | |
1449 | }; | |
1450 | ||
1451 | static struct spear_modemux i2c1_modemux[] = { | |
1452 | { | |
1453 | .muxregs = i2c1_muxreg, | |
1454 | .nmuxregs = ARRAY_SIZE(i2c1_muxreg), | |
1455 | }, | |
1456 | }; | |
1457 | ||
1458 | static struct spear_pingroup i2c1_pingroup = { | |
1459 | .name = "i2c1_grp", | |
1460 | .pins = i2c1_pins, | |
1461 | .npins = ARRAY_SIZE(i2c1_pins), | |
1462 | .modemuxs = i2c1_modemux, | |
1463 | .nmodemuxs = ARRAY_SIZE(i2c1_modemux), | |
1464 | }; | |
1465 | ||
1466 | static const char *const i2c1_grps[] = { "i2c1_grp" }; | |
1467 | static struct spear_function i2c1_function = { | |
1468 | .name = "i2c1", | |
1469 | .groups = i2c1_grps, | |
1470 | .ngroups = ARRAY_SIZE(i2c1_grps), | |
1471 | }; | |
1472 | ||
1473 | /* pad multiplexing for cec0 device */ | |
1474 | static const unsigned cec0_pins[] = { 135 }; | |
1475 | static struct spear_muxreg cec0_muxreg[] = { | |
1476 | { | |
1477 | .reg = PAD_FUNCTION_EN_5, | |
1478 | .mask = CEC0_REG4_MASK, | |
1479 | .val = CEC0_REG4_MASK, | |
1480 | }, | |
1481 | }; | |
1482 | ||
1483 | static struct spear_modemux cec0_modemux[] = { | |
1484 | { | |
1485 | .muxregs = cec0_muxreg, | |
1486 | .nmuxregs = ARRAY_SIZE(cec0_muxreg), | |
1487 | }, | |
1488 | }; | |
1489 | ||
1490 | static struct spear_pingroup cec0_pingroup = { | |
1491 | .name = "cec0_grp", | |
1492 | .pins = cec0_pins, | |
1493 | .npins = ARRAY_SIZE(cec0_pins), | |
1494 | .modemuxs = cec0_modemux, | |
1495 | .nmodemuxs = ARRAY_SIZE(cec0_modemux), | |
1496 | }; | |
1497 | ||
1498 | static const char *const cec0_grps[] = { "cec0_grp" }; | |
1499 | static struct spear_function cec0_function = { | |
1500 | .name = "cec0", | |
1501 | .groups = cec0_grps, | |
1502 | .ngroups = ARRAY_SIZE(cec0_grps), | |
1503 | }; | |
1504 | ||
1505 | /* pad multiplexing for cec1 device */ | |
1506 | static const unsigned cec1_pins[] = { 136 }; | |
1507 | static struct spear_muxreg cec1_muxreg[] = { | |
1508 | { | |
1509 | .reg = PAD_FUNCTION_EN_5, | |
1510 | .mask = CEC1_REG4_MASK, | |
1511 | .val = CEC1_REG4_MASK, | |
1512 | }, | |
1513 | }; | |
1514 | ||
1515 | static struct spear_modemux cec1_modemux[] = { | |
1516 | { | |
1517 | .muxregs = cec1_muxreg, | |
1518 | .nmuxregs = ARRAY_SIZE(cec1_muxreg), | |
1519 | }, | |
1520 | }; | |
1521 | ||
1522 | static struct spear_pingroup cec1_pingroup = { | |
1523 | .name = "cec1_grp", | |
1524 | .pins = cec1_pins, | |
1525 | .npins = ARRAY_SIZE(cec1_pins), | |
1526 | .modemuxs = cec1_modemux, | |
1527 | .nmodemuxs = ARRAY_SIZE(cec1_modemux), | |
1528 | }; | |
1529 | ||
1530 | static const char *const cec1_grps[] = { "cec1_grp" }; | |
1531 | static struct spear_function cec1_function = { | |
1532 | .name = "cec1", | |
1533 | .groups = cec1_grps, | |
1534 | .ngroups = ARRAY_SIZE(cec1_grps), | |
1535 | }; | |
1536 | ||
1537 | /* pad multiplexing for mcif devices */ | |
1538 | static const unsigned mcif_pins[] = { 193, 194, 195, 196, 197, 198, 199, 200, | |
1539 | 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, | |
1540 | 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, | |
1541 | 229, 230, 231, 232, 237 }; | |
1542 | #define MCIF_MUXREG \ | |
1543 | { \ | |
1544 | .reg = PAD_SHARED_IP_EN_1, \ | |
1545 | .mask = MCIF_MASK, \ | |
1546 | .val = MCIF_MASK, \ | |
1547 | }, { \ | |
1548 | .reg = PAD_FUNCTION_EN_7, \ | |
1549 | .mask = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ | |
1550 | .val = FSMC_PNOR_AND_MCIF_REG6_MASK | MCIF_REG6_MASK, \ | |
1551 | }, { \ | |
1552 | .reg = PAD_FUNCTION_EN_8, \ | |
1553 | .mask = MCIF_REG7_MASK, \ | |
1554 | .val = MCIF_REG7_MASK, \ | |
1555 | } | |
1556 | ||
1557 | /* Pad multiplexing for sdhci device */ | |
1558 | static struct spear_muxreg sdhci_muxreg[] = { | |
1559 | MCIF_MUXREG, | |
1560 | { | |
1561 | .reg = PERIP_CFG, | |
1562 | .mask = MCIF_SEL_MASK, | |
1563 | .val = MCIF_SEL_SD, | |
1564 | }, | |
1565 | }; | |
1566 | ||
1567 | static struct spear_modemux sdhci_modemux[] = { | |
1568 | { | |
1569 | .muxregs = sdhci_muxreg, | |
1570 | .nmuxregs = ARRAY_SIZE(sdhci_muxreg), | |
1571 | }, | |
1572 | }; | |
1573 | ||
1574 | static struct spear_pingroup sdhci_pingroup = { | |
1575 | .name = "sdhci_grp", | |
1576 | .pins = mcif_pins, | |
1577 | .npins = ARRAY_SIZE(mcif_pins), | |
1578 | .modemuxs = sdhci_modemux, | |
1579 | .nmodemuxs = ARRAY_SIZE(sdhci_modemux), | |
1580 | }; | |
1581 | ||
1582 | static const char *const sdhci_grps[] = { "sdhci_grp" }; | |
1583 | static struct spear_function sdhci_function = { | |
1584 | .name = "sdhci", | |
1585 | .groups = sdhci_grps, | |
1586 | .ngroups = ARRAY_SIZE(sdhci_grps), | |
1587 | }; | |
1588 | ||
1589 | /* Pad multiplexing for cf device */ | |
1590 | static struct spear_muxreg cf_muxreg[] = { | |
1591 | MCIF_MUXREG, | |
1592 | { | |
1593 | .reg = PERIP_CFG, | |
1594 | .mask = MCIF_SEL_MASK, | |
1595 | .val = MCIF_SEL_CF, | |
1596 | }, | |
1597 | }; | |
1598 | ||
1599 | static struct spear_modemux cf_modemux[] = { | |
1600 | { | |
1601 | .muxregs = cf_muxreg, | |
1602 | .nmuxregs = ARRAY_SIZE(cf_muxreg), | |
1603 | }, | |
1604 | }; | |
1605 | ||
1606 | static struct spear_pingroup cf_pingroup = { | |
1607 | .name = "cf_grp", | |
1608 | .pins = mcif_pins, | |
1609 | .npins = ARRAY_SIZE(mcif_pins), | |
1610 | .modemuxs = cf_modemux, | |
1611 | .nmodemuxs = ARRAY_SIZE(cf_modemux), | |
1612 | }; | |
1613 | ||
1614 | static const char *const cf_grps[] = { "cf_grp" }; | |
1615 | static struct spear_function cf_function = { | |
1616 | .name = "cf", | |
1617 | .groups = cf_grps, | |
1618 | .ngroups = ARRAY_SIZE(cf_grps), | |
1619 | }; | |
1620 | ||
1621 | /* Pad multiplexing for xd device */ | |
1622 | static struct spear_muxreg xd_muxreg[] = { | |
1623 | MCIF_MUXREG, | |
1624 | { | |
1625 | .reg = PERIP_CFG, | |
1626 | .mask = MCIF_SEL_MASK, | |
1627 | .val = MCIF_SEL_XD, | |
1628 | }, | |
1629 | }; | |
1630 | ||
1631 | static struct spear_modemux xd_modemux[] = { | |
1632 | { | |
1633 | .muxregs = xd_muxreg, | |
1634 | .nmuxregs = ARRAY_SIZE(xd_muxreg), | |
1635 | }, | |
1636 | }; | |
1637 | ||
1638 | static struct spear_pingroup xd_pingroup = { | |
1639 | .name = "xd_grp", | |
1640 | .pins = mcif_pins, | |
1641 | .npins = ARRAY_SIZE(mcif_pins), | |
1642 | .modemuxs = xd_modemux, | |
1643 | .nmodemuxs = ARRAY_SIZE(xd_modemux), | |
1644 | }; | |
1645 | ||
1646 | static const char *const xd_grps[] = { "xd_grp" }; | |
1647 | static struct spear_function xd_function = { | |
1648 | .name = "xd", | |
1649 | .groups = xd_grps, | |
1650 | .ngroups = ARRAY_SIZE(xd_grps), | |
1651 | }; | |
1652 | ||
1653 | /* pad multiplexing for clcd device */ | |
1654 | static const unsigned clcd_pins[] = { 138, 139, 140, 141, 142, 143, 144, 145, | |
1655 | 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, | |
1656 | 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, | |
1657 | 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, | |
1658 | 188, 189, 190, 191 }; | |
1659 | static struct spear_muxreg clcd_muxreg[] = { | |
1660 | { | |
1661 | .reg = PAD_SHARED_IP_EN_1, | |
1662 | .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, | |
1663 | .val = 0, | |
1664 | }, { | |
1665 | .reg = PAD_FUNCTION_EN_5, | |
1666 | .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, | |
1667 | .val = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, | |
1668 | }, { | |
1669 | .reg = PAD_FUNCTION_EN_6, | |
1670 | .mask = CLCD_AND_ARM_TRACE_REG5_MASK, | |
1671 | .val = CLCD_AND_ARM_TRACE_REG5_MASK, | |
1672 | }, { | |
1673 | .reg = PAD_FUNCTION_EN_7, | |
1674 | .mask = CLCD_AND_ARM_TRACE_REG6_MASK, | |
1675 | .val = CLCD_AND_ARM_TRACE_REG6_MASK, | |
1676 | }, | |
1677 | }; | |
1678 | ||
1679 | static struct spear_modemux clcd_modemux[] = { | |
1680 | { | |
1681 | .muxregs = clcd_muxreg, | |
1682 | .nmuxregs = ARRAY_SIZE(clcd_muxreg), | |
1683 | }, | |
1684 | }; | |
1685 | ||
1686 | static struct spear_pingroup clcd_pingroup = { | |
1687 | .name = "clcd_grp", | |
1688 | .pins = clcd_pins, | |
1689 | .npins = ARRAY_SIZE(clcd_pins), | |
1690 | .modemuxs = clcd_modemux, | |
1691 | .nmodemuxs = ARRAY_SIZE(clcd_modemux), | |
1692 | }; | |
1693 | ||
0504271c VKS |
1694 | /* Disable cld runtime to save panel damage */ |
1695 | static struct spear_muxreg clcd_sleep_muxreg[] = { | |
1696 | { | |
1697 | .reg = PAD_SHARED_IP_EN_1, | |
1698 | .mask = ARM_TRACE_MASK | MIPHY_DBG_MASK, | |
1699 | .val = 0, | |
1700 | }, { | |
1701 | .reg = PAD_FUNCTION_EN_5, | |
1702 | .mask = CLCD_REG4_MASK | CLCD_AND_ARM_TRACE_REG4_MASK, | |
1703 | .val = 0x0, | |
1704 | }, { | |
1705 | .reg = PAD_FUNCTION_EN_6, | |
1706 | .mask = CLCD_AND_ARM_TRACE_REG5_MASK, | |
1707 | .val = 0x0, | |
1708 | }, { | |
1709 | .reg = PAD_FUNCTION_EN_7, | |
1710 | .mask = CLCD_AND_ARM_TRACE_REG6_MASK, | |
1711 | .val = 0x0, | |
1712 | }, | |
1713 | }; | |
1714 | ||
1715 | static struct spear_modemux clcd_sleep_modemux[] = { | |
1716 | { | |
1717 | .muxregs = clcd_sleep_muxreg, | |
1718 | .nmuxregs = ARRAY_SIZE(clcd_sleep_muxreg), | |
1719 | }, | |
1720 | }; | |
1721 | ||
1722 | static struct spear_pingroup clcd_sleep_pingroup = { | |
1723 | .name = "clcd_sleep_grp", | |
1724 | .pins = clcd_pins, | |
1725 | .npins = ARRAY_SIZE(clcd_pins), | |
1726 | .modemuxs = clcd_sleep_modemux, | |
1727 | .nmodemuxs = ARRAY_SIZE(clcd_sleep_modemux), | |
1728 | }; | |
1729 | ||
1730 | static const char *const clcd_grps[] = { "clcd_grp", "clcd_sleep_grp" }; | |
85ed41a7 VK |
1731 | static struct spear_function clcd_function = { |
1732 | .name = "clcd", | |
1733 | .groups = clcd_grps, | |
1734 | .ngroups = ARRAY_SIZE(clcd_grps), | |
1735 | }; | |
1736 | ||
1737 | /* pad multiplexing for arm_trace device */ | |
1738 | static const unsigned arm_trace_pins[] = { 158, 159, 160, 161, 162, 163, 164, | |
1739 | 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, | |
1740 | 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, | |
1741 | 193, 194, 195, 196, 197, 198, 199, 200 }; | |
1742 | static struct spear_muxreg arm_trace_muxreg[] = { | |
1743 | { | |
1744 | .reg = PAD_SHARED_IP_EN_1, | |
1745 | .mask = ARM_TRACE_MASK, | |
1746 | .val = ARM_TRACE_MASK, | |
1747 | }, { | |
1748 | .reg = PAD_FUNCTION_EN_5, | |
1749 | .mask = CLCD_AND_ARM_TRACE_REG4_MASK, | |
1750 | .val = CLCD_AND_ARM_TRACE_REG4_MASK, | |
1751 | }, { | |
1752 | .reg = PAD_FUNCTION_EN_6, | |
1753 | .mask = CLCD_AND_ARM_TRACE_REG5_MASK, | |
1754 | .val = CLCD_AND_ARM_TRACE_REG5_MASK, | |
1755 | }, { | |
1756 | .reg = PAD_FUNCTION_EN_7, | |
1757 | .mask = CLCD_AND_ARM_TRACE_REG6_MASK, | |
1758 | .val = CLCD_AND_ARM_TRACE_REG6_MASK, | |
1759 | }, | |
1760 | }; | |
1761 | ||
1762 | static struct spear_modemux arm_trace_modemux[] = { | |
1763 | { | |
1764 | .muxregs = arm_trace_muxreg, | |
1765 | .nmuxregs = ARRAY_SIZE(arm_trace_muxreg), | |
1766 | }, | |
1767 | }; | |
1768 | ||
1769 | static struct spear_pingroup arm_trace_pingroup = { | |
1770 | .name = "arm_trace_grp", | |
1771 | .pins = arm_trace_pins, | |
1772 | .npins = ARRAY_SIZE(arm_trace_pins), | |
1773 | .modemuxs = arm_trace_modemux, | |
1774 | .nmodemuxs = ARRAY_SIZE(arm_trace_modemux), | |
1775 | }; | |
1776 | ||
1777 | static const char *const arm_trace_grps[] = { "arm_trace_grp" }; | |
1778 | static struct spear_function arm_trace_function = { | |
1779 | .name = "arm_trace", | |
1780 | .groups = arm_trace_grps, | |
1781 | .ngroups = ARRAY_SIZE(arm_trace_grps), | |
1782 | }; | |
1783 | ||
1784 | /* pad multiplexing for miphy_dbg device */ | |
1785 | static const unsigned miphy_dbg_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, | |
1786 | 132, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, | |
1787 | 148, 149, 150, 151, 152, 153, 154, 155, 156, 157 }; | |
1788 | static struct spear_muxreg miphy_dbg_muxreg[] = { | |
1789 | { | |
1790 | .reg = PAD_SHARED_IP_EN_1, | |
1791 | .mask = MIPHY_DBG_MASK, | |
1792 | .val = MIPHY_DBG_MASK, | |
1793 | }, { | |
1794 | .reg = PAD_FUNCTION_EN_5, | |
1795 | .mask = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, | |
1796 | .val = DEVS_GRP_AND_MIPHY_DBG_REG4_MASK, | |
1797 | }, | |
1798 | }; | |
1799 | ||
1800 | static struct spear_modemux miphy_dbg_modemux[] = { | |
1801 | { | |
1802 | .muxregs = miphy_dbg_muxreg, | |
1803 | .nmuxregs = ARRAY_SIZE(miphy_dbg_muxreg), | |
1804 | }, | |
1805 | }; | |
1806 | ||
1807 | static struct spear_pingroup miphy_dbg_pingroup = { | |
1808 | .name = "miphy_dbg_grp", | |
1809 | .pins = miphy_dbg_pins, | |
1810 | .npins = ARRAY_SIZE(miphy_dbg_pins), | |
1811 | .modemuxs = miphy_dbg_modemux, | |
1812 | .nmodemuxs = ARRAY_SIZE(miphy_dbg_modemux), | |
1813 | }; | |
1814 | ||
1815 | static const char *const miphy_dbg_grps[] = { "miphy_dbg_grp" }; | |
1816 | static struct spear_function miphy_dbg_function = { | |
1817 | .name = "miphy_dbg", | |
1818 | .groups = miphy_dbg_grps, | |
1819 | .ngroups = ARRAY_SIZE(miphy_dbg_grps), | |
1820 | }; | |
1821 | ||
1822 | /* pad multiplexing for pcie device */ | |
1823 | static const unsigned pcie_pins[] = { 250 }; | |
1824 | static struct spear_muxreg pcie_muxreg[] = { | |
1825 | { | |
1826 | .reg = PCIE_SATA_CFG, | |
1827 | .mask = SATA_PCIE_CFG_MASK, | |
1828 | .val = PCIE_CFG_VAL, | |
1829 | }, | |
1830 | }; | |
1831 | ||
1832 | static struct spear_modemux pcie_modemux[] = { | |
1833 | { | |
1834 | .muxregs = pcie_muxreg, | |
1835 | .nmuxregs = ARRAY_SIZE(pcie_muxreg), | |
1836 | }, | |
1837 | }; | |
1838 | ||
1839 | static struct spear_pingroup pcie_pingroup = { | |
1840 | .name = "pcie_grp", | |
1841 | .pins = pcie_pins, | |
1842 | .npins = ARRAY_SIZE(pcie_pins), | |
1843 | .modemuxs = pcie_modemux, | |
1844 | .nmodemuxs = ARRAY_SIZE(pcie_modemux), | |
1845 | }; | |
1846 | ||
1847 | static const char *const pcie_grps[] = { "pcie_grp" }; | |
1848 | static struct spear_function pcie_function = { | |
1849 | .name = "pcie", | |
1850 | .groups = pcie_grps, | |
1851 | .ngroups = ARRAY_SIZE(pcie_grps), | |
1852 | }; | |
1853 | ||
1854 | /* pad multiplexing for sata device */ | |
1855 | static const unsigned sata_pins[] = { 250 }; | |
1856 | static struct spear_muxreg sata_muxreg[] = { | |
1857 | { | |
1858 | .reg = PCIE_SATA_CFG, | |
1859 | .mask = SATA_PCIE_CFG_MASK, | |
1860 | .val = SATA_CFG_VAL, | |
1861 | }, | |
1862 | }; | |
1863 | ||
1864 | static struct spear_modemux sata_modemux[] = { | |
1865 | { | |
1866 | .muxregs = sata_muxreg, | |
1867 | .nmuxregs = ARRAY_SIZE(sata_muxreg), | |
1868 | }, | |
1869 | }; | |
1870 | ||
1871 | static struct spear_pingroup sata_pingroup = { | |
1872 | .name = "sata_grp", | |
1873 | .pins = sata_pins, | |
1874 | .npins = ARRAY_SIZE(sata_pins), | |
1875 | .modemuxs = sata_modemux, | |
1876 | .nmodemuxs = ARRAY_SIZE(sata_modemux), | |
1877 | }; | |
1878 | ||
1879 | static const char *const sata_grps[] = { "sata_grp" }; | |
1880 | static struct spear_function sata_function = { | |
1881 | .name = "sata", | |
1882 | .groups = sata_grps, | |
1883 | .ngroups = ARRAY_SIZE(sata_grps), | |
1884 | }; | |
1885 | ||
1886 | /* pingroups */ | |
1887 | static struct spear_pingroup *spear1340_pingroups[] = { | |
1888 | &pads_as_gpio_pingroup, | |
1889 | &fsmc_8bit_pingroup, | |
1890 | &fsmc_16bit_pingroup, | |
1891 | &fsmc_pnor_pingroup, | |
1892 | &keyboard_row_col_pingroup, | |
1893 | &keyboard_col5_pingroup, | |
1894 | &spdif_in_pingroup, | |
1895 | &spdif_out_pingroup, | |
1896 | &gpt_0_1_pingroup, | |
1897 | &pwm0_pingroup, | |
1898 | &pwm1_pingroup, | |
1899 | &pwm2_pingroup, | |
1900 | &pwm3_pingroup, | |
1901 | &vip_mux_pingroup, | |
1902 | &vip_mux_cam0_pingroup, | |
1903 | &vip_mux_cam1_pingroup, | |
1904 | &vip_mux_cam2_pingroup, | |
1905 | &vip_mux_cam3_pingroup, | |
1906 | &cam0_pingroup, | |
1907 | &cam1_pingroup, | |
1908 | &cam2_pingroup, | |
1909 | &cam3_pingroup, | |
1910 | &smi_pingroup, | |
1911 | &ssp0_pingroup, | |
1912 | &ssp0_cs1_pingroup, | |
1913 | &ssp0_cs2_pingroup, | |
1914 | &ssp0_cs3_pingroup, | |
1915 | &uart0_pingroup, | |
1916 | &uart0_enh_pingroup, | |
1917 | &uart1_pingroup, | |
1918 | &i2s_in_pingroup, | |
1919 | &i2s_out_pingroup, | |
1920 | &gmii_pingroup, | |
1921 | &rgmii_pingroup, | |
1922 | &rmii_pingroup, | |
1923 | &sgmii_pingroup, | |
1924 | &i2c0_pingroup, | |
1925 | &i2c1_pingroup, | |
1926 | &cec0_pingroup, | |
1927 | &cec1_pingroup, | |
1928 | &sdhci_pingroup, | |
1929 | &cf_pingroup, | |
1930 | &xd_pingroup, | |
0504271c | 1931 | &clcd_sleep_pingroup, |
85ed41a7 VK |
1932 | &clcd_pingroup, |
1933 | &arm_trace_pingroup, | |
1934 | &miphy_dbg_pingroup, | |
1935 | &pcie_pingroup, | |
1936 | &sata_pingroup, | |
1937 | }; | |
1938 | ||
1939 | /* functions */ | |
1940 | static struct spear_function *spear1340_functions[] = { | |
1941 | &pads_as_gpio_function, | |
1942 | &fsmc_function, | |
1943 | &keyboard_function, | |
1944 | &spdif_in_function, | |
1945 | &spdif_out_function, | |
1946 | &gpt_0_1_function, | |
1947 | &pwm_function, | |
1948 | &vip_function, | |
1949 | &cam0_function, | |
1950 | &cam1_function, | |
1951 | &cam2_function, | |
1952 | &cam3_function, | |
1953 | &smi_function, | |
1954 | &ssp0_function, | |
1955 | &uart0_function, | |
1956 | &uart1_function, | |
1957 | &i2s_function, | |
1958 | &gmac_function, | |
1959 | &i2c0_function, | |
1960 | &i2c1_function, | |
1961 | &cec0_function, | |
1962 | &cec1_function, | |
1963 | &sdhci_function, | |
1964 | &cf_function, | |
1965 | &xd_function, | |
1966 | &clcd_function, | |
1967 | &arm_trace_function, | |
1968 | &miphy_dbg_function, | |
1969 | &pcie_function, | |
1970 | &sata_function, | |
1971 | }; | |
1972 | ||
826d6ca8 SH |
1973 | static void gpio_request_endisable(struct spear_pmx *pmx, int pin, |
1974 | bool enable) | |
1975 | { | |
1976 | unsigned int regoffset, regindex, bitoffset; | |
1977 | unsigned int val; | |
1978 | ||
1979 | /* pin++ as gpio configuration starts from 2nd bit of base register */ | |
1980 | pin++; | |
1981 | ||
1982 | regindex = pin / 32; | |
1983 | bitoffset = pin % 32; | |
1984 | ||
1985 | if (regindex <= 3) | |
1986 | regoffset = PAD_FUNCTION_EN_1 + regindex * sizeof(int *); | |
1987 | else | |
1988 | regoffset = PAD_FUNCTION_EN_5 + (regindex - 4) * sizeof(int *); | |
1989 | ||
1990 | val = pmx_readl(pmx, regoffset); | |
1991 | if (enable) | |
1992 | val &= ~(0x1 << bitoffset); | |
1993 | else | |
1994 | val |= 0x1 << bitoffset; | |
1995 | ||
1996 | pmx_writel(pmx, val, regoffset); | |
1997 | } | |
1998 | ||
85ed41a7 VK |
1999 | static struct spear_pinctrl_machdata spear1340_machdata = { |
2000 | .pins = spear1340_pins, | |
2001 | .npins = ARRAY_SIZE(spear1340_pins), | |
2002 | .groups = spear1340_pingroups, | |
2003 | .ngroups = ARRAY_SIZE(spear1340_pingroups), | |
2004 | .functions = spear1340_functions, | |
2005 | .nfunctions = ARRAY_SIZE(spear1340_functions), | |
826d6ca8 | 2006 | .gpio_request_endisable = gpio_request_endisable, |
85ed41a7 VK |
2007 | .modes_supported = false, |
2008 | }; | |
2009 | ||
5dfe10b4 | 2010 | static const struct of_device_id spear1340_pinctrl_of_match[] = { |
85ed41a7 VK |
2011 | { |
2012 | .compatible = "st,spear1340-pinmux", | |
2013 | }, | |
2014 | {}, | |
2015 | }; | |
2016 | ||
150632b0 | 2017 | static int spear1340_pinctrl_probe(struct platform_device *pdev) |
85ed41a7 VK |
2018 | { |
2019 | return spear_pinctrl_probe(pdev, &spear1340_machdata); | |
2020 | } | |
2021 | ||
85ed41a7 VK |
2022 | static struct platform_driver spear1340_pinctrl_driver = { |
2023 | .driver = { | |
2024 | .name = DRIVER_NAME, | |
85ed41a7 VK |
2025 | .of_match_table = spear1340_pinctrl_of_match, |
2026 | }, | |
2027 | .probe = spear1340_pinctrl_probe, | |
85ed41a7 VK |
2028 | }; |
2029 | ||
2030 | static int __init spear1340_pinctrl_init(void) | |
2031 | { | |
2032 | return platform_driver_register(&spear1340_pinctrl_driver); | |
2033 | } | |
2034 | arch_initcall(spear1340_pinctrl_init); |