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aceb16dc MC |
1 | /* |
2 | * Copyright (C) Maxime Coquelin 2015 | |
3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | * | |
6 | * Heavily based on Mediatek's pinctrl driver | |
7 | */ | |
8 | #include <linux/clk.h> | |
1300568a | 9 | #include <linux/gpio/driver.h> |
aceb16dc | 10 | #include <linux/io.h> |
0eb9f683 AT |
11 | #include <linux/irq.h> |
12 | #include <linux/mfd/syscon.h> | |
aceb16dc MC |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_device.h> | |
17 | #include <linux/of_irq.h> | |
18 | #include <linux/pinctrl/consumer.h> | |
19 | #include <linux/pinctrl/machine.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/platform_device.h> | |
0eb9f683 | 25 | #include <linux/regmap.h> |
aceb16dc MC |
26 | #include <linux/reset.h> |
27 | #include <linux/slab.h> | |
28 | ||
aceb16dc MC |
29 | #include "../core.h" |
30 | #include "../pinconf.h" | |
31 | #include "../pinctrl-utils.h" | |
32 | #include "pinctrl-stm32.h" | |
33 | ||
34 | #define STM32_GPIO_MODER 0x00 | |
35 | #define STM32_GPIO_TYPER 0x04 | |
36 | #define STM32_GPIO_SPEEDR 0x08 | |
37 | #define STM32_GPIO_PUPDR 0x0c | |
38 | #define STM32_GPIO_IDR 0x10 | |
39 | #define STM32_GPIO_ODR 0x14 | |
40 | #define STM32_GPIO_BSRR 0x18 | |
41 | #define STM32_GPIO_LCKR 0x1c | |
42 | #define STM32_GPIO_AFRL 0x20 | |
43 | #define STM32_GPIO_AFRH 0x24 | |
44 | ||
45 | #define STM32_GPIO_PINS_PER_BANK 16 | |
0eb9f683 | 46 | #define STM32_GPIO_IRQ_LINE 16 |
aceb16dc MC |
47 | |
48 | #define gpio_range_to_bank(chip) \ | |
49 | container_of(chip, struct stm32_gpio_bank, range) | |
50 | ||
aceb16dc MC |
51 | static const char * const stm32_gpio_functions[] = { |
52 | "gpio", "af0", "af1", | |
53 | "af2", "af3", "af4", | |
54 | "af5", "af6", "af7", | |
55 | "af8", "af9", "af10", | |
56 | "af11", "af12", "af13", | |
57 | "af14", "af15", "analog", | |
58 | }; | |
59 | ||
60 | struct stm32_pinctrl_group { | |
61 | const char *name; | |
62 | unsigned long config; | |
63 | unsigned pin; | |
64 | }; | |
65 | ||
66 | struct stm32_gpio_bank { | |
67 | void __iomem *base; | |
68 | struct clk *clk; | |
69 | spinlock_t lock; | |
70 | struct gpio_chip gpio_chip; | |
71 | struct pinctrl_gpio_range range; | |
0eb9f683 AT |
72 | struct fwnode_handle *fwnode; |
73 | struct irq_domain *domain; | |
1dc9d289 | 74 | u32 bank_nr; |
aceb16dc MC |
75 | }; |
76 | ||
77 | struct stm32_pinctrl { | |
78 | struct device *dev; | |
79 | struct pinctrl_dev *pctl_dev; | |
80 | struct pinctrl_desc pctl_desc; | |
81 | struct stm32_pinctrl_group *groups; | |
82 | unsigned ngroups; | |
83 | const char **grp_names; | |
84 | struct stm32_gpio_bank *banks; | |
85 | unsigned nbanks; | |
86 | const struct stm32_pinctrl_match_data *match_data; | |
0eb9f683 AT |
87 | struct irq_domain *domain; |
88 | struct regmap *regmap; | |
89 | struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; | |
aceb16dc MC |
90 | }; |
91 | ||
92 | static inline int stm32_gpio_pin(int gpio) | |
93 | { | |
94 | return gpio % STM32_GPIO_PINS_PER_BANK; | |
95 | } | |
96 | ||
97 | static inline u32 stm32_gpio_get_mode(u32 function) | |
98 | { | |
99 | switch (function) { | |
100 | case STM32_PIN_GPIO: | |
101 | return 0; | |
102 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
103 | return 2; | |
104 | case STM32_PIN_ANALOG: | |
105 | return 3; | |
106 | } | |
107 | ||
108 | return 0; | |
109 | } | |
110 | ||
111 | static inline u32 stm32_gpio_get_alt(u32 function) | |
112 | { | |
113 | switch (function) { | |
114 | case STM32_PIN_GPIO: | |
115 | return 0; | |
116 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
117 | return function - 1; | |
118 | case STM32_PIN_ANALOG: | |
119 | return 0; | |
120 | } | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | /* GPIO functions */ | |
126 | ||
127 | static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, | |
128 | unsigned offset, int value) | |
129 | { | |
130 | if (!value) | |
131 | offset += STM32_GPIO_PINS_PER_BANK; | |
132 | ||
133 | clk_enable(bank->clk); | |
134 | ||
135 | writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); | |
136 | ||
137 | clk_disable(bank->clk); | |
138 | } | |
139 | ||
140 | static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) | |
141 | { | |
1dc9d289 AT |
142 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
143 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
144 | struct pinctrl_gpio_range *range; | |
145 | int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); | |
146 | ||
147 | range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); | |
148 | if (!range) { | |
149 | dev_err(pctl->dev, "pin %d not in range.\n", pin); | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
aceb16dc MC |
153 | return pinctrl_request_gpio(chip->base + offset); |
154 | } | |
155 | ||
156 | static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) | |
157 | { | |
158 | pinctrl_free_gpio(chip->base + offset); | |
159 | } | |
160 | ||
161 | static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) | |
162 | { | |
1300568a | 163 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
164 | int ret; |
165 | ||
166 | clk_enable(bank->clk); | |
167 | ||
168 | ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); | |
169 | ||
170 | clk_disable(bank->clk); | |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
175 | static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
176 | { | |
1300568a | 177 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
178 | |
179 | __stm32_gpio_set(bank, offset, value); | |
180 | } | |
181 | ||
182 | static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
183 | { | |
184 | return pinctrl_gpio_direction_input(chip->base + offset); | |
185 | } | |
186 | ||
187 | static int stm32_gpio_direction_output(struct gpio_chip *chip, | |
188 | unsigned offset, int value) | |
189 | { | |
1300568a | 190 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
191 | |
192 | __stm32_gpio_set(bank, offset, value); | |
193 | pinctrl_gpio_direction_output(chip->base + offset); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
0eb9f683 AT |
198 | |
199 | static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) | |
200 | { | |
201 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); | |
202 | struct irq_fwspec fwspec; | |
203 | ||
204 | fwspec.fwnode = bank->fwnode; | |
205 | fwspec.param_count = 2; | |
206 | fwspec.param[0] = offset; | |
207 | fwspec.param[1] = IRQ_TYPE_NONE; | |
208 | ||
209 | return irq_create_fwspec_mapping(&fwspec); | |
210 | } | |
211 | ||
acaa0379 AT |
212 | static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
213 | { | |
214 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); | |
215 | int pin = stm32_gpio_pin(offset); | |
216 | int ret; | |
217 | u32 mode, alt; | |
218 | ||
219 | stm32_pmx_get_mode(bank, pin, &mode, &alt); | |
220 | if ((alt == 0) && (mode == 0)) | |
221 | ret = 1; | |
222 | else if ((alt == 0) && (mode == 1)) | |
223 | ret = 0; | |
224 | else | |
225 | ret = -EINVAL; | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
d9048cdb | 230 | static const struct gpio_chip stm32_gpio_template = { |
aceb16dc MC |
231 | .request = stm32_gpio_request, |
232 | .free = stm32_gpio_free, | |
233 | .get = stm32_gpio_get, | |
234 | .set = stm32_gpio_set, | |
235 | .direction_input = stm32_gpio_direction_input, | |
236 | .direction_output = stm32_gpio_direction_output, | |
0eb9f683 | 237 | .to_irq = stm32_gpio_to_irq, |
acaa0379 | 238 | .get_direction = stm32_gpio_get_direction, |
aceb16dc MC |
239 | }; |
240 | ||
9efa6d1a AT |
241 | static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) |
242 | { | |
243 | struct stm32_gpio_bank *bank = irq_data->domain->host_data; | |
244 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
245 | int ret; | |
246 | ||
247 | ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
251 | ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); | |
252 | if (ret) { | |
253 | dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
254 | irq_data->hwirq); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) | |
262 | { | |
263 | struct stm32_gpio_bank *bank = irq_data->domain->host_data; | |
264 | ||
265 | gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); | |
266 | } | |
267 | ||
0eb9f683 AT |
268 | static struct irq_chip stm32_gpio_irq_chip = { |
269 | .name = "stm32gpio", | |
270 | .irq_eoi = irq_chip_eoi_parent, | |
271 | .irq_mask = irq_chip_mask_parent, | |
272 | .irq_unmask = irq_chip_unmask_parent, | |
273 | .irq_set_type = irq_chip_set_type_parent, | |
9efa6d1a AT |
274 | .irq_request_resources = stm32_gpio_irq_request_resources, |
275 | .irq_release_resources = stm32_gpio_irq_release_resources, | |
0eb9f683 AT |
276 | }; |
277 | ||
278 | static int stm32_gpio_domain_translate(struct irq_domain *d, | |
279 | struct irq_fwspec *fwspec, | |
280 | unsigned long *hwirq, | |
281 | unsigned int *type) | |
282 | { | |
283 | if ((fwspec->param_count != 2) || | |
284 | (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) | |
285 | return -EINVAL; | |
286 | ||
287 | *hwirq = fwspec->param[0]; | |
288 | *type = fwspec->param[1]; | |
289 | return 0; | |
290 | } | |
aceb16dc | 291 | |
0eb9f683 AT |
292 | static void stm32_gpio_domain_activate(struct irq_domain *d, |
293 | struct irq_data *irq_data) | |
294 | { | |
295 | struct stm32_gpio_bank *bank = d->host_data; | |
296 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
297 | ||
1dc9d289 | 298 | regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); |
0eb9f683 AT |
299 | } |
300 | ||
301 | static int stm32_gpio_domain_alloc(struct irq_domain *d, | |
302 | unsigned int virq, | |
303 | unsigned int nr_irqs, void *data) | |
304 | { | |
305 | struct stm32_gpio_bank *bank = d->host_data; | |
0eb9f683 AT |
306 | struct irq_fwspec *fwspec = data; |
307 | struct irq_fwspec parent_fwspec; | |
308 | irq_hw_number_t hwirq; | |
0eb9f683 AT |
309 | |
310 | hwirq = fwspec->param[0]; | |
311 | parent_fwspec.fwnode = d->parent->fwnode; | |
312 | parent_fwspec.param_count = 2; | |
313 | parent_fwspec.param[0] = fwspec->param[0]; | |
314 | parent_fwspec.param[1] = fwspec->param[1]; | |
315 | ||
316 | irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, | |
317 | bank); | |
318 | ||
dca72e09 | 319 | return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); |
0eb9f683 AT |
320 | } |
321 | ||
322 | static const struct irq_domain_ops stm32_gpio_domain_ops = { | |
323 | .translate = stm32_gpio_domain_translate, | |
324 | .alloc = stm32_gpio_domain_alloc, | |
dca72e09 | 325 | .free = irq_domain_free_irqs_common, |
0eb9f683 AT |
326 | .activate = stm32_gpio_domain_activate, |
327 | }; | |
328 | ||
329 | /* Pinctrl functions */ | |
aceb16dc MC |
330 | static struct stm32_pinctrl_group * |
331 | stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) | |
332 | { | |
333 | int i; | |
334 | ||
335 | for (i = 0; i < pctl->ngroups; i++) { | |
336 | struct stm32_pinctrl_group *grp = pctl->groups + i; | |
337 | ||
338 | if (grp->pin == pin) | |
339 | return grp; | |
340 | } | |
341 | ||
342 | return NULL; | |
343 | } | |
344 | ||
345 | static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, | |
346 | u32 pin_num, u32 fnum) | |
347 | { | |
348 | int i; | |
349 | ||
350 | for (i = 0; i < pctl->match_data->npins; i++) { | |
351 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
352 | const struct stm32_desc_function *func = pin->functions; | |
353 | ||
354 | if (pin->pin.number != pin_num) | |
355 | continue; | |
356 | ||
357 | while (func && func->name) { | |
358 | if (func->num == fnum) | |
359 | return true; | |
360 | func++; | |
361 | } | |
362 | ||
363 | break; | |
364 | } | |
365 | ||
366 | return false; | |
367 | } | |
368 | ||
369 | static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, | |
370 | u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, | |
371 | struct pinctrl_map **map, unsigned *reserved_maps, | |
372 | unsigned *num_maps) | |
373 | { | |
374 | if (*num_maps == *reserved_maps) | |
375 | return -ENOSPC; | |
376 | ||
377 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
378 | (*map)[*num_maps].data.mux.group = grp->name; | |
379 | ||
380 | if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { | |
381 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", | |
382 | fnum, pin); | |
383 | return -EINVAL; | |
384 | } | |
385 | ||
386 | (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; | |
387 | (*num_maps)++; | |
388 | ||
389 | return 0; | |
390 | } | |
391 | ||
392 | static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
393 | struct device_node *node, | |
394 | struct pinctrl_map **map, | |
395 | unsigned *reserved_maps, | |
396 | unsigned *num_maps) | |
397 | { | |
398 | struct stm32_pinctrl *pctl; | |
399 | struct stm32_pinctrl_group *grp; | |
400 | struct property *pins; | |
401 | u32 pinfunc, pin, func; | |
402 | unsigned long *configs; | |
403 | unsigned int num_configs; | |
404 | bool has_config = 0; | |
405 | unsigned reserve = 0; | |
406 | int num_pins, num_funcs, maps_per_pin, i, err; | |
407 | ||
408 | pctl = pinctrl_dev_get_drvdata(pctldev); | |
409 | ||
410 | pins = of_find_property(node, "pinmux", NULL); | |
411 | if (!pins) { | |
412 | dev_err(pctl->dev, "missing pins property in node %s .\n", | |
413 | node->name); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, | |
418 | &num_configs); | |
419 | if (err) | |
420 | return err; | |
421 | ||
422 | if (num_configs) | |
423 | has_config = 1; | |
424 | ||
425 | num_pins = pins->length / sizeof(u32); | |
426 | num_funcs = num_pins; | |
427 | maps_per_pin = 0; | |
428 | if (num_funcs) | |
429 | maps_per_pin++; | |
430 | if (has_config && num_pins >= 1) | |
431 | maps_per_pin++; | |
432 | ||
433 | if (!num_pins || !maps_per_pin) | |
434 | return -EINVAL; | |
435 | ||
436 | reserve = num_pins * maps_per_pin; | |
437 | ||
438 | err = pinctrl_utils_reserve_map(pctldev, map, | |
439 | reserved_maps, num_maps, reserve); | |
440 | if (err) | |
441 | return err; | |
442 | ||
443 | for (i = 0; i < num_pins; i++) { | |
444 | err = of_property_read_u32_index(node, "pinmux", | |
445 | i, &pinfunc); | |
446 | if (err) | |
447 | return err; | |
448 | ||
449 | pin = STM32_GET_PIN_NO(pinfunc); | |
450 | func = STM32_GET_PIN_FUNC(pinfunc); | |
451 | ||
aceb16dc MC |
452 | if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { |
453 | dev_err(pctl->dev, "invalid function.\n"); | |
454 | return -EINVAL; | |
455 | } | |
456 | ||
457 | grp = stm32_pctrl_find_group_by_pin(pctl, pin); | |
458 | if (!grp) { | |
459 | dev_err(pctl->dev, "unable to match pin %d to group\n", | |
460 | pin); | |
461 | return -EINVAL; | |
462 | } | |
463 | ||
464 | err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, | |
465 | reserved_maps, num_maps); | |
466 | if (err) | |
467 | return err; | |
468 | ||
469 | if (has_config) { | |
470 | err = pinctrl_utils_add_map_configs(pctldev, map, | |
471 | reserved_maps, num_maps, grp->name, | |
472 | configs, num_configs, | |
473 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
474 | if (err) | |
475 | return err; | |
476 | } | |
477 | } | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
482 | static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
483 | struct device_node *np_config, | |
484 | struct pinctrl_map **map, unsigned *num_maps) | |
485 | { | |
486 | struct device_node *np; | |
487 | unsigned reserved_maps; | |
488 | int ret; | |
489 | ||
490 | *map = NULL; | |
491 | *num_maps = 0; | |
492 | reserved_maps = 0; | |
493 | ||
494 | for_each_child_of_node(np_config, np) { | |
495 | ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, | |
496 | &reserved_maps, num_maps); | |
497 | if (ret < 0) { | |
d32f7fd3 | 498 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
aceb16dc MC |
499 | return ret; |
500 | } | |
501 | } | |
502 | ||
503 | return 0; | |
504 | } | |
505 | ||
506 | static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
507 | { | |
508 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
509 | ||
510 | return pctl->ngroups; | |
511 | } | |
512 | ||
513 | static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
514 | unsigned group) | |
515 | { | |
516 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
517 | ||
518 | return pctl->groups[group].name; | |
519 | } | |
520 | ||
521 | static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
522 | unsigned group, | |
523 | const unsigned **pins, | |
524 | unsigned *num_pins) | |
525 | { | |
526 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
527 | ||
528 | *pins = (unsigned *)&pctl->groups[group].pin; | |
529 | *num_pins = 1; | |
530 | ||
531 | return 0; | |
532 | } | |
533 | ||
534 | static const struct pinctrl_ops stm32_pctrl_ops = { | |
535 | .dt_node_to_map = stm32_pctrl_dt_node_to_map, | |
d32f7fd3 | 536 | .dt_free_map = pinctrl_utils_free_map, |
aceb16dc MC |
537 | .get_groups_count = stm32_pctrl_get_groups_count, |
538 | .get_group_name = stm32_pctrl_get_group_name, | |
539 | .get_group_pins = stm32_pctrl_get_group_pins, | |
540 | }; | |
541 | ||
542 | ||
543 | /* Pinmux functions */ | |
544 | ||
545 | static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
546 | { | |
547 | return ARRAY_SIZE(stm32_gpio_functions); | |
548 | } | |
549 | ||
550 | static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
551 | unsigned selector) | |
552 | { | |
553 | return stm32_gpio_functions[selector]; | |
554 | } | |
555 | ||
556 | static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
557 | unsigned function, | |
558 | const char * const **groups, | |
559 | unsigned * const num_groups) | |
560 | { | |
561 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
562 | ||
563 | *groups = pctl->grp_names; | |
564 | *num_groups = pctl->ngroups; | |
565 | ||
566 | return 0; | |
567 | } | |
568 | ||
569 | static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, | |
570 | int pin, u32 mode, u32 alt) | |
571 | { | |
572 | u32 val; | |
573 | int alt_shift = (pin % 8) * 4; | |
574 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
575 | unsigned long flags; | |
576 | ||
577 | clk_enable(bank->clk); | |
578 | spin_lock_irqsave(&bank->lock, flags); | |
579 | ||
580 | val = readl_relaxed(bank->base + alt_offset); | |
581 | val &= ~GENMASK(alt_shift + 3, alt_shift); | |
582 | val |= (alt << alt_shift); | |
583 | writel_relaxed(val, bank->base + alt_offset); | |
584 | ||
585 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
586 | val &= ~GENMASK(pin * 2 + 1, pin * 2); | |
587 | val |= mode << (pin * 2); | |
588 | writel_relaxed(val, bank->base + STM32_GPIO_MODER); | |
589 | ||
590 | spin_unlock_irqrestore(&bank->lock, flags); | |
591 | clk_disable(bank->clk); | |
592 | } | |
593 | ||
acaa0379 AT |
594 | void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, |
595 | u32 *alt) | |
3beed93c PC |
596 | { |
597 | u32 val; | |
598 | int alt_shift = (pin % 8) * 4; | |
599 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
600 | unsigned long flags; | |
601 | ||
602 | clk_enable(bank->clk); | |
603 | spin_lock_irqsave(&bank->lock, flags); | |
604 | ||
605 | val = readl_relaxed(bank->base + alt_offset); | |
606 | val &= GENMASK(alt_shift + 3, alt_shift); | |
607 | *alt = val >> alt_shift; | |
608 | ||
609 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
610 | val &= GENMASK(pin * 2 + 1, pin * 2); | |
611 | *mode = val >> (pin * 2); | |
612 | ||
613 | spin_unlock_irqrestore(&bank->lock, flags); | |
614 | clk_disable(bank->clk); | |
615 | } | |
616 | ||
aceb16dc MC |
617 | static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, |
618 | unsigned function, | |
619 | unsigned group) | |
620 | { | |
621 | bool ret; | |
622 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
623 | struct stm32_pinctrl_group *g = pctl->groups + group; | |
624 | struct pinctrl_gpio_range *range; | |
625 | struct stm32_gpio_bank *bank; | |
626 | u32 mode, alt; | |
627 | int pin; | |
628 | ||
629 | ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); | |
630 | if (!ret) { | |
631 | dev_err(pctl->dev, "invalid function %d on group %d .\n", | |
632 | function, group); | |
633 | return -EINVAL; | |
634 | } | |
635 | ||
636 | range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); | |
1dc9d289 | 637 | bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
638 | pin = stm32_gpio_pin(g->pin); |
639 | ||
640 | mode = stm32_gpio_get_mode(function); | |
641 | alt = stm32_gpio_get_alt(function); | |
642 | ||
643 | stm32_pmx_set_mode(bank, pin, mode, alt); | |
644 | ||
645 | return 0; | |
646 | } | |
647 | ||
648 | static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
649 | struct pinctrl_gpio_range *range, unsigned gpio, | |
650 | bool input) | |
651 | { | |
1dc9d289 | 652 | struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
653 | int pin = stm32_gpio_pin(gpio); |
654 | ||
655 | stm32_pmx_set_mode(bank, pin, !input, 0); | |
656 | ||
657 | return 0; | |
658 | } | |
659 | ||
660 | static const struct pinmux_ops stm32_pmx_ops = { | |
661 | .get_functions_count = stm32_pmx_get_funcs_cnt, | |
662 | .get_function_name = stm32_pmx_get_func_name, | |
663 | .get_function_groups = stm32_pmx_get_func_groups, | |
664 | .set_mux = stm32_pmx_set_mux, | |
665 | .gpio_set_direction = stm32_pmx_gpio_set_direction, | |
c32c22ee | 666 | .strict = true, |
aceb16dc MC |
667 | }; |
668 | ||
669 | /* Pinconf functions */ | |
670 | ||
671 | static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, | |
672 | unsigned offset, u32 drive) | |
673 | { | |
674 | unsigned long flags; | |
675 | u32 val; | |
676 | ||
677 | clk_enable(bank->clk); | |
678 | spin_lock_irqsave(&bank->lock, flags); | |
679 | ||
680 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
681 | val &= ~BIT(offset); | |
682 | val |= drive << offset; | |
683 | writel_relaxed(val, bank->base + STM32_GPIO_TYPER); | |
684 | ||
685 | spin_unlock_irqrestore(&bank->lock, flags); | |
686 | clk_disable(bank->clk); | |
687 | } | |
688 | ||
3beed93c PC |
689 | static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, |
690 | unsigned int offset) | |
691 | { | |
692 | unsigned long flags; | |
693 | u32 val; | |
694 | ||
695 | clk_enable(bank->clk); | |
696 | spin_lock_irqsave(&bank->lock, flags); | |
697 | ||
698 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
699 | val &= BIT(offset); | |
700 | ||
701 | spin_unlock_irqrestore(&bank->lock, flags); | |
702 | clk_disable(bank->clk); | |
703 | ||
704 | return (val >> offset); | |
705 | } | |
706 | ||
aceb16dc MC |
707 | static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, |
708 | unsigned offset, u32 speed) | |
709 | { | |
710 | unsigned long flags; | |
711 | u32 val; | |
712 | ||
713 | clk_enable(bank->clk); | |
714 | spin_lock_irqsave(&bank->lock, flags); | |
715 | ||
716 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
717 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
718 | val |= speed << (offset * 2); | |
719 | writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); | |
720 | ||
721 | spin_unlock_irqrestore(&bank->lock, flags); | |
722 | clk_disable(bank->clk); | |
723 | } | |
724 | ||
3beed93c PC |
725 | static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, |
726 | unsigned int offset) | |
727 | { | |
728 | unsigned long flags; | |
729 | u32 val; | |
730 | ||
731 | clk_enable(bank->clk); | |
732 | spin_lock_irqsave(&bank->lock, flags); | |
733 | ||
734 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
735 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
736 | ||
737 | spin_unlock_irqrestore(&bank->lock, flags); | |
738 | clk_disable(bank->clk); | |
739 | ||
740 | return (val >> (offset * 2)); | |
741 | } | |
742 | ||
aceb16dc MC |
743 | static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, |
744 | unsigned offset, u32 bias) | |
745 | { | |
746 | unsigned long flags; | |
747 | u32 val; | |
748 | ||
749 | clk_enable(bank->clk); | |
750 | spin_lock_irqsave(&bank->lock, flags); | |
751 | ||
752 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
753 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
754 | val |= bias << (offset * 2); | |
755 | writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); | |
756 | ||
757 | spin_unlock_irqrestore(&bank->lock, flags); | |
758 | clk_disable(bank->clk); | |
759 | } | |
760 | ||
3beed93c PC |
761 | static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, |
762 | unsigned int offset) | |
763 | { | |
764 | unsigned long flags; | |
765 | u32 val; | |
766 | ||
767 | clk_enable(bank->clk); | |
768 | spin_lock_irqsave(&bank->lock, flags); | |
769 | ||
770 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
771 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
772 | ||
773 | spin_unlock_irqrestore(&bank->lock, flags); | |
774 | clk_disable(bank->clk); | |
775 | ||
776 | return (val >> (offset * 2)); | |
777 | } | |
778 | ||
4fac724f PC |
779 | static bool stm32_pconf_get(struct stm32_gpio_bank *bank, |
780 | unsigned int offset, bool dir) | |
3beed93c PC |
781 | { |
782 | unsigned long flags; | |
783 | u32 val; | |
784 | ||
785 | clk_enable(bank->clk); | |
786 | spin_lock_irqsave(&bank->lock, flags); | |
787 | ||
4fac724f PC |
788 | if (dir) |
789 | val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & | |
790 | BIT(offset)); | |
791 | else | |
792 | val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & | |
793 | BIT(offset)); | |
3beed93c PC |
794 | |
795 | spin_unlock_irqrestore(&bank->lock, flags); | |
796 | clk_disable(bank->clk); | |
797 | ||
798 | return val; | |
799 | } | |
800 | ||
aceb16dc MC |
801 | static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, |
802 | unsigned int pin, enum pin_config_param param, | |
803 | enum pin_config_param arg) | |
804 | { | |
805 | struct pinctrl_gpio_range *range; | |
806 | struct stm32_gpio_bank *bank; | |
807 | int offset, ret = 0; | |
808 | ||
809 | range = pinctrl_find_gpio_range_from_pin(pctldev, pin); | |
1dc9d289 | 810 | bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
811 | offset = stm32_gpio_pin(pin); |
812 | ||
813 | switch (param) { | |
814 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
815 | stm32_pconf_set_driving(bank, offset, 0); | |
816 | break; | |
817 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
818 | stm32_pconf_set_driving(bank, offset, 1); | |
819 | break; | |
820 | case PIN_CONFIG_SLEW_RATE: | |
821 | stm32_pconf_set_speed(bank, offset, arg); | |
822 | break; | |
823 | case PIN_CONFIG_BIAS_DISABLE: | |
824 | stm32_pconf_set_bias(bank, offset, 0); | |
825 | break; | |
826 | case PIN_CONFIG_BIAS_PULL_UP: | |
827 | stm32_pconf_set_bias(bank, offset, 1); | |
828 | break; | |
829 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
830 | stm32_pconf_set_bias(bank, offset, 2); | |
831 | break; | |
832 | case PIN_CONFIG_OUTPUT: | |
833 | __stm32_gpio_set(bank, offset, arg); | |
b7c747d4 | 834 | ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); |
aceb16dc MC |
835 | break; |
836 | default: | |
837 | ret = -EINVAL; | |
838 | } | |
839 | ||
840 | return ret; | |
841 | } | |
842 | ||
843 | static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, | |
844 | unsigned group, | |
845 | unsigned long *config) | |
846 | { | |
847 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
848 | ||
849 | *config = pctl->groups[group].config; | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
854 | static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, | |
855 | unsigned long *configs, unsigned num_configs) | |
856 | { | |
857 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
858 | struct stm32_pinctrl_group *g = &pctl->groups[group]; | |
859 | int i, ret; | |
860 | ||
861 | for (i = 0; i < num_configs; i++) { | |
862 | ret = stm32_pconf_parse_conf(pctldev, g->pin, | |
863 | pinconf_to_config_param(configs[i]), | |
864 | pinconf_to_config_argument(configs[i])); | |
865 | if (ret < 0) | |
866 | return ret; | |
867 | ||
868 | g->config = configs[i]; | |
869 | } | |
870 | ||
871 | return 0; | |
872 | } | |
873 | ||
3beed93c PC |
874 | static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, |
875 | struct seq_file *s, | |
876 | unsigned int pin) | |
877 | { | |
878 | struct pinctrl_gpio_range *range; | |
879 | struct stm32_gpio_bank *bank; | |
880 | int offset; | |
881 | u32 mode, alt, drive, speed, bias; | |
882 | static const char * const modes[] = { | |
883 | "input", "output", "alternate", "analog" }; | |
884 | static const char * const speeds[] = { | |
885 | "low", "medium", "high", "very high" }; | |
886 | static const char * const biasing[] = { | |
887 | "floating", "pull up", "pull down", "" }; | |
888 | bool val; | |
889 | ||
890 | range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); | |
1dc9d289 | 891 | bank = gpiochip_get_data(range->gc); |
3beed93c PC |
892 | offset = stm32_gpio_pin(pin); |
893 | ||
894 | stm32_pmx_get_mode(bank, offset, &mode, &alt); | |
895 | bias = stm32_pconf_get_bias(bank, offset); | |
896 | ||
897 | seq_printf(s, "%s ", modes[mode]); | |
898 | ||
899 | switch (mode) { | |
900 | /* input */ | |
901 | case 0: | |
4fac724f | 902 | val = stm32_pconf_get(bank, offset, true); |
3beed93c PC |
903 | seq_printf(s, "- %s - %s", |
904 | val ? "high" : "low", | |
905 | biasing[bias]); | |
906 | break; | |
907 | ||
908 | /* output */ | |
909 | case 1: | |
910 | drive = stm32_pconf_get_driving(bank, offset); | |
911 | speed = stm32_pconf_get_speed(bank, offset); | |
4fac724f | 912 | val = stm32_pconf_get(bank, offset, false); |
3beed93c PC |
913 | seq_printf(s, "- %s - %s - %s - %s %s", |
914 | val ? "high" : "low", | |
915 | drive ? "open drain" : "push pull", | |
916 | biasing[bias], | |
917 | speeds[speed], "speed"); | |
918 | break; | |
919 | ||
920 | /* alternate */ | |
921 | case 2: | |
922 | drive = stm32_pconf_get_driving(bank, offset); | |
923 | speed = stm32_pconf_get_speed(bank, offset); | |
a37571a2 | 924 | seq_printf(s, "%d - %s - %s - %s %s", alt, |
3beed93c PC |
925 | drive ? "open drain" : "push pull", |
926 | biasing[bias], | |
927 | speeds[speed], "speed"); | |
928 | break; | |
929 | ||
930 | /* analog */ | |
931 | case 3: | |
932 | break; | |
933 | } | |
934 | } | |
935 | ||
936 | ||
aceb16dc MC |
937 | static const struct pinconf_ops stm32_pconf_ops = { |
938 | .pin_config_group_get = stm32_pconf_group_get, | |
939 | .pin_config_group_set = stm32_pconf_group_set, | |
3beed93c | 940 | .pin_config_dbg_show = stm32_pconf_dbg_show, |
aceb16dc MC |
941 | }; |
942 | ||
943 | static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, | |
944 | struct device_node *np) | |
945 | { | |
1dc9d289 | 946 | struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; |
aceb16dc | 947 | struct pinctrl_gpio_range *range = &bank->range; |
1dc9d289 | 948 | struct of_phandle_args args; |
aceb16dc MC |
949 | struct device *dev = pctl->dev; |
950 | struct resource res; | |
951 | struct reset_control *rstc; | |
1dc9d289 AT |
952 | int npins = STM32_GPIO_PINS_PER_BANK; |
953 | int bank_nr, err; | |
aceb16dc | 954 | |
d9e99bdf | 955 | rstc = of_reset_control_get_exclusive(np, NULL); |
aceb16dc MC |
956 | if (!IS_ERR(rstc)) |
957 | reset_control_deassert(rstc); | |
958 | ||
959 | if (of_address_to_resource(np, 0, &res)) | |
960 | return -ENODEV; | |
961 | ||
962 | bank->base = devm_ioremap_resource(dev, &res); | |
963 | if (IS_ERR(bank->base)) | |
964 | return PTR_ERR(bank->base); | |
965 | ||
966 | bank->clk = of_clk_get_by_name(np, NULL); | |
967 | if (IS_ERR(bank->clk)) { | |
968 | dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); | |
969 | return PTR_ERR(bank->clk); | |
970 | } | |
971 | ||
972 | err = clk_prepare(bank->clk); | |
973 | if (err) { | |
974 | dev_err(dev, "failed to prepare clk (%d)\n", err); | |
975 | return err; | |
976 | } | |
977 | ||
aceb16dc | 978 | bank->gpio_chip = stm32_gpio_template; |
1dc9d289 AT |
979 | |
980 | of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); | |
981 | ||
982 | if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { | |
983 | bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; | |
984 | bank->gpio_chip.base = args.args[1]; | |
985 | } else { | |
986 | bank_nr = pctl->nbanks; | |
987 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; | |
988 | range->name = bank->gpio_chip.label; | |
989 | range->id = bank_nr; | |
990 | range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; | |
991 | range->base = range->id * STM32_GPIO_PINS_PER_BANK; | |
992 | range->npins = npins; | |
993 | range->gc = &bank->gpio_chip; | |
994 | pinctrl_add_gpio_range(pctl->pctl_dev, | |
995 | &pctl->banks[bank_nr].range); | |
996 | } | |
aceb16dc | 997 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; |
1dc9d289 | 998 | |
aceb16dc MC |
999 | bank->gpio_chip.ngpio = npins; |
1000 | bank->gpio_chip.of_node = np; | |
1300568a | 1001 | bank->gpio_chip.parent = dev; |
1dc9d289 | 1002 | bank->bank_nr = bank_nr; |
aceb16dc MC |
1003 | spin_lock_init(&bank->lock); |
1004 | ||
0eb9f683 AT |
1005 | /* create irq hierarchical domain */ |
1006 | bank->fwnode = of_node_to_fwnode(np); | |
1007 | ||
1008 | bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, | |
1009 | STM32_GPIO_IRQ_LINE, bank->fwnode, | |
1010 | &stm32_gpio_domain_ops, bank); | |
1011 | ||
1012 | if (!bank->domain) | |
1013 | return -ENODEV; | |
1014 | ||
1300568a | 1015 | err = gpiochip_add_data(&bank->gpio_chip, bank); |
aceb16dc MC |
1016 | if (err) { |
1017 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); | |
1018 | return err; | |
1019 | } | |
1020 | ||
1dc9d289 | 1021 | dev_info(dev, "%s bank added\n", bank->gpio_chip.label); |
aceb16dc MC |
1022 | return 0; |
1023 | } | |
1024 | ||
0eb9f683 AT |
1025 | static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, |
1026 | struct stm32_pinctrl *pctl) | |
1027 | { | |
1028 | struct device_node *np = pdev->dev.of_node, *parent; | |
1029 | struct device *dev = &pdev->dev; | |
1030 | struct regmap *rm; | |
1031 | int offset, ret, i; | |
1032 | ||
1033 | parent = of_irq_find_parent(np); | |
1034 | if (!parent) | |
1035 | return -ENXIO; | |
1036 | ||
1037 | pctl->domain = irq_find_host(parent); | |
1038 | if (!pctl->domain) | |
1039 | return -ENXIO; | |
1040 | ||
1041 | pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); | |
1042 | if (IS_ERR(pctl->regmap)) | |
1043 | return PTR_ERR(pctl->regmap); | |
1044 | ||
1045 | rm = pctl->regmap; | |
1046 | ||
1047 | ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); | |
1048 | if (ret) | |
1049 | return ret; | |
1050 | ||
1051 | for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { | |
1052 | struct reg_field mux; | |
1053 | ||
1054 | mux.reg = offset + (i / 4) * 4; | |
1055 | mux.lsb = (i % 4) * 4; | |
1056 | mux.msb = mux.lsb + 3; | |
1057 | ||
1058 | pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); | |
1059 | if (IS_ERR(pctl->irqmux[i])) | |
1060 | return PTR_ERR(pctl->irqmux[i]); | |
1061 | } | |
1062 | ||
1063 | return 0; | |
1064 | } | |
1065 | ||
aceb16dc MC |
1066 | static int stm32_pctrl_build_state(struct platform_device *pdev) |
1067 | { | |
1068 | struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); | |
1069 | int i; | |
1070 | ||
1071 | pctl->ngroups = pctl->match_data->npins; | |
1072 | ||
1073 | /* Allocate groups */ | |
1074 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
1075 | sizeof(*pctl->groups), GFP_KERNEL); | |
1076 | if (!pctl->groups) | |
1077 | return -ENOMEM; | |
1078 | ||
1079 | /* We assume that one pin is one group, use pin name as group name. */ | |
1080 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
1081 | sizeof(*pctl->grp_names), GFP_KERNEL); | |
1082 | if (!pctl->grp_names) | |
1083 | return -ENOMEM; | |
1084 | ||
1085 | for (i = 0; i < pctl->match_data->npins; i++) { | |
1086 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
1087 | struct stm32_pinctrl_group *group = pctl->groups + i; | |
1088 | ||
1089 | group->name = pin->pin.name; | |
1090 | group->pin = pin->pin.number; | |
1091 | ||
1092 | pctl->grp_names[i] = pin->pin.name; | |
1093 | } | |
1094 | ||
1095 | return 0; | |
1096 | } | |
1097 | ||
1098 | int stm32_pctl_probe(struct platform_device *pdev) | |
1099 | { | |
1100 | struct device_node *np = pdev->dev.of_node; | |
1101 | struct device_node *child; | |
1102 | const struct of_device_id *match; | |
1103 | struct device *dev = &pdev->dev; | |
1104 | struct stm32_pinctrl *pctl; | |
1105 | struct pinctrl_pin_desc *pins; | |
1106 | int i, ret, banks = 0; | |
1107 | ||
1108 | if (!np) | |
1109 | return -EINVAL; | |
1110 | ||
1111 | match = of_match_device(dev->driver->of_match_table, dev); | |
1112 | if (!match || !match->data) | |
1113 | return -EINVAL; | |
1114 | ||
1115 | if (!of_find_property(np, "pins-are-numbered", NULL)) { | |
1116 | dev_err(dev, "only support pins-are-numbered format\n"); | |
1117 | return -EINVAL; | |
1118 | } | |
1119 | ||
1120 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
1121 | if (!pctl) | |
1122 | return -ENOMEM; | |
1123 | ||
1124 | platform_set_drvdata(pdev, pctl); | |
1125 | ||
1126 | pctl->dev = dev; | |
1127 | pctl->match_data = match->data; | |
1128 | ret = stm32_pctrl_build_state(pdev); | |
1129 | if (ret) { | |
1130 | dev_err(dev, "build state failed: %d\n", ret); | |
1131 | return -EINVAL; | |
1132 | } | |
1133 | ||
1064a2b4 AT |
1134 | if (of_find_property(np, "interrupt-parent", NULL)) { |
1135 | ret = stm32_pctrl_dt_setup_irq(pdev, pctl); | |
1136 | if (ret) | |
1137 | return ret; | |
1138 | } | |
0eb9f683 | 1139 | |
aceb16dc MC |
1140 | pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), |
1141 | GFP_KERNEL); | |
1142 | if (!pins) | |
1143 | return -ENOMEM; | |
1144 | ||
1145 | for (i = 0; i < pctl->match_data->npins; i++) | |
1146 | pins[i] = pctl->match_data->pins[i].pin; | |
1147 | ||
1148 | pctl->pctl_desc.name = dev_name(&pdev->dev); | |
1149 | pctl->pctl_desc.owner = THIS_MODULE; | |
1150 | pctl->pctl_desc.pins = pins; | |
1151 | pctl->pctl_desc.npins = pctl->match_data->npins; | |
1152 | pctl->pctl_desc.confops = &stm32_pconf_ops; | |
1153 | pctl->pctl_desc.pctlops = &stm32_pctrl_ops; | |
1154 | pctl->pctl_desc.pmxops = &stm32_pmx_ops; | |
1155 | pctl->dev = &pdev->dev; | |
1156 | ||
88edad04 LD |
1157 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, |
1158 | pctl); | |
1dc9d289 | 1159 | |
88edad04 | 1160 | if (IS_ERR(pctl->pctl_dev)) { |
aceb16dc | 1161 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
88edad04 | 1162 | return PTR_ERR(pctl->pctl_dev); |
aceb16dc MC |
1163 | } |
1164 | ||
1dc9d289 AT |
1165 | for_each_child_of_node(np, child) |
1166 | if (of_property_read_bool(child, "gpio-controller")) | |
1167 | banks++; | |
1168 | ||
1169 | if (!banks) { | |
1170 | dev_err(dev, "at least one GPIO bank is required\n"); | |
1171 | return -EINVAL; | |
1172 | } | |
1173 | pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), | |
1174 | GFP_KERNEL); | |
1175 | if (!pctl->banks) | |
1176 | return -ENOMEM; | |
1177 | ||
1178 | for_each_child_of_node(np, child) { | |
1179 | if (of_property_read_bool(child, "gpio-controller")) { | |
1180 | ret = stm32_gpiolib_register_bank(pctl, child); | |
1181 | if (ret) | |
1182 | return ret; | |
1183 | ||
1184 | pctl->nbanks++; | |
1185 | } | |
1186 | } | |
aceb16dc MC |
1187 | |
1188 | dev_info(dev, "Pinctrl STM32 initialized\n"); | |
1189 | ||
1190 | return 0; | |
1191 | } | |
1192 |