]>
Commit | Line | Data |
---|---|---|
aceb16dc MC |
1 | /* |
2 | * Copyright (C) Maxime Coquelin 2015 | |
3 | * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
4 | * License terms: GNU General Public License (GPL), version 2 | |
5 | * | |
6 | * Heavily based on Mediatek's pinctrl driver | |
7 | */ | |
8 | #include <linux/clk.h> | |
1300568a | 9 | #include <linux/gpio/driver.h> |
aceb16dc | 10 | #include <linux/io.h> |
0eb9f683 AT |
11 | #include <linux/irq.h> |
12 | #include <linux/mfd/syscon.h> | |
aceb16dc MC |
13 | #include <linux/module.h> |
14 | #include <linux/of.h> | |
15 | #include <linux/of_address.h> | |
16 | #include <linux/of_device.h> | |
17 | #include <linux/of_irq.h> | |
18 | #include <linux/pinctrl/consumer.h> | |
19 | #include <linux/pinctrl/machine.h> | |
20 | #include <linux/pinctrl/pinconf.h> | |
21 | #include <linux/pinctrl/pinconf-generic.h> | |
22 | #include <linux/pinctrl/pinctrl.h> | |
23 | #include <linux/pinctrl/pinmux.h> | |
24 | #include <linux/platform_device.h> | |
0eb9f683 | 25 | #include <linux/regmap.h> |
aceb16dc MC |
26 | #include <linux/reset.h> |
27 | #include <linux/slab.h> | |
28 | ||
aceb16dc MC |
29 | #include "../core.h" |
30 | #include "../pinconf.h" | |
31 | #include "../pinctrl-utils.h" | |
32 | #include "pinctrl-stm32.h" | |
33 | ||
34 | #define STM32_GPIO_MODER 0x00 | |
35 | #define STM32_GPIO_TYPER 0x04 | |
36 | #define STM32_GPIO_SPEEDR 0x08 | |
37 | #define STM32_GPIO_PUPDR 0x0c | |
38 | #define STM32_GPIO_IDR 0x10 | |
39 | #define STM32_GPIO_ODR 0x14 | |
40 | #define STM32_GPIO_BSRR 0x18 | |
41 | #define STM32_GPIO_LCKR 0x1c | |
42 | #define STM32_GPIO_AFRL 0x20 | |
43 | #define STM32_GPIO_AFRH 0x24 | |
44 | ||
45 | #define STM32_GPIO_PINS_PER_BANK 16 | |
0eb9f683 | 46 | #define STM32_GPIO_IRQ_LINE 16 |
aceb16dc MC |
47 | |
48 | #define gpio_range_to_bank(chip) \ | |
49 | container_of(chip, struct stm32_gpio_bank, range) | |
50 | ||
aceb16dc MC |
51 | static const char * const stm32_gpio_functions[] = { |
52 | "gpio", "af0", "af1", | |
53 | "af2", "af3", "af4", | |
54 | "af5", "af6", "af7", | |
55 | "af8", "af9", "af10", | |
56 | "af11", "af12", "af13", | |
57 | "af14", "af15", "analog", | |
58 | }; | |
59 | ||
60 | struct stm32_pinctrl_group { | |
61 | const char *name; | |
62 | unsigned long config; | |
63 | unsigned pin; | |
64 | }; | |
65 | ||
66 | struct stm32_gpio_bank { | |
67 | void __iomem *base; | |
68 | struct clk *clk; | |
69 | spinlock_t lock; | |
70 | struct gpio_chip gpio_chip; | |
71 | struct pinctrl_gpio_range range; | |
0eb9f683 AT |
72 | struct fwnode_handle *fwnode; |
73 | struct irq_domain *domain; | |
1dc9d289 | 74 | u32 bank_nr; |
aceb16dc MC |
75 | }; |
76 | ||
77 | struct stm32_pinctrl { | |
78 | struct device *dev; | |
79 | struct pinctrl_dev *pctl_dev; | |
80 | struct pinctrl_desc pctl_desc; | |
81 | struct stm32_pinctrl_group *groups; | |
82 | unsigned ngroups; | |
83 | const char **grp_names; | |
84 | struct stm32_gpio_bank *banks; | |
85 | unsigned nbanks; | |
86 | const struct stm32_pinctrl_match_data *match_data; | |
0eb9f683 AT |
87 | struct irq_domain *domain; |
88 | struct regmap *regmap; | |
89 | struct regmap_field *irqmux[STM32_GPIO_PINS_PER_BANK]; | |
aceb16dc MC |
90 | }; |
91 | ||
92 | static inline int stm32_gpio_pin(int gpio) | |
93 | { | |
94 | return gpio % STM32_GPIO_PINS_PER_BANK; | |
95 | } | |
96 | ||
97 | static inline u32 stm32_gpio_get_mode(u32 function) | |
98 | { | |
99 | switch (function) { | |
100 | case STM32_PIN_GPIO: | |
101 | return 0; | |
102 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
103 | return 2; | |
104 | case STM32_PIN_ANALOG: | |
105 | return 3; | |
106 | } | |
107 | ||
108 | return 0; | |
109 | } | |
110 | ||
111 | static inline u32 stm32_gpio_get_alt(u32 function) | |
112 | { | |
113 | switch (function) { | |
114 | case STM32_PIN_GPIO: | |
115 | return 0; | |
116 | case STM32_PIN_AF(0) ... STM32_PIN_AF(15): | |
117 | return function - 1; | |
118 | case STM32_PIN_ANALOG: | |
119 | return 0; | |
120 | } | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | /* GPIO functions */ | |
126 | ||
127 | static inline void __stm32_gpio_set(struct stm32_gpio_bank *bank, | |
128 | unsigned offset, int value) | |
129 | { | |
130 | if (!value) | |
131 | offset += STM32_GPIO_PINS_PER_BANK; | |
132 | ||
133 | clk_enable(bank->clk); | |
134 | ||
135 | writel_relaxed(BIT(offset), bank->base + STM32_GPIO_BSRR); | |
136 | ||
137 | clk_disable(bank->clk); | |
138 | } | |
139 | ||
140 | static int stm32_gpio_request(struct gpio_chip *chip, unsigned offset) | |
141 | { | |
1dc9d289 AT |
142 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
143 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
144 | struct pinctrl_gpio_range *range; | |
145 | int pin = offset + (bank->bank_nr * STM32_GPIO_PINS_PER_BANK); | |
146 | ||
147 | range = pinctrl_find_gpio_range_from_pin_nolock(pctl->pctl_dev, pin); | |
148 | if (!range) { | |
149 | dev_err(pctl->dev, "pin %d not in range.\n", pin); | |
150 | return -EINVAL; | |
151 | } | |
152 | ||
a9a1d2a7 | 153 | return pinctrl_gpio_request(chip->base + offset); |
aceb16dc MC |
154 | } |
155 | ||
156 | static void stm32_gpio_free(struct gpio_chip *chip, unsigned offset) | |
157 | { | |
a9a1d2a7 | 158 | pinctrl_gpio_free(chip->base + offset); |
aceb16dc MC |
159 | } |
160 | ||
161 | static int stm32_gpio_get(struct gpio_chip *chip, unsigned offset) | |
162 | { | |
1300568a | 163 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
164 | int ret; |
165 | ||
166 | clk_enable(bank->clk); | |
167 | ||
168 | ret = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & BIT(offset)); | |
169 | ||
170 | clk_disable(bank->clk); | |
171 | ||
172 | return ret; | |
173 | } | |
174 | ||
175 | static void stm32_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
176 | { | |
1300568a | 177 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
178 | |
179 | __stm32_gpio_set(bank, offset, value); | |
180 | } | |
181 | ||
182 | static int stm32_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
183 | { | |
184 | return pinctrl_gpio_direction_input(chip->base + offset); | |
185 | } | |
186 | ||
187 | static int stm32_gpio_direction_output(struct gpio_chip *chip, | |
188 | unsigned offset, int value) | |
189 | { | |
1300568a | 190 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); |
aceb16dc MC |
191 | |
192 | __stm32_gpio_set(bank, offset, value); | |
193 | pinctrl_gpio_direction_output(chip->base + offset); | |
194 | ||
195 | return 0; | |
196 | } | |
197 | ||
0eb9f683 AT |
198 | |
199 | static int stm32_gpio_to_irq(struct gpio_chip *chip, unsigned int offset) | |
200 | { | |
201 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); | |
202 | struct irq_fwspec fwspec; | |
203 | ||
204 | fwspec.fwnode = bank->fwnode; | |
205 | fwspec.param_count = 2; | |
206 | fwspec.param[0] = offset; | |
207 | fwspec.param[1] = IRQ_TYPE_NONE; | |
208 | ||
209 | return irq_create_fwspec_mapping(&fwspec); | |
210 | } | |
211 | ||
acaa0379 AT |
212 | static int stm32_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) |
213 | { | |
214 | struct stm32_gpio_bank *bank = gpiochip_get_data(chip); | |
215 | int pin = stm32_gpio_pin(offset); | |
216 | int ret; | |
217 | u32 mode, alt; | |
218 | ||
219 | stm32_pmx_get_mode(bank, pin, &mode, &alt); | |
220 | if ((alt == 0) && (mode == 0)) | |
221 | ret = 1; | |
222 | else if ((alt == 0) && (mode == 1)) | |
223 | ret = 0; | |
224 | else | |
225 | ret = -EINVAL; | |
226 | ||
227 | return ret; | |
228 | } | |
229 | ||
d9048cdb | 230 | static const struct gpio_chip stm32_gpio_template = { |
aceb16dc MC |
231 | .request = stm32_gpio_request, |
232 | .free = stm32_gpio_free, | |
233 | .get = stm32_gpio_get, | |
234 | .set = stm32_gpio_set, | |
235 | .direction_input = stm32_gpio_direction_input, | |
236 | .direction_output = stm32_gpio_direction_output, | |
0eb9f683 | 237 | .to_irq = stm32_gpio_to_irq, |
acaa0379 | 238 | .get_direction = stm32_gpio_get_direction, |
aceb16dc MC |
239 | }; |
240 | ||
9efa6d1a AT |
241 | static int stm32_gpio_irq_request_resources(struct irq_data *irq_data) |
242 | { | |
243 | struct stm32_gpio_bank *bank = irq_data->domain->host_data; | |
244 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
245 | int ret; | |
246 | ||
247 | ret = stm32_gpio_direction_input(&bank->gpio_chip, irq_data->hwirq); | |
248 | if (ret) | |
249 | return ret; | |
250 | ||
251 | ret = gpiochip_lock_as_irq(&bank->gpio_chip, irq_data->hwirq); | |
252 | if (ret) { | |
253 | dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", | |
254 | irq_data->hwirq); | |
255 | return ret; | |
256 | } | |
257 | ||
258 | return 0; | |
259 | } | |
260 | ||
261 | static void stm32_gpio_irq_release_resources(struct irq_data *irq_data) | |
262 | { | |
263 | struct stm32_gpio_bank *bank = irq_data->domain->host_data; | |
264 | ||
265 | gpiochip_unlock_as_irq(&bank->gpio_chip, irq_data->hwirq); | |
266 | } | |
267 | ||
0eb9f683 AT |
268 | static struct irq_chip stm32_gpio_irq_chip = { |
269 | .name = "stm32gpio", | |
270 | .irq_eoi = irq_chip_eoi_parent, | |
271 | .irq_mask = irq_chip_mask_parent, | |
272 | .irq_unmask = irq_chip_unmask_parent, | |
273 | .irq_set_type = irq_chip_set_type_parent, | |
9efa6d1a AT |
274 | .irq_request_resources = stm32_gpio_irq_request_resources, |
275 | .irq_release_resources = stm32_gpio_irq_release_resources, | |
0eb9f683 AT |
276 | }; |
277 | ||
278 | static int stm32_gpio_domain_translate(struct irq_domain *d, | |
279 | struct irq_fwspec *fwspec, | |
280 | unsigned long *hwirq, | |
281 | unsigned int *type) | |
282 | { | |
283 | if ((fwspec->param_count != 2) || | |
284 | (fwspec->param[0] >= STM32_GPIO_IRQ_LINE)) | |
285 | return -EINVAL; | |
286 | ||
287 | *hwirq = fwspec->param[0]; | |
288 | *type = fwspec->param[1]; | |
289 | return 0; | |
290 | } | |
aceb16dc | 291 | |
72491643 | 292 | static int stm32_gpio_domain_activate(struct irq_domain *d, |
702cb0a0 | 293 | struct irq_data *irq_data, bool reserve) |
0eb9f683 AT |
294 | { |
295 | struct stm32_gpio_bank *bank = d->host_data; | |
296 | struct stm32_pinctrl *pctl = dev_get_drvdata(bank->gpio_chip.parent); | |
297 | ||
1dc9d289 | 298 | regmap_field_write(pctl->irqmux[irq_data->hwirq], bank->bank_nr); |
72491643 | 299 | return 0; |
0eb9f683 AT |
300 | } |
301 | ||
302 | static int stm32_gpio_domain_alloc(struct irq_domain *d, | |
303 | unsigned int virq, | |
304 | unsigned int nr_irqs, void *data) | |
305 | { | |
306 | struct stm32_gpio_bank *bank = d->host_data; | |
0eb9f683 AT |
307 | struct irq_fwspec *fwspec = data; |
308 | struct irq_fwspec parent_fwspec; | |
309 | irq_hw_number_t hwirq; | |
0eb9f683 AT |
310 | |
311 | hwirq = fwspec->param[0]; | |
312 | parent_fwspec.fwnode = d->parent->fwnode; | |
313 | parent_fwspec.param_count = 2; | |
314 | parent_fwspec.param[0] = fwspec->param[0]; | |
315 | parent_fwspec.param[1] = fwspec->param[1]; | |
316 | ||
317 | irq_domain_set_hwirq_and_chip(d, virq, hwirq, &stm32_gpio_irq_chip, | |
318 | bank); | |
319 | ||
dca72e09 | 320 | return irq_domain_alloc_irqs_parent(d, virq, nr_irqs, &parent_fwspec); |
0eb9f683 AT |
321 | } |
322 | ||
323 | static const struct irq_domain_ops stm32_gpio_domain_ops = { | |
324 | .translate = stm32_gpio_domain_translate, | |
325 | .alloc = stm32_gpio_domain_alloc, | |
dca72e09 | 326 | .free = irq_domain_free_irqs_common, |
0eb9f683 AT |
327 | .activate = stm32_gpio_domain_activate, |
328 | }; | |
329 | ||
330 | /* Pinctrl functions */ | |
aceb16dc MC |
331 | static struct stm32_pinctrl_group * |
332 | stm32_pctrl_find_group_by_pin(struct stm32_pinctrl *pctl, u32 pin) | |
333 | { | |
334 | int i; | |
335 | ||
336 | for (i = 0; i < pctl->ngroups; i++) { | |
337 | struct stm32_pinctrl_group *grp = pctl->groups + i; | |
338 | ||
339 | if (grp->pin == pin) | |
340 | return grp; | |
341 | } | |
342 | ||
343 | return NULL; | |
344 | } | |
345 | ||
346 | static bool stm32_pctrl_is_function_valid(struct stm32_pinctrl *pctl, | |
347 | u32 pin_num, u32 fnum) | |
348 | { | |
349 | int i; | |
350 | ||
351 | for (i = 0; i < pctl->match_data->npins; i++) { | |
352 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
353 | const struct stm32_desc_function *func = pin->functions; | |
354 | ||
355 | if (pin->pin.number != pin_num) | |
356 | continue; | |
357 | ||
358 | while (func && func->name) { | |
359 | if (func->num == fnum) | |
360 | return true; | |
361 | func++; | |
362 | } | |
363 | ||
364 | break; | |
365 | } | |
366 | ||
367 | return false; | |
368 | } | |
369 | ||
370 | static int stm32_pctrl_dt_node_to_map_func(struct stm32_pinctrl *pctl, | |
371 | u32 pin, u32 fnum, struct stm32_pinctrl_group *grp, | |
372 | struct pinctrl_map **map, unsigned *reserved_maps, | |
373 | unsigned *num_maps) | |
374 | { | |
375 | if (*num_maps == *reserved_maps) | |
376 | return -ENOSPC; | |
377 | ||
378 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | |
379 | (*map)[*num_maps].data.mux.group = grp->name; | |
380 | ||
381 | if (!stm32_pctrl_is_function_valid(pctl, pin, fnum)) { | |
382 | dev_err(pctl->dev, "invalid function %d on pin %d .\n", | |
383 | fnum, pin); | |
384 | return -EINVAL; | |
385 | } | |
386 | ||
387 | (*map)[*num_maps].data.mux.function = stm32_gpio_functions[fnum]; | |
388 | (*num_maps)++; | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static int stm32_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev, | |
394 | struct device_node *node, | |
395 | struct pinctrl_map **map, | |
396 | unsigned *reserved_maps, | |
397 | unsigned *num_maps) | |
398 | { | |
399 | struct stm32_pinctrl *pctl; | |
400 | struct stm32_pinctrl_group *grp; | |
401 | struct property *pins; | |
402 | u32 pinfunc, pin, func; | |
403 | unsigned long *configs; | |
404 | unsigned int num_configs; | |
405 | bool has_config = 0; | |
406 | unsigned reserve = 0; | |
407 | int num_pins, num_funcs, maps_per_pin, i, err; | |
408 | ||
409 | pctl = pinctrl_dev_get_drvdata(pctldev); | |
410 | ||
411 | pins = of_find_property(node, "pinmux", NULL); | |
412 | if (!pins) { | |
413 | dev_err(pctl->dev, "missing pins property in node %s .\n", | |
414 | node->name); | |
415 | return -EINVAL; | |
416 | } | |
417 | ||
418 | err = pinconf_generic_parse_dt_config(node, pctldev, &configs, | |
419 | &num_configs); | |
420 | if (err) | |
421 | return err; | |
422 | ||
423 | if (num_configs) | |
424 | has_config = 1; | |
425 | ||
426 | num_pins = pins->length / sizeof(u32); | |
427 | num_funcs = num_pins; | |
428 | maps_per_pin = 0; | |
429 | if (num_funcs) | |
430 | maps_per_pin++; | |
431 | if (has_config && num_pins >= 1) | |
432 | maps_per_pin++; | |
433 | ||
434 | if (!num_pins || !maps_per_pin) | |
435 | return -EINVAL; | |
436 | ||
437 | reserve = num_pins * maps_per_pin; | |
438 | ||
439 | err = pinctrl_utils_reserve_map(pctldev, map, | |
440 | reserved_maps, num_maps, reserve); | |
441 | if (err) | |
442 | return err; | |
443 | ||
444 | for (i = 0; i < num_pins; i++) { | |
445 | err = of_property_read_u32_index(node, "pinmux", | |
446 | i, &pinfunc); | |
447 | if (err) | |
448 | return err; | |
449 | ||
450 | pin = STM32_GET_PIN_NO(pinfunc); | |
451 | func = STM32_GET_PIN_FUNC(pinfunc); | |
452 | ||
aceb16dc MC |
453 | if (!stm32_pctrl_is_function_valid(pctl, pin, func)) { |
454 | dev_err(pctl->dev, "invalid function.\n"); | |
455 | return -EINVAL; | |
456 | } | |
457 | ||
458 | grp = stm32_pctrl_find_group_by_pin(pctl, pin); | |
459 | if (!grp) { | |
460 | dev_err(pctl->dev, "unable to match pin %d to group\n", | |
461 | pin); | |
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | err = stm32_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map, | |
466 | reserved_maps, num_maps); | |
467 | if (err) | |
468 | return err; | |
469 | ||
470 | if (has_config) { | |
471 | err = pinctrl_utils_add_map_configs(pctldev, map, | |
472 | reserved_maps, num_maps, grp->name, | |
473 | configs, num_configs, | |
474 | PIN_MAP_TYPE_CONFIGS_GROUP); | |
475 | if (err) | |
476 | return err; | |
477 | } | |
478 | } | |
479 | ||
480 | return 0; | |
481 | } | |
482 | ||
483 | static int stm32_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |
484 | struct device_node *np_config, | |
485 | struct pinctrl_map **map, unsigned *num_maps) | |
486 | { | |
487 | struct device_node *np; | |
488 | unsigned reserved_maps; | |
489 | int ret; | |
490 | ||
491 | *map = NULL; | |
492 | *num_maps = 0; | |
493 | reserved_maps = 0; | |
494 | ||
495 | for_each_child_of_node(np_config, np) { | |
496 | ret = stm32_pctrl_dt_subnode_to_map(pctldev, np, map, | |
497 | &reserved_maps, num_maps); | |
498 | if (ret < 0) { | |
d32f7fd3 | 499 | pinctrl_utils_free_map(pctldev, *map, *num_maps); |
aceb16dc MC |
500 | return ret; |
501 | } | |
502 | } | |
503 | ||
504 | return 0; | |
505 | } | |
506 | ||
507 | static int stm32_pctrl_get_groups_count(struct pinctrl_dev *pctldev) | |
508 | { | |
509 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
510 | ||
511 | return pctl->ngroups; | |
512 | } | |
513 | ||
514 | static const char *stm32_pctrl_get_group_name(struct pinctrl_dev *pctldev, | |
515 | unsigned group) | |
516 | { | |
517 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
518 | ||
519 | return pctl->groups[group].name; | |
520 | } | |
521 | ||
522 | static int stm32_pctrl_get_group_pins(struct pinctrl_dev *pctldev, | |
523 | unsigned group, | |
524 | const unsigned **pins, | |
525 | unsigned *num_pins) | |
526 | { | |
527 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
528 | ||
529 | *pins = (unsigned *)&pctl->groups[group].pin; | |
530 | *num_pins = 1; | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
535 | static const struct pinctrl_ops stm32_pctrl_ops = { | |
536 | .dt_node_to_map = stm32_pctrl_dt_node_to_map, | |
d32f7fd3 | 537 | .dt_free_map = pinctrl_utils_free_map, |
aceb16dc MC |
538 | .get_groups_count = stm32_pctrl_get_groups_count, |
539 | .get_group_name = stm32_pctrl_get_group_name, | |
540 | .get_group_pins = stm32_pctrl_get_group_pins, | |
541 | }; | |
542 | ||
543 | ||
544 | /* Pinmux functions */ | |
545 | ||
546 | static int stm32_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | |
547 | { | |
548 | return ARRAY_SIZE(stm32_gpio_functions); | |
549 | } | |
550 | ||
551 | static const char *stm32_pmx_get_func_name(struct pinctrl_dev *pctldev, | |
552 | unsigned selector) | |
553 | { | |
554 | return stm32_gpio_functions[selector]; | |
555 | } | |
556 | ||
557 | static int stm32_pmx_get_func_groups(struct pinctrl_dev *pctldev, | |
558 | unsigned function, | |
559 | const char * const **groups, | |
560 | unsigned * const num_groups) | |
561 | { | |
562 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
563 | ||
564 | *groups = pctl->grp_names; | |
565 | *num_groups = pctl->ngroups; | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | static void stm32_pmx_set_mode(struct stm32_gpio_bank *bank, | |
571 | int pin, u32 mode, u32 alt) | |
572 | { | |
573 | u32 val; | |
574 | int alt_shift = (pin % 8) * 4; | |
575 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
576 | unsigned long flags; | |
577 | ||
578 | clk_enable(bank->clk); | |
579 | spin_lock_irqsave(&bank->lock, flags); | |
580 | ||
581 | val = readl_relaxed(bank->base + alt_offset); | |
582 | val &= ~GENMASK(alt_shift + 3, alt_shift); | |
583 | val |= (alt << alt_shift); | |
584 | writel_relaxed(val, bank->base + alt_offset); | |
585 | ||
586 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
587 | val &= ~GENMASK(pin * 2 + 1, pin * 2); | |
588 | val |= mode << (pin * 2); | |
589 | writel_relaxed(val, bank->base + STM32_GPIO_MODER); | |
590 | ||
591 | spin_unlock_irqrestore(&bank->lock, flags); | |
592 | clk_disable(bank->clk); | |
593 | } | |
594 | ||
acaa0379 AT |
595 | void stm32_pmx_get_mode(struct stm32_gpio_bank *bank, int pin, u32 *mode, |
596 | u32 *alt) | |
3beed93c PC |
597 | { |
598 | u32 val; | |
599 | int alt_shift = (pin % 8) * 4; | |
600 | int alt_offset = STM32_GPIO_AFRL + (pin / 8) * 4; | |
601 | unsigned long flags; | |
602 | ||
603 | clk_enable(bank->clk); | |
604 | spin_lock_irqsave(&bank->lock, flags); | |
605 | ||
606 | val = readl_relaxed(bank->base + alt_offset); | |
607 | val &= GENMASK(alt_shift + 3, alt_shift); | |
608 | *alt = val >> alt_shift; | |
609 | ||
610 | val = readl_relaxed(bank->base + STM32_GPIO_MODER); | |
611 | val &= GENMASK(pin * 2 + 1, pin * 2); | |
612 | *mode = val >> (pin * 2); | |
613 | ||
614 | spin_unlock_irqrestore(&bank->lock, flags); | |
615 | clk_disable(bank->clk); | |
616 | } | |
617 | ||
aceb16dc MC |
618 | static int stm32_pmx_set_mux(struct pinctrl_dev *pctldev, |
619 | unsigned function, | |
620 | unsigned group) | |
621 | { | |
622 | bool ret; | |
623 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
624 | struct stm32_pinctrl_group *g = pctl->groups + group; | |
625 | struct pinctrl_gpio_range *range; | |
626 | struct stm32_gpio_bank *bank; | |
627 | u32 mode, alt; | |
628 | int pin; | |
629 | ||
630 | ret = stm32_pctrl_is_function_valid(pctl, g->pin, function); | |
631 | if (!ret) { | |
632 | dev_err(pctl->dev, "invalid function %d on group %d .\n", | |
633 | function, group); | |
634 | return -EINVAL; | |
635 | } | |
636 | ||
637 | range = pinctrl_find_gpio_range_from_pin(pctldev, g->pin); | |
1dc9d289 | 638 | bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
639 | pin = stm32_gpio_pin(g->pin); |
640 | ||
641 | mode = stm32_gpio_get_mode(function); | |
642 | alt = stm32_gpio_get_alt(function); | |
643 | ||
644 | stm32_pmx_set_mode(bank, pin, mode, alt); | |
645 | ||
646 | return 0; | |
647 | } | |
648 | ||
649 | static int stm32_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, | |
650 | struct pinctrl_gpio_range *range, unsigned gpio, | |
651 | bool input) | |
652 | { | |
1dc9d289 | 653 | struct stm32_gpio_bank *bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
654 | int pin = stm32_gpio_pin(gpio); |
655 | ||
656 | stm32_pmx_set_mode(bank, pin, !input, 0); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static const struct pinmux_ops stm32_pmx_ops = { | |
662 | .get_functions_count = stm32_pmx_get_funcs_cnt, | |
663 | .get_function_name = stm32_pmx_get_func_name, | |
664 | .get_function_groups = stm32_pmx_get_func_groups, | |
665 | .set_mux = stm32_pmx_set_mux, | |
666 | .gpio_set_direction = stm32_pmx_gpio_set_direction, | |
c32c22ee | 667 | .strict = true, |
aceb16dc MC |
668 | }; |
669 | ||
670 | /* Pinconf functions */ | |
671 | ||
672 | static void stm32_pconf_set_driving(struct stm32_gpio_bank *bank, | |
673 | unsigned offset, u32 drive) | |
674 | { | |
675 | unsigned long flags; | |
676 | u32 val; | |
677 | ||
678 | clk_enable(bank->clk); | |
679 | spin_lock_irqsave(&bank->lock, flags); | |
680 | ||
681 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
682 | val &= ~BIT(offset); | |
683 | val |= drive << offset; | |
684 | writel_relaxed(val, bank->base + STM32_GPIO_TYPER); | |
685 | ||
686 | spin_unlock_irqrestore(&bank->lock, flags); | |
687 | clk_disable(bank->clk); | |
688 | } | |
689 | ||
3beed93c PC |
690 | static u32 stm32_pconf_get_driving(struct stm32_gpio_bank *bank, |
691 | unsigned int offset) | |
692 | { | |
693 | unsigned long flags; | |
694 | u32 val; | |
695 | ||
696 | clk_enable(bank->clk); | |
697 | spin_lock_irqsave(&bank->lock, flags); | |
698 | ||
699 | val = readl_relaxed(bank->base + STM32_GPIO_TYPER); | |
700 | val &= BIT(offset); | |
701 | ||
702 | spin_unlock_irqrestore(&bank->lock, flags); | |
703 | clk_disable(bank->clk); | |
704 | ||
705 | return (val >> offset); | |
706 | } | |
707 | ||
aceb16dc MC |
708 | static void stm32_pconf_set_speed(struct stm32_gpio_bank *bank, |
709 | unsigned offset, u32 speed) | |
710 | { | |
711 | unsigned long flags; | |
712 | u32 val; | |
713 | ||
714 | clk_enable(bank->clk); | |
715 | spin_lock_irqsave(&bank->lock, flags); | |
716 | ||
717 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
718 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
719 | val |= speed << (offset * 2); | |
720 | writel_relaxed(val, bank->base + STM32_GPIO_SPEEDR); | |
721 | ||
722 | spin_unlock_irqrestore(&bank->lock, flags); | |
723 | clk_disable(bank->clk); | |
724 | } | |
725 | ||
3beed93c PC |
726 | static u32 stm32_pconf_get_speed(struct stm32_gpio_bank *bank, |
727 | unsigned int offset) | |
728 | { | |
729 | unsigned long flags; | |
730 | u32 val; | |
731 | ||
732 | clk_enable(bank->clk); | |
733 | spin_lock_irqsave(&bank->lock, flags); | |
734 | ||
735 | val = readl_relaxed(bank->base + STM32_GPIO_SPEEDR); | |
736 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
737 | ||
738 | spin_unlock_irqrestore(&bank->lock, flags); | |
739 | clk_disable(bank->clk); | |
740 | ||
741 | return (val >> (offset * 2)); | |
742 | } | |
743 | ||
aceb16dc MC |
744 | static void stm32_pconf_set_bias(struct stm32_gpio_bank *bank, |
745 | unsigned offset, u32 bias) | |
746 | { | |
747 | unsigned long flags; | |
748 | u32 val; | |
749 | ||
750 | clk_enable(bank->clk); | |
751 | spin_lock_irqsave(&bank->lock, flags); | |
752 | ||
753 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
754 | val &= ~GENMASK(offset * 2 + 1, offset * 2); | |
755 | val |= bias << (offset * 2); | |
756 | writel_relaxed(val, bank->base + STM32_GPIO_PUPDR); | |
757 | ||
758 | spin_unlock_irqrestore(&bank->lock, flags); | |
759 | clk_disable(bank->clk); | |
760 | } | |
761 | ||
3beed93c PC |
762 | static u32 stm32_pconf_get_bias(struct stm32_gpio_bank *bank, |
763 | unsigned int offset) | |
764 | { | |
765 | unsigned long flags; | |
766 | u32 val; | |
767 | ||
768 | clk_enable(bank->clk); | |
769 | spin_lock_irqsave(&bank->lock, flags); | |
770 | ||
771 | val = readl_relaxed(bank->base + STM32_GPIO_PUPDR); | |
772 | val &= GENMASK(offset * 2 + 1, offset * 2); | |
773 | ||
774 | spin_unlock_irqrestore(&bank->lock, flags); | |
775 | clk_disable(bank->clk); | |
776 | ||
777 | return (val >> (offset * 2)); | |
778 | } | |
779 | ||
4fac724f PC |
780 | static bool stm32_pconf_get(struct stm32_gpio_bank *bank, |
781 | unsigned int offset, bool dir) | |
3beed93c PC |
782 | { |
783 | unsigned long flags; | |
784 | u32 val; | |
785 | ||
786 | clk_enable(bank->clk); | |
787 | spin_lock_irqsave(&bank->lock, flags); | |
788 | ||
4fac724f PC |
789 | if (dir) |
790 | val = !!(readl_relaxed(bank->base + STM32_GPIO_IDR) & | |
791 | BIT(offset)); | |
792 | else | |
793 | val = !!(readl_relaxed(bank->base + STM32_GPIO_ODR) & | |
794 | BIT(offset)); | |
3beed93c PC |
795 | |
796 | spin_unlock_irqrestore(&bank->lock, flags); | |
797 | clk_disable(bank->clk); | |
798 | ||
799 | return val; | |
800 | } | |
801 | ||
aceb16dc MC |
802 | static int stm32_pconf_parse_conf(struct pinctrl_dev *pctldev, |
803 | unsigned int pin, enum pin_config_param param, | |
804 | enum pin_config_param arg) | |
805 | { | |
806 | struct pinctrl_gpio_range *range; | |
807 | struct stm32_gpio_bank *bank; | |
808 | int offset, ret = 0; | |
809 | ||
810 | range = pinctrl_find_gpio_range_from_pin(pctldev, pin); | |
1dc9d289 | 811 | bank = gpiochip_get_data(range->gc); |
aceb16dc MC |
812 | offset = stm32_gpio_pin(pin); |
813 | ||
814 | switch (param) { | |
815 | case PIN_CONFIG_DRIVE_PUSH_PULL: | |
816 | stm32_pconf_set_driving(bank, offset, 0); | |
817 | break; | |
818 | case PIN_CONFIG_DRIVE_OPEN_DRAIN: | |
819 | stm32_pconf_set_driving(bank, offset, 1); | |
820 | break; | |
821 | case PIN_CONFIG_SLEW_RATE: | |
822 | stm32_pconf_set_speed(bank, offset, arg); | |
823 | break; | |
824 | case PIN_CONFIG_BIAS_DISABLE: | |
825 | stm32_pconf_set_bias(bank, offset, 0); | |
826 | break; | |
827 | case PIN_CONFIG_BIAS_PULL_UP: | |
828 | stm32_pconf_set_bias(bank, offset, 1); | |
829 | break; | |
830 | case PIN_CONFIG_BIAS_PULL_DOWN: | |
831 | stm32_pconf_set_bias(bank, offset, 2); | |
832 | break; | |
833 | case PIN_CONFIG_OUTPUT: | |
834 | __stm32_gpio_set(bank, offset, arg); | |
b7c747d4 | 835 | ret = stm32_pmx_gpio_set_direction(pctldev, range, pin, false); |
aceb16dc MC |
836 | break; |
837 | default: | |
838 | ret = -EINVAL; | |
839 | } | |
840 | ||
841 | return ret; | |
842 | } | |
843 | ||
844 | static int stm32_pconf_group_get(struct pinctrl_dev *pctldev, | |
845 | unsigned group, | |
846 | unsigned long *config) | |
847 | { | |
848 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
849 | ||
850 | *config = pctl->groups[group].config; | |
851 | ||
852 | return 0; | |
853 | } | |
854 | ||
855 | static int stm32_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, | |
856 | unsigned long *configs, unsigned num_configs) | |
857 | { | |
858 | struct stm32_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); | |
859 | struct stm32_pinctrl_group *g = &pctl->groups[group]; | |
860 | int i, ret; | |
861 | ||
862 | for (i = 0; i < num_configs; i++) { | |
863 | ret = stm32_pconf_parse_conf(pctldev, g->pin, | |
864 | pinconf_to_config_param(configs[i]), | |
865 | pinconf_to_config_argument(configs[i])); | |
866 | if (ret < 0) | |
867 | return ret; | |
868 | ||
869 | g->config = configs[i]; | |
870 | } | |
871 | ||
872 | return 0; | |
873 | } | |
874 | ||
3beed93c PC |
875 | static void stm32_pconf_dbg_show(struct pinctrl_dev *pctldev, |
876 | struct seq_file *s, | |
877 | unsigned int pin) | |
878 | { | |
879 | struct pinctrl_gpio_range *range; | |
880 | struct stm32_gpio_bank *bank; | |
881 | int offset; | |
882 | u32 mode, alt, drive, speed, bias; | |
883 | static const char * const modes[] = { | |
884 | "input", "output", "alternate", "analog" }; | |
885 | static const char * const speeds[] = { | |
886 | "low", "medium", "high", "very high" }; | |
887 | static const char * const biasing[] = { | |
888 | "floating", "pull up", "pull down", "" }; | |
889 | bool val; | |
890 | ||
891 | range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin); | |
1dc9d289 | 892 | bank = gpiochip_get_data(range->gc); |
3beed93c PC |
893 | offset = stm32_gpio_pin(pin); |
894 | ||
895 | stm32_pmx_get_mode(bank, offset, &mode, &alt); | |
896 | bias = stm32_pconf_get_bias(bank, offset); | |
897 | ||
898 | seq_printf(s, "%s ", modes[mode]); | |
899 | ||
900 | switch (mode) { | |
901 | /* input */ | |
902 | case 0: | |
4fac724f | 903 | val = stm32_pconf_get(bank, offset, true); |
3beed93c PC |
904 | seq_printf(s, "- %s - %s", |
905 | val ? "high" : "low", | |
906 | biasing[bias]); | |
907 | break; | |
908 | ||
909 | /* output */ | |
910 | case 1: | |
911 | drive = stm32_pconf_get_driving(bank, offset); | |
912 | speed = stm32_pconf_get_speed(bank, offset); | |
4fac724f | 913 | val = stm32_pconf_get(bank, offset, false); |
3beed93c PC |
914 | seq_printf(s, "- %s - %s - %s - %s %s", |
915 | val ? "high" : "low", | |
916 | drive ? "open drain" : "push pull", | |
917 | biasing[bias], | |
918 | speeds[speed], "speed"); | |
919 | break; | |
920 | ||
921 | /* alternate */ | |
922 | case 2: | |
923 | drive = stm32_pconf_get_driving(bank, offset); | |
924 | speed = stm32_pconf_get_speed(bank, offset); | |
a37571a2 | 925 | seq_printf(s, "%d - %s - %s - %s %s", alt, |
3beed93c PC |
926 | drive ? "open drain" : "push pull", |
927 | biasing[bias], | |
928 | speeds[speed], "speed"); | |
929 | break; | |
930 | ||
931 | /* analog */ | |
932 | case 3: | |
933 | break; | |
934 | } | |
935 | } | |
936 | ||
937 | ||
aceb16dc MC |
938 | static const struct pinconf_ops stm32_pconf_ops = { |
939 | .pin_config_group_get = stm32_pconf_group_get, | |
940 | .pin_config_group_set = stm32_pconf_group_set, | |
3beed93c | 941 | .pin_config_dbg_show = stm32_pconf_dbg_show, |
aceb16dc MC |
942 | }; |
943 | ||
944 | static int stm32_gpiolib_register_bank(struct stm32_pinctrl *pctl, | |
945 | struct device_node *np) | |
946 | { | |
1dc9d289 | 947 | struct stm32_gpio_bank *bank = &pctl->banks[pctl->nbanks]; |
aceb16dc | 948 | struct pinctrl_gpio_range *range = &bank->range; |
1dc9d289 | 949 | struct of_phandle_args args; |
aceb16dc MC |
950 | struct device *dev = pctl->dev; |
951 | struct resource res; | |
952 | struct reset_control *rstc; | |
1dc9d289 AT |
953 | int npins = STM32_GPIO_PINS_PER_BANK; |
954 | int bank_nr, err; | |
aceb16dc | 955 | |
d9e99bdf | 956 | rstc = of_reset_control_get_exclusive(np, NULL); |
aceb16dc MC |
957 | if (!IS_ERR(rstc)) |
958 | reset_control_deassert(rstc); | |
959 | ||
960 | if (of_address_to_resource(np, 0, &res)) | |
961 | return -ENODEV; | |
962 | ||
963 | bank->base = devm_ioremap_resource(dev, &res); | |
964 | if (IS_ERR(bank->base)) | |
965 | return PTR_ERR(bank->base); | |
966 | ||
967 | bank->clk = of_clk_get_by_name(np, NULL); | |
968 | if (IS_ERR(bank->clk)) { | |
969 | dev_err(dev, "failed to get clk (%ld)\n", PTR_ERR(bank->clk)); | |
970 | return PTR_ERR(bank->clk); | |
971 | } | |
972 | ||
973 | err = clk_prepare(bank->clk); | |
974 | if (err) { | |
975 | dev_err(dev, "failed to prepare clk (%d)\n", err); | |
976 | return err; | |
977 | } | |
978 | ||
aceb16dc | 979 | bank->gpio_chip = stm32_gpio_template; |
1dc9d289 AT |
980 | |
981 | of_property_read_string(np, "st,bank-name", &bank->gpio_chip.label); | |
982 | ||
983 | if (!of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &args)) { | |
984 | bank_nr = args.args[1] / STM32_GPIO_PINS_PER_BANK; | |
985 | bank->gpio_chip.base = args.args[1]; | |
986 | } else { | |
987 | bank_nr = pctl->nbanks; | |
988 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; | |
989 | range->name = bank->gpio_chip.label; | |
990 | range->id = bank_nr; | |
991 | range->pin_base = range->id * STM32_GPIO_PINS_PER_BANK; | |
992 | range->base = range->id * STM32_GPIO_PINS_PER_BANK; | |
993 | range->npins = npins; | |
994 | range->gc = &bank->gpio_chip; | |
995 | pinctrl_add_gpio_range(pctl->pctl_dev, | |
996 | &pctl->banks[bank_nr].range); | |
997 | } | |
aceb16dc | 998 | bank->gpio_chip.base = bank_nr * STM32_GPIO_PINS_PER_BANK; |
1dc9d289 | 999 | |
aceb16dc MC |
1000 | bank->gpio_chip.ngpio = npins; |
1001 | bank->gpio_chip.of_node = np; | |
1300568a | 1002 | bank->gpio_chip.parent = dev; |
1dc9d289 | 1003 | bank->bank_nr = bank_nr; |
aceb16dc MC |
1004 | spin_lock_init(&bank->lock); |
1005 | ||
0eb9f683 AT |
1006 | /* create irq hierarchical domain */ |
1007 | bank->fwnode = of_node_to_fwnode(np); | |
1008 | ||
1009 | bank->domain = irq_domain_create_hierarchy(pctl->domain, 0, | |
1010 | STM32_GPIO_IRQ_LINE, bank->fwnode, | |
1011 | &stm32_gpio_domain_ops, bank); | |
1012 | ||
1013 | if (!bank->domain) | |
1014 | return -ENODEV; | |
1015 | ||
1300568a | 1016 | err = gpiochip_add_data(&bank->gpio_chip, bank); |
aceb16dc MC |
1017 | if (err) { |
1018 | dev_err(dev, "Failed to add gpiochip(%d)!\n", bank_nr); | |
1019 | return err; | |
1020 | } | |
1021 | ||
1dc9d289 | 1022 | dev_info(dev, "%s bank added\n", bank->gpio_chip.label); |
aceb16dc MC |
1023 | return 0; |
1024 | } | |
1025 | ||
0eb9f683 AT |
1026 | static int stm32_pctrl_dt_setup_irq(struct platform_device *pdev, |
1027 | struct stm32_pinctrl *pctl) | |
1028 | { | |
1029 | struct device_node *np = pdev->dev.of_node, *parent; | |
1030 | struct device *dev = &pdev->dev; | |
1031 | struct regmap *rm; | |
1032 | int offset, ret, i; | |
1033 | ||
1034 | parent = of_irq_find_parent(np); | |
1035 | if (!parent) | |
1036 | return -ENXIO; | |
1037 | ||
1038 | pctl->domain = irq_find_host(parent); | |
1039 | if (!pctl->domain) | |
1040 | return -ENXIO; | |
1041 | ||
1042 | pctl->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); | |
1043 | if (IS_ERR(pctl->regmap)) | |
1044 | return PTR_ERR(pctl->regmap); | |
1045 | ||
1046 | rm = pctl->regmap; | |
1047 | ||
1048 | ret = of_property_read_u32_index(np, "st,syscfg", 1, &offset); | |
1049 | if (ret) | |
1050 | return ret; | |
1051 | ||
1052 | for (i = 0; i < STM32_GPIO_PINS_PER_BANK; i++) { | |
1053 | struct reg_field mux; | |
1054 | ||
1055 | mux.reg = offset + (i / 4) * 4; | |
1056 | mux.lsb = (i % 4) * 4; | |
1057 | mux.msb = mux.lsb + 3; | |
1058 | ||
1059 | pctl->irqmux[i] = devm_regmap_field_alloc(dev, rm, mux); | |
1060 | if (IS_ERR(pctl->irqmux[i])) | |
1061 | return PTR_ERR(pctl->irqmux[i]); | |
1062 | } | |
1063 | ||
1064 | return 0; | |
1065 | } | |
1066 | ||
aceb16dc MC |
1067 | static int stm32_pctrl_build_state(struct platform_device *pdev) |
1068 | { | |
1069 | struct stm32_pinctrl *pctl = platform_get_drvdata(pdev); | |
1070 | int i; | |
1071 | ||
1072 | pctl->ngroups = pctl->match_data->npins; | |
1073 | ||
1074 | /* Allocate groups */ | |
1075 | pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
1076 | sizeof(*pctl->groups), GFP_KERNEL); | |
1077 | if (!pctl->groups) | |
1078 | return -ENOMEM; | |
1079 | ||
1080 | /* We assume that one pin is one group, use pin name as group name. */ | |
1081 | pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups, | |
1082 | sizeof(*pctl->grp_names), GFP_KERNEL); | |
1083 | if (!pctl->grp_names) | |
1084 | return -ENOMEM; | |
1085 | ||
1086 | for (i = 0; i < pctl->match_data->npins; i++) { | |
1087 | const struct stm32_desc_pin *pin = pctl->match_data->pins + i; | |
1088 | struct stm32_pinctrl_group *group = pctl->groups + i; | |
1089 | ||
1090 | group->name = pin->pin.name; | |
1091 | group->pin = pin->pin.number; | |
1092 | ||
1093 | pctl->grp_names[i] = pin->pin.name; | |
1094 | } | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
1099 | int stm32_pctl_probe(struct platform_device *pdev) | |
1100 | { | |
1101 | struct device_node *np = pdev->dev.of_node; | |
1102 | struct device_node *child; | |
1103 | const struct of_device_id *match; | |
1104 | struct device *dev = &pdev->dev; | |
1105 | struct stm32_pinctrl *pctl; | |
1106 | struct pinctrl_pin_desc *pins; | |
1107 | int i, ret, banks = 0; | |
1108 | ||
1109 | if (!np) | |
1110 | return -EINVAL; | |
1111 | ||
1112 | match = of_match_device(dev->driver->of_match_table, dev); | |
1113 | if (!match || !match->data) | |
1114 | return -EINVAL; | |
1115 | ||
1116 | if (!of_find_property(np, "pins-are-numbered", NULL)) { | |
1117 | dev_err(dev, "only support pins-are-numbered format\n"); | |
1118 | return -EINVAL; | |
1119 | } | |
1120 | ||
1121 | pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL); | |
1122 | if (!pctl) | |
1123 | return -ENOMEM; | |
1124 | ||
1125 | platform_set_drvdata(pdev, pctl); | |
1126 | ||
1127 | pctl->dev = dev; | |
1128 | pctl->match_data = match->data; | |
1129 | ret = stm32_pctrl_build_state(pdev); | |
1130 | if (ret) { | |
1131 | dev_err(dev, "build state failed: %d\n", ret); | |
1132 | return -EINVAL; | |
1133 | } | |
1134 | ||
1064a2b4 AT |
1135 | if (of_find_property(np, "interrupt-parent", NULL)) { |
1136 | ret = stm32_pctrl_dt_setup_irq(pdev, pctl); | |
1137 | if (ret) | |
1138 | return ret; | |
1139 | } | |
0eb9f683 | 1140 | |
aceb16dc MC |
1141 | pins = devm_kcalloc(&pdev->dev, pctl->match_data->npins, sizeof(*pins), |
1142 | GFP_KERNEL); | |
1143 | if (!pins) | |
1144 | return -ENOMEM; | |
1145 | ||
1146 | for (i = 0; i < pctl->match_data->npins; i++) | |
1147 | pins[i] = pctl->match_data->pins[i].pin; | |
1148 | ||
1149 | pctl->pctl_desc.name = dev_name(&pdev->dev); | |
1150 | pctl->pctl_desc.owner = THIS_MODULE; | |
1151 | pctl->pctl_desc.pins = pins; | |
1152 | pctl->pctl_desc.npins = pctl->match_data->npins; | |
1153 | pctl->pctl_desc.confops = &stm32_pconf_ops; | |
1154 | pctl->pctl_desc.pctlops = &stm32_pctrl_ops; | |
1155 | pctl->pctl_desc.pmxops = &stm32_pmx_ops; | |
1156 | pctl->dev = &pdev->dev; | |
1157 | ||
88edad04 LD |
1158 | pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc, |
1159 | pctl); | |
1dc9d289 | 1160 | |
88edad04 | 1161 | if (IS_ERR(pctl->pctl_dev)) { |
aceb16dc | 1162 | dev_err(&pdev->dev, "Failed pinctrl registration\n"); |
88edad04 | 1163 | return PTR_ERR(pctl->pctl_dev); |
aceb16dc MC |
1164 | } |
1165 | ||
1dc9d289 AT |
1166 | for_each_child_of_node(np, child) |
1167 | if (of_property_read_bool(child, "gpio-controller")) | |
1168 | banks++; | |
1169 | ||
1170 | if (!banks) { | |
1171 | dev_err(dev, "at least one GPIO bank is required\n"); | |
1172 | return -EINVAL; | |
1173 | } | |
1174 | pctl->banks = devm_kcalloc(dev, banks, sizeof(*pctl->banks), | |
1175 | GFP_KERNEL); | |
1176 | if (!pctl->banks) | |
1177 | return -ENOMEM; | |
1178 | ||
1179 | for_each_child_of_node(np, child) { | |
1180 | if (of_property_read_bool(child, "gpio-controller")) { | |
1181 | ret = stm32_gpiolib_register_bank(pctl, child); | |
1182 | if (ret) | |
1183 | return ret; | |
1184 | ||
1185 | pctl->nbanks++; | |
1186 | } | |
1187 | } | |
aceb16dc MC |
1188 | |
1189 | dev_info(dev, "Pinctrl STM32 initialized\n"); | |
1190 | ||
1191 | return 0; | |
1192 | } | |
1193 |