[mirror_ubuntu-hirsute-kernel.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.h

/*
 * Allwinner A1X SoCs pinctrl driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINCTRL_SUNXI_H
#define __PINCTRL_SUNXI_H

#include <linux/kernel.h>
#include <linux/spinlock.h>

#define PA_BASE	0
#define PB_BASE	32
#define PC_BASE	64
#define PD_BASE	96
#define PE_BASE	128
#define PF_BASE	160
#define PG_BASE	192
#define PH_BASE	224
#define PI_BASE	256
#define PL_BASE	352
#define PM_BASE	384
#define PN_BASE	416

#define SUNXI_PINCTRL_PIN(bank, pin)		\
	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

#define SUNXI_PIN_NAME_MAX_LEN	5

#define BANK_MEM_SIZE		0x24
#define MUX_REGS_OFFSET		0x0
#define DATA_REGS_OFFSET	0x10
#define DLEVEL_REGS_OFFSET	0x14
#define PULL_REGS_OFFSET	0x1c

#define PINS_PER_BANK		32
#define MUX_PINS_PER_REG	8
#define MUX_PINS_BITS		4
#define MUX_PINS_MASK		0x0f
#define DATA_PINS_PER_REG	32
#define DATA_PINS_BITS		1
#define DATA_PINS_MASK		0x01
#define DLEVEL_PINS_PER_REG	16
#define DLEVEL_PINS_BITS	2
#define DLEVEL_PINS_MASK	0x03
#define PULL_PINS_PER_REG	16
#define PULL_PINS_BITS		2
#define PULL_PINS_MASK		0x03

#define IRQ_PER_BANK		32

#define IRQ_CFG_REG		0x200
#define IRQ_CFG_IRQ_PER_REG		8
#define IRQ_CFG_IRQ_BITS		4
#define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
#define IRQ_CTRL_REG		0x210
#define IRQ_CTRL_IRQ_PER_REG		32
#define IRQ_CTRL_IRQ_BITS		1
#define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
#define IRQ_STATUS_REG		0x214
#define IRQ_STATUS_IRQ_PER_REG		32
#define IRQ_STATUS_IRQ_BITS		1
#define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)

#define IRQ_DEBOUNCE_REG	0x218

#define IRQ_MEM_SIZE		0x20

#define IRQ_EDGE_RISING		0x00
#define IRQ_EDGE_FALLING	0x01
#define IRQ_LEVEL_HIGH		0x02
#define IRQ_LEVEL_LOW		0x03
#define IRQ_EDGE_BOTH		0x04

#define GRP_CFG_REG		0x300

#define IO_BIAS_MASK		GENMASK(3, 0)

#define SUN4I_FUNC_INPUT	0
#define SUN4I_FUNC_IRQ		6

#define PINCTRL_SUN5I_A10S	BIT(1)
#define PINCTRL_SUN5I_A13	BIT(2)
#define PINCTRL_SUN5I_GR8	BIT(3)
#define PINCTRL_SUN6I_A31	BIT(4)
#define PINCTRL_SUN6I_A31S	BIT(5)
#define PINCTRL_SUN4I_A10	BIT(6)
#define PINCTRL_SUN7I_A20	BIT(7)
#define PINCTRL_SUN8I_R40	BIT(8)
#define PINCTRL_SUN8I_V3	BIT(9)
#define PINCTRL_SUN8I_V3S	BIT(10)

#define PIO_POW_MOD_SEL_REG	0x340

enum sunxi_desc_bias_voltage {
	BIAS_VOLTAGE_NONE,
	/*
	 * Bias voltage configuration is done through
	 * Pn_GRP_CONFIG registers, as seen on A80 SoC.
	 */
	BIAS_VOLTAGE_GRP_CONFIG,
	/*
	 * Bias voltage is set through PIO_POW_MOD_SEL_REG
	 * register, as seen on H6 SoC, for example.
	 */
	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
};

struct sunxi_desc_function {
	unsigned long	variant;
	const char	*name;
	u8		muxval;
	u8		irqbank;
	u8		irqnum;
};

struct sunxi_desc_pin {
	struct pinctrl_pin_desc		pin;
	unsigned long			variant;
	struct sunxi_desc_function	*functions;
};

struct sunxi_pinctrl_desc {
	const struct sunxi_desc_pin	*pins;
	int				npins;
	unsigned			pin_base;
	unsigned			irq_banks;
	const unsigned int		*irq_bank_map;
	bool				irq_read_needs_mux;
	bool				disable_strict_mode;
	enum sunxi_desc_bias_voltage	io_bias_cfg_variant;
};

struct sunxi_pinctrl_function {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct sunxi_pinctrl_group {
	const char	*name;
	unsigned	pin;
};

struct sunxi_pinctrl_regulator {
	struct regulator	*regulator;
	refcount_t		refcount;
};

struct sunxi_pinctrl {
	void __iomem			*membase;
	struct gpio_chip		*chip;
	const struct sunxi_pinctrl_desc	*desc;
	struct device			*dev;
	struct sunxi_pinctrl_regulator	regulators[9];
	struct irq_domain		*domain;
	struct sunxi_pinctrl_function	*functions;
	unsigned			nfunctions;
	struct sunxi_pinctrl_group	*groups;
	unsigned			ngroups;
	int				*irq;
	unsigned			*irq_array;
	raw_spinlock_t			lock;
	struct pinctrl_dev		*pctl_dev;
	unsigned long			variant;
};

#define SUNXI_PIN(_pin, ...)					\
	{							\
		.pin = _pin,					\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_PIN_VARIANT(_pin, _variant, ...)			\
	{							\
		.pin = _pin,					\
		.variant = _variant,				\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_FUNCTION(_val, _name)				\
	{							\
		.name = _name,					\
		.muxval = _val,					\
	}

#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant)		\
	{							\
		.name = _name,					\
		.muxval = _val,					\
		.variant = _variant,				\
	}

#define SUNXI_FUNCTION_IRQ(_val, _irq)				\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqnum = _irq,					\
	}

#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqbank = _bank,				\
		.irqnum = _irq,					\
	}

/*
 * The sunXi PIO registers are organized as is:
 * 0x00 - 0x0c	Muxing values.
 *		8 pins per register, each pin having a 4bits value
 * 0x10		Pin values
 *		32 bits per register, each pin corresponding to one bit
 * 0x14 - 0x18	Drive level
 *		16 pins per register, each pin having a 2bits value
 * 0x1c - 0x20	Pull-Up values
 *		16 pins per register, each pin having a 2bits value
 *
 * This is for the first bank. Each bank will have the same layout,
 * with an offset being a multiple of 0x24.
 *
 * The following functions calculate from the pin number the register
 * and the bit offset that we should access.
 */
static inline u32 sunxi_mux_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += MUX_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_mux_offset(u16 pin)
{
	u32 pin_num = pin % MUX_PINS_PER_REG;
	return pin_num * MUX_PINS_BITS;
}

static inline u32 sunxi_data_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DATA_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_data_offset(u16 pin)
{
	u32 pin_num = pin % DATA_PINS_PER_REG;
	return pin_num * DATA_PINS_BITS;
}

static inline u32 sunxi_dlevel_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DLEVEL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_dlevel_offset(u16 pin)
{
	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	return pin_num * DLEVEL_PINS_BITS;
}

static inline u32 sunxi_pull_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += PULL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_pull_offset(u16 pin)
{
	u32 pin_num = pin % PULL_PINS_PER_REG;
	return pin_num * PULL_PINS_BITS;
}

static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	if (!desc->irq_bank_map)
		return bank;
	else
		return desc->irq_bank_map[bank];
}

static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
				    u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;
	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;

	return IRQ_CFG_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
}

static inline u32 sunxi_irq_cfg_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	return irq_num * IRQ_CFG_IRQ_BITS;
}

static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
				     u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_ctrl_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	return irq_num * IRQ_CTRL_IRQ_BITS;
}

static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_DEBOUNCE_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_STATUS_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
				       u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_status_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_status_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	return irq_num * IRQ_STATUS_IRQ_BITS;
}

static inline u32 sunxi_grp_config_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;

	return GRP_CFG_REG + bank * 0x4;
}

int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
				    const struct sunxi_pinctrl_desc *desc,
				    unsigned long variant);

#define sunxi_pinctrl_init(_dev, _desc) \
	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)

#endif /* __PINCTRL_SUNXI_H */
Commit	Line	Data
0e37f88d MR	1	/*
	2	* Allwinner A1X SoCs pinctrl driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#ifndef __PINCTRL_SUNXI_H
	14	#define __PINCTRL_SUNXI_H
	15
	16	#include <linux/kernel.h>
1bee963d	17	#include <linux/spinlock.h>
0e37f88d MR	18
	19	#define PA_BASE 0
	20	#define PB_BASE 32
	21	#define PC_BASE 64
	22	#define PD_BASE 96
	23	#define PE_BASE 128
	24	#define PF_BASE 160
	25	#define PG_BASE 192
9f5b6b30 MR	26	#define PH_BASE 224
9f5b6b30 MR	27	#define PI_BASE 256
0aba6178 BB	28	#define PL_BASE 352
0aba6178 BB	29	#define PM_BASE 384
4f6bd5cf	30	#define PN_BASE 416
0e37f88d	31
d10acc63 MR	32	#define SUNXI_PINCTRL_PIN(bank, pin) \
d10acc63 MR	33	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
0aba6178	34
08e9e614 MR	35	#define SUNXI_PIN_NAME_MAX_LEN 5
08e9e614 MR	36
0e37f88d MR	37	#define BANK_MEM_SIZE 0x24
0e37f88d MR	38	#define MUX_REGS_OFFSET 0x0
08e9e614	39	#define DATA_REGS_OFFSET 0x10
0e37f88d MR	40	#define DLEVEL_REGS_OFFSET 0x14
	41	#define PULL_REGS_OFFSET 0x1c
	42
	43	#define PINS_PER_BANK 32
	44	#define MUX_PINS_PER_REG 8
	45	#define MUX_PINS_BITS 4
	46	#define MUX_PINS_MASK 0x0f
08e9e614 MR	47	#define DATA_PINS_PER_REG 32
	48	#define DATA_PINS_BITS 1
	49	#define DATA_PINS_MASK 0x01
0e37f88d MR	50	#define DLEVEL_PINS_PER_REG 16
	51	#define DLEVEL_PINS_BITS 2
	52	#define DLEVEL_PINS_MASK 0x03
	53	#define PULL_PINS_PER_REG 16
	54	#define PULL_PINS_BITS 2
	55	#define PULL_PINS_MASK 0x03
	56
aebdc8ab	57	#define IRQ_PER_BANK 32
60242db1 MR	58
	59	#define IRQ_CFG_REG 0x200
	60	#define IRQ_CFG_IRQ_PER_REG 8
	61	#define IRQ_CFG_IRQ_BITS 4
	62	#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
	63	#define IRQ_CTRL_REG 0x210
	64	#define IRQ_CTRL_IRQ_PER_REG 32
	65	#define IRQ_CTRL_IRQ_BITS 1
	66	#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
	67	#define IRQ_STATUS_REG 0x214
	68	#define IRQ_STATUS_IRQ_PER_REG 32
	69	#define IRQ_STATUS_IRQ_BITS 1
	70	#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
	71
7c926492 MR	72	#define IRQ_DEBOUNCE_REG 0x218
7c926492 MR	73
aebdc8ab MR	74	#define IRQ_MEM_SIZE 0x20
aebdc8ab MR	75
60242db1 MR	76	#define IRQ_EDGE_RISING 0x00
	77	#define IRQ_EDGE_FALLING 0x01
	78	#define IRQ_LEVEL_HIGH 0x02
	79	#define IRQ_LEVEL_LOW 0x03
	80	#define IRQ_EDGE_BOTH 0x04
	81
402bfb3c CYT	82	#define GRP_CFG_REG 0x300
	83
	84	#define IO_BIAS_MASK GENMASK(3, 0)
	85
ef6d24cc HG	86	#define SUN4I_FUNC_INPUT 0
	87	#define SUN4I_FUNC_IRQ 6
	88
858f559f MR	89	#define PINCTRL_SUN5I_A10S BIT(1)
	90	#define PINCTRL_SUN5I_A13 BIT(2)
	91	#define PINCTRL_SUN5I_GR8 BIT(3)
4924982e CYT	92	#define PINCTRL_SUN6I_A31 BIT(4)
4924982e CYT	93	#define PINCTRL_SUN6I_A31S BIT(5)
88798ba2 IZ	94	#define PINCTRL_SUN4I_A10 BIT(6)
	95	#define PINCTRL_SUN7I_A20 BIT(7)
	96	#define PINCTRL_SUN8I_R40 BIT(8)
fb18f188 IZ	97	#define PINCTRL_SUN8I_V3 BIT(9)
fb18f188 IZ	98	#define PINCTRL_SUN8I_V3S BIT(10)
858f559f	99
cc62383f OJ	100	#define PIO_POW_MOD_SEL_REG 0x340
cc62383f OJ	101
f7275345 OJ	102	enum sunxi_desc_bias_voltage {
	103	BIAS_VOLTAGE_NONE,
	104	/*
	105	* Bias voltage configuration is done through
	106	* Pn_GRP_CONFIG registers, as seen on A80 SoC.
	107	*/
	108	BIAS_VOLTAGE_GRP_CONFIG,
cc62383f OJ	109	/*
	110	* Bias voltage is set through PIO_POW_MOD_SEL_REG
	111	* register, as seen on H6 SoC, for example.
	112	*/
	113	BIAS_VOLTAGE_PIO_POW_MODE_SEL,
f7275345 OJ	114	};
f7275345 OJ	115
0e37f88d	116	struct sunxi_desc_function {
578db85f	117	unsigned long variant;
0e37f88d MR	118	const char *name;
0e37f88d MR	119	u8 muxval;
6e1c3023	120	u8 irqbank;
60242db1	121	u8 irqnum;
0e37f88d MR	122	};
	123
	124	struct sunxi_desc_pin {
	125	struct pinctrl_pin_desc pin;
578db85f	126	unsigned long variant;
0e37f88d MR	127	struct sunxi_desc_function *functions;
	128	};
	129
	130	struct sunxi_pinctrl_desc {
	131	const struct sunxi_desc_pin *pins;
	132	int npins;
d83c82ce	133	unsigned pin_base;
8966ada2	134	unsigned irq_banks;
35817d34	135	const unsigned int *irq_bank_map;
ef6d24cc	136	bool irq_read_needs_mux;
aae842a3	137	bool disable_strict_mode;
f7275345	138	enum sunxi_desc_bias_voltage io_bias_cfg_variant;
0e37f88d MR	139	};
	140
	141	struct sunxi_pinctrl_function {
	142	const char *name;
	143	const char **groups;
	144	unsigned ngroups;
	145	};
	146
	147	struct sunxi_pinctrl_group {
	148	const char *name;
0e37f88d MR	149	unsigned pin;
	150	};
	151
9a2a566a MR	152	struct sunxi_pinctrl_regulator {
	153	struct regulator *regulator;
	154	refcount_t refcount;
	155	};
	156
0e37f88d MR	157	struct sunxi_pinctrl {
0e37f88d MR	158	void __iomem *membase;
08e9e614	159	struct gpio_chip *chip;
d39bd845	160	const struct sunxi_pinctrl_desc *desc;
0e37f88d	161	struct device *dev;
ca443844	162	struct sunxi_pinctrl_regulator regulators[9];
60242db1	163	struct irq_domain *domain;
0e37f88d MR	164	struct sunxi_pinctrl_function *functions;
	165	unsigned nfunctions;
	166	struct sunxi_pinctrl_group *groups;
	167	unsigned ngroups;
aebdc8ab MR	168	int *irq;
aebdc8ab MR	169	unsigned *irq_array;
f658ed36	170	raw_spinlock_t lock;
0e37f88d	171	struct pinctrl_dev *pctl_dev;
578db85f	172	unsigned long variant;
0e37f88d MR	173	};
	174
	175	#define SUNXI_PIN(_pin, ...) \
	176	{ \
	177	.pin = _pin, \
	178	.functions = (struct sunxi_desc_function[]){ \
	179	__VA_ARGS__, { } }, \
	180	}
	181
578db85f MR	182	#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
	183	{ \
	184	.pin = _pin, \
	185	.variant = _variant, \
	186	.functions = (struct sunxi_desc_function[]){ \
	187	__VA_ARGS__, { } }, \
	188	}
	189
0e37f88d MR	190	#define SUNXI_FUNCTION(_val, _name) \
	191	{ \
	192	.name = _name, \
	193	.muxval = _val, \
	194	}
	195
578db85f MR	196	#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
	197	{ \
	198	.name = _name, \
	199	.muxval = _val, \
	200	.variant = _variant, \
	201	}
	202
60242db1 MR	203	#define SUNXI_FUNCTION_IRQ(_val, _irq) \
	204	{ \
	205	.name = "irq", \
	206	.muxval = _val, \
	207	.irqnum = _irq, \
	208	}
	209
6e1c3023 MR	210	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
	211	{ \
	212	.name = "irq", \
	213	.muxval = _val, \
	214	.irqbank = _bank, \
	215	.irqnum = _irq, \
	216	}
	217
0e37f88d MR	218	/*
	219	* The sunXi PIO registers are organized as is:
	220	* 0x00 - 0x0c Muxing values.
	221	* 8 pins per register, each pin having a 4bits value
	222	* 0x10 Pin values
	223	* 32 bits per register, each pin corresponding to one bit
	224	* 0x14 - 0x18 Drive level
	225	* 16 pins per register, each pin having a 2bits value
	226	* 0x1c - 0x20 Pull-Up values
	227	* 16 pins per register, each pin having a 2bits value
	228	*
	229	* This is for the first bank. Each bank will have the same layout,
	230	* with an offset being a multiple of 0x24.
	231	*
	232	* The following functions calculate from the pin number the register
	233	* and the bit offset that we should access.
	234	*/
	235	static inline u32 sunxi_mux_reg(u16 pin)
	236	{
	237	u8 bank = pin / PINS_PER_BANK;
	238	u32 offset = bank * BANK_MEM_SIZE;
	239	offset += MUX_REGS_OFFSET;
	240	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	241	return round_down(offset, 4);
	242	}
	243
	244	static inline u32 sunxi_mux_offset(u16 pin)
	245	{
	246	u32 pin_num = pin % MUX_PINS_PER_REG;
	247	return pin_num * MUX_PINS_BITS;
	248	}
	249
08e9e614 MR	250	static inline u32 sunxi_data_reg(u16 pin)
	251	{
	252	u8 bank = pin / PINS_PER_BANK;
	253	u32 offset = bank * BANK_MEM_SIZE;
	254	offset += DATA_REGS_OFFSET;
	255	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	256	return round_down(offset, 4);
	257	}
	258
	259	static inline u32 sunxi_data_offset(u16 pin)
	260	{
	261	u32 pin_num = pin % DATA_PINS_PER_REG;
	262	return pin_num * DATA_PINS_BITS;
	263	}
	264
0e37f88d MR	265	static inline u32 sunxi_dlevel_reg(u16 pin)
	266	{
	267	u8 bank = pin / PINS_PER_BANK;
	268	u32 offset = bank * BANK_MEM_SIZE;
	269	offset += DLEVEL_REGS_OFFSET;
	270	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	271	return round_down(offset, 4);
	272	}
	273
	274	static inline u32 sunxi_dlevel_offset(u16 pin)
	275	{
	276	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	277	return pin_num * DLEVEL_PINS_BITS;
	278	}
	279
	280	static inline u32 sunxi_pull_reg(u16 pin)
	281	{
	282	u8 bank = pin / PINS_PER_BANK;
	283	u32 offset = bank * BANK_MEM_SIZE;
	284	offset += PULL_REGS_OFFSET;
	285	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	286	return round_down(offset, 4);
	287	}
	288
	289	static inline u32 sunxi_pull_offset(u16 pin)
	290	{
	291	u32 pin_num = pin % PULL_PINS_PER_REG;
	292	return pin_num * PULL_PINS_BITS;
	293	}
	294
29dfc6bb IZ	295	static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
29dfc6bb IZ	296	{
35817d34 IZ	297	if (!desc->irq_bank_map)
	298	return bank;
	299	else
	300	return desc->irq_bank_map[bank];
29dfc6bb IZ	301	}
29dfc6bb IZ	302
4b0d6c5a IZ	303	static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	304	u16 irq)
60242db1	305	{
aebdc8ab MR	306	u8 bank = irq / IRQ_PER_BANK;
	307	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
	308
29dfc6bb IZ	309	return IRQ_CFG_REG +
29dfc6bb IZ	310	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
60242db1 MR	311	}
	312
	313	static inline u32 sunxi_irq_cfg_offset(u16 irq)
	314	{
	315	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	316	return irq_num * IRQ_CFG_IRQ_BITS;
	317	}
	318
4b0d6c5a	319	static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	320	{
29dfc6bb	321	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	322	}
aebdc8ab MR	323
4b0d6c5a IZ	324	static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	325	u16 irq)
60242db1	326	{
aebdc8ab MR	327	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	328
4b0d6c5a	329	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
60242db1 MR	330	}
	331
	332	static inline u32 sunxi_irq_ctrl_offset(u16 irq)
	333	{
	334	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	335	return irq_num * IRQ_CTRL_IRQ_BITS;
	336	}
	337
4b0d6c5a	338	static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
7c926492	339	{
29dfc6bb IZ	340	return IRQ_DEBOUNCE_REG +
29dfc6bb IZ	341	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
7c926492 MR	342	}
7c926492 MR	343
4b0d6c5a	344	static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	345	{
29dfc6bb IZ	346	return IRQ_STATUS_REG +
29dfc6bb IZ	347	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	348	}
aebdc8ab MR	349
4b0d6c5a IZ	350	static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	351	u16 irq)
60242db1	352	{
aebdc8ab MR	353	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	354
4b0d6c5a	355	return sunxi_irq_status_reg_from_bank(desc, bank);
60242db1 MR	356	}
	357
	358	static inline u32 sunxi_irq_status_offset(u16 irq)
	359	{
	360	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	361	return irq_num * IRQ_STATUS_IRQ_BITS;
	362	}
	363
402bfb3c CYT	364	static inline u32 sunxi_grp_config_reg(u16 pin)
	365	{
	366	u8 bank = pin / PINS_PER_BANK;
	367
	368	return GRP_CFG_REG + bank * 0x4;
	369	}
	370
578db85f MR	371	int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
	372	const struct sunxi_pinctrl_desc *desc,
	373	unsigned long variant);
	374
	375	#define sunxi_pinctrl_init(_dev, _desc) \
	376	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
2284ba6b	377
0e37f88d	378	#endif /* __PINCTRL_SUNXI_H */