[mirror_ubuntu-eoan-kernel.git] / drivers / pinctrl / sunxi / pinctrl-sunxi.h

/*
 * Allwinner A1X SoCs pinctrl driver.
 *
 * Copyright (C) 2012 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#ifndef __PINCTRL_SUNXI_H
#define __PINCTRL_SUNXI_H

#include <linux/kernel.h>
#include <linux/spinlock.h>

#define PA_BASE	0
#define PB_BASE	32
#define PC_BASE	64
#define PD_BASE	96
#define PE_BASE	128
#define PF_BASE	160
#define PG_BASE	192
#define PH_BASE	224
#define PI_BASE	256
#define PL_BASE	352
#define PM_BASE	384
#define PN_BASE	416

#define SUNXI_PINCTRL_PIN(bank, pin)		\
	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

#define SUNXI_PIN_NAME_MAX_LEN	5

#define BANK_MEM_SIZE		0x24
#define MUX_REGS_OFFSET		0x0
#define DATA_REGS_OFFSET	0x10
#define DLEVEL_REGS_OFFSET	0x14
#define PULL_REGS_OFFSET	0x1c

#define PINS_PER_BANK		32
#define MUX_PINS_PER_REG	8
#define MUX_PINS_BITS		4
#define MUX_PINS_MASK		0x0f
#define DATA_PINS_PER_REG	32
#define DATA_PINS_BITS		1
#define DATA_PINS_MASK		0x01
#define DLEVEL_PINS_PER_REG	16
#define DLEVEL_PINS_BITS	2
#define DLEVEL_PINS_MASK	0x03
#define PULL_PINS_PER_REG	16
#define PULL_PINS_BITS		2
#define PULL_PINS_MASK		0x03

#define IRQ_PER_BANK		32

#define IRQ_CFG_REG		0x200
#define IRQ_CFG_IRQ_PER_REG		8
#define IRQ_CFG_IRQ_BITS		4
#define IRQ_CFG_IRQ_MASK		((1 << IRQ_CFG_IRQ_BITS) - 1)
#define IRQ_CTRL_REG		0x210
#define IRQ_CTRL_IRQ_PER_REG		32
#define IRQ_CTRL_IRQ_BITS		1
#define IRQ_CTRL_IRQ_MASK		((1 << IRQ_CTRL_IRQ_BITS) - 1)
#define IRQ_STATUS_REG		0x214
#define IRQ_STATUS_IRQ_PER_REG		32
#define IRQ_STATUS_IRQ_BITS		1
#define IRQ_STATUS_IRQ_MASK		((1 << IRQ_STATUS_IRQ_BITS) - 1)

#define IRQ_DEBOUNCE_REG	0x218

#define IRQ_MEM_SIZE		0x20

#define IRQ_EDGE_RISING		0x00
#define IRQ_EDGE_FALLING	0x01
#define IRQ_LEVEL_HIGH		0x02
#define IRQ_LEVEL_LOW		0x03
#define IRQ_EDGE_BOTH		0x04

#define SUN4I_FUNC_INPUT	0
#define SUN4I_FUNC_IRQ		6

#define PINCTRL_SUN5I_A10S	BIT(1)
#define PINCTRL_SUN5I_A13	BIT(2)
#define PINCTRL_SUN5I_GR8	BIT(3)
#define PINCTRL_SUN6I_A31	BIT(4)
#define PINCTRL_SUN6I_A31S	BIT(5)
#define PINCTRL_SUN4I_A10	BIT(6)
#define PINCTRL_SUN7I_A20	BIT(7)
#define PINCTRL_SUN8I_R40	BIT(8)

struct sunxi_desc_function {
	unsigned long	variant;
	const char	*name;
	u8		muxval;
	u8		irqbank;
	u8		irqnum;
};

struct sunxi_desc_pin {
	struct pinctrl_pin_desc		pin;
	unsigned long			variant;
	struct sunxi_desc_function	*functions;
};

struct sunxi_pinctrl_desc {
	const struct sunxi_desc_pin	*pins;
	int				npins;
	unsigned			pin_base;
	unsigned			irq_banks;
	const unsigned int		*irq_bank_map;
	bool				irq_read_needs_mux;
	bool				disable_strict_mode;
};

struct sunxi_pinctrl_function {
	const char	*name;
	const char	**groups;
	unsigned	ngroups;
};

struct sunxi_pinctrl_group {
	const char	*name;
	unsigned	pin;
};

struct sunxi_pinctrl_regulator {
	struct regulator	*regulator;
	refcount_t		refcount;
};

struct sunxi_pinctrl {
	void __iomem			*membase;
	struct gpio_chip		*chip;
	const struct sunxi_pinctrl_desc	*desc;
	struct device			*dev;
	struct sunxi_pinctrl_regulator	regulators[9];
	struct irq_domain		*domain;
	struct sunxi_pinctrl_function	*functions;
	unsigned			nfunctions;
	struct sunxi_pinctrl_group	*groups;
	unsigned			ngroups;
	int				*irq;
	unsigned			*irq_array;
	raw_spinlock_t			lock;
	struct pinctrl_dev		*pctl_dev;
	unsigned long			variant;
};

#define SUNXI_PIN(_pin, ...)					\
	{							\
		.pin = _pin,					\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_PIN_VARIANT(_pin, _variant, ...)			\
	{							\
		.pin = _pin,					\
		.variant = _variant,				\
		.functions = (struct sunxi_desc_function[]){	\
			__VA_ARGS__, { } },			\
	}

#define SUNXI_FUNCTION(_val, _name)				\
	{							\
		.name = _name,					\
		.muxval = _val,					\
	}

#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant)		\
	{							\
		.name = _name,					\
		.muxval = _val,					\
		.variant = _variant,				\
	}

#define SUNXI_FUNCTION_IRQ(_val, _irq)				\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqnum = _irq,					\
	}

#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq)		\
	{							\
		.name = "irq",					\
		.muxval = _val,					\
		.irqbank = _bank,				\
		.irqnum = _irq,					\
	}

/*
 * The sunXi PIO registers are organized as is:
 * 0x00 - 0x0c	Muxing values.
 *		8 pins per register, each pin having a 4bits value
 * 0x10		Pin values
 *		32 bits per register, each pin corresponding to one bit
 * 0x14 - 0x18	Drive level
 *		16 pins per register, each pin having a 2bits value
 * 0x1c - 0x20	Pull-Up values
 *		16 pins per register, each pin having a 2bits value
 *
 * This is for the first bank. Each bank will have the same layout,
 * with an offset being a multiple of 0x24.
 *
 * The following functions calculate from the pin number the register
 * and the bit offset that we should access.
 */
static inline u32 sunxi_mux_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += MUX_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_mux_offset(u16 pin)
{
	u32 pin_num = pin % MUX_PINS_PER_REG;
	return pin_num * MUX_PINS_BITS;
}

static inline u32 sunxi_data_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DATA_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_data_offset(u16 pin)
{
	u32 pin_num = pin % DATA_PINS_PER_REG;
	return pin_num * DATA_PINS_BITS;
}

static inline u32 sunxi_dlevel_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += DLEVEL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_dlevel_offset(u16 pin)
{
	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	return pin_num * DLEVEL_PINS_BITS;
}

static inline u32 sunxi_pull_reg(u16 pin)
{
	u8 bank = pin / PINS_PER_BANK;
	u32 offset = bank * BANK_MEM_SIZE;
	offset += PULL_REGS_OFFSET;
	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	return round_down(offset, 4);
}

static inline u32 sunxi_pull_offset(u16 pin)
{
	u32 pin_num = pin % PULL_PINS_PER_REG;
	return pin_num * PULL_PINS_BITS;
}

static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	if (!desc->irq_bank_map)
		return bank;
	else
		return desc->irq_bank_map[bank];
}

static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
				    u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;
	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;

	return IRQ_CFG_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
}

static inline u32 sunxi_irq_cfg_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	return irq_num * IRQ_CFG_IRQ_BITS;
}

static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
				     u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_ctrl_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	return irq_num * IRQ_CTRL_IRQ_BITS;
}

static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_DEBOUNCE_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
{
	return IRQ_STATUS_REG +
	       sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
}

static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
				       u16 irq)
{
	u8 bank = irq / IRQ_PER_BANK;

	return sunxi_irq_status_reg_from_bank(desc, bank);
}

static inline u32 sunxi_irq_status_offset(u16 irq)
{
	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	return irq_num * IRQ_STATUS_IRQ_BITS;
}

int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
				    const struct sunxi_pinctrl_desc *desc,
				    unsigned long variant);

#define sunxi_pinctrl_init(_dev, _desc) \
	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)

#endif /* __PINCTRL_SUNXI_H */
Commit	Line	Data
0e37f88d MR	1	/*
	2	* Allwinner A1X SoCs pinctrl driver.
	3	*
	4	* Copyright (C) 2012 Maxime Ripard
	5	*
	6	* Maxime Ripard <maxime.ripard@free-electrons.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
	9	* License version 2. This program is licensed "as is" without any
	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#ifndef __PINCTRL_SUNXI_H
	14	#define __PINCTRL_SUNXI_H
	15
	16	#include <linux/kernel.h>
1bee963d	17	#include <linux/spinlock.h>
0e37f88d MR	18
	19	#define PA_BASE 0
	20	#define PB_BASE 32
	21	#define PC_BASE 64
	22	#define PD_BASE 96
	23	#define PE_BASE 128
	24	#define PF_BASE 160
	25	#define PG_BASE 192
9f5b6b30 MR	26	#define PH_BASE 224
9f5b6b30 MR	27	#define PI_BASE 256
0aba6178 BB	28	#define PL_BASE 352
0aba6178 BB	29	#define PM_BASE 384
4f6bd5cf	30	#define PN_BASE 416
0e37f88d	31
d10acc63 MR	32	#define SUNXI_PINCTRL_PIN(bank, pin) \
d10acc63 MR	33	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)
0aba6178	34
08e9e614 MR	35	#define SUNXI_PIN_NAME_MAX_LEN 5
08e9e614 MR	36
0e37f88d MR	37	#define BANK_MEM_SIZE 0x24
0e37f88d MR	38	#define MUX_REGS_OFFSET 0x0
08e9e614	39	#define DATA_REGS_OFFSET 0x10
0e37f88d MR	40	#define DLEVEL_REGS_OFFSET 0x14
	41	#define PULL_REGS_OFFSET 0x1c
	42
	43	#define PINS_PER_BANK 32
	44	#define MUX_PINS_PER_REG 8
	45	#define MUX_PINS_BITS 4
	46	#define MUX_PINS_MASK 0x0f
08e9e614 MR	47	#define DATA_PINS_PER_REG 32
	48	#define DATA_PINS_BITS 1
	49	#define DATA_PINS_MASK 0x01
0e37f88d MR	50	#define DLEVEL_PINS_PER_REG 16
	51	#define DLEVEL_PINS_BITS 2
	52	#define DLEVEL_PINS_MASK 0x03
	53	#define PULL_PINS_PER_REG 16
	54	#define PULL_PINS_BITS 2
	55	#define PULL_PINS_MASK 0x03
	56
aebdc8ab	57	#define IRQ_PER_BANK 32
60242db1 MR	58
	59	#define IRQ_CFG_REG 0x200
	60	#define IRQ_CFG_IRQ_PER_REG 8
	61	#define IRQ_CFG_IRQ_BITS 4
	62	#define IRQ_CFG_IRQ_MASK ((1 << IRQ_CFG_IRQ_BITS) - 1)
	63	#define IRQ_CTRL_REG 0x210
	64	#define IRQ_CTRL_IRQ_PER_REG 32
	65	#define IRQ_CTRL_IRQ_BITS 1
	66	#define IRQ_CTRL_IRQ_MASK ((1 << IRQ_CTRL_IRQ_BITS) - 1)
	67	#define IRQ_STATUS_REG 0x214
	68	#define IRQ_STATUS_IRQ_PER_REG 32
	69	#define IRQ_STATUS_IRQ_BITS 1
	70	#define IRQ_STATUS_IRQ_MASK ((1 << IRQ_STATUS_IRQ_BITS) - 1)
	71
7c926492 MR	72	#define IRQ_DEBOUNCE_REG 0x218
7c926492 MR	73
aebdc8ab MR	74	#define IRQ_MEM_SIZE 0x20
aebdc8ab MR	75
60242db1 MR	76	#define IRQ_EDGE_RISING 0x00
	77	#define IRQ_EDGE_FALLING 0x01
	78	#define IRQ_LEVEL_HIGH 0x02
	79	#define IRQ_LEVEL_LOW 0x03
	80	#define IRQ_EDGE_BOTH 0x04
	81
ef6d24cc HG	82	#define SUN4I_FUNC_INPUT 0
	83	#define SUN4I_FUNC_IRQ 6
	84
858f559f MR	85	#define PINCTRL_SUN5I_A10S BIT(1)
	86	#define PINCTRL_SUN5I_A13 BIT(2)
	87	#define PINCTRL_SUN5I_GR8 BIT(3)
4924982e CYT	88	#define PINCTRL_SUN6I_A31 BIT(4)
4924982e CYT	89	#define PINCTRL_SUN6I_A31S BIT(5)
88798ba2 IZ	90	#define PINCTRL_SUN4I_A10 BIT(6)
	91	#define PINCTRL_SUN7I_A20 BIT(7)
	92	#define PINCTRL_SUN8I_R40 BIT(8)
858f559f	93
0e37f88d	94	struct sunxi_desc_function {
578db85f	95	unsigned long variant;
0e37f88d MR	96	const char *name;
0e37f88d MR	97	u8 muxval;
6e1c3023	98	u8 irqbank;
60242db1	99	u8 irqnum;
0e37f88d MR	100	};
	101
	102	struct sunxi_desc_pin {
	103	struct pinctrl_pin_desc pin;
578db85f	104	unsigned long variant;
0e37f88d MR	105	struct sunxi_desc_function *functions;
	106	};
	107
	108	struct sunxi_pinctrl_desc {
	109	const struct sunxi_desc_pin *pins;
	110	int npins;
d83c82ce	111	unsigned pin_base;
8966ada2	112	unsigned irq_banks;
35817d34	113	const unsigned int *irq_bank_map;
ef6d24cc	114	bool irq_read_needs_mux;
aae842a3	115	bool disable_strict_mode;
0e37f88d MR	116	};
	117
	118	struct sunxi_pinctrl_function {
	119	const char *name;
	120	const char **groups;
	121	unsigned ngroups;
	122	};
	123
	124	struct sunxi_pinctrl_group {
	125	const char *name;
0e37f88d MR	126	unsigned pin;
	127	};
	128
9a2a566a MR	129	struct sunxi_pinctrl_regulator {
	130	struct regulator *regulator;
	131	refcount_t refcount;
	132	};
	133
0e37f88d MR	134	struct sunxi_pinctrl {
0e37f88d MR	135	void __iomem *membase;
08e9e614	136	struct gpio_chip *chip;
d39bd845	137	const struct sunxi_pinctrl_desc *desc;
0e37f88d	138	struct device *dev;
ca443844	139	struct sunxi_pinctrl_regulator regulators[9];
60242db1	140	struct irq_domain *domain;
0e37f88d MR	141	struct sunxi_pinctrl_function *functions;
	142	unsigned nfunctions;
	143	struct sunxi_pinctrl_group *groups;
	144	unsigned ngroups;
aebdc8ab MR	145	int *irq;
aebdc8ab MR	146	unsigned *irq_array;
f658ed36	147	raw_spinlock_t lock;
0e37f88d	148	struct pinctrl_dev *pctl_dev;
578db85f	149	unsigned long variant;
0e37f88d MR	150	};
	151
	152	#define SUNXI_PIN(_pin, ...) \
	153	{ \
	154	.pin = _pin, \
	155	.functions = (struct sunxi_desc_function[]){ \
	156	__VA_ARGS__, { } }, \
	157	}
	158
578db85f MR	159	#define SUNXI_PIN_VARIANT(_pin, _variant, ...) \
	160	{ \
	161	.pin = _pin, \
	162	.variant = _variant, \
	163	.functions = (struct sunxi_desc_function[]){ \
	164	__VA_ARGS__, { } }, \
	165	}
	166
0e37f88d MR	167	#define SUNXI_FUNCTION(_val, _name) \
	168	{ \
	169	.name = _name, \
	170	.muxval = _val, \
	171	}
	172
578db85f MR	173	#define SUNXI_FUNCTION_VARIANT(_val, _name, _variant) \
	174	{ \
	175	.name = _name, \
	176	.muxval = _val, \
	177	.variant = _variant, \
	178	}
	179
60242db1 MR	180	#define SUNXI_FUNCTION_IRQ(_val, _irq) \
	181	{ \
	182	.name = "irq", \
	183	.muxval = _val, \
	184	.irqnum = _irq, \
	185	}
	186
6e1c3023 MR	187	#define SUNXI_FUNCTION_IRQ_BANK(_val, _bank, _irq) \
	188	{ \
	189	.name = "irq", \
	190	.muxval = _val, \
	191	.irqbank = _bank, \
	192	.irqnum = _irq, \
	193	}
	194
0e37f88d MR	195	/*
	196	* The sunXi PIO registers are organized as is:
	197	* 0x00 - 0x0c Muxing values.
	198	* 8 pins per register, each pin having a 4bits value
	199	* 0x10 Pin values
	200	* 32 bits per register, each pin corresponding to one bit
	201	* 0x14 - 0x18 Drive level
	202	* 16 pins per register, each pin having a 2bits value
	203	* 0x1c - 0x20 Pull-Up values
	204	* 16 pins per register, each pin having a 2bits value
	205	*
	206	* This is for the first bank. Each bank will have the same layout,
	207	* with an offset being a multiple of 0x24.
	208	*
	209	* The following functions calculate from the pin number the register
	210	* and the bit offset that we should access.
	211	*/
	212	static inline u32 sunxi_mux_reg(u16 pin)
	213	{
	214	u8 bank = pin / PINS_PER_BANK;
	215	u32 offset = bank * BANK_MEM_SIZE;
	216	offset += MUX_REGS_OFFSET;
	217	offset += pin % PINS_PER_BANK / MUX_PINS_PER_REG * 0x04;
	218	return round_down(offset, 4);
	219	}
	220
	221	static inline u32 sunxi_mux_offset(u16 pin)
	222	{
	223	u32 pin_num = pin % MUX_PINS_PER_REG;
	224	return pin_num * MUX_PINS_BITS;
	225	}
	226
08e9e614 MR	227	static inline u32 sunxi_data_reg(u16 pin)
	228	{
	229	u8 bank = pin / PINS_PER_BANK;
	230	u32 offset = bank * BANK_MEM_SIZE;
	231	offset += DATA_REGS_OFFSET;
	232	offset += pin % PINS_PER_BANK / DATA_PINS_PER_REG * 0x04;
	233	return round_down(offset, 4);
	234	}
	235
	236	static inline u32 sunxi_data_offset(u16 pin)
	237	{
	238	u32 pin_num = pin % DATA_PINS_PER_REG;
	239	return pin_num * DATA_PINS_BITS;
	240	}
	241
0e37f88d MR	242	static inline u32 sunxi_dlevel_reg(u16 pin)
	243	{
	244	u8 bank = pin / PINS_PER_BANK;
	245	u32 offset = bank * BANK_MEM_SIZE;
	246	offset += DLEVEL_REGS_OFFSET;
	247	offset += pin % PINS_PER_BANK / DLEVEL_PINS_PER_REG * 0x04;
	248	return round_down(offset, 4);
	249	}
	250
	251	static inline u32 sunxi_dlevel_offset(u16 pin)
	252	{
	253	u32 pin_num = pin % DLEVEL_PINS_PER_REG;
	254	return pin_num * DLEVEL_PINS_BITS;
	255	}
	256
	257	static inline u32 sunxi_pull_reg(u16 pin)
	258	{
	259	u8 bank = pin / PINS_PER_BANK;
	260	u32 offset = bank * BANK_MEM_SIZE;
	261	offset += PULL_REGS_OFFSET;
	262	offset += pin % PINS_PER_BANK / PULL_PINS_PER_REG * 0x04;
	263	return round_down(offset, 4);
	264	}
	265
	266	static inline u32 sunxi_pull_offset(u16 pin)
	267	{
	268	u32 pin_num = pin % PULL_PINS_PER_REG;
	269	return pin_num * PULL_PINS_BITS;
	270	}
	271
29dfc6bb IZ	272	static inline u32 sunxi_irq_hw_bank_num(const struct sunxi_pinctrl_desc *desc, u8 bank)
29dfc6bb IZ	273	{
35817d34 IZ	274	if (!desc->irq_bank_map)
	275	return bank;
	276	else
	277	return desc->irq_bank_map[bank];
29dfc6bb IZ	278	}
29dfc6bb IZ	279
4b0d6c5a IZ	280	static inline u32 sunxi_irq_cfg_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	281	u16 irq)
60242db1	282	{
aebdc8ab MR	283	u8 bank = irq / IRQ_PER_BANK;
	284	u8 reg = (irq % IRQ_PER_BANK) / IRQ_CFG_IRQ_PER_REG * 0x04;
	285
29dfc6bb IZ	286	return IRQ_CFG_REG +
29dfc6bb IZ	287	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE + reg;
60242db1 MR	288	}
	289
	290	static inline u32 sunxi_irq_cfg_offset(u16 irq)
	291	{
	292	u32 irq_num = irq % IRQ_CFG_IRQ_PER_REG;
	293	return irq_num * IRQ_CFG_IRQ_BITS;
	294	}
	295
4b0d6c5a	296	static inline u32 sunxi_irq_ctrl_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	297	{
29dfc6bb	298	return IRQ_CTRL_REG + sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	299	}
aebdc8ab MR	300
4b0d6c5a IZ	301	static inline u32 sunxi_irq_ctrl_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	302	u16 irq)
60242db1	303	{
aebdc8ab MR	304	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	305
4b0d6c5a	306	return sunxi_irq_ctrl_reg_from_bank(desc, bank);
60242db1 MR	307	}
	308
	309	static inline u32 sunxi_irq_ctrl_offset(u16 irq)
	310	{
	311	u32 irq_num = irq % IRQ_CTRL_IRQ_PER_REG;
	312	return irq_num * IRQ_CTRL_IRQ_BITS;
	313	}
	314
4b0d6c5a	315	static inline u32 sunxi_irq_debounce_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
7c926492	316	{
29dfc6bb IZ	317	return IRQ_DEBOUNCE_REG +
29dfc6bb IZ	318	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
7c926492 MR	319	}
7c926492 MR	320
4b0d6c5a	321	static inline u32 sunxi_irq_status_reg_from_bank(const struct sunxi_pinctrl_desc *desc, u8 bank)
aebdc8ab	322	{
29dfc6bb IZ	323	return IRQ_STATUS_REG +
29dfc6bb IZ	324	sunxi_irq_hw_bank_num(desc, bank) * IRQ_MEM_SIZE;
aebdc8ab MR	325	}
aebdc8ab MR	326
4b0d6c5a IZ	327	static inline u32 sunxi_irq_status_reg(const struct sunxi_pinctrl_desc *desc,
4b0d6c5a IZ	328	u16 irq)
60242db1	329	{
aebdc8ab MR	330	u8 bank = irq / IRQ_PER_BANK;
aebdc8ab MR	331
4b0d6c5a	332	return sunxi_irq_status_reg_from_bank(desc, bank);
60242db1 MR	333	}
	334
	335	static inline u32 sunxi_irq_status_offset(u16 irq)
	336	{
	337	u32 irq_num = irq % IRQ_STATUS_IRQ_PER_REG;
	338	return irq_num * IRQ_STATUS_IRQ_BITS;
	339	}
	340
578db85f MR	341	int sunxi_pinctrl_init_with_variant(struct platform_device *pdev,
	342	const struct sunxi_pinctrl_desc *desc,
	343	unsigned long variant);
	344
	345	#define sunxi_pinctrl_init(_dev, _desc) \
	346	sunxi_pinctrl_init_with_variant(_dev, _desc, 0)
2284ba6b	347
0e37f88d	348	#endif /* __PINCTRL_SUNXI_H */